Page table searching method and device and electronic equipment

Abstract

The invention provides a page table searching method and device and electronic equipment, and the method comprises the steps: designing a second page table entry comprising position information and m physical addresses, and enabling the m physical addresses recorded in the second page table entry to be the physical addresses of m page table entries in a second continuous page table group, the position information represents the position of the second page table entry in the second continuous page table group to which the second page table entry belongs. Therefore, m page table entries with continuous virtual addresses stored in the memory can be represented by one second page table entry, the effect of compressing PTE is achieved, and the utilization rate of TLB is further improved. Meanwhile, compared with a traditional continuity scheme, the scheme of the invention does not have the limitation that physical addresses must be continuous, and the applicability of the scheme is higher.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more specifically, to a page table lookup method, apparatus, and electronic device. Background Technology

[0002] The rise of artificial intelligence has led to an explosive growth in the amount of data processed, resulting in a continuous increase in memory demand. For example, the memory required by peripherals such as GPUs (Graphics Processing Units) has expanded to hundreds of gigabytes (GB). With memory capacity constantly increasing, efficient memory access becomes crucial. To meet requirements such as security and isolation, peripherals like GPUs and DPUs (Data Processing Units) are typically equipped with their own MMUs (Memory Management Units), responsible for translating virtual machine addresses to physical addresses. The hit rate of the TLB (Translation Lookaside Buffer) directly affects memory access efficiency.

[0003] The TLB is essentially a fixed-size cache used to store page table entries. If a page table entry stored in the TLB can correspond to more physical addresses in physical memory, then the TLB utilization can be higher, thus improving the TLB hit rate. Currently, to achieve more efficient TLB utilization, ARM provides a continue scheme, which merges a set number (usually 8 or 16) physically contiguous PTEs (Page Table Entries) into a single TLB entry, effectively "compressing" PTEs and improving TLB utilization. However, this scheme has significant limitations; it not only requires contiguous physical addresses but also imposes restrictions on the number of page table entries. Summary of the Invention

[0004] The purpose of this application is to provide a page table lookup method, apparatus, and electronic device for improving TLB utilization.

[0005] This application embodiment also provides a page table lookup method, including: in response to a received target virtual address, determining whether a target page table entry that the target virtual address matches exists in the TLB; wherein, the page table entry in the TLB includes a second page table entry; the second page table entry includes location information and m physical addresses; the location information represents the position of the second page table entry in its respective second contiguous page table group; the second contiguous page table group is a set of m consecutive page table entries stored in memory; the m physical addresses are the physical addresses of the m page table entries in the second contiguous page table group; wherein, when the target virtual address is located in the second page table entry... When the target virtual address falls within the virtual address range of the second consecutive page table group, it is determined that the target virtual address hits the second page table entry. The virtual address range of the second consecutive page table group is calculated based on the virtual address of the second page table entry, the location information of the second page table entry, and the value of m. If there is a target page table entry in the TLB that hits the target virtual address, and the target page table entry is a second page table entry, the target location information corresponding to the target virtual address is determined based on the target virtual address, the virtual address of the second page table entry, and the location information. The target physical address corresponding to the target location information is then obtained from the m physical addresses recorded in the second page table entry.

[0006] In the above implementation scheme of this application, a second page table entry is designed. The second page table entry includes location information representing the position of the second page table entry within the second contiguous page table group, and m physical addresses. The second contiguous page table group is a set of m page table entries stored in memory with consecutive virtual addresses, and the m physical addresses recorded in the second page table entry are the physical addresses of the m page table entries within the second contiguous page table group. Thus, for m consecutive page table entries stored in memory (page table entries stored consecutively in memory are necessarily contiguous in virtual address), regardless of whether their physical addresses are contiguous, they can all be represented by a single second page table entry. Specifically, the virtual address range of the second consecutive page table group can be determined by the virtual address of the second page table entry, its location information (indicating which page table entry in the second consecutive page table group it is), and the value of m (indicating the total number of page table entries in the second consecutive page table group). Furthermore, the target location information corresponding to the target virtual address (i.e., the position of the page table entry actually corresponding to the target virtual address in the second consecutive page table group) can be determined based on the target virtual address, the virtual address of the second page table entry, and its location information. Then, the target physical address corresponding to the target location information can be determined from the m physical addresses recorded in the second page table entry based on the target location information. In other words, in the above scheme of this application, the representation of m consecutive page table entries stored in memory can be achieved through a single second page table entry, effectively "compressing" the PTE and thus improving the utilization of the TLB. Furthermore, compared to the traditional continue scheme, the above-mentioned scheme in this application does not have the restriction of physical address contiguousness, and the scheme has greater applicability.

[0007] It can also be understood that the physical addresses of the second page table entries are not required to be contiguous. Therefore, theoretically, all page table entries stored in memory can be "compressed" through the second page table entries, making it more applicable.

[0008] Optionally, the virtual address range of the second consecutive page table group is specifically calculated in the following manner: based on the virtual address and position information of the second page table entries, and the virtual address size corresponding to a single page table entry, the starting virtual address of the second consecutive page table group is calculated; based on the virtual address and position information of the second page table entries, the value of m, and the virtual address size corresponding to a single page table entry, the ending virtual address of the second consecutive page table group is calculated; the virtual address range of the second consecutive page table group is the range formed by the starting virtual address to the ending virtual address.

[0009] Optionally, the starting virtual address of the second consecutive page table group is calculated based on the virtual address and location information of the second page table entry, and the virtual address size corresponding to a single page table entry. This includes: calculating a first virtual address deviation between the virtual address of the second page table entry and the starting virtual address of the second consecutive page table group based on the location information of the second page table entry and the virtual address size corresponding to the single page table entry; and calculating the difference between the virtual address of the second page table entry and the first virtual address deviation to obtain the starting virtual address of the second consecutive page table group.

[0010] In the above implementation, since the virtual addresses of each page table entry in the second consecutive page table group are consecutive, and the position information represents the position of the second page table entry in the second consecutive page table group, that is, which page table entry it is in the second consecutive page table group, the virtual address of the first page table entry in the second consecutive page table group, that is, the starting virtual address of the second consecutive page table group, can be determined quickly, simply and accurately through the above method.

[0011] Optionally, the ending virtual address of the second consecutive page table group is calculated based on the virtual address and location information of the second page table entry, the value of m, and the virtual address size corresponding to a single page table entry. This includes: calculating a second virtual address deviation between the ending virtual address of the second consecutive page table group and the virtual address of the second page table entry based on m, the location information of the second page table entry, and the virtual address size corresponding to the single page table entry; and calculating the sum of the virtual address of the second page table entry and the second virtual address deviation to obtain the ending virtual address of the second consecutive page table group.

[0012] In the above implementation, since the virtual addresses of each page table entry in the second consecutive page table group are consecutive, and the position information represents the position of the second page table entry in the second consecutive page table group, that is, which page table entry it is in the second consecutive page table group, the virtual address of the last page table entry in the first consecutive page table group, that is, the end virtual address of the first consecutive page table group, can be determined quickly, simply and accurately through the above method.

[0013] Optionally, determining the target location information corresponding to the target virtual address based on the target virtual address, the virtual address of the second page table entry, and the location information includes: calculating the deviation between the target virtual address and the virtual address of the second page table entry; determining the positional deviation between the location corresponding to the target virtual address and the positional information of the second page table entry based on the deviation and the size of the virtual address corresponding to a single page table entry; and determining the target location information corresponding to the target virtual address based on the positional information of the second page table entry and the positional deviation.

[0014] In the above implementation, since the virtual addresses of each page table entry in the second consecutive page table group are consecutive, the deviation between the target virtual address and the virtual address of the second page table entry represents the positional deviation between the page table entry that the target virtual address should actually correspond to in the second consecutive page table group and the second page table entry. Therefore, based on this virtual address deviation and the size of the virtual address corresponding to a single page table entry, the positional deviation between the position of the target virtual address (i.e., the position of the page table entry that the target virtual address should actually correspond to in the second consecutive page table group) and the positional information of the second page table entry can be determined. Then, based on the positional information of the second page table entry and this positional deviation, the target positional information corresponding to the target virtual address (i.e., the position of the page table entry that the target virtual address should actually correspond to in the second consecutive page table group) can be quickly and accurately determined.

[0015] Optionally, determining the target location information corresponding to the target virtual address based on the target virtual address, the virtual address of the second page table entry, and the location information includes: determining the starting virtual address of the second consecutive page table group based on the virtual address of the second page table entry, the location information, and the virtual address size corresponding to a single page table entry; calculating the deviation between the target virtual address and the starting virtual address; and determining the target location information corresponding to the target virtual address based on the deviation and the virtual address size corresponding to a single page table entry.

[0016] In the above implementation, since the virtual addresses of each page table entry in the second consecutive page table group are consecutive, the deviation between the target virtual address and the starting virtual address of the second consecutive page table group represents the position deviation of the page table entry that the target virtual address should actually correspond to in the second consecutive page table group and the first page table entry of the second consecutive page table group. Therefore, based on this virtual address deviation and the virtual address size corresponding to a single page table entry, the target position information corresponding to the target virtual address (i.e., the position of the page table entry that the target virtual address should actually correspond to in the second consecutive page table group) can be determined quickly and accurately.

[0017] Optionally, the second page table entry contains pattern information; the pattern information is used to characterize that the page table entry belongs to the second page table entry, and the pattern information and the position information reuse the same bits in the second page table entry.

[0018] In the above implementation, by setting pattern information in the page table entries, it is easy to distinguish whether the hit target page table entry is a second page table entry, reducing the risk of calculation errors. At the same time, by reusing the same bits in the second page table entries for both pattern information and position information, the limited byte resources in the page table entries can be effectively saved.

[0019] Optionally, the method further includes: if there is no target page table entry in the TLB that matches the target virtual address, searching for the target page table entry corresponding to the target virtual address in memory; wherein, if the target page table entry is a second page table entry, the target page table entry includes location information and m physical addresses; and adding the target page table entry to the TLB.

[0020] In the above implementation, for cases where the TLB is not found, the target page table entry is searched in memory and added to the TLB. This ensures that the TLB stores the most recently searched page table entry from memory, thus better conforming to the principle of locality (i.e., when a page table entry is used, it is likely to be used again in the near future), improving the TLB hit rate. Simultaneously, since the page table entries in memory are already stored in the form of second-level page table entries, adding them to the TLB achieves the aforementioned "compression" effect, enabling the representation of multiple page table entries and improving TLB utilization.

[0021] This application embodiment also provides a page table lookup apparatus, including: a second lookup module, configured to determine, in response to a received target virtual address, whether a target page table entry matched by the target virtual address exists in the TLB; wherein, the page table entry in the TLB includes a second page table entry; the second page table entry includes location information and m physical addresses; the location information represents the position of the second page table entry in its respective second contiguous page table group; the second contiguous page table group is a set of m consecutive page table entries stored in memory; the m physical addresses are the physical addresses of the m page table entries in the second contiguous page table group; wherein, when the target virtual address is located in the second page table entry... When the target virtual address falls within the virtual address range of the second consecutive page table group, it is determined that the target virtual address matches the second page table entry. The virtual address range of the second consecutive page table group is calculated based on the virtual address of the second page table entry, the location information of the second page table entry, and the value of m. The second conversion module is used to determine the target location information corresponding to the target virtual address based on the target virtual address, the virtual address of the second page table entry, and the location information when there is a target page table entry in the TLB that matches the target virtual address and the target page table entry is the second page table entry, and to obtain the target physical address corresponding to the target location information from the m physical addresses recorded in the second page table entry.

[0022] This application also provides an electronic device, including: a processor, a memory management unit, memory, and a communication bus; the communication bus is used to realize the connection and communication between the processor, the memory management unit, and the memory; the memory stores page table entries; the processor is used to send a target virtual address to the memory management unit; the memory management unit includes a TLB, used to execute any of the aforementioned page table lookup methods. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 A schematic diagram illustrating the basic structure of the first page table lookup method provided in this application embodiment; Figure 2 A method provided for embodiments of this application and Figure 1 Example diagram of PTE compression corresponding to the method; Figure 3 A schematic diagram illustrating the basic structure of the second page table lookup method provided in this application embodiment; Figure 4 A method provided for embodiments of this application and Figure 3 Example diagram of PTE compression corresponding to the method; Figure 5 A method provided for embodiments of this application and Figure 3 A schematic diagram of the PTE format corresponding to the method; Figure 6 This application provides a schematic diagram of the basic format of a PTE. Figure 7 A method provided for embodiments of this application and Figure 1 A schematic diagram of the PTE format corresponding to the method; Figure 8 This is a schematic diagram of the basic structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0025] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0026] To facilitate understanding of the technology in the embodiments of this application, some related technologies will be introduced below.

[0027] In computer technology, a computer has a set of addresses that a program can generate, called the address range. The size of this range is determined by the number of bits in the processor. For example, a 32-bit processor has an address range of 0 to 0xFFFFFFFF (4GB), while a 64-bit processor has an address range of 0 to 0xFFFFFFFFFFFFFFFF (16E). This range is the address range that a program can generate, and it is called the virtual address space. An address within this space is called a virtual address. Corresponding to the virtual address space and virtual addresses are the physical address space and physical addresses. Most of the time, the physical address space possessed by the system is only a subset of the virtual address space. For example, for a 32-bit x86 host with 256MB of memory, its virtual address space range is 0 to 0xFFFFFFFF (4GB), while its physical address space range is 0x00000000 to 0x0FFFFFFF (256MB).

[0028] In a computer system, the program provides the processor with a virtual address. The processor needs to map the virtual address to a physical address in the physical address space in order to perform operations at the corresponding location in memory.

[0029] In order to achieve the mapping from virtual addresses to physical addresses, the computer uses an MMU to implement the corresponding mapping control.

[0030] Specifically, the virtual address space is divided into pages, while the corresponding physical address space is divided into page frames, with page frames being the same size as pages. A mapping relationship between pages and page frames (PTEs) is established and stored in the page table area of ​​memory. The MMU uses the PTEs to implement the mapping from virtual addresses to physical addresses.

[0031] To improve the efficiency of accessing Page Table Entries (PTEs), the Page Table Library (TLB) was introduced. Based on the principle of locality (i.e., when a page table entry is used, it is likely to be used again in the near future), the most likely page table entries to be accessed are placed in the TLB. This ensures that when mapping physical addresses, the corresponding page table entry is first looked up in the TLB. Only when the required page table entry is not found in the TLB is it searched in memory.

[0032] As can be seen from the above introduction, the TLB hit rate directly affects memory access efficiency. Currently, to achieve more efficient TLB utilization and improve the TLB hit rate, ARM provides a continue scheme, which merges a set number of physically contiguous page table entries into a single TLB entry, achieving the effect of "compressing" page table entries. Below is an example of the continue scheme: If there are exactly 8 consecutive page table entries in memory that are also physically contiguous, the continue function can be enabled. After enabling it, only one page table entry needs to be stored in the TLB, reducing the occupied space by 7 / 8. The remaining TLB space can be used to store other PTEs, achieving page table "compression". However, the limitations of the continue scheme are obvious: it requires that the physical addresses of the compressed page table entries be contiguous, and the number of page tables must be a fixed number such as 8 or 16. If there are 7 or 5 PTEs, the continue function cannot be used.

[0033] Example 1: For the issues mentioned above, see [link / reference]. Figure 1 As shown, Figure 1 This application illustrates a page table lookup method provided by an embodiment, including: S101: In response to the received target virtual address, determine whether there is a target page table entry in the TLB that the target virtual address matches.

[0034] In this embodiment, the page table lookup method can be executed by the MMU (Memory Management Unit). The target virtual address can be issued by the processor.

[0035] In practical applications, after the processor obtains a virtual address, it typically needs to translate the virtual address into a physical address. At this point, the processor passes the target virtual address to the MMU (Memory Management Unit). The MMU first searches in the TLB (Track Level Buffer). If a TLB match occurs (i.e., a target page table entry corresponding to the target virtual address exists in the TLB), the physical address of the queried virtual address can be mapped. However, if a TLB miss occurs (i.e., a target page table entry corresponding to the target virtual address does not exist in the TLB), a further search is performed in memory.

[0036] In the embodiments of this application, the processor may be, but is not limited to, a CPU (Central Processing Unit), a GPU, a GPGPU (General-Purpose Computing on Graphics Processing Units), an NPU (Neural Network Processing Unit), an ISP (Image Signal Processor), a DPU (Display Processing Unit), a VPU (Video Processing Unit), a DSP (Digital Signal Processor), etc.

[0037] In this embodiment of the application, the page table entries in the TLB may include a first page table entry.

[0038] The first page table entry includes count information and index information. The count information represents the total number of page table entries in the first contiguous page table group to which the first page table entry belongs, and the index information represents the position of the first page table entry in the first contiguous page table group. The first contiguous page table group is a collection of multiple page table entries that are contiguous in both virtual and physical addresses stored in memory.

[0039] For example, see Figure 2 As shown, Figure 2 The right side shows the PTEs stored contiguously in memory. Each entry includes the virtual address (not shown), physical address pa, total number information, and index information. Figure 2 The right side shows 10 consecutive PTEs with both virtual and physical addresses. These 10 PTEs constitute a first contiguous page table group. Figure 2 The left side shows a first page table entry stored in the TLB. This first page table entry is... Figure 2 One of the first contiguous page table entries on the left can typically be the page table entry that the MMU first accesses from memory in the first contiguous page table group, which is written into the TLB to represent the first page table entry of the entire first contiguous page table group. Figure 2 The example illustrates the case where the 7th PTE is used as the first page table entry written to the TLB. In practical applications, it could also be any other page table entry in the first consecutive page table group.

[0040] In the embodiments of this application, for any first page table entry, the MMU can calculate the virtual address range of the first consecutive page table group to which the first page table entry belongs based on the virtual address of the first page table entry, the number of first page table entries, and the index information.

[0041] For example, the MMU can calculate the starting virtual address of the first contiguous page table group based on the virtual address of the first page table entry, the index information of the first page table entry, and the virtual address size corresponding to a single page table entry; and calculate the ending virtual address of the first contiguous page table group based on the virtual address of the first page table entry, the number and index information of the first page table entries, and the virtual address size corresponding to a single page table entry. The virtual address range of the first contiguous page table group is the range formed by the starting virtual address to the ending virtual address.

[0042] For example, the MMU can calculate the starting virtual address of the first contiguous page table group using the formula: van – index * X; and the ending virtual address of the first contiguous page table group using the formula: van + (total – index) * X. Here, van is the virtual address of the first page table entry, total is the number of first page table entries, index is the index of the first page table entry, and X is the virtual address size corresponding to a single page table entry.

[0043] Here, the index is counted starting from 0. If the index starts counting from 1 or any other value, then the formula van – index * X can be modified to van – (index - I) * X, and the formula van + (total – index) * X can be modified to van + (total – index + I) * X, where I is the starting value of the index. For example, if the index starts counting from 1, the formulas can be modified to van – (index - 1) * X and van + (total – index + 1) * X.

[0044] In the embodiments of this application, when the target virtual address is within the virtual address range of the first consecutive page table group to which the first page table entry belongs, it can be determined that the target virtual address hits the first page table entry.

[0045] S102: If a target page table entry that matches the target virtual address exists in the TLB, and the target page table entry is the first target entry, calculate the target physical address corresponding to the target virtual address based on the target virtual address, the virtual address of the first page table entry, and the physical address.

[0046] Optionally, the MMU can calculate the deviation between the target virtual address and the virtual address of the first page table entry, and then calculate the sum of the physical address of the first page table entry and the deviation to obtain the target physical address. Since the virtual and physical addresses of each page table entry in the first contiguous page table group are consecutive, the deviation between the target virtual address and the virtual address of the first page table entry is equal to the deviation between the target physical address corresponding to the target virtual address and the physical address of the first page table entry. Therefore, by calculating the deviation between the target virtual address and the virtual address of the first page table entry, and then calculating the sum of the physical address of the first page table entry and the deviation, the target physical address can be obtained quickly and accurately.

[0047] For example, with Figure 2 Taking the example shown, if the target virtual address is va, the virtual address of the first page table entry is va7, and the physical address of the first page table entry is pa7, then the deviation between the target virtual address and the virtual address of the first page table entry is equal to va - va7, and the target physical address pa is equal to va - va7 + pa7. Here, va can be less than or greater than va7.

[0048] Optionally, the MMU can also calculate the deviation between the target virtual address and the starting virtual address of the first contiguous page table group. Then, based on the physical address of the first page table entry, the index information of the first page table entry, and the virtual address size corresponding to a single page table entry, it calculates the starting physical address of the first contiguous page table group (the calculation method for the starting physical address is the same as that for the starting virtual address, only the calculation basis is changed from virtual address to physical address). Finally, it calculates the sum of the starting physical address of the first contiguous page table group and the aforementioned deviation to obtain the target physical address. In this way, since the virtual and physical addresses of each page table entry in the first contiguous page table group are contiguous, the deviation between the target virtual address and the starting virtual address of the first contiguous page table group is equal to the deviation between the target physical address corresponding to the target virtual address and the starting physical address of the first contiguous page table group. Therefore, by calculating the deviation between the target virtual address and the starting virtual address of the first contiguous page table group, and calculating the sum of the starting physical address of the first contiguous page table group and the deviation, the target physical address can be obtained quickly and accurately.

[0049] For example, still using Figure 2Taking the example shown, the target virtual address is va, the virtual address of the first page table entry is va7, and the physical address of the first page table entry is pa7. Assume x equals 2M. Then, the deviation between the target virtual address and the virtual address of the first page table entry can be calculated as va – (va7 – index (value 6) * 2M). The starting physical address of the first contiguous page table group is pa7 – index (value 6) * 2M. The target physical address pa is equal to pa7 – index (value 6) * 2M + (va – (va7 – index (value 6) * 2M)).

[0050] Optionally, the MMU can also calculate the deviation between the end virtual address and the target virtual address of the first contiguous page table group, and then calculate the end physical address of the first contiguous page table group based on the physical address of the first page table entry, the index information of the first page table entry, and the virtual address size corresponding to a single page table entry (the calculation method of the end physical address is the same as that of the end virtual address, except that the calculation basis is changed from virtual address to physical address). Finally, the difference between the end physical address of the first contiguous page table group and the deviation is calculated to obtain the target physical address.

[0051] In an optional embodiment of this application, the first page table entry may further include pattern information. The pattern information is used to characterize whether the page table entry to which it belongs is the first page table entry, thereby distinguishing page table entries and reducing calculation errors caused by incorrect identification of page table entry types.

[0052] In some optional embodiments of this application, the method may further include: if no target page table entry for the target virtual address is found in the TLB, searching for the target page table entry corresponding to the target virtual address in memory; and adding the target page table entry to the TLB.

[0053] In this way, for cases where the TLB is not found, the target page table entry is searched in memory and added to the TLB. This ensures that the TLB stores the page table entry that has been most recently searched in memory, which is more in line with the principle of locality (i.e., when a page table entry is used, it may be used again in the near future), thus improving the TLB hit rate.

[0054] Furthermore, in memory, multiple PTEs that are contiguous in both virtual and physical addresses can be stored in memory in a form that includes both number and index information, so that after being added to the TLB, they can directly represent the first contiguous page table group to which they belong.

[0055] In the scheme of this application embodiment, a first page table entry is designed. The first page table entry includes information representing the total number of page table entries in the first contiguous page table group to which the first page table entry belongs, and index information representing the position of the first page table entry in the first contiguous page table group. Thus, based on the virtual address of the first page table entry itself, the number of first page table entries, and the index information, multiple page table entries (i.e., the first contiguous page table group) with contiguous virtual and physical addresses stored in memory can be represented by a single first page table entry. As described in the above implementation scheme, a single first page table entry can be used to determine the virtual address range of the first contiguous page table group composed of multiple page table entries with contiguous virtual and physical addresses, and to determine the physical address corresponding to any virtual address in the first contiguous page table group. In other words, in the scheme of this application, a single first page table entry can represent any number of multiple page table entries with contiguous virtual and physical addresses in memory, achieving the effect of "compressing" the PTE, thereby improving the utilization of the TLB. Furthermore, compared to the traditional continue scheme, the scheme in this application does not have the limitation of merging page table entries, making the scheme more applicable.

[0056] In this first embodiment, for PTEs where the virtual addresses in memory are contiguous but the physical addresses are not, i.e., PTEs that cannot be represented by first page table entries in memory, in one optional embodiment, the traditional PTE form can be used. In this case, if the PTE is hit, the target physical address corresponding to the target virtual address can be directly obtained based on the PTE. In another optional embodiment, the following second embodiment can be used for expression.

[0057] Example 2: For the issues mentioned above, see [link / reference]. Figure 3 As shown, Figure 3 This application illustrates another page table lookup method provided by an embodiment, including: S301: In response to the received target virtual address, determine whether there is a target page table entry in the TLB that the target virtual address matches.

[0058] In this embodiment of the application, page table entries in the TLB may include second page table entries.

[0059] The second page table entry includes location information and m physical addresses. The location information indicates the position of the second page table entry within its corresponding second contiguous page table set. The second contiguous page table set is a collection of m page table entries stored in memory with consecutive virtual addresses. The m physical addresses are the physical addresses of the m page table entries within the second contiguous page table set.

[0060] For example, see Figure 4 As shown, Figure 4 The right side shows the PTEs stored contiguously in memory. Each entry includes the virtual address (not shown), its own physical address pa, location information mod, and the physical addresses of the other m-1 page table entries ( Figure 4 This illustrates the case where m equals 3, and the physical addresses of the other two page table entries are denoted as pre pa and next pa, respectively.

[0061] Figure 4 The right side shows three consecutive PTEs for virtual addresses, which together form a second consecutive page table group. Figure 4 The left side shows a second page table entry stored in the TLB. This second page table entry is... Figure 4 One of the entries in the second contiguous page table group on the left can typically be the page table entry that the MMU first accesses from memory in the second contiguous page table group, which is written into the TLB to represent the second page table entry of the entire second contiguous page table group. Figure 4 The example illustrates the case where the second PTE is used as the second page table entry written to the TLB. In practical applications, it could also be written to other page table entries in the second consecutive page table group.

[0062] In this embodiment of the application, the value of m needs to be determined based on the length of the physical address of a single page table entry and the length of the remaining free bytes in the PTE after deducting the record location information and some other necessary information (such as valid (validity indicator), read and write permissions, cache attributes, its own physical address, etc.).

[0063] For example, the length of the remaining free bytes can be divided by the length of the physical address of a single page table entry, rounded down, and then incremented by 1. This value is denoted as M, and m can be a positive integer less than or equal to M but greater than 1.

[0064] For example, see Figure 5 As shown, Figure 5The diagram illustrates the field structure of a typical Page Table Entrance (PTE) with a page table size of 2MB and a physical address length of 38 bits (in this case, the page size is 21 bits, the lower 21 bits of the physical address represent the page offset, and the PTE only records the higher 17 bits of the physical address PA). Bits 10 to 0 of the PTE typically contain fields for valid, read & write permissions, and cache attributes. Bits 37 to 21 are the field for its own physical address. Free fields include bits 63 to 38 and bits 19 to 11. Bits 13 to 11 can be used to record location information. Bits 63 to 38 and bits 19 to 14 (34 bits in total) can be divided into two groups of 17 bits each, used to record the physical addresses of two other page table entries. Therefore, based on... Figure 5 The PTE shown can record the physical addresses of up to two other page table entries, so the value of m can be 3. Of course, if the PTE has more free bytes, it can record the physical addresses of more other page table entries, and the value of m can be larger.

[0065] In one optional embodiment of this application, the second page table entry may further include pattern information, which is used to characterize whether the page table entry to which it belongs is a second page table entry.

[0066] For example, pattern information can reuse the same bits in the second-page table entry as location information. For instance... Figure 5 As shown, bits 13 to 11 can be used to record both position and pattern information. For example, if the highest bit is 1 and the next two bits are not both 1, it indicates that the current page table entry is the second page table entry, and the value of these 3 bits represents the position information.

[0067] In this embodiment, for any second page table entry, the MMU can calculate the virtual address range of the second consecutive page table group to which the second page table entry belongs based on the location information of the second page table entry and the value of m.

[0068] For example, the MMU can calculate the starting virtual address of the second consecutive page table group based on the virtual address and location information of the second page table entry, and the virtual address size corresponding to a single page table entry; and calculate the ending virtual address of the second consecutive page table group based on the virtual address and location information of the second page table entry, the value of m, and the virtual address size corresponding to a single page table entry. The virtual address range of the second consecutive page table group is the range formed by the starting virtual address to the ending virtual address.

[0069] For example, the MMU can calculate the first virtual address deviation between the virtual address of the second page table entry and the starting virtual address of the second consecutive page table group based on the location information of the second page table entry and the virtual address size corresponding to a single page table entry. Then, it can calculate the difference between the virtual address of the second page table entry and the first virtual address deviation to obtain the starting virtual address of the second consecutive page table group.

[0070] The MMU can calculate the second virtual address deviation between the ending virtual address of the second consecutive page table group and the virtual address of the second page table entry based on m, the position information of the second page table entry, and the virtual address size corresponding to a single page table entry; then, it calculates the sum of the virtual address of the second page table entry and the second virtual address deviation to obtain the ending virtual address of the second consecutive page table group.

[0071] For example, the virtual address range of the second contiguous page table group can be represented as: [vam –(mod&m)*X, vam+(m-mod&m) * X], where: vam represents the virtual address of the second page table entry, mod represents the position information of the second page table entry, & represents the AND operation, and X is the virtual address size corresponding to a single page table entry.

[0072] In the embodiments of this application, when the target virtual address is within the virtual address range of the second consecutive page table group to which the second page table entry belongs, it can be determined that the target virtual address hits the second page table entry.

[0073] S302: If a target page table entry that hits the target virtual address exists in the TLB, and the target page table entry is a second page table entry, determine the target location information corresponding to the target virtual address based on the target virtual address, the virtual address of the second page table entry, and the location information, and obtain the target physical address corresponding to the target location information from the m physical addresses recorded in the second page table entry.

[0074] Optionally, the MMU can calculate the deviation between the target virtual address and the virtual address of the second page table entry. Then, based on this deviation and the size of the virtual address corresponding to a single page table entry, it determines the positional deviation between the target virtual address and the position information of the second page table entry. Finally, based on the position information of the second page table entry and the positional deviation, it determines the target position information corresponding to the target virtual address. Thus, since the virtual addresses of each page table entry in the second consecutive page table group are consecutive, the deviation between the target virtual address and the virtual address of the second page table entry represents the positional deviation between the page table entry and the actual page table entry that the target virtual address should correspond to in the second consecutive page table group. Therefore, based on this virtual address deviation and the size of the virtual address corresponding to a single page table entry, the position of the target virtual address (i.e., the position of the page table entry that the target virtual address should actually correspond to in the second consecutive page table group) and the positional deviation between the second page table entry and the position information of the second page table entry can be determined. Furthermore, based on the position information of the second page table entry and this positional deviation, the target position information corresponding to the target virtual address (i.e., the position of the page table entry that the target virtual address should actually correspond to in the second consecutive page table group) can be quickly and accurately determined.

[0075] For example, the deviation between the target virtual address va and the virtual address vam of the second page table entry is equal to va – vam; the position deviation (denoted as D) is equal to (va – vam) / X, rounded down. For example, if (va – vam) / X equals 0.something, it can be rounded down to 0; if (va – vam) / X equals 1.something, it can be rounded down to 1; if (va – vam) / X equals negative 0.something, it can be rounded down to -1; if (va – vam) / X equals negative 1.something, it can be rounded down to -2. The target position information is equal to (mod & m) + D.

[0076] Optionally, the MMU can also determine the starting virtual address of the second consecutive page table group based on the virtual address and location information of the second page table entry, as well as the virtual address size corresponding to a single page table entry. Then, it calculates the deviation between the target virtual address and the starting virtual address, and finally determines the target location information corresponding to the target virtual address based on this deviation and the virtual address size corresponding to a single page table entry. In this way, since the virtual addresses of each page table entry in the second consecutive page table group are consecutive, the deviation between the target virtual address and the starting virtual address of the second consecutive page table group represents the positional deviation between the page table entry that the target virtual address should actually correspond to in the second consecutive page table group and the first page table entry in the second consecutive page table group. Therefore, based on this virtual address deviation and the virtual address size corresponding to a single page table entry, the target location information corresponding to the target virtual address (i.e., the position of the page table entry that the target virtual address should actually correspond to in the second consecutive page table group) can be determined quickly and accurately.

[0077] For example, the target location information can be equal to (va – (vam – (mod&m) *X) / X rounded down. For instance, if (va – (vam – (mod&m) *X) / X equals 0.something, it can be rounded down to 0, indicating that the target virtual address should actually correspond to the first page table entry in the second consecutive page table group. If (va – (vam – (mod&m) *X) / X equals 1.something, it can be rounded down to 1, indicating that the target virtual address should actually correspond to the second page table entry in the second consecutive page table group.

[0078] Alternatively, you can round up (va – (vam – (mod&m) *X) / X. For example, if (va – (vam – (mod&m) *X) / X equals 0.something, then rounding up to 1 indicates that the actual page table entry corresponding to the target virtual address in the second contiguous page table group is the first page table entry in the second contiguous page table group. If (va – (vam – (mod&m) *X) / X equals 1.something, then rounding up to 2 indicates that the actual page table entry corresponding to the target virtual address in the second contiguous page table group is the second page table entry in the second contiguous page table group.

[0079] Optionally, the MMU can also determine the ending virtual address of the second consecutive page table group based on the virtual address and location information of the second page table entry, the value of m, and the virtual address size corresponding to a single page table entry. Then, it calculates the deviation between the target virtual address and the ending virtual address, and finally determines the target location information corresponding to the target virtual address based on this deviation and the virtual address size corresponding to a single page table entry. The calculation method in this case is similar to that described above and will not be repeated here.

[0080] In some optional embodiments of this application, if the target virtual address is exactly the virtual address of any page table entry in the second consecutive page table group, then the target physical address corresponding to the target location information obtained from the m physical addresses recorded in the second page table entry is the actual physical address corresponding to the target virtual address.

[0081] However, if the target virtual address is not exactly the virtual address of any page table entry in the second consecutive page table group, but falls within the virtual address range of the second consecutive page table group, then since the m physical addresses recorded in the second page table entry are actually the starting physical addresses corresponding to the starting addresses of the virtual addresses of each page table entry in the second consecutive page table group, we can further calculate va – van + pan to obtain the physical address actually corresponding to the target virtual address. Here, va is the target virtual address, van is the virtual address (starting address) of the page table entry that the determined target virtual address should actually correspond to in the second consecutive page table group, and pan is the physical address of the page table entry that the target virtual address should actually correspond to among the m physical addresses recorded in the second page table.

[0082] In some optional embodiments of this application, the method may further include: if no target page table entry for the target virtual address is found in the TLB, searching for the target page table entry corresponding to the target virtual address in memory; and adding the target page table entry to the TLB.

[0083] In this way, for cases where the TLB is not found, the target page table entry is searched in memory and added to the TLB. This ensures that the TLB stores the page table entry that has been most recently searched in memory, which is more in line with the principle of locality (i.e., when a page table entry is used, it may be used again in the near future), thus improving the TLB hit rate.

[0084] Furthermore, in memory, multiple PTEs that are contiguous in both virtual and physical addresses can be stored in memory in a form that includes location information and m physical addresses, so that after being added to the TLB, they can directly represent the second contiguous page table group to which they belong.

[0085] In the scheme of this application embodiment, a second page table entry is designed. The second page table entry includes location information representing the position of the second page table entry within a second contiguous page table group and m physical addresses. The second contiguous page table group is a set of m page table entries with consecutive virtual addresses stored in memory, and the m physical addresses recorded in the second page table entry are the physical addresses of the m page table entries within the second contiguous page table group. Thus, for m consecutive page table entries stored in memory (page table entries stored consecutively in memory are necessarily contiguous in virtual address), regardless of whether their physical addresses are contiguous, they can all be represented by a single second page table entry. Specifically, the virtual address range of the second consecutive page table group can be determined by the virtual address of the second page table entry, its location information (indicating which page table entry in the second consecutive page table group it is), and the value of m (indicating the total number of page table entries in the second consecutive page table group). Furthermore, the target location information corresponding to the target virtual address (i.e., the position of the page table entry actually corresponding to the target virtual address in the second consecutive page table group) can be determined based on the target virtual address, the virtual address of the second page table entry, and its location information. Then, the target physical address corresponding to the target location information can be determined from the m physical addresses recorded in the second page table entry based on the target location information. In other words, in the above scheme of this application, the representation of m consecutive page table entries stored in memory can be achieved through a single second page table entry, effectively "compressing" the PTE and thus improving the utilization of the TLB. Furthermore, compared to the traditional continue scheme, the above-mentioned scheme in this application does not have the restriction of physical address contiguousness, and the scheme has greater applicability.

[0086] It can also be understood that the physical addresses of the second page table entries are not required to be contiguous. Therefore, theoretically, all page table entries stored in memory can be "compressed" through the second page table entries, making it more applicable.

[0087] Example 3: In this embodiment, the schemes of Embodiment 1 and Embodiment 2 are combined. For each PTE in memory, if there are multiple PTEs with both virtual and physical addresses being contiguous, these PTEs are stored in the form of first page table entries. For other PTEs with contiguous virtual addresses but non-contiguous physical addresses, they are stored in the form of second page table entries.

[0088] Thus, the first page table entry has no limit on the number of page table entries that can be "compressed," while the second page table entry must be a single page table entry stored in the TLB that is "compressed" from m page table entries in memory. The "compression" rate of the first page table entry is often higher. Theoretically, compressing page table entries with contiguous virtual and physical addresses in memory using the first page table entry, and compressing page table entries with contiguous virtual addresses but non-contiguous physical addresses using the second page table entry, can achieve a higher compression rate while compressing all page table entries stored in memory. Therefore, by using both the first and second page table entries, the utilization rate of the TLB can be further improved.

[0089] To facilitate understanding of the solutions in the embodiments of this application, a specific example solution is provided below to illustrate the solutions in the embodiments of this application: Assuming a page table size of 2MB and device memory not exceeding 256GB, the PTE format is as follows: Figure 6 As shown: The blue portion represents the free fields of the PTE. In this embodiment, these free bits are used to "compress" page table entries. Bits 13 to 11 are the mode fields. 000 indicates that compression mode is not enabled (i.e., a traditional page table entry), 111 is used for scenarios where pa (physical address) is contiguous (indicating that the page table entry is the first page table entry), and 1xx is used for scenarios where pa is not contiguous (indicating that the page table entry is the second page table entry). They have different compression methods and compression ratios.

[0090] See Figure 7. Figure 7 The PTE format is for the first page of table entries. The high 26 bits are divided into two groups of 13 bits each, which are used to record the index information and the total information of the current PTE.

[0091] Combination Figure 2 As shown, Figure 2 The 10 PTEs in the right-hand memory only require one entry in the TLB. When the TLB performs address translation, it first checks if there is a hit in the TLB. The rule is: calculate the virtual address range that the PTE entry can cover based on va7, pa7, total, and index: [va7 – index * 2M, va7 + (total – index) * 2M] If the current target virtual address va to be translated falls within this range, it is a hit. The corresponding target physical address pa is calculated as follows: pa = pa7 – index * 2M + (va – (va7 – index * 2M)).

[0092] As can be seen, by introducing total & index, it is possible to "compress" any number of PTEs where both virtual and physical addresses are contiguous.

[0093] See Figure 5. Figure 5 This is the PTE format for the second page table entry case, where bits [13~11] have values ​​of 1xx. Bit 13=1 indicates that non-contiguous mode is enabled. When enabled, three PTE entries are grouped together. Bits 12~11 are used to indicate which entry in the second contiguous page table group the current PTE belongs to. Bits 63~38 and 19~14, a total of 34 bits, are used to record the pa address corresponding to the previous and next PTEs, thereby achieving PTE compression.

[0094] Combination Figure 4 As shown, the three PTEs stored contiguously in memory form a second contiguous page table group. Assuming the PTE stored in the TLB is the second entry in this second contiguous page table group, the virtual address range covered can be derived using va3 and mod=5: [va3 –(mod&3)*2M, va3 + (3 –mod&3) *2M] Based on pa3, pre pa, next pa, and mod=5, we can deduce that the three PTEs correspond to the second consecutive page table group (pa1, pa3, pa8) (mod=5 indicates that the current PTE is the second item in the second consecutive page table group, so pre pa1 means the first item is pa1, and next pa8 means the third item is pa8). If the target virtual address va to be translated happens to fall within this range, then the calculation process for the target physical address pa corresponding to va is as follows: Step 1: Calculate the index of va in the group: index = (va –(va3 –(5&3) * 2M)) / 2M.

[0095] It can be understood that 5&3 is equivalent to 101&011, which is equal to 001, or 1, indicating that the second page table entry is the second page table entry in the second consecutive page table group.

[0096] Step 2: Based on the index Figure 5 Find the corresponding pan in the PTE shown.

[0097] At this point, we can further obtain the actual physical address corresponding to the target virtual address va based on va – van+pan.

[0098] As can be seen from the above process, in non-continuous scenarios, three PTEs only need to occupy one entry in the TLB, saving 2 / 3 of the space.

[0099] Based on the same inventive concept, this application also provides an electronic device, see [link to relevant documentation]. Figure 8 As shown, it includes a processor, MMU, memory, and communication bus.

[0100] The communication bus is used to enable communication between the processor, MMU, and memory.

[0101] Page table entries are stored in memory.

[0102] When the processor receives the target virtual address from the program, it sends the target virtual address to the MMU.

[0103] The MMU includes a TLB, which can be used to execute the page table lookup method described above in the embodiments of this application.

[0104] It should be understood that since the TLB is a high-speed cache within the MMU, storing page table entries corresponding to recently accessed virtual addresses, virtual addresses first reach the TLB, where a lookup of the corresponding page table entry is performed. Only when a TLB miss occurs will the MMU perform a lookup in memory.

[0105] After the MMU obtains the physical address corresponding to the virtual address, it can send the converted physical address to the processor's external address pin, thus facilitating the processor's access to the physical address.

[0106] It should be understood that the above-described method of this application can be implemented using existing MMU circuitry.

[0107] It should be noted that, Figure 8 The structure shown is for illustrative purposes only; the electronic device may also include components that are more advanced than those shown. Figure 8 The more or fewer components shown, or having the same Figure 8 The different configurations shown can include components such as a battery, display screen, and keyboard.

[0108] Furthermore, in the embodiments of this application, the processor and MMU can be integrated into a single processor chip.

[0109] The electronic device described in this application embodiment can be any electronic device with processor addressing function, such as a mobile terminal such as a mobile phone or tablet computer, a fixed terminal such as a desktop computer, or a non-terminal electronic device such as a server.

[0110] In the embodiments provided in this application, it should be understood that the disclosed methods can be implemented in other ways.

[0111] Furthermore, the units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0112] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.

[0113] In this article, "multiple" refers to two or more.

[0114] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A page table lookup method, characterized in that, include: In response to a received target virtual address, it is determined whether a target page table entry matching the target virtual address exists in the TLB; wherein, the page table entry in the TLB includes a second page table entry; the second page table entry includes location information and m physical addresses; the location information represents the position of the second page table entry in its respective second contiguous page table group; the second contiguous page table group is a set of m consecutive page table entries stored in memory; the m physical addresses are the physical addresses of the m page table entries in the second contiguous page table group; wherein, when the target virtual address is within the virtual address range of the second contiguous page table group to which the second page table entry belongs, it is determined that the target virtual address matches the second page table entry; the virtual address range of the second contiguous page table group is calculated based on the virtual address of the second page table entry, the location information of the second page table entry, and the value of m; If a target page table entry that matches the target virtual address exists in the TLB, and the target page table entry is the second page table entry, the target location information corresponding to the target virtual address is determined based on the target virtual address, the virtual address of the second page table entry, and the location information. Then, the target physical address corresponding to the target location information is obtained from the m physical addresses recorded in the second page table entry.

2. The page table lookup method as described in claim 1, characterized in that, The virtual address range of the second contiguous page table group is calculated in the following manner: Based on the virtual address and location information of the second page table entry, and the virtual address size corresponding to a single page table entry, the starting virtual address of the second consecutive page table group is calculated. Based on the virtual address and location information of the second page table entry, the value of m, and the virtual address size corresponding to a single page table entry, the ending virtual address of the second consecutive page table group is calculated. The virtual address range of the second consecutive page table group is the range formed by the starting virtual address to the ending virtual address.

3. The page table lookup method as described in claim 2, characterized in that, Based on the virtual address and location information of the second page table entry, and the virtual address size corresponding to a single page table entry, the starting virtual address of the second contiguous page table group is calculated, including: Based on the position information of the second page table entry and the virtual address size corresponding to the single page table entry, the first virtual address deviation between the virtual address of the second page table entry and the starting virtual address of the second consecutive page table group is calculated. The difference between the virtual address of the second page table entry and the deviation of the first virtual address is calculated to obtain the starting virtual address of the second consecutive page table group.

4. The page table lookup method as described in claim 2, characterized in that, Based on the virtual address and location information of the second page table entry, the value of m, and the virtual address size corresponding to a single page table entry, the ending virtual address of the second consecutive page table group is calculated, including: Based on the position information of m, the second page table entry, and the virtual address size corresponding to the single page table entry, the second virtual address deviation between the end virtual address of the second consecutive page table group and the virtual address of the second page table entry is calculated. The sum of the virtual address of the second page table entry and the second virtual address offset is calculated to obtain the ending virtual address of the second consecutive page table group.

5. The page table lookup method as described in claim 2, characterized in that, The target location information corresponding to the target virtual address is determined based on the target virtual address, the virtual address of the second page table entry, and the location information, including: Calculate the deviation between the target virtual address and the virtual address of the second page table entry; The positional deviation between the position of the target virtual address and the position information of the second page table entry is determined based on the deviation and the virtual address size corresponding to a single page table entry. The target location information corresponding to the target virtual address is determined based on the location information of the second page table entry and the location deviation.

6. The page table lookup method as described in claim 2, characterized in that, The target location information corresponding to the target virtual address is determined based on the target virtual address, the virtual address of the second page table entry, and the location information, including: The starting virtual address of the second consecutive page table group is determined based on the virtual address of the second page table entry, the location information, and the virtual address size corresponding to a single page table entry. Calculate the deviation between the target virtual address and the starting virtual address; The target location information corresponding to the target virtual address is determined based on the deviation and the virtual address size corresponding to a single page table entry.

7. The page table lookup method as described in claim 1, characterized in that, The second page table entry contains pattern information; the pattern information is used to identify that the page table entry belongs to the second page table entry, and the pattern information and the position information reuse the same bits in the second page table entry.

8. The page table lookup method according to any one of claims 1-7, characterized in that, The method further includes: If no target page table entry matching the target virtual address is found in the TLB, the target page table entry corresponding to the target virtual address is searched in memory; wherein, if the target page table entry is a second page table entry, the target page table entry includes location information and m physical addresses; Add the target page table entry to the TLB.

9. A page table lookup device, characterized in that, include: The second lookup module is configured to, in response to a received target virtual address, determine whether a target page table entry matching the target virtual address exists in the TLB; wherein, the page table entry in the TLB includes a second page table entry; the second page table entry includes location information and m physical addresses; the location information represents the position of the second page table entry in its respective second contiguous page table group; the second contiguous page table group is a set of m consecutive page table entries stored in memory; the m physical addresses are the physical addresses of the m page table entries in the second contiguous page table group; wherein, when the target virtual address is within the virtual address range of the second contiguous page table group to which the second page table entry belongs, it is determined that the target virtual address matches the second page table entry; the virtual address range of the second contiguous page table group is calculated based on the virtual address of the second page table entry, the location information of the second page table entry, and the value of m; The second conversion module is used to determine the target location information corresponding to the target virtual address based on the target virtual address, the virtual address of the second page table entry, and the location information when there is a target page table entry in the TLB that matches the target virtual address and the target page table entry is the second page table entry, and to obtain the target physical address corresponding to the target location information from the m physical addresses recorded in the second page table entry.

10. An electronic device, characterized in that, include: Processor, memory management unit, memory, and communication bus; The communication bus is used to enable communication between the processor, the memory management unit, and the memory. The memory contains page table entries; The processor is used to send the target virtual address to the memory management unit; The memory management unit includes a TLB for performing the page table lookup method as described in any one of claims 1-8.

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