Communication system and communication method

Abstract

The invention discloses a communication system and a communication method, and the method comprises the steps: enabling a first processor to transmit a corresponding data reading signal to a second processor when the current write-in data of the first processor meets a preset condition; and the second processor obtains the data reading signal and obtains the write-in starting address and the write-in ending address corresponding to the data reading signal from the first processor, so that data from the write-in starting address of the memory to the write-in ending address of the memory can be read. After the first processor sends the data reading signal to the second processor, the first processor continues to write the data into the memory and continues to execute the data writing step, so that the second processor can read the data while the first processor writes the data. The double processors can operate data reading and writing of different addresses of the same memory at the same time so as to carry out high-speed data transmission between the double processors.

Description

Technical Field

[0001] This invention relates to data communication, and more specifically to a communication system and communication method. Background Technology

[0002] In the field of data communication, data transmission between two independent CPUs is typically achieved through communication bus protocols. However, existing communication bus protocols cannot handle large volumes of transmitted data quickly and efficiently.

[0003] Existing shared memory transfer technologies suffer from full-duplex communication defects. They typically employ an exclusive access mechanism, where one CPU must pause its write operation while another CPU is performing a data read operation, leading to interruptions in data transmission and the transmission process. In high-speed, large-volume data transmission scenarios, problems such as insufficient transmission rate, excessively long additional time consumption, and interrupted data interaction are common, resulting in a high risk of data loss and an inability to guarantee the integrity and real-time performance of transmitted data. Summary of the Invention

[0004] The main technical problem solved by this invention is the inability of existing dual-CPU systems to quickly transfer data.

[0005] According to a first aspect, one embodiment provides a communication system, including a first processor, a second processor, and a memory;

[0006] The memory is used to store data, and the memory includes multiple addresses for storing data; the memory has a storage start address and a storage end address;

[0007] The first processor is used to write data into the memory;

[0008] The second processor is used to read data written by the first processor from the memory;

[0009] The first processor is capable of performing the data writing step: when the first processor starts writing data into the memory, it obtains the write start address to begin writing data;

[0010] Determine whether the currently written data meets the preset conditions. If so, the first processor obtains the end address of the current written data and sends the corresponding data read signal to the second processor.

[0011] The second processor acquires the data read signal and obtains the write start address and write end address corresponding to the data read signal from the first processor, so as to be able to read data from the write start address to the write end address of the memory;

[0012] After the first processor sends the data read signal to the second processor, it continues to write data into the memory and continues to execute the data writing step, so that the second processor can read data while the first processor is writing data.

[0013] In a further embodiment of the present invention, when the first processor performs the data writing step, after writing from the storage end address, the first processor is able to rewrite data from the storage start address;

[0014] After the second processor reads data from the end address of the storage, the second processor can read data again from the start address of the storage.

[0015] In a further embodiment of the present invention, the communication system further includes:

[0016] When the first processor starts writing data from the write start address of the memory, it begins to record the amount of data written by the first processor and / or the time of data writing;

[0017] When the amount of data and / or the time for writing data is greater than a preset threshold, it is determined that the data currently written by the first processor meets the preset conditions. The first processor obtains the end address of the current data write and sends the corresponding data read signal to the second processor. The value of the amount of data written by the first processor and / or the time for writing data recorded before this is reset to zero.

[0018] In a further provision of the present invention, when the data currently written by the first processor meets a preset condition, and the second processor has not completed reading the data from the start address to the end address of the memory write, the first processor is prohibited from sending the data read signal to the second processor until the second processor completes reading the data from the start address to the end address of the memory write.

[0019] In a further provision of the present invention, when the address of the data currently being written by the first processor in the memory is within the range from the start address to the end address of the memory write as currently read by the second processor, the first processor stops writing data to the memory.

[0020] According to a second aspect, one embodiment provides a communication method applied to a communication system, the communication system including a first processor, a second processor, and a memory, comprising:

[0021] The first processor performs the data writing step: when the first processor starts writing data into the memory, the first processor obtains the write start address to start writing data;

[0022] The first processor determines whether the currently written data meets the preset conditions. If so, the first processor obtains the write end address of the currently written data and sends the corresponding data read signal to the second processor, so that the second processor obtains the data read signal, as well as the write start address and the write end address corresponding to the data read signal, so that the second processor can read the data from the write start address to the write end address of the memory.

[0023] After the first processor sends the data read signal to the second processor, it continues to write data into the memory and continues to execute the data writing step, so that the second processor can read data while the first processor is writing data.

[0024] In a further embodiment of the present invention, the memory has a storage start address and a storage end address; when the first processor performs the data writing step, after writing from the storage end address, the first processor can rewrite data from the storage start address, so that after the second processor reads data from the storage end address, it can reread data from the storage start address.

[0025] In a further embodiment of the present invention, the first processor determines whether the currently written data meets a preset condition, including:

[0026] When the first processor starts writing data from the write start address of the memory, the first processor starts recording the amount of data written by the first processor and / or the time of writing the data;

[0027] When the amount of data and / or the time for writing data is greater than a preset threshold, the first processor determines that the data currently written by the first processor meets the preset conditions. The first processor obtains the end address of the current data write and sends the corresponding data read signal to the second processor. The value of the amount of data written by the first processor and / or the time for writing data recorded before this is reset to zero.

[0028] In a further embodiment of the present invention, when the data currently written by the first processor meets the preset conditions, and the second processor has not completed reading the data from the start address to the end address of the memory write, the first processor will not send the data read signal to the second processor until the second processor completes reading the data from the start address to the end address of the memory write.

[0029] In a further provision of the present invention, when the address of the data currently being written by the first processor in the memory is within the range from the start address to the end address of the memory write as currently read by the second processor, the first processor stops writing data to the memory.

[0030] This application discloses a communication system and method. When the current write data of the first processor meets preset conditions, the first processor sends a corresponding data read signal to the second processor. The second processor obtains the data read signal and retrieves the write start address and write end address corresponding to the data read signal from the first processor, enabling it to read data from the write start address to the write end address of the memory. After sending the data read signal to the second processor, the first processor continues to write data to the memory and continues to execute the data writing steps, so that the second processor can read data while the first processor is writing data. The two processors can simultaneously operate on data read and write operations at different addresses of the same memory to achieve high-speed data transmission between the two processors. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the communication system in an embodiment of the present invention;

[0032] Figure 2 This is a flowchart of the communication method in an embodiment of the present invention;

[0033] Figure 3 This is a schematic diagram of the communication method in an embodiment of the present invention. Detailed Implementation

[0034] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of this application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to this application are not shown or described in the specification. This is to avoid obscuring the core parts of this application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0035] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0036] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0037] In the field of data communication, data transmission between two independent CPUs is typically achieved through communication bus protocols. However, existing communication bus protocols cannot handle large volumes of transmitted data quickly and efficiently.

[0038] In practical applications, existing shared memory transmission technology suffers from full-duplex communication defects. It typically employs an exclusive access mechanism, where one CPU must pause its write operation while another CPU is performing a data read operation, resulting in interruptions to data transmission and the transmission process. In high-speed, large-volume data transmission scenarios, problems such as insufficient transmission rate, excessively long additional time consumption, and interrupted data interaction are common, leading to a high risk of data loss and failing to guarantee the integrity and real-time performance of transmitted data.

[0039] Based on this discovery, the present invention discloses a communication system and method. When the current write data of the first processor meets preset conditions, the first processor sends a corresponding data read signal to the second processor. The second processor obtains the data read signal and retrieves the write start address and write end address corresponding to the data read signal from the first processor, so as to be able to read data from the write start address to the write end address of the memory. After sending the data read signal to the second processor, the first processor continues to write data to the memory and continues to execute the data writing steps, so that the second processor can read data while the first processor is writing data. The two processors can simultaneously operate on data read and write operations for different addresses of the same memory to achieve high-speed data transmission between the two processors.

[0040] The concept of the present invention will be explained in detail below through specific embodiments.

[0041] In some embodiments, please refer to Figure 1 , Figure 1 This is a schematic diagram of the communication system in an embodiment of the present invention. The communication system includes a first processor 100, a second processor 300, and a memory 200.

[0042] The memory 200 is used to store data. The memory 200 includes multiple addresses for storing data and has a storage start address and a storage end address. In some embodiments, the memory 200 serves as a data transfer buffer in shared memory, providing data write interfaces and data read interfaces, and supporting concurrent access by multiple processors, thus solving the problem of insufficient traditional transmission bandwidth.

[0043] The first processor 100 is used to write data into the memory 200. In some embodiments, the first processor 100 is a field-programmable gate array (FPGA), which consists of a large number of programmable logic units, registers, and high-speed interconnect resources, supporting parallel computing. FPGAs have no instruction execution latency, making them suitable for scenarios with extremely high real-time requirements. FPGAs can write data into the memory 200 without latency.

[0044] The second processor 300 is used to read data written by the first processor 100 from the memory 200. In some embodiments, the second processor 300 is a microcontroller unit, which is a microcomputer integrating a processor core and can independently read data from the memory 200.

[0045] In some embodiments, please refer to Figure 2 , Figure 2This is a flowchart of a communication method in an embodiment of the present invention. The communication method is applied to a communication system, which includes a first processor 100, a second processor 300, and a memory 200. The communication method includes steps S10-S40.

[0046] Step S10: Data writing step.

[0047] When the first processor 100 begins writing data to the memory 200, the first processor 100 obtains the write start address. In some embodiments, the first processor 100 typically starts writing data from the memory start address, such that the write start address obtained by the first processor 100 is the memory start address.

[0048] In some embodiments, when the first processor 100 performs the data writing step, after writing from the end address of storage, the first processor 100 is able to rewrite data from the start address of storage.

[0049] Step S20: Determine whether the currently written data meets the preset conditions.

[0050] The first processor 100 determines whether the currently written data meets the preset conditions. If so, the first processor 100 obtains the end address of the current written data and sends the corresponding data read signal to the second processor 300.

[0051] In some embodiments, when the first processor 100 starts writing data from the write start address of the memory 200, it begins to record the amount of data written by the first processor 100 and / or the time of the data being written.

[0052] When the amount of data and / or the time for writing data is greater than a preset threshold, it is determined that the data currently written by the first processor 100 meets the preset conditions. The first processor 100 obtains the end address of the current data write and sends the corresponding data read signal to the second processor 300. The value of the amount of data written by the first processor 100 and / or the time for writing data recorded before this is reset to zero.

[0053] If the first processor 100 writes data too quickly, causing the previously recorded data quantity and / or writing time of the first processor 100 to be reset to zero, the first processor 100 can still meet the preset conditions before the second processor 300 completes reading the data. In this case, the first processor 100 suspends sending the corresponding data read signal to the second processor 300 until the second processor 300 completes reading the data from the start address to the end address of the write operation in the memory 200. The specific judgment process is as follows: In some embodiments, when the first processor 100 currently writes data that meets the preset conditions, and the second processor 300 has not completed reading the data from the start address to the end address of the write operation in the memory 200, the first processor 100 is prohibited from sending the data read signal to the second processor 300 until the second processor 300 completes reading the data from the start address to the end address of the write operation in the memory 200.

[0054] Step S30: The second processor 300 reads the data from the write start address to the write end address of the memory 200.

[0055] The second processor 300 acquires the data read signal and obtains the write start address and write end address corresponding to the data read signal from the first processor 100, so as to be able to read the data from the write start address to the write end address of the memory 200.

[0056] In some embodiments, when the second processor 300 completes reading data from the start address to the end address of the write operation of the memory 200, it can send a data read signal recovery signal to the first processor 100, so that the first processor 100 can send a data read signal to the second processor 300 immediately after the second processor 300 completes reading data from the start address to the end address of the write operation of the memory 200.

[0057] In some embodiments, after the second processor 300 reads data from the end address of storage, the second processor 300 is able to read data again from the start address of storage.

[0058] Step S40: After the first processor 100 sends a data read signal to the second processor 300, it continues to write data into the memory 200 and continues to execute the data writing step.

[0059] After sending a data read signal to the second processor 300, the first processor 100 continues to write data into the memory 200 and continues to execute step S10, the data writing step, so that the second processor 300 can read data while the first processor 100 is writing data. The two processors can simultaneously perform data read and write operations on different addresses of the same memory 200 to achieve high-speed data transfer between them.

[0060] If the first processor 100 writes data too quickly, such that the address of the data currently being written by the first processor 100 in memory 200 falls within the range from the start address to the end address of the write operation in memory 200 currently being read by the second processor 300, the first processor 100 will stop writing data to memory 200. This occurs because after writing from the end address, the first processor 100 can rewrite data from the start address; similarly, after reading data from the end address, the second processor 300 can reread data from the start address. If the first processor 100 writes too quickly, the address of the data being rewritten from the start address may overlap with the address of the data being processed by the second processor 300, causing the new data written by the first processor 100 to overwrite the previously written data, resulting in the second processor 300 reading incorrect data. Therefore, when the address of the data currently written by the first processor 100 in the memory 200 is within the range from the start address to the end address of the write operation in the memory 200 currently read by the second processor 300, the first processor 100 stops writing data to the memory 200 and reports a warning that the second processor 300 is reading data too slowly under the current conditions, and the configuration of the second processor 300 needs to be adjusted.

[0061] In practical applications, the first processor 100 and the second processor 300 can repeatedly complete data reading and writing through steps S10-S40. After sending a data read signal to the second processor 300, the first processor 100 continues to write data into the memory 200 and continues to execute the data writing step, so that the second processor 300 can read data while the first processor 100 is writing data. The two processors can simultaneously operate on data reading and writing to different addresses of the same memory 200 to achieve high-speed data transmission between the two processors.

[0062] In some embodiments, please refer to Figure 3 , Figure 3This is a schematic diagram of the communication method in an embodiment of the present invention. The FPGA is a field-programmable gate array, which is equivalent to a processor. MCU-B corresponds to the first processor 100, and MCU-A is a microcontroller unit corresponding to the second processor 300. A block of memory, called Mdma, is allocated in the memory that the MCU and FPGA can access for fast data acquisition and transmission. It corresponds to memory 200 and has a storage start address MS_addr and a storage end address ME_addr.

[0063] During the data writing process, when the FPGA begins writing data to Mdma, it obtains the write start address VS_addr. As the FPGA starts writing data from the write start address on Mdma, it begins recording the amount of data written and / or the writing time. When the amount of data and / or the writing time exceed a preset threshold, it is determined that the current data written by the FPGA meets the preset conditions. The FPGA then obtains the write end address VE_addr and sends the corresponding data read signal to the MCU, resetting the previously recorded values ​​of the amount of data written and / or the writing time to zero.

[0064] The MCU acquires a data read signal and obtains the corresponding write start address VS_addr and write end address VE_addr from the FPGA. This allows it to read data from the write start address to the write end address of MDMA. The MCU then sends a data read signal recovery signal to the FPGA, enabling the FPGA to send a new data read signal to the MCU. After sending the data read signal to the MCU, the FPGA continues writing data to MDMA and executes the data writing steps, allowing the MCU to read data while the FPGA is writing. Through cyclic filling and reading / writing data to MDMA, circular data transfer within the MDMA shared memory is achieved.

[0065] In this embodiment, when the FPGA performs the data writing step, after writing from the end address, the FPGA can rewrite data from the start address. Similarly, after the MCU reads data from the end address, the MCU can reread data from the start address. If the FPGA's current data writing meets preset conditions, and the MCU has not completed reading the data from the start address to the end address of the MDMA write operation, the FPGA is prohibited from sending a data read signal to the MCU until the MCU completes reading the data from the start address to the end address of the MDMA write operation. If the address of the data currently written by the FPGA in the MDMA is within the range of the start address to the end address of the MDMA write operation currently read by the MCU, the FPGA stops writing data to the MDMA.

[0066] This invention discloses a communication system and method. When the current write data of the first processor 100 meets preset conditions, the first processor 100 sends a corresponding data read signal to the second processor 300. The second processor 300 obtains the data read signal and retrieves the write start address and write end address corresponding to the data read signal from the first processor 100, enabling it to read data from the write start address to the write end address of the memory 200. After sending the data read signal to the second processor 300, the first processor 100 continues to write data to the memory 200 and continues to execute the data writing steps, so that the second processor 300 can read data while the first processor 100 is writing data. The two processors can simultaneously operate on data read and write operations at different addresses of the same memory 200 to perform high-speed data transmission between the two processors.

[0067] The above examples illustrate the present invention only to aid in understanding it and are not intended to limit the scope of the invention. Those skilled in the art can make various simple deductions, modifications, or substitutions based on the principles of this invention.

Claims

1. A communication system, characterized in that, Includes a first processor, a second processor, and memory; The memory is used to store data, and the memory includes multiple addresses for storing data; the memory has a storage start address and a storage end address; The first processor is used to write data into the memory; The second processor is used to read data written by the first processor from the memory; The first processor is capable of performing the data writing step: when the first processor starts writing data into the memory, it obtains the write start address to begin writing data; Determine whether the currently written data meets the preset conditions. If so, the first processor obtains the end address of the current written data and sends the corresponding data read signal to the second processor. The second processor acquires the data read signal and obtains the write start address and write end address corresponding to the data read signal from the first processor, so as to be able to read data from the write start address to the write end address of the memory; After the first processor sends the data read signal to the second processor, it continues to write data into the memory and continues to execute the data writing step, so that the second processor can read data while the first processor is writing data.

2. The communication system as described in claim 1, characterized in that, When the first processor performs the data writing step, after writing from the storage end address, the first processor can rewrite data from the storage start address; After the second processor reads data from the end address of the storage, the second processor can read data again from the start address of the storage.

3. The communication system as described in claim 1, characterized in that, Also includes: When the first processor starts writing data from the write start address of the memory, it begins to record the amount of data written by the first processor and / or the time of data writing; When the amount of data and / or the time for writing data is greater than a preset threshold, it is determined that the data currently written by the first processor meets the preset conditions. The first processor obtains the end address of the current data write and sends the corresponding data read signal to the second processor. The value of the amount of data written by the first processor and / or the time for writing data recorded before this is reset to zero.

4. The communication system as described in claim 1, characterized in that, If the data currently written by the first processor meets the preset conditions, and the second processor has not completed reading the data from the start address to the end address of the memory, then the first processor is prohibited from sending the data read signal to the second processor until the second processor completes reading the data from the start address to the end address of the memory.

5. The communication system as described in claim 2, characterized in that, When the address of the data currently being written by the first processor in the memory is within the range from the start address to the end address of the memory write as currently read by the second processor, the first processor stops writing data to the memory.

6. A communication method applied to a communication system, the communication system comprising a first processor, a second processor, and a memory, characterized in that, include: The first processor performs the data writing step: when the first processor starts writing data into the memory, the first processor obtains the write start address to start writing data; The first processor determines whether the currently written data meets the preset conditions. If so, the first processor obtains the write end address of the currently written data and sends the corresponding data read signal to the second processor, so that the second processor obtains the data read signal, as well as the write start address and the write end address corresponding to the data read signal, so that the second processor can read the data from the write start address to the write end address of the memory. After the first processor sends the data read signal to the second processor, it continues to write data into the memory and continues to execute the data writing step, so that the second processor can read data while the first processor is writing data.

7. The communication method as described in claim 6, characterized in that, The memory has a storage start address and a storage end address; When the first processor performs the data writing step, after writing from the storage end address, the first processor can rewrite data from the storage start address, so that after the second processor reads data from the storage end address, it can reread data from the storage start address.

8. The communication method as described in claim 6, characterized in that, The first processor determines whether the currently written data meets preset conditions, including: When the first processor starts writing data from the write start address of the memory, the first processor starts recording the amount of data written by the first processor and / or the time of writing the data; When the amount of data and / or the time for writing data is greater than a preset threshold, the first processor determines that the data currently written by the first processor meets the preset conditions. The first processor obtains the end address of the current data write and sends the corresponding data read signal to the second processor. The value of the amount of data written by the first processor and / or the time for writing data recorded before this is reset to zero.

9. The communication method as described in claim 6, characterized in that, When the data currently written by the first processor meets the preset conditions, and the second processor has not completed reading the data from the start address to the end address of the memory, the first processor will not send the data read signal to the second processor until the second processor completes reading the data from the start address to the end address of the memory.

10. The communication method as described in claim 6, characterized in that, When the address of the data currently being written by the first processor in the memory is within the range from the start address to the end address of the memory write as currently read by the second processor, the first processor stops writing data to the memory.

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