Display panel and display device

Abstract

The invention provides a display panel and a display device.The display panel comprises a display area and a peripheral area located on the periphery of the display area, the peripheral area comprises a GOA area, a non-GOA area and a binding area, and the binding area comprises a plurality of bonding pad sets arranged in the preset direction; each of the two bonding pad groups located at the edge in the preset direction comprises a first bonding pad region corresponding to the GOA region and a second bonding pad region corresponding to the non-GOA region; the driving signal of the GOA area comprises a clock signal and a plurality of auxiliary signals; the binding pin of the clock signal is arranged in the first bonding pad area, and the binding pin of the at least one auxiliary signal is arranged in the second bonding pad area, so that the space of the first bonding pad area is increased. According to the display panel, it is guaranteed that the number of the binding pins of the GOA driving signal is maximized while the total number of the pins of the bonding pad set is not increased, the display panel has the high refresh rate, the long service life, the intelligent display function and the like, and then the product competitiveness of the display panel is improved.

Description

Technical Field

[0001] This invention generally relates to the field of display technology, and more specifically to a display panel and a display device. Background Technology

[0002] In display panel pad design, the Data Channel is typically centered, with GOA signal and dummy traces on the left and right sides, respectively. Due to COF (Chip on Film) specifications, the number of leads that can be arranged on a single COF is limited. As the demands on display panels increase, the large number of pins on the GOA side of the COF leads to insufficient design requirements, while the non-GOA side pins remain idle, resulting in low utilization. Summary of the Invention

[0003] In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide a display panel and display device that increases the pad space on the GOA side by setting some of the bonding pins of the GOA signal on the non-GOA side or shifting the bonding pins of the corresponding data channel toward the non-GOA side. This is beneficial to maximize the number of bonding pins of the GOA drive signal without increasing the total number of pins of the pad group, which is conducive to the display panel having high refresh rate, long service life and intelligent display functions, thereby improving the product competitiveness of the display panel.

[0004] In a first aspect, the present invention provides a display panel, including a display area and a peripheral area located around the display area. The peripheral area includes a GOA area, a non-GOA area and a bonding area. The bonding area includes a plurality of pad groups arranged along a preset direction. Two pad groups located at the edge along the preset direction each include a first pad area corresponding to the GOA area and a second pad area corresponding to the non-GOA area. The driving signals for the GOA area include clock signals and multiple auxiliary signals; The clock signal bonding pin is located in the first pad area, and at least one auxiliary signal bonding pin is located in the second pad area to increase the space of the first pad area.

[0005] As an optional solution, the clock signal bonding pins include original bonding pins and additional bonding pins. Both original bonding pins and additional bonding pins are located in the first pad area, and the number of additional bonding pins is equal to the number of bonding pins corresponding to the auxiliary signals located in the second pad area.

[0006] As an optional solution, the number of additional bonding pins is equal to the number of clock signal channels or the number of additional bonding pins for a single clock signal.

[0007] As an optional solution, each pad group includes a third pad area corresponding to the data channel. Each pad group located in the middle area along the preset direction also includes a fourth pad area located on both sides of the third pad area corresponding to the non-GOA area. Each of the two fourth pad areas is provided with the same number of additional dummy pins, and the number of additional dummy pins in each fourth pad area is equal to the number of bonding pins corresponding to the auxiliary signal located in the second pad area.

[0008] As an optional solution, the total number of bonded pins on each pad group is equal.

[0009] As an optional solution, the peripheral area also includes a fan-out area, which is located between the bonding area and the display area. The auxiliary signals located in the second pad area are connected to the GOA area through the traces in the fan-out area on the side closer to the display area. Additional dummy pins are located on the side closest to the display area and are connected within the fan-out area via bridging traces.

[0010] As an optional solution, the peripheral area also includes a sensor driving area. The driving signal of the sensor driving area is set in the second pad area or the fourth pad area, and the driving signal of the sensor driving area is connected to the sensor driving area through the traces in the fan-out area.

[0011] As an optional solution, the first pad area and the second pad area are symmetrically arranged on both sides of the third pad area, and the number of pins at symmetrical positions in the first pad area and the second pad area is the same. Two fourth pad areas are symmetrically arranged on both sides of the third pad area, and the number of pins at symmetrical positions in the two fourth pad areas is the same.

[0012] In a second aspect, the present invention provides a display panel, including a display area and a peripheral area located around the display area. The peripheral area includes a GOA area, a non-GOA area and a bonding area. The bonding area includes a plurality of pad groups arranged along a preset direction. Each pad group includes a third pad area corresponding to a data channel. Two pad groups located at the edge along the preset direction also include a first pad area corresponding to the GOA area and a second pad area corresponding to the non-GOA area. The first pad area and the second pad area are located on both sides of the third pad area. The third pad area of ​​the two pad groups located at the edge is offset toward the second pad area along a preset direction to increase the space of the first pad area; The bonding pins for the drive signals in the GOA area are all located in the first pad area.

[0013] As an optional solution, the third pad area of ​​each pad group located in the middle area is offset to one side along a preset direction so that the offset directions of the third pad areas of any two adjacent pad groups in the multiple pad groups are opposite.

[0014] As an optional solution, the offset of the third pad area in each pad group is equal.

[0015] As an optional solution, the peripheral area also includes a fan-out area, where the fan-out traces correspond to the eccentric traces of each pad group.

[0016] Thirdly, the present invention provides a display panel, including a display area and a peripheral area located around the display area. The peripheral area includes a GOA area, a non-GOA area and a bonding area. The bonding area includes a plurality of pad groups arranged along a preset direction. Each pad group includes a third pad area corresponding to a data channel. Two pad groups located at the edge along the preset direction also include a first pad area corresponding to the GOA area and a second pad area corresponding to the non-GOA area. The first pad area and the second pad area are located on both sides of the third pad area. The driving signals for the GOA area include clock signals and multiple auxiliary signals; The third pad area of ​​the two pad groups located at the edge is offset toward the second pad area along a preset direction; The clock signal bonding pin is located in the first pad area, and at least one auxiliary signal bonding pin is located in the second pad area to increase the space of the first pad area.

[0017] As an optional solution, the clock signal bonding pins include original bonding pins and additional bonding pins. Both original bonding pins and additional bonding pins are located in the first pad area, and the number of additional bonding pins is equal to the number of bonding pins corresponding to the auxiliary signals located in the second pad area.

[0018] As an optional solution, the third pad area of ​​each pad group in the middle area is offset to one side along a preset direction so that the offset directions of the third pad areas of any two adjacent pad groups in the multiple pad groups are opposite. Each pad group located in the middle area along the preset direction also includes a fourth pad area located on both sides of the third pad area corresponding to the non-GOA area. Each of the two fourth pad areas is provided with the same number of additional dummy pins, and the number of additional dummy pins in each fourth pad area is equal to the number of bonding pins corresponding to the auxiliary signal in the second pad area.

[0019] As an optional solution, the peripheral area also includes a fan-out area, which is located between the bonding area and the display area. The fan-out traces corresponding to the pad groups in the fan-out area correspond to the eccentric traces of each pad group. The auxiliary signal located in the second pad area is connected to the GOA area via traces in the fan-out area on the side closest to the display area; Additional dummy pins are located on the side closest to the display area and are connected within the fan-out area via bridging traces.

[0020] Fourthly, the present invention provides a display device, including a display panel as described in the first aspect.

[0021] The display panel of this invention sets some of the GOA drive signal bonding pins in the pad area corresponding to the non-GOA area, and sets additional bonding pins for the added clock signal in the pad area corresponding to the GOA area. This is beneficial to improve the pin utilization rate on the pad group and allows for setting more GOA drive signals according to the actual functional requirements of the display panel. In addition, by offsetting the pad area corresponding to the data channel on the pad group close to the GOA area toward the pad area corresponding to the non-GOA area, it is beneficial to increase the space of the pad area corresponding to the GOA area, thereby facilitating the setting of GOA drive signals. This ensures that the number of bonding pins for GOA drive signals is maximized without increasing the total number of pins in the pad group. This is beneficial for the display panel to have high refresh rate, long service life, and intelligent display functions, thereby improving the product competitiveness of the display panel. Attached Figure Description

[0022] Other features, objectives, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 A schematic diagram showing the arrangement of the pads in the bonding area of ​​the display panel; Figure 2 This is a schematic diagram showing the arrangement of bonding pins in each pad group of the bonding area in related technologies; Figure 3 This is a schematic diagram of the structure of the peripheral area of ​​a display panel in related technologies; Figure 4 This is a schematic diagram showing the arrangement of bonding pins in each pad group of the bonding area in the display panel of an embodiment of this application; Figure 5 This is a schematic diagram of the structure of the peripheral area of ​​the display panel according to an embodiment of this application; Figure 6 This is a schematic diagram of the traces for the pad group X6 in the bonding area of ​​an embodiment of this application; Figure 7 This is a schematic diagram of a symmetrically distributed pad group bonding pins according to an embodiment of this application; Figure 8 This is a schematic diagram showing the symmetrical distribution of pins in the pad group following the non-GOA side, as part of an embodiment of this application. Figure 9 A schematic diagram of the bonding pin distribution of a second type of pad group for the third pad area offset in an embodiment of this application; Figure 10 correspond Figure 9 A schematic diagram of the wiring distribution in the fan-out area; Figure 11 A schematic diagram of the trace distribution of the fan-out area corresponding to the third pad area offset setting for all pad groups in the embodiments of this application; Figure 12 This is a schematic diagram of the bonding pin distribution of a third pad area offset setting and a portion of the GOA signal setting on the non-GOA side of the embodiment of this application.

[0023] In the picture, AA, Display Area; S1, GOA Area; S2, Non-GOA Area; S3, Binding Area; S4, Fan-out Area. 20. Pad group; 21. First pad area; 22. Second pad area; 23. Third pad area; 24. Fourth pad area; 311. Original bonded pin; 312. Additional bonded pin; 32. Bonded pin for auxiliary signal; 33. Additional dummy pin; 34. Dummy bonded pin; Detailed Implementation The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0024] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0025] In related technologies, the signal settings on conventional pad groups are as follows: Figures 1-3 As shown in the diagram, side A is the left side and side B is the right side. Figure 2 As shown, the Data Channel is placed in the center. The right side of pad group X1 and the left side of pad group X6 are the GOA (Gate on Array) side, where GOA drive signals, GND (Ground), and Com (Com) are configured. The left side of pad group X1, the left and right sides of pad groups X2-X5, and the right side of pad group X6 are the non-GOA side, where dummy leads are configured or Com and GND signals are added. Considering the increasing market demand for product specifications, such as high refresh rates and longer lifespans, the GOA side needs to add CLK signals or increase the number of leads for each CLK to improve GOA reliability. Furthermore, the addition of smart display functions also requires the introduction of new signals. Therefore, the number of leads on the GOA side cannot meet the design requirements, while the leads on the non-GOA side are idle, resulting in low space utilization on the entire pad group.

[0026] Based on the above issues, such as Figure 4 and Figure 5 As shown, Figure 4 and Figure 5 Taking a group of 6 pads (X1, X2, X3, X4, X5, and X6) as an example, Figure 4 The diagram illustrates the distribution of bonding pins in each pad group 20. An embodiment of this application provides a display panel, including a display area AA and a peripheral area surrounding the display area AA. The peripheral area includes a GOA area S1, a non-GOA area S2, and a bonding area S3. The bonding area S3 includes a bonding area along a preset direction (e.g., along a predetermined direction). Figure 5 Multiple pad groups 20 arranged in the X direction, and two pad groups 20 (X1 and X6) located at the edge along the preset direction each include a first pad area 21 corresponding to the GOA area S1 and a second pad area 22 corresponding to the non-GOA area S2; The drive signals for GOA area S1 include a clock signal and multiple auxiliary signals; The clock signal bonding pin is located in the first pad area 21, and at least one auxiliary signal bonding pin 32 is located in the second pad area 22 to increase the space of the first pad area 21.

[0027] It should be noted that the GOA area S1 of the display panel is usually located on the left and right sides of the display area AA, the bonding area S3 is located on the lower side of the display area AA, and the non-GOA area S2 is located on the periphery of the display area AA opposite to the GOA area S1. The GOA area S1 mainly refers to the area where the GOA circuits are located. Each GOA circuit is set in the peripheral area according to the pixel arrangement structure and is used to drive the operation of each pixel unit. The bonding area S3 refers to the area where the display panel and the driver chip are electrically connected. The bonding area S3 includes multiple pad groups 20 arranged along a preset direction. Each pad group 20 has multiple metal leads. The driver chip is bonded to the pad group 20 of the bonding area S3 in the form of COF (Chip on Film).

[0028] It is understandable that the preset direction can be from left to right of the display area AA or the arrangement direction of the data channel. Each pad group 20 includes a third pad area 23 corresponding to the data channel and pad areas corresponding to other areas.

[0029] The two pad groups 20 located at the edge along the preset direction refer to the two pad groups 20 closest to the GOA region S1 among multiple pad groups 20. Each of the two pad groups 20 closest to the GOA region S1 includes a first pad area 21 corresponding to the GOA region S1 and a second pad area 22 corresponding to the non-GOA region S2. The first pad area 21 includes traces for bonding and connecting the input GOA drive signal. The drive signal for the GOA region S1 includes CLK (clock signal) and multiple auxiliary signals. The multiple auxiliary signals can be other functional signals besides the clock signal, such as, but not limited to, STV (start signal), Reset (reset signal), VDDO / E (high-level power signal), VSS / LVSS (low-level power signal), Vcom (common electrode voltage signal), and other functional signals. The second pad area 22 is mainly used to set up dummy bonded pins (DUMMY lead) 34 to balance the load of the pad group 20 and ensure the consistency of the pad group 20.

[0030] It is also understandable that setting at least one auxiliary signal bonding pin 32 in the second pad area 22 means setting at least one GOA area S1 drive signal on the non-GOA side of the pad group 20. This makes full use of the space of the pad area (second pad area 22) on the non-GOA side of the pad group 20, reduces the setting of dummy bonding pins 34, increases the space of the pad area (first pad area 21) on the GOA side, and effectively improves the utilization rate of bonding pins of the pad group 20.

[0031] The display panel of this application addresses the problem of low pin utilization on pad group 20 in related technologies. By placing the bonding pins of some GOA drive signals in the pad area corresponding to the non-GOA area S2, the pin utilization on pad group 20 is improved. This allows for the setting of more GOA drive signals according to the actual functional requirements of the display panel, maximizing the number of bonding pins for GOA drive signals without increasing the total number of pins in pad group 20. This results in a display panel with high refresh rate, long lifespan, and intelligent display functions, thereby enhancing the product competitiveness of the display panel.

[0032] In some embodiments, such as Figure 4 As shown, the clock signal bonding pins include original bonding pin 311 and additional bonding pin 312. Both original bonding pin 311 and additional bonding pin 312 are located in the first pad area 21. The number of additional bonding pins 312 is equal to the number of bonding pins corresponding to the auxiliary signals located in the second pad area 22.

[0033] It should be noted that the original bonding pin 311 and the additional bonding pin 312 are only used for distinction. The original bonding pin 311 refers to the bonding pin originally set to drive the clock signal to work reliably for the GOA circuit. The additional bonding pin 312 refers to the bonding pin corresponding to the clock signal added after some auxiliary signals are moved to the second pad area 22 in order to reduce the load on the clock signal.

[0034] Specifically, an additional bonding pin 312 corresponding to the clock signal is added to the first pad area 21, which increases the number of bonding pins for the clock signal, reduces the load on the clock signal, and is beneficial for supporting higher resolutions / refresh rates or reducing impedance, improving drive capability and reliability. The number of additional bonding pins 312 is equal to the number of bonding pins corresponding to the auxiliary signals located in the second pad area 22, which helps to ensure that the total number of bonding pins in the first pad area 21 and the second pad area 22 is the same, thus balancing the load on the pad group 20.

[0035] In this embodiment, the additional bonding pin 312 added to the first pad area 21 helps to reduce the load on the clock signal and at the same time helps to ensure that there is no difference in the inter-row input of each GOA driver circuit.

[0036] As an implementation method, the number of additional bonding pins 312 is equal to the number of clock signal channels or the number of additional bonding pins for a single clock signal.

[0037] For example, if the bonding pins 32 of the four auxiliary signals originally located in the first pad area 21 are moved out, four pin positions are freed up in the first pad area 21. All the freed pin positions are used to enhance the clock signal. There are two specific enhancement methods: one is to increase the total number of clock signal channels (for example, to add four clock channels using these four pins to upgrade from 12CLK to 16CLK); the other is to increase the number of parallel pins of the existing single clock channel (for example, if each CLK channel was originally driven by four pins in parallel, it can now be increased to eight pins in parallel) to reduce resistance and load, and improve driving capability and reliability.

[0038] In some embodiments, the total number of bonding pins in the first pad area 21 is equal to the total number of bonding pins in the second pad area 22.

[0039] In this embodiment, having an equal number of pins ensures balanced load distribution across the 20 pad groups and also simplifies the manufacturing process.

[0040] As an implementation method, each pad group 20 includes a third pad area 23 corresponding to a data channel, and each pad group 20 located in the middle area along a preset direction (e.g., Figure 4The pad groups (X2-X5) also include fourth pads 24 located on both sides of the third pad area 23 corresponding to the non-GOA area S2. Each of the two fourth pads 24 is provided with the same number of additional dummy pins 33, and the number of additional dummy pins 33 of each fourth pad 24 is equal to the number of bonding pins corresponding to the auxiliary signals located in the second pad area 22.

[0041] Understandably, to ensure reliable input data signals, the pad groups 20 in the middle area are used to bond and connect the driver chips that connect the input data signals. Each pad group 20 in the middle area has dummy bonding pins 34 on both sides of the third pad area 23 of the corresponding data channel to ensure that the load of each pad group 20 is consistent, thereby ensuring that the load of the data signals of the entire display panel is consistent. Among them, the dummy bonding pins 34 are not connected to the actual functional signals, but have a similar shape and length to the traces transferred to the auxiliary signals in the second pad area 22.

[0042] In the second pad area 22 of the two pad groups 20 located at the edge, a binding pin for the GOA drive signal is set. After adding an additional binding pin 312 for the clock signal in the first pad area 21, a virtual binding pin 34 for the corresponding GOA drive signal is also set on the fourth pad 24 of each pad group 20 located in the middle area. This is to ensure the load consistency of the data signal of the entire display screen and to ensure the display effect of the display panel.

[0043] Furthermore, the total number of bonding pins on each pad group 20 is equal, which facilitates processing. At the same time, the load on each pad group 20 is consistent, which helps to ensure the uniformity of the display panel and improve the display effect.

[0044] As a feasible approach, such as Figure 5 and Figure 6 As shown, the peripheral area also includes a fan-out area S4, which is located between the bonding area S3 and the display area AA. The auxiliary signal located in the second pad area 22 is connected to the GOA area S1 via the trace L1 in the fan-out area S4 on the side closer to the display area AA. Additional dummy pin 33 is located on the side near the display area AA and is connected in the fan-out area S4 via a bridging trace L2.

[0045] In this embodiment, the auxiliary signal located in the second pad area 22 is routed through the metal traces in the fan-out area S4, crossing the fan-out area S4 on the side closest to the display area AA, and finally connecting to the corresponding input terminal in the GOA area S1. This wire-wound connection enables cross-area signal transmission. Similarly, the dummy bonding pin 34 is connected within the fan-out area S4 on the side closest to the display area AA via a bridging trace, thereby simulating the signal load on both sides in terms of electrical characteristics and balancing the impedance.

[0046] As an alternative implementation, the peripheral area also includes a sensor driving area, the driving signal of which is set in the second pad area 22 or the fourth pad 24, and the driving signal of which is connected to the sensor driving area through the traces in the fan-out area S4.

[0047] Understandably, the display panel integrates touch sensing functionality. The bonding pins of its drive signal can be flexibly configured to correspond to the second pad area 22 or the fourth pad 24 on the non-GOA side according to the arrangement structure of the touch sensor and the space of the pad group 20. The signal is introduced into the sensor drive area through the metal wiring of the fan-out area S4 to achieve reliable touch sensing.

[0048] In some embodiments, such as Figure 7 As shown, the first pad area 21 and the second pad area 22 are symmetrically arranged on both sides of the third pad area 23, and the number of pins at symmetrical positions in the first pad area 21 and the second pad area 22 is the same. Two fourth pads 24 are symmetrically arranged on both sides of the third pad area 23, and the number of pins at symmetrical positions in the two fourth pads 24 is the same.

[0049] For example, such as Figure 7 and Figure 8 As shown, when the number of pins corresponding to each signal in the first pad area 21 along the direction away from the third pad area 23 is 2, 4, 4, 2 respectively, the number of bonded pins in the second pad area 22 at symmetrical positions along the direction away from the third pad area 23 is also 2, 4, 4, 2 respectively. Similarly, after moving at least one auxiliary signal to the second pad area 22, if the bonded pin of the auxiliary signal in the second pad area 22 is 5, then the additional bonded pins 312 of the clock signal in the first pad area 21 at symmetrical positions are also 5.

[0050] In this embodiment, the bonding pins located on both sides of the third pad area 23 are symmetrically arranged and the symmetrical positions are equal. This helps to ensure that all pad groups 20 have consistency and that the pad groups 20 have commonality, which simplifies the processing technology, reduces the processing difficulty, and allows each pad area to be selected arbitrarily in actual use and bound to the corresponding driver chip according to time.

[0051] Secondly, embodiments of this application provide a display panel, such as... Figure 9 and Figure 10As shown, similar to the first aspect, taking 6 pad groups 20 as an example, it includes a display area AA and a peripheral area around the display area AA. The peripheral area includes a GOA area S1, a non-GOA area S2 and a bonding area S3. The bonding area S3 includes multiple pad groups 20 arranged along a preset direction. Each pad group 20 includes a third pad area 23 corresponding to the data channel. The two pad groups 20 located at the edge along the preset direction also include a first pad area 21 corresponding to the GOA area S1 and a second pad area 22 corresponding to the non-GOA area S2. The first pad area 21 and the second pad area 22 are located on both sides of the third pad area 23. The third pad area 23 of the two pad groups 20 located at the edge is offset towards the second pad area 22 along a preset direction to increase the space of the first pad area 21 (e.g., Figure 9 As shown, Figure 9 This shows that the third pad area 23 of pad group X6 is offset to the right of the second pad area 22, and similarly, the third pad area 23 of pad group X1 is offset to the left of the second pad area 22. Figure 10 The routing of the middle fan-out area S4 illustrates the offset settings of the third pad area for pad groups X1 and X6.

[0052] It should be noted that the preset direction in this embodiment is the same as the direction described above.

[0053] It is understandable that the two pad groups 20 located at the edge, that is, the two pad groups 20 close to the GOA area S1, have the third pad group 20 corresponding to the data channel on the two pad groups 20 offset toward the second pad area 22 corresponding to the non-GOA area S2. This reduces the space of the second pad area 22, reduces the setting of dummy bonding pins 34, and increases the space of the first pad area 21, so as to increase the GOA signal or other functional signals without changing the total number of bonding pins of the pad group 20.

[0054] The bonding pins of the drive signals of the GOA area S1 can all be set in the first pad area 21, and some of the auxiliary signals can also be set in the second pad area 22.

[0055] In this embodiment, by offsetting the pad area corresponding to the data channel on the pad group 20 near the GOA area S1 toward the pad area corresponding to the non-GOA area S2, it is beneficial to increase the space of the pad area corresponding to the GOA area S1, thereby facilitating the setting of the GOA drive signal. This ensures that the number of bonding pins of the GOA drive signal is maximized without increasing the total number of pins in the pad group 20, which is beneficial for the display panel to have high refresh rate, long service life and intelligent display functions, thereby improving the product competitiveness of the display panel.

[0056] In some embodiments, such as Figure 11As shown, the third pad area 23 of each pad group 20 located in the middle area is offset to one side along a preset direction so that the offset directions of the third pad areas 23 of any two adjacent pad groups 20 are opposite.

[0057] In this embodiment, after the third pad area 23 on the two pad groups 20 located at the edge is offset, the third pad area 23 on each pad group 20 located in the middle area is offset, that is, the third pad area 23 of each pad group 20 located in the middle area is offset toward the fourth pad 24 on any side, so that the offset direction of the third pad in two adjacent pad groups 20 of all pad groups 20 is opposite, which is beneficial to the uniform distribution of metal traces of the entire display panel.

[0058] For example, such as Figure 11 As shown, the pad groups 20 of the display panel bonding area S3 are numbered X1, X2, X3, X4, X5, and X6 from right to left. Among them, the third pad area 23 of X1 is offset to the left, the third pad area 23 of X3 is offset to the left, the third pad area 23 of X5 is offset to the left, the third pad area 23 of X2 is offset to the right, the third pad area 23 of X4 is offset to the right, and the third pad area 23 of X6 is offset to the right.

[0059] In some embodiments, the offset of the third pad area 23 of each pad group 20 is equal, which helps to simplify the manufacturing process and allows for two different pad groups 20 on the display panel, making it convenient to use.

[0060] In some embodiments, such as Figure 10 and Figure 11 As shown, the surrounding area also includes a fan-out area S4, and the fan-out traces corresponding to the pad group 20 within the fan-out area correspond to the eccentric traces of each pad group 20.

[0061] Understandably, in order to correspond to the pad group 20, the traces of the fan-out area S4 correspond to the eccentric traces of the pad group 20. Thus, the eccentric directions of the traces of two adjacent fan-out areas S4 are opposite, which allows the data lines drawn from different offset directions to be efficiently and without crossing to each pixel column of the display area AA, making the maximum use of the wiring space of the fan-out area S4 and reducing signal crosstalk.

[0062] Thirdly, embodiments of this application provide a display panel, including a display area AA and a peripheral area located around the display area AA. The peripheral area includes a GOA area S1, a non-GOA area S2 and a bonding area S3. The bonding area S3 includes a plurality of pad groups 20 arranged along a preset direction. Each pad group 20 includes a third pad area 23 corresponding to a data channel. Two pad groups 20 located at the edge along the preset direction also include a first pad area 21 corresponding to the GOA area S1 and a second pad area 22 corresponding to the non-GOA area S2. The first pad area 21 and the second pad area 22 are located on both sides of the third pad area 23. The drive signals for GOA area S1 include a clock signal and multiple auxiliary signals; The third pad area 23 of the two pad groups 20 located at the edge is offset toward the second pad area 22 along a preset direction; The clock signal bonding pin is located in the first pad area 21, and at least one auxiliary signal bonding pin 32 is located in the second pad area 22 to increase the space of the first pad area 21.

[0063] As an optional solution, the clock signal bonding pins include original bonding pin 311 and additional bonding pin 312. Both original bonding pin 311 and additional bonding pin 312 are located in the first pad area 21. The number of additional bonding pins 312 is equal to the number of bonding pins corresponding to the auxiliary signal located in the second pad area 22.

[0064] For example, Figure 12 Taking pad X6 as an example, the third pad area 23 is offset to the right of the second pad area 22, and the bonding pins of the auxiliary signals VDDE and STV0 of the GOA drive signal are moved to the second pad area 22. An additional bonding pin 312 for the clock signal is added to the first pad 21.

[0065] As an implementation method, the third pad area 23 of each pad group 20 located in the middle region is offset to one side along a preset direction so that the offset directions of the third pad areas 23 of any two adjacent pad groups 20 in the plurality of pad groups 20 are opposite. Each pad group 20 located in the middle area along the preset direction also includes a fourth pad 24 located on both sides of the third pad area 23 corresponding to the non-GOA area S2. Each of the two fourth pads 24 is provided with the same number of additional dummy pins 33, and the number of additional dummy pins 33 of each fourth pad 24 is equal to the number of bonding pins corresponding to the auxiliary signal located in the second pad area 22.

[0066] As an implementation method, the peripheral area also includes a fan-out area S4, which is located between the bonding area S3 and the display area AA. The fan-out traces corresponding to the pad group 20 in the fan-out area correspond to the eccentric traces of each pad group 20. The auxiliary signal located in the second pad area 22 is connected to the GOA area S1 via the trace in the fan-out area S4 on the side close to the display area AA; Additional dummy pin 33 is located on the side near the display area AA and is connected in the fan-out area S4 via a bridging trace.

[0067] It should be noted that the display panel in this embodiment possesses all the features and advantages of the display panels in the first and second aspects described above, and will not be repeated here. In summary, the display panel of the embodiment of this application, by offsetting the corresponding pad area of ​​the data channel and moving part of the GOA signal to the second pad area 22 on the non-GOA side, is beneficial for the overall allocation of the pins of the pad group 20, improving pin utilization, while also ensuring uniform wiring distribution, load balance, and ensuring the display uniformity and reliability of the display panel.

[0068] Fourthly, embodiments of this application provide a display device, including a display panel of the first aspect, a display panel of the second aspect, or a display panel of the third aspect. It is understood that this display device possesses all the features and advantages of the aforementioned display panels, which will not be repeated here. In summary, this display device has good display performance and high overall product competitiveness.

[0069] The display device is a product with image display capabilities. For example, a display device can be any of the following: monitor, television, billboard, digital photo frame, laser printer with display function, telephone, mobile phone, personal digital assistant (PDA), digital camera, portable camcorder, viewfinder, navigator, vehicle, large-area wall, home appliance, information query equipment (such as business query equipment for e-government, banks, hospitals, power companies, etc.), monitor, etc. The display device can also be a microdisplay or a product containing a microdisplay. Products containing microdisplays can be any of the following: smartwatch, smart bracelet, helmet display, stereoscopic display, and AR devices (such as AR glasses), VR devices (such as VR glasses), etc. For example, a microdisplay can be a display with a display size ranging from approximately 0.2 inches to approximately 2.5 inches, but is not limited to this. Understandably, a microdisplay can also be a display with a smaller display size, such as a display size less than or equal to 0.2 inches.

[0070] The display panel of the present invention will be described below through specific embodiments.

[0071] Example 1 like Figure 4 , Figure 5 and Figure 6As shown, the display panel includes a display area AA and a peripheral area around the display area AA. The peripheral area includes a GOA area S1, a non-GOA area S2, a fan-out area S4, and a bonding area S3. The bonding area S3 includes pad groups X1, X2, X3, X4, X5, and X6 arranged from right to left. Each pad group 20 includes a third pad area 23 corresponding to the data channel. Pad groups X1 and X6 each include a first pad area 21 corresponding to the GOA area S1 and a second pad area 22 corresponding to the non-GOA area S2. The drive signals for GOA area S1 include a clock signal (CLK) and multiple auxiliary signals. The bonding pins for the clock signal include the original bonding pin 311 and the additional bonding pin 312. At least one auxiliary signal (VCOM, VSS, VDD, STV) has a bonding pin set in the second pad area 22, and correspondingly additional bonding pins 312 are added in the first pad area 21. The number of additional bonding pins 312 is equal to the number of bonding pins corresponding to the auxiliary signals located in the second pad area 22. The auxiliary signals (VCOM, VSS, VDD, STV) located in the second pad area 22 are connected to the GOA area S1 via the trace L1 in the fan-out area S4 on the side close to the display area AA; To ensure the load consistency of the data signals of the display panel, pad groups X2, X3, X4, and X5 each add additional dummy pins 33 for corresponding auxiliary signals (VCOM, VSS, VDD, STV) on both sides of the third pad area 23. The additional dummy pins 33 are located on the side closer to the display area AA and are connected in the fan-out area S4 through the bridging trace L2. Example 2 The display panel includes a display area AA and a peripheral area surrounding the display area AA. The peripheral area includes a GOA area S1, a non-GOA area S2, a fan-out area S4, and a bonding area S3. The bonding area S3 includes pad groups X1, X2, X3, X4, X5, and X6 arranged from right to left. Each pad group 20 includes a third pad area 23 corresponding to a data channel. Pad groups X1 and X6 each include a first pad area 21 corresponding to the GOA area S1 and a second pad area 22 corresponding to the non-GOA area S2. The first pad area 21 and the second pad area 22 are located on both sides of the third pad area 23. like Figure 9 and Figure 10 As shown, the third pad area 23 of pad group X1 and pad group X6 is offset towards the second pad area 22 along a preset direction to increase the space of the first pad area 21. The bonding pins of the drive signal of the GOA area S1 are all set in the first pad area 21, and the traces of the corresponding fan-out area S4 are also set off-center.

[0072] Example 3 Unlike Example 2, as Figure 11 As shown, in this embodiment, the third pad area 23 of pad group X2 is offset to the right, the third pad area 23 of pad group X3 is offset to the left, the third pad area 23 of pad group X4 is offset to the right, and the third pad area 23 of pad group X5 is offset to the left.

[0073] Example 4 Unlike Example 1, as Figure 12 As shown, in this embodiment, the third pad area 23 of pad group X1 and pad group X6 is offset towards the second pad area 22 along a preset direction to increase the space of the first pad area 21.

[0074] Example 5 Unlike Embodiment 1, in this embodiment, the third pad area 23 of pad group X1 and pad group X6 is offset towards the second pad area 22 along a preset direction, the third pad area 23 of pad group X2 is offset to the right, the third pad area 23 of pad group X3 is offset to the left, the third pad area 23 of pad group X4 is offset to the right, and the third pad area 23 of pad group X5 is offset to the left.

[0075] It should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., used above to indicate orientation or positional relationships are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the panel or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the invention, unless otherwise stated, "a plurality of" means two or more.

[0076] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A display panel, characterized in that, It includes a display area and a peripheral area around the display area. The peripheral area includes a GOA area, a non-GOA area and a bonding area. The bonding area includes multiple pad groups arranged along a preset direction. Two pad groups located at the edge along the preset direction each include a first pad area corresponding to the GOA area and a second pad area corresponding to the non-GOA area. The driving signals for the GOA region include a clock signal and multiple auxiliary signals; The clock signal binding pin is located in the first pad area, and at least one of the auxiliary signals binding pins is located in the second pad area to increase the space of the first pad area.

2. The display panel according to claim 1, characterized in that, The clock signal bonding pins include original bonding pins and additional bonding pins. Both the original bonding pins and the additional bonding pins are located in the first pad area. The number of additional bonding pins is equal to the number of bonding pins corresponding to the auxiliary signal located in the second pad area.

3. The display panel according to claim 2, characterized in that, The number of additional bonding pins is equal to the number of channels of the clock signal or equal to the number of additional bonding pins added to a single clock signal.

4. The display panel according to claim 1, characterized in that, Each of the pad groups includes a third pad area corresponding to a data channel. Each of the pad groups located in the middle area along a preset direction also includes a fourth pad area located on both sides of the third pad area corresponding to the non-GOA area. Each of the two fourth pad areas is provided with the same number of additional dummy pins, and the number of additional dummy pins in each fourth pad area is equal to the number of bonding pins corresponding to the auxiliary signal located in the second pad area.

5. The display panel according to claim 4, characterized in that, The total number of bonded pins on each of the said pad groups is equal.

6. The display panel according to claim 4, characterized in that, The peripheral area also includes a fan-out area, which is located between the bonding area and the display area. The auxiliary signal located in the second pad area is connected to the GOA area via a trace in the fan-out area on the side closer to the display area. The additional dummy pin is located on the side closest to the display area and is connected within the fan-out area via a bridging trace.

7. The display panel according to claim 6, characterized in that, The peripheral area also includes a sensor driving area, the driving signal of which is set in the second pad area or the fourth pad area, and the driving signal of which is connected to the sensor driving area through the trace in the fan-out area.

8. The display panel according to claim 4, characterized in that, The first pad area and the second pad area are symmetrically arranged on both sides of the third pad area, and the number of pins at symmetrical positions in the first pad area and the second pad area is the same; The two fourth pad areas are symmetrically arranged on both sides of the third pad area, and the number of pins at symmetrical positions in the two fourth pad areas is the same.

9. A display panel, characterized in that, It includes a display area and a peripheral area around the display area. The peripheral area includes a GOA area, a non-GOA area, and a bonding area. The bonding area includes multiple pad groups arranged along a preset direction. Each pad group includes a third pad area corresponding to a data channel. Two pad groups located at the edge along the preset direction also include a first pad area corresponding to the GOA area and a second pad area corresponding to the non-GOA area. The first pad area and the second pad area are located on both sides of the third pad area. The third pad area of ​​the two pad groups located at the edge is offset toward the second pad area in a preset direction to increase the space of the first pad area.

10. The display panel according to claim 9, characterized in that, The third pad area of ​​each pad group located in the middle region is offset to one side along a preset direction so that the offset directions of the third pad areas of any two adjacent pad groups in the plurality of pad groups are opposite.

11. The display panel according to claim 10, characterized in that, The offset of the third pad area in each of the said pad groups is equal.

12. The display panel according to claim 10, characterized in that, The peripheral area also includes a fan-out area, and the fan-out traces within the fan-out area correspond to the eccentric traces of each pad group.

13. A display panel, characterized in that, It includes a display area and a peripheral area around the display area. The peripheral area includes a GOA area, a non-GOA area, and a bonding area. The bonding area includes multiple pad groups arranged along a preset direction. Each pad group includes a third pad area corresponding to a data channel. Two pad groups located at the edge along the preset direction also include a first pad area corresponding to the GOA area and a second pad area corresponding to the non-GOA area. The first pad area and the second pad area are located on both sides of the third pad area. The driving signals for the GOA region include a clock signal and multiple auxiliary signals; The third pad area of ​​the two pad groups located at the edge is offset toward the second pad area along a preset direction; The clock signal binding pin is located in the first pad area, and at least one of the auxiliary signals binding pins is located in the second pad area to increase the space of the first pad area.

14. The display panel according to claim 13, characterized in that, The clock signal bonding pins include original bonding pins and additional bonding pins. Both the original bonding pins and the additional bonding pins are located in the first pad area. The number of additional bonding pins is equal to the number of bonding pins corresponding to the auxiliary signal located in the second pad area.

15. The display panel according to claim 13, characterized in that, The third pad area of ​​each of the pad groups located in the middle region is offset to one side along a preset direction, so that the offset directions of the third pad areas of any two adjacent pad groups in the plurality of pad groups are opposite. Each pad group located in the middle area along the preset direction also includes a fourth pad area located on both sides of the third pad area corresponding to the non-GOA area. Each of the two fourth pad areas is provided with the same number of additional dummy pins, and the number of additional dummy pins in each fourth pad area is equal to the number of bonding pins corresponding to the auxiliary signal located in the second pad area.

16. The display panel according to claim 15, characterized in that, The peripheral area also includes a fan-out area, which is located between the bonding area and the display area. The fan-out traces corresponding to the pad groups within the fan-out area correspond to the eccentric traces of each pad group. The auxiliary signal located in the second pad area is connected to the GOA area via a trace in the fan-out area on the side closer to the display area; The additional dummy pin is located on the side closest to the display area and is connected within the fan-out area via a bridging trace.

17. A display device, characterized in that, Includes the display panel as described in any one of claims 1-8, 9-12, or 13-16.

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