Display panel and display device

Abstract

The invention relates to the technical field of display, in particular to a display panel and a display device. The display panel comprises a plurality of pixel circuit columns, the pixel circuit columns comprise a plurality of pixel circuits, the pixel circuit columns comprise a first pixel circuit column and a second pixel circuit column, and the number of the pixel circuits in the first pixel circuit column is smaller than the number of the pixel circuits in the second pixel circuit column; the data lines correspond to the pixel circuit columns, the data lines are electrically connected with the pixel circuits in the pixel circuit columns corresponding to the data lines, the data lines comprise the first data lines and the second data lines, the first data lines correspond to the first pixel circuit columns, and the second data lines correspond to the second pixel circuit columns; the vertical projection of the capacitance compensation part on the display panel is at least partially overlapped with the vertical projection of the first data line on the display panel, and the capacitance compensation part and the data line are located on different film layers. The display uniformity of the special-shaped display panel can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] Currently, full-screen and irregularly shaped display panels are becoming increasingly popular among consumers. Full-screen displays feature ultra-narrow bezels on all four sides, combined with a panel architecture that incorporates holes in the display area to house devices such as cameras. Irregularly shaped display panels generally include irregular outlines, such as circular display panels or display panels with rounded corners.

[0003] However, the applicant discovered that the display area corresponding to the cutout area of ​​the full-screen display and the irregular area in the irregular display panel have different load (RC Loading) compared with the normal display area, resulting in uneven display. Summary of the Invention

[0004] In order to solve the above-mentioned technical problems, or at least partially solve the above-mentioned technical problems, this disclosure provides a display panel and a display device, which is beneficial to improving the display uniformity of irregularly shaped display panels.

[0005] This disclosure provides a display panel, comprising: a plurality of pixel circuit columns arranged along a first direction, each pixel circuit column including a plurality of pixel circuits arranged along a second direction, each pixel circuit column including a first pixel circuit column and a second pixel circuit column, wherein the number of pixel circuits in the first pixel circuit column is less than the number of pixel circuits in the second pixel circuit column, wherein the first direction and the second direction intersect; a plurality of data lines arranged along the first direction, the data lines extending along the second direction, the data lines corresponding to the pixel circuit columns, and the data lines being electrically connected to each pixel circuit in their corresponding pixel circuit columns, the data lines including a first data line and a second data line, the first data line corresponding to the first pixel circuit column, and the second data line corresponding to the second pixel circuit column; and a capacitance compensation unit, the vertical projection of the capacitance compensation unit on the display panel at least partially overlapping the vertical projection of the first data lines on the display panel, the capacitance compensation unit and the data lines being located in different film layers.

[0006] This disclosure also provides a display device including the aforementioned display panel.

[0007] The technical solution provided in this disclosure has the following advantages compared with the prior art: The display panel disclosed herein includes a capacitor compensation section. The vertical projection of the capacitor compensation section onto the display panel at least partially overlaps with the vertical projection of the first data line onto the display panel. The capacitor compensation section and the data line are located on different film layers, and a coupling capacitor can be formed between the capacitor compensation section and the first data line, thereby increasing the load on the first data line and making the loads on the first data line and the second data line more similar, thus improving display uniformity. Simultaneously, since the vertical projection of the capacitor compensation section onto the display panel at least partially overlaps with the vertical projection of the first data line onto the display panel, the capacitor compensation section can be directly set in the area corresponding to the first data line. The capacitor compensation section is located in the display area, eliminating the need to set a separate capacitor compensation section in the non-display area, which is beneficial for achieving a narrow bezel. Furthermore, the setting of the capacitor compensation section does not affect the original layout and size of the data line, thereby simplifying the manufacturing process of the display panel.

[0008] Correspondingly, the display device provided in this disclosure also has the above-mentioned technical effects. Attached Figure Description

[0009] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0010] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a plan view of a display panel provided in this disclosure; Figure 2 This is a schematic diagram of the layout structure of a display panel provided in this disclosure; Figure 3 This is a circuit diagram of a pixel circuit provided in this disclosure; Figure 4 This is a plan view of another display panel provided in this disclosure; Figure 5 This is a schematic diagram of another layout structure of the display panel provided in this disclosure; Figure 6 This is another schematic diagram of the layout structure of the display panel provided in this disclosure; Figure 7 This is another schematic diagram of the layout structure of the display panel provided in this disclosure; Figure 8 This is another schematic diagram of the layout structure of the display panel provided in this disclosure; Figure 9This is another schematic diagram of the layout structure of the display panel provided in this disclosure; Figure 10 This is a plan view of a display device provided in this disclosure. Detailed Implementation

[0012] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0013] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0014] In related technologies, conventional display panels are rectangular, with multiple pixels arranged in a matrix. Gate drive circuits and source drive circuits are located in the non-display areas of the panel. The gate drive circuits provide scan signals to each row of pixels, and the source drive circuits provide data signals to each column of pixels. In conventional display panels, each data line connects to an equal number of pixels in a column. During actual manufacturing, the data lines pass through the non-opening areas of a column of pixels. Therefore, the resistance of the data line itself, as well as the resistance and capacitance between the data line and components such as transistors in the pixel circuit, become the load on that data line. To accommodate special requirements, display panels may be designed in non-rectangular shapes. In such cases, some pixels may be cut off at the edges or inside the pixel matrix, resulting in unequal pixel counts in each column. The load on the data lines connecting each column of pixels will differ due to the unequal number of pixels. Consequently, when the same signal is applied, the signals input to each column of pixels will also differ, causing uneven display.

[0015] Based on this, the present disclosure provides a display panel and a display device, which is beneficial to improving the display uniformity of irregularly shaped display panels.

[0016] The display panel and display device provided in the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0017] Figure 1 This is a plan view of a display panel provided in this disclosure. Figure 2 This is a schematic diagram of the layout structure of a display panel provided in this disclosure. Figure 3 This is a circuit diagram of a pixel circuit provided in this disclosure, for reference. Figures 1-3 This embodiment provides a display panel, which includes: Multiple pixel circuit columns 10 are arranged along a first direction X. Each pixel circuit column 10 includes multiple pixel circuits 11 arranged along a second direction Y. Each pixel circuit column 10 includes a first pixel circuit column 101 and a second pixel circuit column 102. The number of pixel circuits in the first pixel circuit column 101 is less than the number of pixel circuits 11 in the second pixel circuit column 102. The first direction X and the second direction Y intersect. Multiple data lines D are arranged along the first direction X. The data lines D extend along the second direction Y. The data lines D are correspondingly set with the pixel circuit column 10. The data lines D and each pixel circuit 11 in the corresponding pixel circuit column 10 are electrically connected. The data lines D include a first data line D1 and a second data line D2. The first data line D1 is correspondingly set with the first pixel circuit column 101, and the second data line D2 is correspondingly set with the second pixel circuit column 102. The capacitance compensation unit 20 has a vertical projection on the display panel that at least partially overlaps with the vertical projection of the first data line D1 on the display panel. The capacitance compensation unit 20 and the data line D1 are located in different film layers.

[0018] Specifically, the display panel provided in this embodiment is an irregularly shaped display panel, comprising a display area AA and a non-display area NA surrounding the display area AA. The edges of the display area AA in the irregularly shaped display panel are irregularly shaped. It should be noted that... Figure 1 An exemplary illustration shows a circular display panel. In other embodiments of this disclosure, the display panel may also be other irregularly shaped display panels; for example, see reference... Figure 4 , Figure 4 This is a plan view of another display panel provided in this disclosure. The display panel is a conventionally shaped (rectangular) display panel, which includes an opening 30 for arranging optical components, thus the edge of the display area AA in the display panel is also irregularly shaped. The shape of the display panel can be set according to actual needs, which will not be described in detail here.

[0019] The display panel includes a plurality of pixel circuit columns 10 arranged along a first direction X. Each pixel circuit column 10 includes a plurality of pixel circuits 11 arranged along a second direction Y. Since the edges of the display area AA in the display panel are irregularly shaped, the pixel circuit columns 10 include a first pixel circuit column 101 and a second pixel circuit column 102, where the number of pixel circuits in the first pixel circuit column 101 is less than the number of pixel circuits in the second pixel circuit column 102. The first direction X and the second direction Y intersect. Optionally, the first direction X and the second direction Y are perpendicular.

[0020] It should be noted that, Figure 1The example shows one number setting of pixel circuits 11 in the first pixel circuit column 101 and the second pixel circuit column 102. In other embodiments of this disclosure, the number of pixel circuits 11 in the first pixel circuit column 101 and the second pixel circuit column 102 may be other values, and this disclosure does not specifically limit them.

[0021] The display panel also includes multiple data lines D arranged along a first direction X, extending along a second direction Y. The data lines D are correspondingly arranged with pixel circuit columns 10, and each pixel circuit 11 in the corresponding pixel circuit column 10 is electrically connected to the data line D. The data lines D are used to provide data voltage signals to the pixel circuits 11 electrically connected to them. The data lines D include a first data line D1 and a second data line D2. The first data line D1 is correspondingly arranged with the first pixel circuit column 101, and the second data line D2 is correspondingly arranged with the second pixel circuit column 102. That is, the first data line D1 is electrically connected to the pixel circuit 11 in the corresponding first pixel circuit column 101, and the second data line D2 is electrically connected to the pixel circuit 11 in the corresponding second pixel circuit column 102. Since the number of pixel circuits in the first pixel circuit column 101 is less than the number of pixel circuits in the second pixel circuit column 102, the number of pixel circuits 11 electrically connected to the first data line D1 is less than the number of pixel circuits 11 electrically connected to the second data line D2.

[0022] The display panel also includes a capacitor compensation section 20. The vertical projection of the capacitor compensation section 20 on the display panel at least partially overlaps with the vertical projection of the first data line D1 on the display panel. The capacitor compensation section 20 and the data line D are located in different film layers. A coupling capacitor can be formed between the capacitor compensation section 20 and the first data line D1, thereby increasing the load on the first data line D1 and making the loads on the first data line D1 and the second data line D2 tend to be the same, thereby improving the display uniformity.

[0023] Meanwhile, the vertical projection of the capacitor compensation unit 20 onto the display panel at least partially overlaps with the vertical projection of the first data line D1 onto the display panel. This allows the capacitor compensation unit 20 to be directly positioned in the area corresponding to the first data line D1. Since the capacitor compensation unit 20 is located in the display area AA, there is no need to separately position it in the non-display area NA, thus facilitating the achievement of a narrow bezel. Furthermore, the placement of the capacitor compensation unit 20 does not affect the original layout and size of the data line D, thereby simplifying the display panel manufacturing process.

[0024] Optionally, in the display panel, the pixel circuit 11 is electrically connected to the organic light-emitting diode, and the pixel circuit 11 includes a plurality of switching transistors, driving transistors and storage capacitor C1 that cooperate to control the light emission of the organic light-emitting diode. Figure 2 and Figure 3An exemplary pixel circuit is shown as a 7T1C pixel circuit, which includes six switching transistors M1-M2, M4-M7, one driving transistor M3, and one storage capacitor C1. In other embodiments of this disclosure, the pixel circuit may also adopt other circuit structures, which are not specifically limited herein.

[0025] Optionally, the number of pixel circuits 11 in the first pixel circuit column 101 is pi, the number of pixel circuits 11 in the second pixel circuit column 102 is X, the number of missing pixel circuits 11 in the first pixel circuit column 101 is X-pi, and the capacitance corresponding to a single pixel circuit 11 is Cp. Therefore, the missing load on the first data line D1 is Cp×(X-pi). j capacitor compensation units 20 can be set at the corresponding location on the first data line D1. The coupling capacitance formed between a single capacitor compensation unit 20 and the first data line D1 must satisfy Cp×(X-pi)÷j. It should be noted that the number of capacitor compensation units 20 corresponding to the first data line D1 can be set according to actual needs, and the coupling capacitance formed between a single capacitor compensation unit 20 and the first data line D1 can be adjusted according to the number of capacitor compensation units 20. This disclosure does not specifically limit this.

[0026] Continue to refer to Figures 1-3 In some alternative embodiments, the vertical projection of the capacitor compensation unit 20 on the display panel is located between the vertical projections of two adjacent pixel circuits 11 on the display panel along the first direction X.

[0027] Specifically, the vertical projection of the capacitor compensation unit 20 on the display panel is located between the vertical projections of two adjacent pixel circuits 11 along the first direction X on the display panel. That is, the vertical projection of the capacitor compensation unit 20 on the display panel is located in the gap area between two adjacent pixel circuits 11 along the first direction X. The setting of the capacitor compensation unit 20 will not affect the original layout of the pixel circuits 11, thereby simplifying the manufacturing process of the display panel.

[0028] Continue to refer to Figures 1-3 In some optional embodiments, the display panel further includes a first metal layer MC, which includes multiple reference voltage signal lines VREF extending along the first direction X and multiple first power supply voltage signal lines PVDD1 extending along the first direction X. Both the reference voltage signal lines VREF and the first power supply voltage signal lines PVDD1 are electrically connected to the pixel circuit 11. The capacitor compensation unit 20 is located in the first metal layer MC.

[0029] Specifically, the display panel also includes a first metal layer MC, which includes multiple reference voltage signal lines VREF extending along a first direction X. The reference voltage signal lines VREF are electrically connected to the pixel circuit 11 and are used to provide a stable reference voltage signal to the pixel circuit 11 for threshold voltage compensation or level reference. The first metal layer MC also includes multiple first power supply voltage signal lines PVDD1 extending along the first direction X. The first power supply voltage signal lines PVDD1 are electrically connected to the pixel circuit 11 and are used to provide the pixel circuit 11 with the high-level power supply voltage required for driving.

[0030] A capacitor compensation section 20 can be provided in the first metal layer MC. The capacitor compensation section 20, the reference voltage signal line VREF, and the first power supply voltage signal line PVDD1 can be made of the same material and in the same process. This means that the process of the reference voltage signal line VREF and the first power supply voltage signal line PVDD1 can be reused to make the capacitor compensation section 20, which helps to reduce the process and production cost.

[0031] Continue to refer to Figures 1-3 In some alternative embodiments, the display panel includes a plurality of first signal line groups 41 arranged along the second direction Y. The first signal line group 41 includes a reference voltage signal line VREF and a first power supply voltage signal line PVDD1. The vertical projection of the pixel circuit 11 on the display panel overlaps with the vertical projection portions of the reference voltage signal line VREF and the first power supply voltage signal line PVDD1 in the same group of first signal line groups 41 on the display panel. Along the second direction Y, at least a portion of the first signal line group 41 has a capacitor compensation section 20 provided between the reference voltage signal line VREF and the first power supply voltage signal line PVDD1.

[0032] Specifically, the display panel includes multiple first signal line groups 41 arranged along the second direction Y. Each first signal line group 41 includes a reference voltage signal line VREF and a first power supply voltage signal line PVDD1. A pixel circuit 11 is only configured corresponding to the reference voltage signal line VREF and the first power supply voltage signal line PVDD1 in the same first signal line group 41. The vertical projection of the pixel circuit 11 onto the display panel overlaps with the vertical projection of the reference voltage signal line VREF and the first power supply voltage signal line PVDD1 in the same first signal line group 41. A capacitor compensation section 20 is provided between the reference voltage signal line VREF and the first power supply voltage signal line PVDD1 in at least one first signal line group 41. The capacitor compensation section 20 can be configured using the gap space between the reference voltage signal line VREF and the first power supply voltage signal line PVDD1. The configuration of the capacitor compensation section 20 does not affect the original layout design of the pixel circuit 11, thereby simplifying the manufacturing process of the display panel. Furthermore, the capacitor compensation unit 20 does not require additional space and utilizes the free space in the original layout design of the pixel circuit 11, which is beneficial to improving the space utilization of the display panel, thereby enabling the display panel to maintain the existing pixel density design.

[0033] Figure 5 This is a schematic diagram of another layout structure of the display panel provided in this disclosure, for reference. Figure 1 , Figure 3 and Figure 5 In some optional embodiments, the first metal layer MC further includes a shielding part 50. Along the second direction Y, in the same first signal line group 41, a shielding part 50 is provided between the reference voltage signal line VREF and the first power supply voltage signal line PVDD1. The shielding part 50 is multiplexed as a capacitor compensation part 20. The shielding part 50 includes a first shielding part 51 and a second shielding part 52. The vertical projection of the first shielding part 51 on the display panel at least partially overlaps with the vertical projection of the first data line D1 on the display panel, and the vertical projection of the second shielding part 52 on the display panel at least partially overlaps with the vertical projection of the second data line D2 on the display panel. At least part of the overlap area between the vertical projection of the first shielding part 51 on the display panel and the vertical projection of the first data line D1 on the display panel is greater than the overlap area between the vertical projection of the second shielding part 52 on the display panel and the vertical projection of the second data line D2 on the display panel.

[0034] Specifically, the first metal layer M1 also includes a shielding part 50. Along the second direction Y, in the same first signal line group 41, a shielding part 50 is provided between the reference voltage signal line VREF and the first power supply voltage signal line PVDD1. The shielding part 50 is used to shield the influence of the electric field on the transistor M5.

[0035] The shielding portion 50 includes a first shielding portion 51 and a second shielding portion 52. The vertical projection of the first shielding portion 51 onto the display panel at least partially overlaps with the vertical projection of the first data line D1 onto the display panel, and the vertical projection of the second shielding portion 52 onto the display panel at least partially overlaps with the vertical projection of the second data line D2 onto the display panel. Since the overlapping area of ​​the vertical projections of the first shielding portion 51 and the first data line D1 onto the display panel is at least partially larger than the overlapping area of ​​the vertical projections of the second shielding portion 52 and the second data line D2 onto the display panel, increasing the overlapping area of ​​the first shielding portion 51 and the first data line D1 onto the display panel increases the load on the first data line D1, making the loads on the first data line D1 and the second data line D2 more similar, thereby improving display uniformity. Meanwhile, by reusing the shielding part 50 as the capacitor compensation part 20, there is no need to set up a separate capacitor compensation part 20, which helps to reduce the complexity of the process and avoid wiring conflicts or area waste caused by the addition of new structures. This helps to improve the space utilization of the display panel, so that the display panel can maintain the existing pixel density design.

[0036] It should be noted that the overlap area between the vertical projection of the first shielding part 51 on the display panel and the vertical projection of the first data line D1 on the display panel can be set according to actual needs, and will not be elaborated here.

[0037] Continue to refer to Figure 1 , Figure 3 and Figure 5 In some alternative embodiments, the width of the portion of the first shielding portion 51 overlapping the vertical projection of the first data line D1 on the display panel along the second direction Y is greater than the width of the portion of the second shielding portion 52 overlapping the vertical projection of the second data line D2 on the display panel along the second direction Y.

[0038] Specifically, the width of the portion of the vertical projection of at least a portion of the first shielding part 51 on the display panel overlapping the vertical projection of the first data line D1 on the display panel along the second direction Y is greater than the width of the portion of the vertical projection of the second shielding part 52 on the display panel overlapping the vertical projection of the second data line D2 on the display panel along the second direction Y. This results in the overlapping area of ​​at least a portion of the vertical projection of the first shielding part 51 on the display panel overlapping the vertical projection of the first data line D1 on the display panel being greater than the overlapping area of ​​the vertical projection of the second shielding part 52 on the display panel overlapping the vertical projection of the second data line D2 on the display panel. In other words, the width of the portion of the vertical projection of the first shielding part 51 on the display panel overlapping the vertical projection of the first data line D1 on the display panel is larger. This increases the overlapping area of ​​the vertical projection of the first shielding part 51 on the display panel overlapping the vertical projection of the first data line D1 on the display panel, thereby increasing the load on the first data line D1 and making the loads on the first data line D1 and the second data line D2 more similar, thus improving display uniformity.

[0039] Meanwhile, by increasing the width along the second direction Y of the portion where the vertical projection of the first shielding part 51 on the display panel overlaps with the vertical projection of the first data line D1 on the display panel, the overlap area of ​​the vertical projection of the first shielding part 51 on the display panel and the vertical projection of the first data line D1 on the display panel is realized, thereby without affecting the original layout and size of the data line D, thus simplifying the manufacturing process of the display panel.

[0040] Figure 6 This is another schematic diagram of the layout structure of the display panel provided in this disclosure, for reference. Figure 1 , Figure 3 and Figure 6 In some alternative embodiments, the first power supply voltage signal line PVDD1 is multiplexed as a capacitor compensation unit 20; The first power supply voltage signal line PVDD1 includes a first sub-part PVDD11 and a second sub-part PVDD12. The vertical projection of the first sub-part PVDD11 on the display panel at least partially overlaps with the vertical projection of the first data line D1 on the display panel, and the vertical projection of the second sub-part PVDD12 on the display panel at least partially overlaps with the vertical projection of the second data line D1 on the display panel. At least the overlapping area of ​​the vertical projection of the first sub-part PVDD11 on the display panel and the vertical projection of the first data line D1 on the display panel is greater than the overlapping area of ​​the vertical projection of the second sub-part PVDD12 on the display panel and the vertical projection of the second data line D2 on the display panel.

[0041] Specifically, the first power supply voltage signal line PVDD1 includes a first sub-section PVDD11 and a second sub-section PVDD12. The vertical projection of the first sub-section PVDD11 onto the display panel at least partially overlaps with the vertical projection of the first data line D1 onto the display panel, and the vertical projection of the second sub-section PVDD12 onto the display panel at least partially overlaps with the vertical projection of the second data line D1 onto the display panel. The overlapping area of ​​the vertical projections of the first sub-section PVDD11 and the first data line D1 onto the display panel is greater than the overlapping area of ​​the vertical projections of the second sub-section PVDD12 and the second data line D2 onto the display panel. That is, by increasing the overlapping area of ​​the vertical projections of the first sub-section PVDD11 and the first data line D1 onto the display panel, the load on the first data line D1 is increased, making the loads on the first data line D1 and the second data line D2 more similar, thereby improving display uniformity. Meanwhile, by reusing the first power supply voltage signal line PVDD1 as the capacitor compensation section 20, there is no need to set up a separate capacitor compensation section 20, which helps to reduce process complexity and avoid wiring conflicts or area waste caused by the addition of new structures. This helps to improve the space utilization of the display panel, so that the display panel can maintain the existing pixel density design.

[0042] It should be noted that the overlap area between the vertical projection of the first sub-part PVDD11 on the display panel and the vertical projection of the first data line D1 on the display panel can be set according to actual needs, and will not be elaborated here.

[0043] Continue to refer to Figure 1 , Figure 3 and Figure 6 In some alternative embodiments, at least a portion of the first sub-part PVDD11 has a width along the second direction Y that is greater than the width of the second sub-part PVDD12 along the second direction Y.

[0044] Specifically, at least a portion of the width of the first sub-part PVDD11 along the second direction Y is greater than the width of the second sub-part PVDD12 along the second direction Y. This results in the overlap area of ​​the vertical projection of the first sub-part PVDD11 on the display panel and the vertical projection of the first data line D1 on the display panel being greater than the overlap area of ​​the vertical projection of the second sub-part PVDD12 on the display panel and the vertical projection of the second data line D2 on the display panel. In other words, the width of the first sub-part PVDD11 along the second direction Y is larger, thereby increasing the overlap area of ​​the vertical projection of the first sub-part PVDD11 on the display panel and the vertical projection of the first data line D1 on the display panel. This increases the load on the first data line D1, making the loads on the first data line D1 and the second data line D2 more similar, thereby improving display uniformity.

[0045] Meanwhile, by increasing the width of the first sub-part PVDD11 along the second direction Y, the overlap area of ​​the vertical projection of the first sub-part PVDD11 on the display panel and the vertical projection of the first data line D1 on the display panel is realized, so as not to affect the original layout and size of the data line D, thereby simplifying the manufacturing process of the display panel.

[0046] Figure 7 This is another schematic diagram of the layout structure of the display panel provided in this disclosure, for reference. Figure 1 , Figure 3 and Figure 7 In some alternative embodiments, the display panel includes a plurality of first signal line groups 41 arranged along the second direction Y. The first signal line group 41 includes a reference voltage signal line VREF and a first power supply voltage signal line PVDD1. The vertical projection of the pixel circuit 11 on the display panel overlaps with the vertical projection portions of the reference voltage signal line VREF and the first power supply voltage signal line PVDD1 in the same group of first signal line groups 41 on the display panel. Along the second direction Y, the vertical projection of the capacitor compensation unit 20 on the display panel is located on the same side of the vertical projection of the first power supply voltage signal line PVDD1 in the same group of first signal lines 41 as the reference voltage signal line VREF on the display panel.

[0047] Specifically, the display panel includes multiple first signal line groups 41 arranged along the second direction Y. Each first signal line group 41 includes a reference voltage signal line VREF and a first power supply voltage signal line PVDD1. A pixel circuit 11 is only configured corresponding to the reference voltage signal line VREF and the first power supply voltage signal line PVDD1 in the same first signal line group 41. The vertical projection of the pixel circuit 11 onto the display panel overlaps with the vertical projection of the reference voltage signal line VREF and the first power supply voltage signal line PVDD1 in the same first signal line group 41. Along the second direction Y, there is more space on the side of the vertical projection of the first power supply voltage signal line PVDD1 in the same first signal line group 41 that is farther from the vertical projection of the reference voltage signal line VREF on the display panel. Along the second direction Y, the vertical projection of the capacitor compensation unit 20 onto the display panel is located on the side of the vertical projection of the first power supply voltage signal line PVDD1 in the same group of first signal lines 41 that is far from the vertical projection of the reference voltage signal line VREF. This allows the capacitor compensation unit 20 to be installed in the gap space on the side of the first power supply voltage signal line PVDD1 in the same group of first signal lines 41 that is far from the reference voltage signal line VREF. The installation of the capacitor compensation unit 20 does not affect the original layout design of the pixel circuit 11, thereby simplifying the manufacturing process of the display panel. Furthermore, the capacitor compensation unit 20 does not require additional space, utilizing the free space in the original layout design of the pixel circuit 11, which helps improve the space utilization of the display panel, allowing the display panel to maintain its existing pixel density design.

[0048] Figure 8 This is another schematic diagram of the layout structure of the display panel provided in this disclosure, for reference. Figure 1 , Figure 3 and Figure 8 Optionally, along the second direction Y, the capacitor compensation part 20 disposed on the side of the vertical projection of the first power supply voltage signal line PVDD1 on the display panel away from the vertical projection of the reference voltage signal line VREF on the display panel in the same group of first signal lines 41 can be disposed on the first metal layer MC. That is, the capacitor compensation part 20, the reference voltage signal line VREF and the first power supply voltage signal line PVDD1 can be made of the same material and in the same process. The process of manufacturing the reference voltage signal line VREF and the first power supply voltage signal line PVDD1 can be reused to manufacture the capacitor compensation part 20, which helps to reduce the process and reduce production costs.

[0049] Meanwhile, in the first metal layer MC, along the second direction Y, there is a large gap space on the side of the first power supply voltage signal line PVDD1 in the same group of first signal lines 41 that is far away from the reference voltage signal line VREF. Setting the capacitor compensation part 20 in this gap space is beneficial to increasing the setting area of ​​the capacitor compensation part 20, thereby further increasing the load on the first data line D1.

[0050] It should be noted that, along the second direction Y, the capacitor compensation part 20 provided on the side of the vertical projection of the first power supply voltage signal line PVDD1 on the display panel away from the vertical projection of the reference voltage signal line VREF on the display panel in the same group of first signal lines 41 can also be provided on other metal layers, as long as the capacitor compensation part 20 and the first data line D1 are provided on different film layers. This disclosure will not elaborate on them here.

[0051] Figure 9 This is another schematic diagram of the layout structure of the display panel provided in this disclosure, for reference. Figure 1 , Figure 3 and Figure 9 Optionally, along the second direction Y, a capacitor compensation part 20 can be provided simultaneously between the reference voltage signal line VREF and the first power supply voltage signal line PVDD1 in the same group of first signal lines 41, and on the side of the vertical projection of the first power supply voltage signal line PVDD1 in the same group of first signal lines 41 away from the vertical projection of the reference voltage signal line VREF on the display panel. This is beneficial to increase the load on the first data line D1, so that the load on the first data line D1 and the second data line D2 tend to be the same, thereby improving the display uniformity.

[0052] It should be noted that whether a capacitor compensation part 20 is provided between the reference voltage signal line VREF and the first power supply voltage signal line PVDD1 in the same group of first signal lines 41, and on the side of the vertical projection of the first power supply voltage signal line PVDD1 in the same group of first signal lines 41 away from the vertical projection of the reference voltage signal line VREF on the display panel, can be flexibly set according to requirements. It is only necessary to ensure that the load on the first data line D1 and the second data line D2 tends to be the same. This disclosure will not elaborate further here.

[0053] Continue to refer to Figure 1 , Figure 3 and Figure 9 In some optional embodiments, the display panel further includes multiple scan signal lines S and multiple light emission control signal lines EMIT, both of which extend along the first direction X and are electrically connected to the pixel circuit 11. The vertical projection of the capacitor compensation unit 20 on the display panel does not overlap with the vertical projection of the scan signal line S on the display panel, and the vertical projection of the capacitor compensation unit 20 on the display panel does not overlap with the vertical projection of the light emission control signal line EMIT on the display panel.

[0054] Specifically, the display panel also includes multiple scan signal lines S and multiple light emission control signal lines EMIT. Both the scan signal lines S and the light emission control signal lines EMIT extend along a first direction X and are electrically connected to the pixel circuit 11. The scan signal lines S control some of the switching transistors in the pixel circuit 11, triggering the charging or data writing process of the pixel circuit 11. The light emission control signal lines EMIT control some of the switching transistors in the pixel circuit 11, thereby controlling the on / off time of the organic light-emitting diodes (OLEDs). The vertical projection of the capacitor compensation unit 20 onto the display panel does not overlap with the vertical projection of the scan signal lines S and EMIT, thus reducing the coupling of the capacitor compensation unit 20 to the scan signal lines S and EMIT and preventing pixel display abnormalities or driving timing misalignments caused by signal distortion on the scan signal lines S and EMIT.

[0055] It should be noted that the capacitance compensation unit 20 can be flexibly set according to the arrangement of the scan signal line S and the light emission control signal line EMIT. It is only necessary to ensure that the vertical projection of the capacitance compensation unit 20 on the display panel does not overlap with the vertical projection of the scan signal line S on the display panel, and that the vertical projection of the capacitance compensation unit 20 on the display panel does not overlap with the vertical projection of the light emission control signal line EMIT on the display panel. This disclosure will not elaborate further here.

[0056] like Figure 10 As shown, Figure 10 This is a plan view of a display device provided in this disclosure. This embodiment provides a display device 1000, which includes a display panel 100 provided in this disclosure embodiment. It is understood that the display device provided in this disclosure embodiment can be any electronic product with display function, including but not limited to the following categories: mobile phones, televisions, laptops, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, vehicle displays, medical devices, industrial control equipment, touch interactive terminals, etc. This disclosure embodiment does not make any special limitations on these categories.

[0057] The display device provided in this disclosure has the same technical features as the display panel provided in the above embodiments, so it can also solve the same technical problems and achieve the same technical effects.

[0058] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0059] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that, include: A plurality of pixel circuit columns arranged along a first direction, the pixel circuit columns including a plurality of pixel circuits arranged along a second direction, the pixel circuit columns including a first pixel circuit column and a second pixel circuit column, wherein the number of pixel circuits in the first pixel circuit column is less than the number of pixel circuits in the second pixel circuit column, wherein the first direction and the second direction intersect. Multiple data lines are arranged along the first direction, the data lines extend along the second direction, the data lines are correspondingly arranged with the pixel circuit column, and the data lines are electrically connected to each pixel circuit in the corresponding pixel circuit column. The data lines include a first data line and a second data line, the first data line is correspondingly arranged with the first pixel circuit column, and the second data line is correspondingly arranged with the second pixel circuit column. A capacitance compensation section is provided, wherein the vertical projection of the capacitance compensation section on the display panel at least partially overlaps with the vertical projection of the first data line on the display panel, and the capacitance compensation section and the data line are located in different film layers.

2. The display panel according to claim 1, characterized in that, The capacitance compensation unit is located in the vertical projection of the display panel between the vertical projections of two adjacent pixel circuits along the first direction.

3. The display panel according to claim 1, characterized in that, The display panel further includes a first metal layer, which includes a plurality of reference voltage signal lines extending along the first direction and a plurality of first power supply voltage signal lines extending along the first direction. The reference voltage signal lines and the first power supply voltage signal lines are both electrically connected to the pixel circuit. The capacitance compensation section is located in the first metal layer.

4. The display panel according to claim 3, characterized in that, The display panel includes a plurality of first signal line groups arranged along the second direction. Each first signal line group includes a reference voltage signal line and a first power supply voltage signal line. The vertical projection of the pixel circuit on the display panel overlaps with the vertical projection portion of the reference voltage signal line and the first power supply voltage signal line in the same first signal line group on the display panel. Along the second direction, in at least a portion of the first signal line group, the capacitor compensation section is provided between the reference voltage signal line and the first power supply voltage signal line.

5. The display panel according to claim 4, characterized in that, The first metal layer further includes a shielding portion. Along the second direction, in the same first signal line group, the shielding portion is disposed between the reference voltage signal line and the first power supply voltage signal line, and the shielding portion is multiplexed as the capacitor compensation portion. The shielding portion includes a first shielding portion and a second shielding portion. The vertical projection of the first shielding portion on the display panel at least partially overlaps with the vertical projection of the first data line on the display panel. The vertical projection of the second shielding portion on the display panel at least partially overlaps with the vertical projection of the second data line on the display panel. At least a portion of the overlap area between the vertical projection of the first shielding portion on the display panel and the vertical projection of the first data line on the display panel is greater than the overlap area between the vertical projection of the second shielding portion on the display panel and the vertical projection of the second data line on the display panel.

6. The display panel according to claim 5, characterized in that, At least a portion of the overlap between the vertical projection of the first shielding portion on the display panel and the vertical projection of the first data line on the display panel, along the second direction, has a width greater than the width of the overlap between the vertical projection of the second shielding portion on the display panel and the vertical projection of the second data line on the display panel, along the second direction.

7. The display panel according to claim 4, characterized in that, The first power supply voltage signal line is multiplexed into the capacitor compensation section; The first power supply voltage signal line includes a first sub-section and a second sub-section. The vertical projection of the first sub-section on the display panel at least partially overlaps with the vertical projection of the first data line on the display panel. The vertical projection of the second sub-section on the display panel at least partially overlaps with the vertical projection of the second data line on the display panel. At least a portion of the vertical projection of the first sub-part onto the display panel and the vertical projection of the first data line onto the display panel overlap in area greater than the vertical projection of the second sub-part onto the display panel and the vertical projection of the second data line onto the display panel.

8. The display panel according to claim 7, characterized in that, At least a portion of the width of the first sub-part along the second direction is greater than the width of the second sub-part along the second direction.

9. The display panel according to claim 1, characterized in that, The display panel includes a plurality of first signal line groups arranged along the second direction. Each first signal line group includes a reference voltage signal line and a first power supply voltage signal line. The vertical projection of the pixel circuit on the display panel overlaps with the vertical projection portion of the reference voltage signal line and the first power supply voltage signal line in the same first signal line group on the display panel. Along the second direction, the vertical projection of the capacitor compensation unit on the display panel is located on the side of the vertical projection of the first power supply voltage signal line on the display panel that is away from the vertical projection of the reference voltage signal line on the display panel in the same group of the first signal lines.

10. The display panel according to claim 1, characterized in that, The display panel also includes multiple scanning signal lines and multiple light emission control signal lines, both of which extend along the first direction and are electrically connected to the pixel circuit. The vertical projection of the capacitor compensation unit on the display panel does not overlap with the vertical projection of the scanning signal line on the display panel, and the vertical projection of the capacitor compensation unit on the display panel does not overlap with the vertical projection of the light emission control signal line on the display panel.

11. A display device, characterized in that, The display device includes the display panel as described in any one of claims 1-10.

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