Storage circuit verification system and storage circuit verification method

Abstract

The present invention relates to a memory circuit verification system and a memory circuit verification method, the memory circuit verification system comprising: a memory circuit for storing data; the storage model is connected with the storage circuit, and the storage model is used for simulating functions of the storage circuit, verifying data of the storage circuit and initializing the storage circuit; and the verification environment is connected with the storage model and is used for configuring the storage model. The storage circuit verification method comprises the following steps: when a data circuit writes data into a storage circuit, synchronously storing the written data into a storage matrix of a storage model; when the data circuit reads the data from the storage circuit, the storage circuit returns the data to the data circuit according to the read address, meanwhile, the storage model synchronously detects the returned data of the storage circuit and compares the returned data with the data of the corresponding address in the storage matrix of the storage model, and if the returned data are not matched with the data of the corresponding address in the storage matrix of the storage model, an error message is reported to the verification environment.

Description

Technical Field

[0001] This invention relates to the field of storage circuit verification technology, and in particular to a storage circuit verification system and a storage circuit verification method. Background Technology

[0002] Storage circuits are widely used in digital circuit chips, responsible for data storage. These circuits often contain a wide variety of storage cells. When verifying storage circuits, the initialization and read / write access checks of these cells are crucial. Furthermore, due to adjustments in physical implementation requirements during project execution, the organization of storage cells often changes frequently; therefore, improving the robustness of the verification method is also critical.

[0003] Current conventional methods for verifying memory circuits typically rely on data producers or consumers accessing the memory circuits through a front-door to perform data read / write checks, and then using the verification environment to access the memory circuits through a back-door to complete initialization. However, these methods often require the development of complex verification stimuli, and the verification environment needs frequent adjustments and modifications as the memory cell structure changes, posing significant challenges to the verification process. Summary of the Invention

[0004] To address at least some of the problems mentioned above in the prior art, the present invention provides a storage circuit verification system, comprising: Storage circuitry, used to store data; A storage model, connected to the storage circuit, is used to simulate the function of the storage circuit, verify the data of the storage circuit, and initialize the storage circuit; and A verification environment, which is connected to the storage model, is used to configure the storage model.

[0005] Furthermore, the storage model includes: A storage matrix is ​​used to simulate storage circuits for data storage. A front door port, connected to the storage circuit, is configured to perform the following actions: In monitoring mode, the read and write behaviors of the storage circuit ports are detected, and data and address information are obtained. Corresponding operations are then performed, including: if the current gate port detects a write behavior of the storage circuit's write port, the data to be written and the write address are sent to the data access module; if the current gate port detects a read behavior of the storage circuit's read port, the return data from the storage circuit is obtained and sent to the automatic comparison module, and the read address is obtained and sent to the data access module. In drive mode, the storage circuit is initialized and data is written to the storage circuit; The data access module is configured to perform the following actions: Receive the read address sent by the front door port, and read data from the storage matrix according to the read address; Receive the data to be written and the write address sent by the front door port, and store the data to be written into the storage matrix according to the write address; The automatic comparison module is configured to perform the following actions: The data returned by the storage circuit from the front gate port is compared with the data sent by the data access module.

[0006] Furthermore, the storage model also includes a configuration information module, which is connected to the verification environment and is used to configure the type of the front door port of the storage model, the address range to be detected in the storage matrix, the mode of initializing the storage circuit, and automatic comparison enable.

[0007] Furthermore, it also includes a data circuit connected to the storage circuit, the data circuit being used to generate data and store the data in the storage circuit and / or read data from the storage circuit.

[0008] This invention provides a method for verifying storage circuits, comprising: When the data circuit writes data to the storage circuit, the written data is simultaneously stored in the storage matrix of the storage model; and When the data circuit reads data from the storage circuit, the storage circuit returns the data to the data circuit according to the read address. At the same time, the storage model synchronously detects the returned data from the storage circuit and compares it with the data at the corresponding address in its own storage matrix. If they do not match, an error message is reported to the verification environment.

[0009] Furthermore, when the data circuit writes data to the storage circuit, the written data is simultaneously stored in the storage matrix of the storage model, including: When the front gate port of the storage model detects the write behavior of the write port of the storage circuit, it obtains the data to be written and the write address, and sends them to the data access module of the storage model. The data access module writes the data to be written into the storage matrix according to the write address.

[0010] Furthermore, when the data circuit reads data from the storage circuit, the storage circuit returns data to the data circuit according to the read address. Simultaneously, the storage model synchronously detects the returned data from the storage circuit and compares it with the data at the corresponding address in its own storage matrix. If a mismatch is found, an error message is reported to the verification environment, including: When the front gate port of the storage model detects the read behavior of the storage circuit read port, it obtains the read address and the return data of the storage circuit. The front gate port sends the return data of the storage circuit to the automatic comparison module of the storage model, and at the same time, the front gate port sends the read address to the data access module of the storage model. The data access module reads data from the storage matrix according to the read address and sends it to the automatic comparison module; and The automatic comparison module compares the data returned by the storage circuit with the data sent by the data access module. If they do not match, it reports an error message to the verification environment.

[0011] Furthermore, it also includes: The storage model initializes the storage circuitry based on the configuration information sent by the verification environment.

[0012] Furthermore, the initialization of the storage circuitry by the storage model based on the configuration information sent by the verification environment includes: The storage model initializes the storage circuit by accessing and writing to the storage circuit through the front door, based on the configuration information of the verification environment. The configuration information includes the interface information and address space of the storage circuit.

[0013] Furthermore, when initializing the storage circuit in the storage model, the data circuit does not perform write operations on the storage circuit.

[0014] The present invention has at least the following beneficial effects: The storage circuit can be verified using the storage model, eliminating the need to develop special stimuli for storage circuit verification and reducing the verification workload. The front-door port of the storage model has rich implementation methods that can match different storage circuit interfaces. The information configuration module, data access module and automatic comparison module inside the storage model can be fully reused, reducing the duplication of development of the verification environment. The storage circuit verification method based on the storage model has good robustness: First, the initialization of the storage circuit is independent of the structure of the storage cell, and subsequent changes to the storage cell do not require updating the verification environment; Second, due to the existence of the storage model and the automatic comparison mechanism to ensure the data consistency between the storage model and the storage circuit, the verification environment can use a backdoor to read the data of the storage model when needed. The backdoor access has the same effect on the storage model as it does on the storage circuit, and it is decoupled from the storage cell structure; Moreover, the verification environment does not consume simulation time by accessing the storage model through the backdoor. Attached Figure Description

[0015] To further illustrate the above and other advantages and features of the various embodiments of the present invention, a more specific description of the embodiments of the invention will be presented with reference to the accompanying drawings. It is to be understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope. In the drawings, identical or corresponding parts will be indicated by identical or similar reference numerals for clarity.

[0016] Figure 1A schematic diagram of a storage circuit verification system according to an embodiment of the present invention is shown.

[0017] Figure 2 A schematic diagram of a storage model according to an embodiment of the present invention is shown.

[0018] Figure 3 A schematic diagram of a storage verification system during a write operation according to an embodiment of the present invention is shown.

[0019] Figure 4 A schematic diagram of a storage verification system during a read operation according to an embodiment of the present invention is shown.

[0020] Figure 5 A schematic diagram of a storage verification system during the initialization of a storage circuit according to an embodiment of the present invention is shown. Detailed Implementation

[0021] It should be noted that the components in the accompanying drawings may be shown exaggerated for illustrative purposes and may not be to scale.

[0022] In this invention, the various embodiments are merely intended to illustrate the solutions of the invention and should not be construed as limiting.

[0023] In this invention, unless otherwise specified, the quantifiers “a” and “one” do not exclude scenarios involving multiple elements.

[0024] It should also be noted that, in the embodiments of the present invention, only a portion of the parts or components may be shown for clarity and simplicity. However, those skilled in the art will understand that, under the teachings of the present invention, the required parts or components can be added as needed for specific scenarios.

[0025] It should also be noted that within the scope of this invention, the terms "same", "equal", and "equal to" do not mean that the two values ​​are absolutely equal, but allow for a certain reasonable error. In other words, the terms also cover "substantially the same", "substantially equal", and "substantially equal to".

[0026] It should also be noted that in the description of this invention, the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not explicitly or implicitly suggest that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0027] Furthermore, the embodiments of the present invention describe the process steps in a specific order. However, this is only for the convenience of distinguishing each step, and is not a limitation on the order of each step. In different embodiments of the present invention, the order of each step can be adjusted according to the process.

[0028] Due to the diverse characteristics of memory circuits and frequent design iterations, conventional verification methods struggle to avoid complex verification stimulus development and maintain high robustness of the verification process, resulting in significant consumption of verification resources, extended verification cycles, and marked constraints on overall verification efficiency and reusability.

[0029] This invention addresses the shortcomings of conventional verification methods by providing a storage circuit verification system and method that exhibits good robustness and can significantly improve verification efficiency.

[0030] Figure 1 A schematic diagram of a storage circuit verification system according to an embodiment of the present invention is shown.

[0031] like Figure 1 As shown, a storage circuit verification system includes a data circuit 101, a storage circuit 102, a storage model 103, and a verification environment 104. The data circuit 101 is connected to the storage circuit 102, the storage model 103 is connected to the storage circuit 102, the storage model 103 is connected to the verification environment 104, and the storage model 103 is integrated into the verification environment 104.

[0032] Data circuit 101 is configured to generate data and store the data in storage circuit 102 and / or read data from storage circuit 102. Data circuit 101 is a data generation circuit or a data usage circuit.

[0033] Storage circuit 102 is configured to store data to meet subsequent data demands. Storage circuit 102 includes a storage matrix, a write port, and a read port. The storage matrix, composed of several storage cells, is used to store data. The write port is used to write data to the storage cells of the storage matrix, and the read port is used to read data from the storage cells of the storage matrix. Storage circuit 102 also includes a front gate port.

[0034] Verification environment 104 is an environment used to verify the storage circuitry, which allows for the configuration of the storage model and data access.

[0035] Storage model 103 is used to simulate the function of the storage circuit, verify the data of the storage circuit, and initialize the storage circuit. When a write operation is detected at the write port of the storage circuit, storage model 103 acquires the data to be written and stores it; when a read operation is detected at the read port of the storage circuit, it acquires the return data of the storage circuit and compares it with the data it has stored.

[0036] When the data circuit writes data to the storage circuit, the storage model 103 cannot verify the written data by comparison. However, when the data circuit reads data from the storage model 103, the storage model 103 can verify whether the data read from the storage model 103 is correct by comparing it with the data stored in itself, thereby verifying whether the data stored in the storage circuit is correct.

[0037] Figure 2 A schematic diagram of a storage model according to an embodiment of the present invention is shown. Figure 3 A schematic diagram of a storage verification system during a write operation according to an embodiment of the present invention is shown. Figure 4 A schematic diagram of a storage verification system during a read operation according to an embodiment of the present invention is shown.

[0038] Storage model 103 is a verification development component, integrated into verification environment 104 for verifying storage circuit 102. For example... Figure 2 As shown, the storage model 103 includes a storage matrix 201, a front door port 202, a configuration information module 203, a data access module 204, and an automatic comparison module 205.

[0039] The storage matrix 201 of the storage model 103 is used to simulate the storage cells of the storage circuit 102 for data storage.

[0040] The front gate port 202 connects to the storage circuit 102. The front gate port 202 typically operates in monitoring mode, detecting read and write activity at the storage circuit 102's ports, acquiring data and address information, and executing corresponding operations. When the front gate port 202 detects write activity at the storage circuit 102's write port, it sends the data to be written and the write address to the data access module 204. When the front gate port 202 detects read activity at the storage circuit 102's read port, it acquires the return data from the storage circuit 102 and sends it to the automatic comparison module 205, while also sending the read address to the data access module 204. Simultaneously, the data returned by the storage circuit 102 to the data circuit 101 remains unaffected.

[0041] In drive mode, front gate port 202 initializes storage circuit 102 and writes data to storage circuit 102. Front gate port 202 often includes rich implementation methods to match different storage circuit interfaces, and can be extended according to new storage circuit interfaces.

[0042] For example, a storage circuit port access signal might be: ce / we / addr / wdata / mask / rdata, used for enable / read / write control / address / write data / write mask / read data respectively. A corresponding interface can be defined, with its internal member variables corresponding to these port signals. After instantiating the interface in the environment, it's connected to the front-door port of the storage circuit, and simultaneously passed to the storage model. This allows the model to monitor the corresponding storage circuit. When new or different types of storage circuit port signals appear, a new interface component needs to be constructed and processed similarly. A storage model can support multiple different interfaces; simply set the corresponding interface numbers in the configuration information.

[0043] The configuration information module 203 is used to configure the type of the front-door port of the storage model 103, the address range to be detected in the storage matrix 201, the initialization mode of the storage circuit 102, and automatic comparison enable information. When the storage model requires automatic comparison function, the automatic comparison module needs to be enabled. Not all data in the storage matrix needs to be compared and written, so the address range to be detected needs to be set. The type of the front-door port of the storage model 103 needs to be configured according to the interface type of the storage circuit 102. The initialization mode of the storage circuit 102 refers to the method used to initialize the storage circuit 102, such as using the front-door access method.

[0044] The verification environment 104 controls the configuration information module 203 to configure the type of the front gate port of the current storage model 103, the address range to be detected in the storage matrix 201, the mode of initializing the storage circuit 102, and the automatic comparison enable information.

[0045] The data access module 204 is used to write data to or read data from the storage matrix of the storage model 103.

[0046] In one embodiment, if the current gate port 202 detects a write operation on the write port of the storage circuit 102, it sends the data to be written and the write address to the data access module 204. The data access module 204 then stores the data in the storage matrix 201 according to the write address. If the current gate port 202 detects a read operation on the read port of the storage circuit 102, it obtains the return data and read address from the storage circuit 102 and sends the read address to the data access module 204. The return data from the storage circuit 102 is then sent to the automatic comparison module 205. The data access module 204 reads the data from the storage matrix 201 according to the read address and sends it to the automatic comparison module 205.

[0047] In another embodiment, when the verification environment 104 needs to view data at one or more addresses in the storage matrix 201 of the storage model 103, the verification environment 104 controls the data access module 204 to read the data in the storage matrix 201. Since the storage model 103 guarantees the correctness of the storage circuit 102, obtaining data at a specific address through the storage model 103 is much faster and more convenient than obtaining data through the actual storage circuit 102. This data reading is a backdoor access, does not consume simulation time, and does not require consideration of the complexity of the specific storage circuit, such as the organization and splicing methods of the storage particles. These methods often change frequently in projects. Obtaining or updating content through the storage model rather than the storage circuit is much more convenient.

[0048] The data access module 204 does not consume simulation time when performing read and write operations.

[0049] The automatic comparison module 205 compares the data returned from the storage circuit 102 sent by the front door port 202 with the data sent by the data access module 204. When a data inconsistency is detected, an error message is reported to the verification environment 104.

[0050] A storage circuit verification method based on a storage model includes detecting and checking the read and write behaviors of the storage circuit 102 and initializing the storage circuit.

[0051] When the data circuit 101 initiates data writing or reading from the storage circuit 102, the relevant operations will be monitored and checked. Specifically, such as... Figure 3 As shown, when the data circuit 101 writes data to the storage circuit 102, the written data is also synchronously stored in the storage matrix 201 of the storage model 103. When the front gate port 202 of the storage model 103 detects the write behavior of the write port of the storage circuit 102, it obtains the data to be written and the write address, and sends them to the data access module 204. The data access module 204 writes the data to be written into the storage matrix 201 according to the write address.

[0052] like Figure 4 As shown, when the data circuit 101 reads data from the storage circuit 102, the storage circuit 102 returns the corresponding data according to the read address. At this time, the storage model 103 synchronously detects the returned data of the storage circuit 102 and compares it with the data at the corresponding address in its own storage matrix. If a mismatch (dissimilarity) occurs, an error message is reported to the verification environment 104.

[0053] Specifically, the front gate port 202 detects the read behavior of the read port of the storage circuit 102, obtains the read address and the return data of the storage circuit 102, and sends the return data of the storage circuit 102 to the automatic comparison module 205. The front gate port 202 also sends the read address to the data access module 204. The data access module 204 reads data from the storage matrix 201 according to the read address and sends it to the automatic comparison module 205. The automatic comparison module 205 compares the return data of the storage circuit 102 with the data sent by the data access module 204. If the two do not match, an error message is reported to the verification environment 104.

[0054] In the above process, all verification of the storage circuits is based entirely on the embedded storage model, and the data circuits and storage circuits are unaware of and unaffected by it. Therefore, there is no need to develop dedicated verification stimuli to trigger the data circuits to verify the storage circuits. It is only necessary to integrate the storage model into the verification environment and enable the automatic comparison mechanism to complete the verification of the storage circuits throughout the entire verification regression.

[0055] Initialization of the memory circuit is also a function that must be supported in chip verification. Conventional memory circuit initialization is divided into front-door access initialization and back-door access initialization.

[0056] Front-door initialization refers to initializing the memory circuit by developing a stimulus to trigger the data circuit to generate a write operation. The advantage of front-door initialization is that it does not require attention to the memory cell structure of the memory circuit, and only write operations are performed through the access interface. The disadvantage is that it requires the development of a dedicated stimulus, and the front-door write operation consumes simulation time.

[0057] Backdoor initialization refers to writing data to the memory circuit by accessing the design code level through the verification environment. This data will not appear on the memory circuit's access interface. The advantage of backdoor initialization is that it does not consume simulation time. The disadvantage is that the initialization method is tightly coupled with the memory cell structure of the memory circuit. Once the memory cell structure changes, the verification environment needs to be updated.

[0058] Figure 5 A schematic diagram of a storage verification system during the initialization of a storage circuit according to an embodiment of the present invention is shown.

[0059] Initializing memory circuits based on a memory model can combine the advantages of both front-door and back-door access. For example... Figure 5 As shown, storage model 103 initializes the storage circuit according to the configuration information sent by verification environment 104. The configuration information includes the interface information of the storage circuit, the address space of the storage circuit, etc.

[0060] Storage model 103 initializes storage circuit 102 by accessing and writing to storage circuit 102 through front door according to the configuration information of verification environment 104.

[0061] The verification environment 104 controls the data access module 204 of the storage model 103 to update the prepared data into the storage matrix 201. Then, it starts the initialization function of the storage model 103, takes over the front gate port of the storage circuit 102, and writes the data in the storage matrix 201 of the storage model 103 into the storage circuit 102. This can initialize the storage circuit while avoiding the need to deal with issues such as the organization of storage circuit particles and address splicing, greatly improving convenience and ease of use.

[0062] Note that when initializing the storage circuit 102, the write conflict between the storage model 103 and the data circuit 101 to the storage circuit 102 needs to be handled properly. Generally, only one of the storage model 103 and the data circuit 101 can be operated on at the same time. The storage model 103 can drive the storage circuit 102 by forced drive, and the front gate port of the storage circuit 102 is released after initialization.

[0063] The memory circuit verification method based on the memory model of the present invention can greatly improve verification efficiency: First, the storage circuit is verified using the storage model, eliminating the need to develop dedicated stimuli for storage circuit verification and reducing the verification workload.

[0064] Secondly, the front-door port of the storage model contains rich implementation methods that can match different storage circuit interfaces. Therefore, the storage model can be adapted to different storage circuits. Moreover, the internal information configuration module, data access module, and automatic comparison module of the storage model can be completely reused, reducing the duplication of development of the verification environment.

[0065] Finally, the memory circuit verification method based on the memory model exhibits good robustness. Firstly, the initialization of the memory circuit is independent of the memory cell structure, and subsequent changes to the memory cells do not require updating the verification environment. Secondly, due to the existence of the memory model and the automatic comparison mechanism ensuring data consistency between the memory model and the memory circuit, the verification environment can use backdoor access methods to read the data of the memory model when needed. These backdoor accesses operate on the memory model, achieving the same effect as those operating on the memory circuit, and are decoupled from the memory cell structure. Similarly, backdoor access to the memory model by the verification environment does not consume simulation time.

[0066] While some embodiments of the present invention have been described in this application, those skilled in the art will understand that these embodiments are merely illustrative. Numerous variations, alternatives, and improvements will arise in those skilled in the art under the teachings of this invention without departing from its scope. The appended claims are intended to define the scope of the invention and thereby cover methods and structures within the scope of the claims themselves and their equivalents.

Claims

1. A storage circuit verification system, characterized in that, include: Storage circuitry, used to store data; A storage model, which is connected to the storage circuit, is used to simulate the function of the storage circuit, verify the data of the storage circuit, and initialize the storage circuit. as well as A verification environment, which is connected to the storage model, is used to configure the storage model.

2. The storage circuit verification system according to claim 1, characterized in that, The storage model includes: A storage matrix is ​​used to simulate storage circuits for data storage. A front door port, connected to the storage circuit, is configured to perform the following actions: In monitoring mode, the read and write behaviors of the storage circuit ports are detected, and data and address information are obtained. Corresponding operations are then performed, including: if the current gate port detects a write behavior of the storage circuit's write port, the data to be written and the write address are sent to the data access module; if the current gate port detects a read behavior of the storage circuit's read port, the return data from the storage circuit is obtained and sent to the automatic comparison module, and the read address is obtained and sent to the data access module. In drive mode, the storage circuit is initialized and data is written to the storage circuit; The data access module is configured to perform the following actions: Receive the read address sent by the front door port, and read data from the storage matrix according to the read address; Receive the data to be written and the write address sent by the front door port, and store the data to be written into the storage matrix according to the write address; The automatic comparison module is configured to perform the following actions: The data returned by the storage circuit from the front gate port is compared with the data sent by the data access module.

3. The storage circuit verification system according to claim 2, characterized in that, The storage model also includes a configuration information module, which is connected to the verification environment and is used to configure the type of the front door port of the storage model, the address range to be detected in the storage matrix, the mode of initializing the storage circuit, and automatic comparison enable.

4. The storage circuit verification system according to claim 1, characterized in that, It also includes a data circuit connected to the storage circuit, the data circuit being used to generate data and store the data in the storage circuit and / or read data from the storage circuit.

5. A method for verifying a storage circuit, characterized in that, include: When the data circuit writes data to the storage circuit, the written data is synchronously stored in the storage matrix of the storage model; as well as When the data circuit reads data from the storage circuit, the storage circuit returns the data to the data circuit according to the read address. At the same time, the storage model synchronously detects the returned data from the storage circuit and compares it with the data at the corresponding address in its own storage matrix. If they do not match, an error message is reported to the verification environment.

6. The storage circuit verification method according to claim 5, characterized in that, When the data circuit writes data to the storage circuit, the written data is synchronously stored in the storage matrix of the storage model, including: When the front gate port of the storage model detects the write behavior of the write port of the storage circuit, it obtains the data to be written and the write address, and sends them to the data access module of the storage model. The data access module writes the data to be written into the storage matrix according to the write address.

7. The storage circuit verification method according to claim 5, characterized in that, When the data circuit reads data from the storage circuit, the storage circuit returns the data to the data circuit according to the read address. Simultaneously, the storage model detects the returned data from the storage circuit and compares it with the data at the corresponding address in its own storage matrix. If a mismatch is found, an error message is reported to the verification environment, including: When the front gate port of the storage model detects the read behavior of the storage circuit read port, it obtains the read address and the return data of the storage circuit. The front gate port sends the return data of the storage circuit to the automatic comparison module of the storage model, and at the same time, the front gate port sends the read address to the data access module of the storage model. The data access module reads data from the storage matrix according to the read address and sends it to the automatic comparison module; and The automatic comparison module compares the data returned by the storage circuit with the data sent by the data access module. If they do not match, it reports an error message to the verification environment.

8. The storage circuit verification method according to claim 5, characterized in that, Also includes: The storage model initializes the storage circuitry based on the configuration information sent by the verification environment.

9. The storage circuit verification method according to claim 8, characterized in that, The initialization of the storage circuitry by the storage model based on the configuration information sent by the verification environment includes: The storage model initializes the storage circuit by accessing and writing to the storage circuit through the front door, based on the configuration information of the verification environment. The configuration information includes the interface information and address space of the storage circuit.

10. The storage circuit verification method according to claim 9, characterized in that, During the initialization of the storage circuit in the storage model, the data circuit does not perform write operations on the storage circuit.

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