Electricity meter backup circuit

Abstract

This invention relates to the field of electronic circuit technology, specifically disclosing a backup power circuit for an electric meter, comprising: a voltage comparison module, a power switch, a voltage conversion module, a charging control module, a boost control module, a first NMOS transistor MN1, a second NMOS transistor MN2, an inductor L1, a capacitor C1, and a backup power supply. When the input voltage VIN is less than the operating voltage threshold, the power switch is turned off. The voltage comparison module outputs a low level to the charging control module and the boost control module. At this time, the boost control module starts working, the charging control module stops charging the backup power supply, and controls the first NMOS transistor MN1 and the second NMOS transistor MN2 to alternately turn on and off, boosting the voltage output from the backup power supply and then splitting it into two paths: one path powers the communication module, and the other path, after being stepped down by the voltage conversion module, powers the metering circuit. This invention simplifies the circuit structure and reduces the chip area.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and more specifically to a backup power circuit for an electric meter. Background Technology

[0002] In systems such as electricity meters that require continuous operation and data collection, the power outage backup power function is crucial. This function ensures that when the power grid experiences a temporary power outage, the system can seamlessly switch to the backup power source to continuously supply power to critical loads for a period of time, thereby ensuring data integrity and timely uploading.

[0003] In existing technologies, a typical power-off backup circuit comprises two relatively independent power loops: one for charging the supercapacitor (SC), and the other for boosting the energy of the supercapacitor SC for output during power outages. This charging circuit typically includes a dedicated charging power transistor and a complex substrate switching circuit (BSW). To meet the large charging current requirements, the charging power transistor is usually large, for example, 9000 micrometers wide, and is generally composed of 300 30-micrometer-wide PMOS transistors connected in parallel. The substrate switching circuit is also relatively complex, similarly increasing the chip area. During a grid power outage, another independent boost circuit is activated to raise the low voltage of the supercapacitor to the operating voltage required by the system.

[0004] However, existing solutions have the following significant drawbacks: the dedicated charging power transistor MP1 is bulky due to its need to handle large charging currents, occupying a large amount of chip area. Simultaneously, the complex structure of the substrate switching circuit (BSW) also adds to the chip area. Both of these factors contribute to a significant increase in chip manufacturing costs. Furthermore, the presence of the substrate switching circuit introduces more control nodes and potential failure points, increasing the difficulty of circuit design and layout routing, and posing a potential threat to the overall reliability of the system.

[0005] Therefore, simplifying circuit structure, reducing chip area, and improving reliability are problems that urgently need to be solved by those skilled in the art. Summary of the Invention

[0006] In view of the above problems, the present invention provides a backup power circuit for an electricity meter to overcome or at least partially solve the above problems.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] A backup power circuit for an electricity meter includes: a voltage comparison module, a power switch, a voltage conversion module, a charging control module, a boost control module, a first NMOS transistor MN1, a second NMOS transistor MN2, an inductor L1, a capacitor C1, and a backup power supply.

[0009] The voltage comparison module compares the input voltage VIN with the operating voltage threshold in real time. When the input voltage VIN is greater than or equal to the operating voltage threshold, it outputs a high level to the charging control module and the boost control module. After receiving the high level, the charging control module controls the second NMOS transistor MN2 to turn on to charge the backup power supply. After receiving the high level, the boost control module stops working. At the same time, the power switch is turned on, and the input voltage is split into two paths after passing through the power switch. One path powers the communication module, and the other path is stepped down by the voltage conversion module to power the metering circuit.

[0010] When the input voltage VIN is less than the operating voltage threshold, the power switch is turned off. At the same time, the voltage comparison module outputs a low level to the charging control module and the boost control module. After receiving the low level, the boost control module starts working. After receiving the low level, the charging control module stops the charging process of the backup power supply and controls the first NMOS transistor MN1 and the second NMOS transistor MN2 to alternately turn on and off, so that the boost control module, the first NMOS transistor MN1, the second NMOS transistor MN2, the inductor L1 and the capacitor C1 together form a boost circuit. The boost circuit boosts the voltage output by the backup power supply and then divides it into two paths: one path powers the communication module, and the other path is stepped down by the voltage conversion module to power the metering circuit.

[0011] Furthermore, one end of the power switch is connected to the input voltage VIN, and the other end serves as the working voltage node; the working voltage node is connected to the voltage conversion module, the communication module, the charging control module, the second NMOS transistor MN2, and the capacitor C1, respectively.

[0012] The voltage comparison module is a comparator, with its input terminal connected to the input voltage VIN, and its output terminal connected to the charging control module and the boost control module, respectively.

[0013] Furthermore, the backup power source is a supercapacitor SC; the charging control module includes five terminals, namely, a level receiving terminal, a working voltage input terminal VSYS, a supercapacitor voltage monitoring terminal VSC, a switch control terminal GN2, and a switch signal switching terminal SWU;

[0014] The level receiving terminal is connected to the output terminal of the voltage comparator module and is used to receive the level signal output by the voltage comparator module;

[0015] The working voltage input terminal VSYS is connected to the working voltage node and is used to input the working voltage during the charging process;

[0016] The supercapacitor voltage monitoring terminal VSC is connected to the positive terminal of the supercapacitor SC and is used to monitor the real-time voltage of the supercapacitor SC and control the charging process.

[0017] The switch control terminal GN2 is connected to the gate of the second NMOS transistor MN2, and the gate of the second NMOS transistor MN2 is also connected to the boost control module; the drain of the second NMOS transistor MN2 is connected to the working voltage node, the source is connected to the positive terminal of the supercapacitor SC through the inductor L1, and the negative terminal of the supercapacitor SC is grounded.

[0018] The switching signal terminal SWU is connected to the source of the second NMOS transistor MN2, the drain of the first NMOS transistor MN1, and the boost control module, respectively; the source of the first NMOS transistor MN1 is grounded, and its gate is connected to the boost control module.

[0019] When the level signal is high, the control signal generated by the switch control terminal GN2 of the switch signal switching terminal SWU is connected to the gate of the second NMOS transistor MN2; when the level signal is low, the control signal generated by the boost control module is connected to the gate of the second NMOS transistor MN2, so that the second NMOS transistor MN2 and the first NMOS transistor MN1 together form the synchronous rectifier of the boost circuit.

[0020] Furthermore, it also includes a capacitor Cbs, the negative terminal of which is connected between the source of the second NMOS transistor MN2 and the inductor L1, and the positive terminal is connected to the boost control module.

[0021] Furthermore, the charging control module includes a current replication circuit, a constant current control loop, a constant voltage control loop, and an enable control circuit.

[0022] The current replication circuit is used to acquire the current of the second NMOS transistor MN2 in real time and convert it into a low-power electrical signal that represents the magnitude of the charging current.

[0023] The constant current control loop is used to compare the low-power electrical signal fed back by the current replication circuit with the internal reference signal when the backup power supply voltage is lower than the preset threshold, and control the charging current to be constant based on the comparison result.

[0024] The constant voltage control loop is used to stabilize the voltage of the backup power supply at the preset threshold when the backup power supply voltage reaches the preset threshold.

[0025] The enable control circuit is used to control the constant current control loop or constant voltage control loop to work when the voltage comparator module outputs a high level, and to disconnect the second NMOS transistor MN2 when the voltage comparator module outputs a low level.

[0026] Furthermore, the current replication circuit includes: a first operational amplifier OP, a third NMOS transistor MNC2, a first PMOS transistor MPC1, and a sampling resistor Rc1;

[0027] The non-inverting input of the first operational amplifier OP is connected to the source of the second NMOS transistor MN2, the inverting input is connected to the source of the third NMOS transistor MNC2 and the source of the first PMOS transistor MPC1, and the output is connected to the gate of the first PMOS transistor MPC1.

[0028] The gate of the third NMOS transistor MNC2 is connected to the same switch control terminal GN2 as the gate of the second NMOS transistor MN2, and the drain of the third NMOS transistor MNC2 is connected to the working voltage node.

[0029] The drain of the first PMOS transistor MPC1 is grounded via the sampling resistor Rc1; the third NMOS transistor MNC2 is configured to replicate the current of the second NMOS transistor MN2 at a replication ratio of 1:k.

[0030] Furthermore, the constant current control loop includes a second operational amplifier OPC, a second PMOS transistor MPI, and a bias resistor Rb or a current source I1;

[0031] In this configuration, the non-inverting input of the second operational amplifier OPC is connected to the reference voltage VR2, the inverting input is connected to the connection node between the sampling resistor and the drain of the first PMOS transistor MPC1, and the output is connected to the gate of the second PMOS transistor MPI; the voltage at the connection node between the sampling resistor Rc1 and the drain of the first PMOS transistor MPC1 is VRc1.

[0032] The source of the second PMOS transistor MPI is connected to the working voltage node through a bias resistor Rb or a current source I1, and is connected to the switch control terminal GN2. The drain of the second PMOS transistor MPI is connected to one end of the sampling resistor RC1 and grounded.

[0033] By controlling the voltage of the control terminal GN2 of the switch, the conduction level of the second NMOS transistor MN2 is adjusted so that VRc1 is equal to the reference voltage VR2, and the current flowing through the second NMOS transistor MN2 is always equal to k×(VR2 / Rc1).

[0034] Furthermore, the constant voltage control loop includes a third operational amplifier OPV, a third PMOS transistor MPV, and voltage divider resistors Rf1 and Rf2;

[0035] The non-inverting input of the third operational amplifier OPV is connected to the reference voltage VR1, the inverting input is connected to the common node of the voltage divider resistors Rf1 and Rf2 to obtain the voltage divider feedback signal VF, and the output is connected to the gate of the third PMOS transistor MPV.

[0036] The source of the third PMOS transistor MPV is connected to the operating voltage node through a bias resistor Rb or a current source I1, and is connected to the switch control terminal GN2, while the drain is grounded.

[0037] Voltage divider resistors Rf1 and Rf2 are connected in series between the positive terminal of the backup power supply and ground;

[0038] By controlling the voltage of the control terminal GN2 of the control switch, the conduction level of the second NMOS transistor MN2 is adjusted so that the voltage divider feedback signal VF is equal to the reference voltage VR1, and the voltage of the backup power supply is always equal to VR1×(Rf1+Rf2) / Rf2.

[0039] Furthermore, the enable control circuit includes an inverter inva and a fourth NMOS transistor MNE; the input of the inverter inva receives the level signal output by the voltage comparison module, and the output is connected to the gate of the fourth NMOS transistor MNE; the drain of the fourth NMOS transistor MNE is connected to the switch control terminal GN2, and the source is grounded.

[0040] Furthermore, the boost control module includes: a boost controller, AND gates, OR gates, a fourth PMOS transistor PM4, a fifth NMOS transistor NM5, and multiple inverters inva1, inva2, inva3, invb1, invb2, invb3, and inv1;

[0041] The boost controller generates a control signal GN1 for the first NMOS transistor and a raw control signal GN2D for the second NMOS transistor; the raw control signal GN2D for the second NMOS transistor is connected to the first input terminal of the AND gate and the first input terminal of the OR gate, respectively.

[0042] The input terminal of inverter inv1 is connected to the level signal output by the voltage comparison module. The output terminal is connected to the second input terminal of AND gate, inverter inva1, inverter inva2 and inverter inva3. The output terminal of inverter inva3 is connected to the gate of the fourth PMOS transistor PM4. The source of the fourth PMOS transistor PM4 is connected to the power supply voltage, and the drain is connected to the switch control terminal GN2.

[0043] The second input terminal of the OR gate is connected to the level signal output by the voltage comparison module. The output terminal is connected to inverters invb1, invb2 and invb3 in turn. The output terminal of inverter invb3 is connected to the gate of the fifth NMOS transistor NM5. The source of the fifth NMOS transistor NM5 is connected to the switching signal switching terminal SWU and the drain is connected to the switching control terminal GN2.

[0044] As can be seen from the above technical solution, compared with the prior art, the present invention has the following beneficial effects:

[0045] 1. This invention achieves constant current-constant voltage charging by controlling MN2 when VIN is powered, and achieves voltage boost by controlling MN1 and MN2 to alternately conduct and disconnect when VIN is powered off. During the backup power charging and backup power discharging phases, the switching transistor MN2 and inductor L1 are reused, eliminating the need for the charging power transistor MP1 and BSW circuit in traditional circuits, significantly reducing chip area and manufacturing costs.

[0046] 2. This invention uses a voltage comparison module to detect the VIN voltage and generate a CEN signal. This CEN signal is then used to control the charging control module and the boost control module, enabling intelligent switching between charging and boost modes. In charging mode, the boost control module is prohibited from controlling the second switching transistor; in boost mode, the charging control module is disabled. This interlocking mechanism ensures that the two modes do not interfere with each other, improving system stability. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0048] Figure 1 This is a structural diagram of the backup power circuit for the power meter provided in an embodiment of the present invention;

[0049] Figure 2 This is a circuit structure diagram of the charging control module provided in an embodiment of the present invention;

[0050] Figure 3 This is another circuit structure diagram of the charging control module provided in an embodiment of the present invention;

[0051] Figure 4 This is a circuit diagram of the boost control module provided in an embodiment of the present invention. Detailed Implementation

[0052] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0053] like Figure 1As shown, an embodiment of the present invention discloses a backup power circuit for an electric meter, including: a voltage comparison module VDET, a power switch PSWitch, a voltage conversion module Buck, a charging control module ChCTL, a boost control module Bst, a first NMOS transistor MN1, a second NMOS transistor MN2, an inductor L1, a capacitor C1, and a backup power supply.

[0054] The voltage comparison module VDET compares the input voltage VIN with the operating voltage threshold in real time. When the input voltage VIN is greater than or equal to the operating voltage threshold, it outputs a high level to the charging control module ChCTL and the boost control module Bst. After receiving the high level, the charging control module ChCTL controls the second NMOS transistor MN2 to turn on to charge the backup power supply. After receiving the high level, the boost control module Bst stops working and disables the boost function. At the same time, the power switch PSWitch is turned on, and the input voltage is split into two paths after passing through the power switch. One path powers the communication module LD, and the other path is stepped down by the voltage conversion module Buck to power the metering circuit PMeter.

[0055] When the input voltage VIN is less than the operating voltage threshold, the power switch PSWitch is turned off. Simultaneously, the voltage comparator module VDET outputs a low level to the charging control module ChCTL and the boost control module Bst. Upon receiving the low level, the boost control module Bst begins operation. Upon receiving a low level from ChCTL, the charging control module stops charging the backup power supply and controls the first NMOS transistor MN1 and the second NMOS transistor MN2 to alternately turn on and off. This allows the boost control module Bst, the first NMOS transistor MN1, the second NMOS transistor MN2, the inductor L1, and the capacitor C1 to form a boost circuit, achieving the boost function. The boost circuit boosts the voltage output from the backup power supply and then divides it into two paths: one path powers the communication module LD, and the other path, after being stepped down by the voltage conversion module Buck, powers the metering circuit PMEter.

[0056] In this implementation, the backup power supply is a supercapacitor SC. The voltage comparison module VDET can be implemented by a comparator, comparing the VIN voltage with the operating voltage threshold. The power switch PSWitch is a power switching module, which functions as an ideal diode. When the VIN voltage is greater than the operating voltage threshold, it is fully conducting, and its output terminal serves as the operating voltage node, outputting the voltage VSYS. When the VIN voltage is less than the operating voltage threshold, it is not conducting, preventing VSYS from flowing back into VIN.

[0057] The purpose of this invention is to simplify the circuit, reduce chip area, and save costs. The principle is to reuse MN2 in the boost circuit as the charging power device. Specifically, when charging the backup power supply, MN2 draws power from VSYS and charges the supercapacitor SC via inductor L1. Compared to traditional circuits, the charging power transistor MP1 and the BSW circuit can be eliminated. Since the VSYS voltage is always higher than VSC (the typical full-charge voltage of a supercapacitor is 2.55V) in all cases, MN2 does not require substrate switching. The substrate of MN2 can always be connected to the VSC node (for NMOS transistors, the substrate is generally connected to a lower potential). The trade-off for this invention is that some components in the charging control circuit need to be high-voltage resistant (these components are inherently small), slightly increasing the chip area. However, the increased chip area is far less than the saved chip area, including the charging power transistor MP1 and the BSW circuit.

[0058] Specifically, the connection relationships between the modules in the backup power circuit of the power meter are as follows:

[0059] One end of the power switch PSWitch is connected to the input voltage VIN, and the other end serves as the working voltage node. The working voltage node is connected to the voltage conversion module Buck, the communication module LD, the charging control module ChCTL, the second NMOS transistor MN2, and the positive terminal of capacitor C1, respectively. The negative terminal of capacitor C1 is grounded.

[0060] The voltage comparison module VDET is a comparator whose input terminal is connected to the input voltage VIN, and whose output terminal is connected to the charging control module ChCTL and the boost control module Bst, respectively.

[0061] The charging control module ChCTL contains five terminals: level receiving terminal CEN, working voltage input terminal VSYS, supercapacitor voltage monitoring terminal VSC, switch control terminal GN2, and switch signal switching terminal SWU.

[0062] The level receiving terminal CEN is connected to the output terminal of the voltage comparator module VDET and is used to receive the level signal output by the voltage comparator module VDET.

[0063] The working voltage input terminal VSYS is connected to the working voltage node and is used to input the working voltage during the charging process;

[0064] The supercapacitor voltage monitoring terminal VSC is connected to the positive terminal of the supercapacitor SC and is used to monitor the real-time voltage of the supercapacitor SC and control the charging process.

[0065] The switch control terminal GN2 is connected to the gate of the second NMOS transistor MN2, and the gate of the second NMOS transistor MN2 is also connected to the boost control module Bst; the drain of the second NMOS transistor MN2 is connected to the working voltage node, and the source is connected to the positive terminal of the supercapacitor SC through the inductor L1, and the negative terminal of the supercapacitor SC is grounded.

[0066] The switching signal terminal SWU is connected to the source of the second NMOS transistor MN2, the drain of the first NMOS transistor MN1, and the boost control module Bst, respectively; the source of the first NMOS transistor MN1 is grounded, and its gate is connected to the boost control module.

[0067] When the level signal is high, the control signal generated by the switch control terminal GN2 of the switch signal switching terminal SWU is connected to the gate of the second NMOS transistor MN2; when the level signal is low, the control signal generated by the boost control module is connected to the gate of the second NMOS transistor MN2, so that the second NMOS transistor MN2 and the first NMOS transistor MN1 together form the synchronous rectifier of the boost circuit.

[0068] The specific boosting process is as follows:

[0069] After receiving a low level, the boost control module Bst receives the turn-on timing of MN1 and MN2 from the charging control module ChCTL. First, it controls the first NMOS transistor MN1 to turn on and the second NMOS transistor MN2 to turn off. The current flows out from the positive terminal of the supercapacitor SC, through the inductor L1, and then through the conducting MN1, finally returning to the negative terminal of SC. In this circuit, because MN1 is conducting, the side of inductor L1 connected to MN2 is forced to be pulled low to near ground potential, and inductor L1 enters the energy storage state.

[0070] After inductor L1 completes energy storage, control MN1 is disconnected and control MN2 is turned on. At this time, inductor L1 generates an induced voltage. The induced voltage of the inductor is superimposed with the voltage of the supercapacitor and used as the operating voltage. This voltage is used to charge capacitor C1 and supply power to LD and PMeter. When the inductor enters the next energy storage stage, capacitor C1 is used to discharge to maintain the voltage stability of the operating voltage node.

[0071] In one embodiment, the backup power circuit of the power meter further includes a capacitor Cbs, the negative terminal of which is connected between the source of the second NMOS transistor MN2 and the inductor L1, and the positive terminal is connected to the boost control module Bst.

[0072] The function of capacitor Cbs is to generate a bootstrap voltage. Generally, the threshold voltage of an NMOS is greater than zero, for example, 1V. The driving gate voltage is, for example, the VSYS voltage. This is insufficient to make the NMOS fully turn on, that is, it cannot make the voltage difference between the drain (connected to VSYS) and the source very small, for example, <100mV. In order to make the NMOS turn on better, the high level of its gate needs to be at least greater than the drain voltage of the NMOS + the threshold voltage of the NMOS. In actual design, the gate voltage of the NMOS will be greater than VSYS + 5V. This extra 5V needs to be generated by the bootstrap capacitor Cbs.

[0073] like Figure 2 The diagram shows one implementation of the charging control module ChCTL of the present invention, which specifically includes: a current replication circuit, a constant current control loop, a constant voltage control loop, and an enable control circuit.

[0074] The current replication circuit is used to acquire the current of the second NMOS transistor MN2 in real time and convert it into a low-power electrical signal that represents the magnitude of the charging current.

[0075] The constant current control loop is used to compare the low-power electrical signal fed back by the current replication circuit with the internal reference signal when the backup power supply voltage is lower than the preset threshold, and control the charging current to be constant based on the comparison result.

[0076] The constant voltage control loop is used to stabilize the voltage of the backup power supply at the preset threshold when the backup power supply voltage reaches the preset threshold.

[0077] The enable control circuit is used to control the constant current control loop or constant voltage control loop to work when the voltage comparator module outputs a high level, and to disconnect the second NMOS transistor MN2 when the voltage comparator module outputs a low level.

[0078] The specific circuit structures of the current replication circuit, constant current control loop, constant voltage control loop, and enable control circuit will be further explained below.

[0079] 1) The current replication circuit includes: a first operational amplifier OP, a third NMOS transistor MNC2, a first PMOS transistor MPC1, and a sampling resistor Rc1;

[0080] The non-inverting input of the first operational amplifier OP is connected to the source of the second NMOS transistor MN2, the inverting input is connected to the source of the third NMOS transistor MNC2 and the source of the first PMOS transistor MPC1, and the output is connected to the gate of the first PMOS transistor MPC1.

[0081] The gate of the third NMOS transistor MNC2 is connected to the same switch control terminal GN2 as the gate of the second NMOS transistor MN2, and the drain of the third NMOS transistor MNC2 is connected to the working voltage node.

[0082] The drain of the first PMOS transistor MPC1 is grounded via the sampling resistor Rc1; the third NMOS transistor MNC2 is configured to replicate the current of the second NMOS transistor MN2 at a replication ratio of 1:k.

[0083] The purpose of the current replication circuit is to replicate the current of MN2 from MNC2. The drain voltages of MNC2 and MN2 are equal (both connected to the operating voltage node, VSYS), their gate voltages are also equal (both connected to GN2), and their source voltages are also equal (controlled by the first operational amplifier OP, which controls the source voltage of MNC2 to be equal to SWU, which is the source voltage of MN2). Therefore, MNC2 replication is achieved. Figure 2 The current in MN2 is typically designed with a width-to-length ratio of MN2 to MNC2 of k:1. Therefore, the ratio of the current in MN2 to the current in MNC2 is k:1, meaning MNC2 samples 1 / k of the current in MN2. According to Kirchhoff's laws, the current in MNC2 is equal to the current in Rc1.

[0084] 2) The constant current control loop includes the second operational amplifier OPC, the second PMOS transistor MPI, and the bias resistor Rb;

[0085] In this configuration, the non-inverting input of the second operational amplifier OPC is connected to the reference voltage VR2, the inverting input is connected to the connection node between the sampling resistor and the drain of the first PMOS transistor MPC1, and the output is connected to the gate of the second PMOS transistor MPI; the voltage at the connection node between the sampling resistor Rc1 and the drain of the first PMOS transistor MPC1 is VRc1.

[0086] The source of the second PMOS transistor MPI is connected to the operating voltage node through the bias resistor Rb and connected to the switch control terminal GN2. The drain of the second PMOS transistor MPI is connected to one end of the sampling resistor RC1 and grounded.

[0087] By controlling the voltage of the control terminal GN2 of the switch, the conduction level of the second NMOS transistor MN2 is adjusted so that VRc1 is equal to the reference voltage VR2, and the current flowing through the second NMOS transistor MN2 is always equal to k×(VR2 / Rc1).

[0088] When the voltage VSC of the supercapacitor SC is low, the second operational amplifier OPC plays a major control role. At this time, OPV controls MPV to not conduct, and GN2 controls MPI and MN2. When the loop is stable, the voltages at its positive and negative input terminals are equal, that is, the voltage of VRc1 is equal to the voltage of VR2, thereby realizing that the current of VRc1 is equal to VR2 / Rc1, where VR2 is the voltage value of the reference voltage VR2, Rc1 is the resistance value of the resistor Rc1, and the current of MN2 is equal to k times the current of MNC2. Therefore, the current of MN2 is equal to k×(VR2 / Rc1), thus realizing constant current control for charging.

[0089] 3) The constant voltage control loop includes the third operational amplifier OPV, the third PMOS transistor MPV, and voltage divider resistors Rf1 and Rf2;

[0090] The non-inverting input of the third operational amplifier OPV is connected to the reference voltage VR1, the inverting input is connected to the common node of the voltage divider resistors Rf1 and Rf2 to obtain the voltage divider feedback signal VF, and the output is connected to the gate of the third PMOS transistor MPV.

[0091] The source of the third PMOS transistor MPV is connected to the operating voltage node through a bias resistor Rb or a current source I1, and is connected to the switch control terminal GN2, while the drain is grounded.

[0092] Voltage divider resistors Rf1 and Rf2 are connected in series between the positive terminal of the backup power supply and ground;

[0093] By controlling the voltage of the control terminal GN2 of the control switch, the conduction level of the second NMOS transistor MN2 is adjusted so that the voltage divider feedback signal VF is equal to the reference voltage VR1, and the voltage of the backup power supply is always equal to VR1×(Rf1+Rf2) / Rf2.

[0094] As the supercapacitor SC is continuously charged, its voltage rises. When it approaches full charge, its charging current decreases. As the charging current decreases, the current sampled across resistor Rc1 also decreases, causing the voltage of VRc1 to drop. This leads to an increase in the output voltage of the operational amplifier OPC, gradually shutting off MPI. At this point, the voltage feedback loop controlled by OPV takes over the dominant role. When the loop is stable, the voltage of VF equals the voltage of VR1, and the voltage of VSC can be controlled to equal VR1×(Rf1+Rf2) / Rf2, where VR1 is the reference voltage VR1, Rf1 is the resistance of resistor Rf1, and Rf2 is the resistance of resistor Rf2.

[0095] 4) The enable control circuit includes an inverter inva and a fourth NMOS transistor MNE; the input of the inverter inva receives the level signal output by the voltage comparison module, and the output is connected to the gate of the fourth NMOS transistor MNE; the drain of the fourth NMOS transistor MNE is connected to the switch control terminal GN2, and the source is grounded.

[0096] When the signal level is low, the signal after passing through the inverter inva is high, which controls MNE to conduct and pulls the GN2 node down to ground level (i.e., 0V). At this time, the control ChCTL is disabled.

[0097] Figure 2 The MPI, MPV, MNE, and MPC1 components require high-voltage devices for implementation.

[0098] The ChCTL charging control module employs a constant current-constant voltage automatic switching charging control strategy. It precisely samples the charging current through a current replication circuit and achieves constant current and constant voltage charging through dual-loop control. This precise control avoids overcharging and overcurrent, which helps extend the lifespan of the supercapacitor SC.

[0099] like Figure 3 The image shows another implementation of the charging control module ChCTL, which is similar to... Figure 2 In contrast, current source I1 was used to replace resistor Rb, and resistor Rb itself can withstand high voltage. Figure 3 In this implementation, I1 requires the use of high-voltage devices, resulting in a slightly larger area.

[0100] like Figure 4 As shown, the boost control module includes: a boost controller, AND gate, OR gate, fourth PMOS transistor PM4, fifth NMOS transistor NM5, and multiple inverters inva1, inva2, inva3, invb1, invb2, invb3, and inv1;

[0101] The boost controller generates a control signal GN1 for the first NMOS transistor and a raw control signal GN2D for the second NMOS transistor; the raw control signal GN2D for the second NMOS transistor is connected to the first input terminal of the AND gate and the first input terminal of the OR gate, respectively.

[0102] The input of inverter inv1 is connected to the level signal output from the voltage comparator module. Its output is connected to the second input of the AND gate, inverters inva1, inva2, and inva3. The output of inverter inva3 is connected to the gate of the fourth PMOS transistor PM4. The source of the fourth PMOS transistor PM4 is connected to the upper plate of capacitor Cbs, with a voltage of BSTU. Its drain is connected to the switch control terminal GN2. The BSTU voltage is the voltage of the upper plate of capacitor Cbs. The basic principle is that the voltage difference across the capacitor will not change abruptly. As MN2 turns on, the voltage at node SWU increases accordingly. SWU is the lower plate node of capacitor Cbs, and the voltage at the upper plate of capacitor Cbs increases accordingly, maintaining a constant voltage difference across the capacitor. When MN1 turns on, the voltage across capacitor Cbs is pre-charged to, for example, 5V (i.e., the voltage difference across Cbs equals 5V).

[0103] The second input terminal of the OR gate is connected to the level signal output by the voltage comparison module. The output terminal is connected to inverters invb1, invb2 and invb3 in turn. The output terminal of inverter invb3 is connected to the gate of the fifth NMOS transistor NM5. The source of the fifth NMOS transistor NM5 is connected to the switching signal switching terminal SWU and the drain is connected to the switching control terminal GN2.

[0104] The boost controller BstCTL uses a classic structure. When the CEN signal is low, it does not affect BstCTL's control of the output GN2. When CEN is high, it becomes low after passing through inverter inv1, then low after passing through an AND gate (shielding the signal GN2D from BstCTL), and then high after passing through inva1~inva3, controlling the PMOS transistor PM4 to turn off. When CEN is high (shielding the signal GN2D from BstCTL), it becomes high after passing through an OR gate, then low after passing through invb1~invb3, controlling the NMOS transistor NM5 to turn off. This ensures that when CEN is high and the charging circuit is working, the boost circuit does not control the GN2 node, thus not affecting the operation of the charging circuit. CEN does not affect the GN1 signal path.

[0105] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.

[0106] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A backup power circuit for an electricity meter, characterized in that, include: Voltage comparison module, power switch, voltage conversion module, charging control module, boost control module, first NMOS transistor MN1, second NMOS transistor MN2, inductor L1, capacitor C1 and backup power supply; The voltage comparison module compares the input voltage VIN with the operating voltage threshold in real time. When the input voltage VIN is greater than or equal to the operating voltage threshold, it outputs a high level to the charging control module and the boost control module. After receiving the high level, the charging control module controls the second NMOS transistor MN2 to turn on to charge the backup power supply. After receiving the high level, the boost control module stops working. At the same time, the power switch is turned on, and the input voltage is split into two paths after passing through the power switch. One path powers the communication module, and the other path is stepped down by the voltage conversion module to power the metering circuit. When the input voltage VIN is less than the operating voltage threshold, the power switch is turned off. At the same time, the voltage comparison module outputs a low level to the charging control module and the boost control module. After receiving the low level, the boost control module starts working. After receiving the low level, the charging control module stops the charging process of the backup power supply and controls the first NMOS transistor MN1 and the second NMOS transistor MN2 to alternately turn on and off, so that the boost control module, the first NMOS transistor MN1, the second NMOS transistor MN2, the inductor L1 and the capacitor C1 together form a boost circuit. The boost circuit boosts the voltage output by the backup power supply and then divides it into two paths: one path powers the communication module, and the other path is stepped down by the voltage conversion module to power the metering circuit.

2. The backup power circuit for the power meter as described in claim 1, characterized in that, One end of the power switch is connected to the input voltage VIN, and the other end serves as the working voltage node; the working voltage node is connected to the voltage conversion module, the communication module, the charging control module, the second NMOS transistor MN2, and the capacitor C1 respectively; The voltage comparison module is a comparator, with its input terminal connected to the input voltage VIN, and its output terminal connected to the charging control module and the boost control module, respectively.

3. The backup power circuit for the power meter as described in claim 2, characterized in that, The backup power source is a supercapacitor SC; the charging control module has five terminals, namely the level receiving terminal, the working voltage input terminal VSYS, the supercapacitor voltage monitoring terminal VSC, the switch control terminal GN2, and the switch signal switching terminal SWU. The level receiving terminal is connected to the output terminal of the voltage comparator module and is used to receive the level signal output by the voltage comparator module; The working voltage input terminal VSYS is connected to the working voltage node and is used to input the working voltage during the charging process; The supercapacitor voltage monitoring terminal VSC is connected to the positive terminal of the supercapacitor SC and is used to monitor the real-time voltage of the supercapacitor SC and control the charging process. The switch control terminal GN2 is connected to the gate of the second NMOS transistor MN2, and the gate of the second NMOS transistor MN2 is also connected to the boost control module; the drain of the second NMOS transistor MN2 is connected to the working voltage node, the source is connected to the positive terminal of the supercapacitor SC through the inductor L1, and the negative terminal of the supercapacitor SC is grounded. The switching signal terminal SWU is connected to the source of the second NMOS transistor MN2, the drain of the first NMOS transistor MN1, and the boost control module, respectively; the source of the first NMOS transistor MN1 is grounded, and its gate is connected to the boost control module. When the level signal is high, the control signal generated by the switch control terminal GN2 of the switch signal switching terminal SWU is connected to the gate of the second NMOS transistor MN2; when the level signal is low, the control signal generated by the boost control module is connected to the gate of the second NMOS transistor MN2, so that the second NMOS transistor MN2 and the first NMOS transistor MN1 together form the synchronous rectifier of the boost circuit.

4. The backup power circuit for the power meter as described in claim 3, characterized in that, It also includes capacitor Cbs, whose negative terminal is connected between the source of the second NMOS transistor MN2 and the inductor L1, and whose positive terminal is connected to the boost control module.

5. The backup power circuit for the power meter as described in claim 4, characterized in that, The charging control module includes a current replication circuit, a constant current control loop, a constant voltage control loop, and an enable control circuit. The current replication circuit is used to acquire the current of the second NMOS transistor MN2 in real time and convert it into a low-power electrical signal that represents the magnitude of the charging current. The constant current control loop is used to compare the low-power electrical signal fed back by the current replication circuit with the internal reference signal when the backup power supply voltage is lower than the preset threshold, and control the charging current to be constant based on the comparison result. The constant voltage control loop is used to stabilize the voltage of the backup power supply at the preset threshold when the backup power supply voltage reaches the preset threshold. The enable control circuit is used to control the constant current control loop or constant voltage control loop to work when the voltage comparator module outputs a high level, and to disconnect the second NMOS transistor MN2 when the voltage comparator module outputs a low level.

6. The backup power circuit for the power meter as described in claim 5, characterized in that, The current replication circuit includes: a first operational amplifier OP, a third NMOS transistor MNC2, a first PMOS transistor MPC1, and a sampling resistor Rc1; The non-inverting input of the first operational amplifier OP is connected to the source of the second NMOS transistor MN2, the inverting input is connected to the source of the third NMOS transistor MNC2 and the source of the first PMOS transistor MPC1, and the output is connected to the gate of the first PMOS transistor MPC1. The gate of the third NMOS transistor MNC2 is connected to the same switch control terminal GN2 as the gate of the second NMOS transistor MN2, and the drain of the third NMOS transistor MNC2 is connected to the working voltage node. The drain of the first PMOS transistor MPC1 is grounded via the sampling resistor Rc1; the third NMOS transistor MNC2 is configured to replicate the current of the second NMOS transistor MN2 at a replication ratio of 1:k.

7. The backup power circuit for the power meter as described in claim 6, characterized in that, The constant current control loop includes a second operational amplifier OPC, a second PMOS transistor MPI, and a bias resistor Rb or a current source I1; In this configuration, the non-inverting input of the second operational amplifier OPC is connected to the reference voltage VR2, the inverting input is connected to the connection node between the sampling resistor and the drain of the first PMOS transistor MPC1, and the output is connected to the gate of the second PMOS transistor MPI; the voltage at the connection node between the sampling resistor Rc1 and the drain of the first PMOS transistor MPC1 is VRc1. The source of the second PMOS transistor MPI is connected to the working voltage node through a bias resistor Rb or a current source I1, and is connected to the switch control terminal GN2. The drain of the second PMOS transistor MPI is connected to one end of the sampling resistor RC1 and grounded. By controlling the voltage of the control terminal GN2 of the switch, the conduction level of the second NMOS transistor MN2 is adjusted so that VRc1 is equal to the reference voltage VR2, and the current flowing through the second NMOS transistor MN2 is always equal to k×(VR2 / Rc1).

8. The backup power circuit for the power meter as described in claim 7, characterized in that, The constant voltage control loop includes the third operational amplifier OPV, the third PMOS transistor MPV, and voltage divider resistors Rf1 and Rf2; The non-inverting input of the third operational amplifier OPV is connected to the reference voltage VR1, the inverting input is connected to the common node of the voltage divider resistors Rf1 and Rf2 to obtain the voltage divider feedback signal VF, and the output is connected to the gate of the third PMOS transistor MPV. The source of the third PMOS transistor MPV is connected to the operating voltage node through a bias resistor Rb or a current source I1, and is connected to the switch control terminal GN2, while the drain is grounded. Voltage divider resistors Rf1 and Rf2 are connected in series between the positive terminal of the backup power supply and ground; By controlling the voltage of the control terminal GN2 of the control switch, the conduction level of the second NMOS transistor MN2 is adjusted so that the voltage divider feedback signal VF is equal to the reference voltage VR1, and the voltage of the backup power supply is always equal to VR1×(Rf1+Rf2) / Rf2.

9. The backup power circuit for the power meter as described in claim 8, characterized in that, The enable control circuit includes an inverter inva and a fourth NMOS transistor MNE; the input of the inverter inva receives the level signal output by the voltage comparison module, and the output is connected to the gate of the fourth NMOS transistor MNE; the drain of the fourth NMOS transistor MNE is connected to the switch control terminal GN2, and the source is grounded.

10. The backup power circuit for the power meter as described in claim 3, characterized in that, The boost control module includes: a boost controller, AND gates, OR gates, a fourth PMOS transistor PM4, a fifth NMOS transistor NM5, and multiple inverters inva1, inva2, inva3, invb1, invb2, invb3, and inv1; The boost controller generates a control signal GN1 for the first NMOS transistor and a raw control signal GN2D for the second NMOS transistor; the raw control signal GN2D for the second NMOS transistor is connected to the first input terminal of the AND gate and the first input terminal of the OR gate, respectively. The input terminal of inverter inv1 is connected to the level signal output by the voltage comparison module. The output terminal is connected to the second input terminal of AND gate, inverter inva1, inverter inva2 and inverter inva3. The output terminal of inverter inva3 is connected to the gate of the fourth PMOS transistor PM4. The source of the fourth PMOS transistor PM4 is connected to the power supply voltage, and the drain is connected to the switch control terminal GN2. The second input terminal of the OR gate is connected to the level signal output by the voltage comparison module. The output terminal is connected to inverters invb1, invb2 and invb3 in turn. The output terminal of inverter invb3 is connected to the gate of the fifth NMOS transistor NM5. The source of the fifth NMOS transistor NM5 is connected to the switching signal switching terminal SWU and the drain is connected to the switching control terminal GN2.

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