Dual-frequency high-efficiency power amplifier based on harmonic tuning

Abstract

The invention discloses a double-frequency high-efficiency power amplifier based on harmonic tuning, which belongs to the technical field of amplifier circuits and comprises an input matching circuit, a first biasing circuit, a second biasing circuit, a stabilizing circuit, a transistor and an output matching circuit. Two ends of the stabilizing circuit are respectively connected with the input matching circuit and the transistor grid. The first biasing circuit is connected with the input matching circuit. The output matching circuit is connected with the drain electrode of the transistor. The second bias circuit is connected with the output matching circuit. The input matching circuit is used for matching source impedance to system impedance; the first biasing circuit is used for providing grid voltage for the transistor; the second biasing circuit is used for providing drain voltage for the transistor; the stabilizing circuit is used for ensuring that the amplifier works stably in a working frequency band; the transistor is used for amplifying signals; the output matching circuit is used for matching load impedance to system impedance and harmonic suppression; the low-power-consumption dual-frequency power amplifier can meet the requirement of a multi-mode multi-band communication system for the low-power-consumption dual-frequency power amplifier

Description

Technical Field

[0001] This invention belongs to the field of amplifier circuit technology, specifically relating to a dual-frequency high-efficiency power amplifier based on harmonic tuning. Background Technology

[0002] In recent years, wireless communication technologies such as Wireless Local Area Networks (WLANs) and mobile communication networks have developed rapidly, and emerging standards have placed higher demands on system throughput and multifunctionality. Against this backdrop, modern communication equipment urgently needs the ability to operate concurrently across multiple frequency bands to meet the ever-increasing demand for high data rate transmission. With the evolution of multi-band communication systems, power amplifiers, as their core modules, must possess the ability to operate efficiently across multiple frequency bands. Compared to traditional single-band power amplifiers, multi-band power amplifiers have become the industry's preferred solution. However, while broadband power amplifiers can cover multiple frequency bands, when processing dual-band / multi-band signals with large frequency intervals, their efficiency deteriorates significantly in the passband due to limitations in the fundamental frequency matching network and harmonic suppression network, which cannot simultaneously achieve optimal performance across a wide frequency range. Therefore, achieving high efficiency across multiple discrete frequency bands constitutes a core challenge in the design of multi-band RF systems. In this context, researching dual-band high-efficiency power amplifiers for wideband scenarios has significant engineering value and theoretical significance. Summary of the Invention

[0003] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0004] A dual-frequency high-efficiency power amplifier based on harmonic tuning includes: an input matching circuit, a first bias circuit, a second bias circuit, a stabilizing circuit, a transistor P1, and an output matching circuit; the two ends of the stabilizing circuit are respectively connected to the input matching circuit and the gate of the transistor P1, the first bias circuit is connected to the input matching circuit; the output matching circuit is connected to the drain of the transistor P1, and the second bias circuit is connected to the output matching circuit.

[0005] The input matching circuit is used to match the source impedance to the system impedance; the first bias circuit is used to provide the gate voltage V to transistor P1. G The second bias circuit is used to provide the drain voltage V for transistor P1. D The stabilization circuit ensures stable operation of the amplifier within its operating frequency band; transistor P1 amplifies the signal; the output matching circuit matches the load impedance to the system impedance and suppresses harmonics.

[0006] The radio frequency input signal RF is input through the input terminal of the input matching circuit. in The output matching circuit outputs the radio frequency (RF) signal. out .

[0007] The present invention has the following beneficial effects:

[0008] This invention enables efficient operation in two frequency bands simultaneously by setting dual-frequency fundamental frequency matching and harmonic suppression, meeting the requirements of multi-mode multi-band communication systems for low-power dual-frequency power amplifiers. This allows the dual-frequency matching network to exhibit good bandwidth characteristics and high efficiency performance at both operating frequency points of the power amplifier. Attached Figure Description

[0009] Figure 1 The circuit topology of the dual-frequency high-efficiency power amplifier based on harmonic tuning of the present invention is as follows: 1-input matching circuit, 2-first bias circuit, 3-second bias circuit, 4-stabilizing circuit, 5-output matching circuit.

[0010] Figure 2 This is a diagram showing the output power and power-added efficiency of the dual-frequency power amplifier in an embodiment of the present invention. Detailed Implementation

[0011] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0012] like Figure 1 As shown, this embodiment of the invention provides a dual-frequency high-efficiency power amplifier (hereinafter referred to as the amplifier) ​​based on harmonic tuning, including an input matching circuit 1, a first bias circuit 2, a second bias circuit 3, a stabilizing circuit 4, a transistor P1, and an output matching circuit 5. The two ends of the stabilizing circuit 4 are connected to the input matching circuit 1 and the gate of the transistor P1, respectively. The first bias circuit 2 is connected to the input matching circuit 1; the output matching circuit 5 is connected to the drain of the transistor P1, and the second bias circuit 3 is connected to the output matching circuit 5. This amplifier uses a high-power gallium nitride transistor and is simulated and optimized using ADS (Advanced Design System) electromagnetic simulation software, ultimately achieving efficient dual-frequency power amplification. The input matching circuit 1 is used to match the source impedance to the system impedance of 50 ohms; the first bias circuit 2 is used to provide the gate voltage V to the transistor P1. G The second bias circuit 3 is used to provide the drain voltage V for transistor P1. D The stabilizing circuit 4 is used to ensure that the amplifier operates stably within the operating frequency band; transistor P1 is used to amplify the signal; the output matching circuit 5 is used to match the load impedance to the system impedance of 50 ohms and to suppress harmonics.

[0013] The input matching circuit 1 includes, in sequence, a first capacitor C1 and a second capacitor C2 connected in parallel, a first microstrip line T1, a second microstrip line T2, and a third microstrip line T3. It also includes a fourth microstrip line T4, one end of which is connected to the node between the second and third microstrip lines T2 and T3, and the other end is open. The other ends of the parallel capacitors C1 and C2 are connected to the radio frequency input signal RF. in .

[0014] The first bias circuit 2 includes, in sequence, a third capacitor C3 and a fourth capacitor C4, a fifth microstrip line T5, a sixth microstrip line T6, and a seventh microstrip line T7 connected in parallel. The seventh microstrip line T7 is connected to the node between the second microstrip line T2 and the third microstrip line T3. The gate voltage V is connected to the node between the third capacitor C3 and the fourth capacitor C4 and the fifth microstrip line T5. G .

[0015] The second bias circuit 3 includes, in sequence: a fifth capacitor C5 and a sixth capacitor C6 connected in parallel, an eighth microstrip line T8, a ninth microstrip line T9, and a tenth microstrip line T1. 10 The tenth microstrip line T 10 The twelfth microstrip line T connected to the output matching circuit 5 12 and the thirteenth microstrip line T 13 At the node between them, the fifth capacitor C5 and the sixth capacitor C6 are connected in parallel, and the drain voltage V is connected at the node between the eighth microstrip line T8. D .

[0016] The stabilizing circuit 4 includes a first resistor R1 and a seventh capacitor C7 connected in parallel. The two ends of the first resistor R1 are connected to the third microstrip line T3 of the input matching circuit 1 and the gate of the transistor P1, respectively.

[0017] The output matching circuit 5 includes an eleventh microstrip line T connected in sequence. 11 Twelfth microstrip line T 12 The thirteenth microstrip line T 13 The fourteenth microstrip line T 14 The fifteenth microstrip line T 15 The eighth capacitor C8 and the ninth capacitor C9 are connected in parallel, as well as the sixteenth microstrip line T. 16 The seventeenth microstrip line T 17 The eighteenth microstrip line T 18 Among them, the sixteenth microstrip line T 16 One end is connected to the eleventh microstrip line T 11 and the twelfth microstrip line T 12 At the node between them, the other end is open-circuited; the seventeenth microstrip line T 17 One end is connected to the twelfth microstrip line T 12 and the thirteenth microstrip line T13 At the node between them, the other end is open-circuited; the eighteenth microstrip line T 18 One end is connected to the thirteenth microstrip line T 13 and the fourteenth microstrip line T 14 At the node between them, the other end is open-circuited; the other ends of the eighth capacitor C8 and the ninth capacitor C9 connected in parallel are connected to the RF output signal RF. out ; Eleventh microstrip line T 11 The other end is connected to the drain of transistor P1.

[0018] The radio frequency input signal RF is input through the input terminal of the input matching circuit 1. in The output matching circuit 5 outputs the radio frequency (RF) signal. out .

[0019] Furthermore, the eleventh microstrip line T 11 Twelfth microstrip line T 12 The sixteenth microstrip line T 16 and the seventeenth microstrip line T 17 Used for second harmonic suppression at the operating frequency.

[0020] At low frequency point 2 and high frequency point 2 At each location, let the sixteenth microstrip line T... 16 and the seventeenth microstrip line T 17 The electrical length is 90 o , ;in, For the sixteenth microstrip line T 16 electrical length, For the seventeenth microstrip line T 17 electrical length, As the first operating frequency, For the second operating frequency, This is the electrical length corresponding to the operating frequency.

[0021] Eleventh microstrip line T 11 satisfy: The twelfth microstrip line T 12 satisfy: ,in, , For transistor P1 in , The optimal second harmonic impedance is given. , These are the eleventh microstrip line T 11 Twelfth microstrip line T 12 Characteristic impedance, , These are the eleventh microstrip line T 11Twelfth microstrip line T 12 The electrical length.

[0022] Furthermore, the thirteenth microstrip line T 13 The fourteenth microstrip line T 14 The fifteenth microstrip line T 15 and the eighteenth microstrip line T 18 Fundamental matching for harmonic-tuned dual-frequency high-efficiency power amplifiers; specifically including: firstly, utilizing the thirteenth microstrip line T... 13 Two frequencies at point A , Complex impedance under , Transformed into a pair of conjugate complex admittances , ,in, This is the conductivity value. The susceptance value is then determined using the eighteenth microstrip line T. 18 Cancel two frequencies , Down , imaginary part Finally, using the fourteenth microstrip line T 14 and the fifteenth microstrip line T 15 Complete the matching between the real impedances of the two frequencies.

[0023] In this embodiment, all microstrip lines are loaded onto a Rogers 4350B (circuit board model) substrate with a dielectric constant of 3.66. Specifically:

[0024] First, the thirteenth microstrip line T 13 Two frequencies at point A , Complex impedance under , Transformed into a pair of conjugate complex admittances , ,in, for The real part of the complex impedance, for The imaginary part of the complex impedance, for The real part of the complex impedance, for The imaginary part of the complex impedance, and the characteristic impedance Z of the thirteenth microstrip line. 13 and electrical length Must meet:

[0025] ;

[0026] ;

[0027] in, express , The ratio, It can be any integer.

[0028] Then, using the eighteenth microstrip line T 18 Cancel two frequencies , Lower conjugate complex admittance , imaginary part The eighteenth microstrip line T 18 At two frequencies , The input impedance must meet the following requirements. :

[0029] ;

[0030] ;

[0031] By solving the above two equations, the eighteenth microstrip line T can be obtained. 18 electrical length and characteristic impedance Z 18 :

[0032] ;

[0033] ;

[0034] Finally, after passing through the thirteenth microstrip line T 13 and the eighteenth microstrip line T 18 The impedance transformation can determine point B. , The impedance of the lower amplifier is ;in, Point B , The susceptance value of the lower amplifier. This is determined by connecting the fourteenth microstrip line T in series. 14 and the fifteenth microstrip line T 15 This is a dual-frequency quarter-wavelength impedance converter that converts the real impedance... exist , Matching to load R L =50Ω. Fourteenth microstrip line T 14 and the fifteenth microstrip line T 15 Characteristic impedance Z 14 Z 15 and electrical length , Must meet:

[0035] ;

[0036] ;

[0037] ;

[0038] in, Given the load impedance, point A is located on the twelve microstrip line T. 12 and the thirteenth microstrip line T 13 At the node between them, point B is located on the thirteenth microstrip line T. 13 and the fourteenth microstrip line T 14 On the nodes between.

[0039] like Figure 2 The table shows the experimental results of the dual-frequency power amplifier according to a specific embodiment of the present invention. The experimental results show that in the frequency range of 0.72 GHz to 1.04 GHz, the saturated output power is 39.4-41 dBm, the power-added efficiency is between 60.1% and 69.5%, and the bandwidth is 320 MHz; in the frequency range of 2.41 GHz to 2.45 GHz, the saturated output power is 38.5-39.7 dBm, the power-added efficiency is between 59.2% and 61.5%, and the bandwidth is 40 MHz. These results verify the effectiveness and superiority of the present invention. Table 1 gives the specific values ​​of the physical parameters of each component:

[0040] Table 1

[0041]

[0042] Based on the above technical solution, this invention can not only achieve dual-frequency fundamental wave matching and harmonic suppression, but also effectively simplify the structure of the power amplifier output matching circuit, greatly improve design efficiency and overall performance, and provide a highly innovative and practical solution for the development of dual-frequency power amplifiers.

[0043] The above description is merely an embodiment of the present invention and does not limit the scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention specification and drawings, or direct or indirect applications in other related system fields, are similarly included within the protection scope of the present invention.

[0044] The contents not described in detail in this specification are existing technologies known to those skilled in the art.

Claims

1. A dual-frequency high-efficiency power amplifier based on harmonic tuning, characterized in that, include: Input matching circuit, first bias circuit, second bias circuit, stabilizing circuit, transistor P1, and output matching circuit; The two ends of the stabilizing circuit are connected to the input matching circuit and the gate of transistor P1, respectively, and the first bias circuit is connected to the input matching circuit. The output matching circuit is connected to the drain of transistor P1, and the second bias circuit is connected to the output matching circuit. The input matching circuit is used to match the source impedance to the system impedance; the first bias circuit is used to provide the gate voltage V to transistor P1. G The second bias circuit is used to provide the drain voltage V for transistor P1. D The stabilization circuit ensures stable operation of the amplifier within its operating frequency band; transistor P1 amplifies the signal; the output matching circuit matches the load impedance to the system impedance and suppresses harmonics. The radio frequency input signal RF is input through the input terminal of the input matching circuit. in The output matching circuit outputs the radio frequency (RF) signal. out .

2. The dual-frequency high-efficiency power amplifier based on harmonic tuning according to claim 1, characterized in that, The input matching circuit includes, in sequence: a first capacitor C1 and a second capacitor C2 connected in parallel, a first microstrip line T1, a second microstrip line T2, and a third microstrip line T3. It also includes a fourth microstrip line T4, one end of which is connected to the node between the second microstrip line T2 and the third microstrip line T3. The other ends of the parallel capacitors C1 and C2 are connected to the radio frequency input signal RF. in .

3. The dual-frequency high-efficiency power amplifier based on harmonic tuning according to claim 2, characterized in that, The first bias circuit includes, in sequence, a third capacitor C3 and a fourth capacitor C4, a fifth microstrip line T5, a sixth microstrip line T6, and a seventh microstrip line T7 connected in parallel. The seventh microstrip line T7 is connected to the node between the second microstrip line T2 and the third microstrip line T3. The gate voltage V is connected to the node between the third capacitor C3 and the fourth capacitor C4 and the fifth microstrip line T5. G .

4. The dual-frequency high-efficiency power amplifier based on harmonic tuning according to claim 3, characterized in that, The second bias circuit includes, in sequence: a fifth capacitor C5 and a sixth capacitor C6 connected in parallel; an eighth microstrip line T8; a ninth microstrip line T9; and a tenth microstrip line T1. 10 The tenth microstrip line T 10 The drain voltage V is connected at the node between the fifth capacitor C5 and the sixth capacitor C6 connected in parallel with the eighth microstrip line T8 in the output matching circuit. D .

5. The dual-frequency high-efficiency power amplifier based on harmonic tuning according to claim 4, characterized in that, The stabilizing circuit includes a first resistor R1 and a seventh capacitor C7 connected in parallel. The two ends of the first resistor R1 are connected to the third microstrip line T3 of the input matching circuit and the gate of transistor P1, respectively.

6. The dual-frequency high-efficiency power amplifier based on harmonic tuning according to claim 5, characterized in that, The output matching circuit includes an eleventh microstrip line T connected in sequence. 11 Twelfth microstrip line T 12 The thirteenth microstrip line T 13 The fourteenth microstrip line T 14 The fifteenth microstrip line T 15 The eighth capacitor C8 and the ninth capacitor C9 are connected in parallel, as well as the sixteenth microstrip line T. 16 The seventeenth microstrip line T 17 The eighteenth microstrip line T 18 Among them, the sixteenth microstrip line T 16 One end is connected to the eleventh microstrip line T 11 and the twelfth microstrip line T 12 At the node between; the seventeenth microstrip line T 17 One end is connected to the twelfth microstrip line T 12 and the thirteenth microstrip line T 13 At the nodes between; the eighteenth microstrip line T 18 Connected to the thirteenth microstrip line T 13 and the fourteenth microstrip line T 14 At the node between them; the other end of the eighth capacitor C8 and the ninth capacitor C9 connected in parallel is connected to the radio frequency output signal RF. out ; Eleventh microstrip line T 11 The other end is connected to the drain of transistor P1; the tenth microstrip line T 10 The twelfth microstrip line T connected to the output matching circuit 12 and the thirteenth microstrip line T 13 On the nodes between.

7. The dual-frequency high-efficiency power amplifier based on harmonic tuning according to claim 6, characterized in that, Eleventh microstrip line T 11 Twelfth microstrip line T 12 The sixteenth microstrip line T 16 and the seventeenth microstrip line T 17 Used for second harmonic suppression at the operating frequency.

8. The dual-frequency high-efficiency power amplifier based on harmonic tuning according to claim 7, characterized in that, At low frequency point 2 and high frequency point 2 At each location, let the sixteenth microstrip line T... 16 and the seventeenth microstrip line T 17 The electrical length is 90 o , ; in, For the sixteenth microstrip line T 16 electrical length, For the seventeenth microstrip line T 17 electrical length, As the first operating frequency, For the second operating frequency, The electrical length corresponding to the operating frequency; Eleventh microstrip line T 11 satisfy: The twelfth microstrip line T 12 satisfy: ; in, , For transistor P1 in , The optimal second harmonic impedance is given. , These are the eleventh microstrip line T 11 Twelfth microstrip line T 12 Characteristic impedance, , These are the eleventh microstrip line T 11 Twelfth microstrip line T 12 The electrical length.

9. The dual-frequency high-efficiency power amplifier based on harmonic tuning according to claim 8, characterized in that, The thirteenth microstrip line T 13 The fourteenth microstrip line T 14 The fifteenth microstrip line T 15 and the eighteenth microstrip line T 18 Fundamental matching for harmonic-tuned dual-frequency high-efficiency power amplifiers; include: First, using the thirteenth microstrip line T 13 Point A , Complex impedance under , Transformed into a pair of conjugate complex admittances , ,in, This is the conductivity value. The susceptance value is then determined using the eighteenth microstrip line T. 18 Cancel two frequencies , Down , imaginary part Finally, using the fourteenth microstrip line T 14 and the fifteenth microstrip line T 15 Complete the matching between the dual-frequency real impedances; where point A is located on the twelfth microstrip line T. 12 and the thirteenth microstrip line T 13 On the nodes between.

10. The dual-frequency high-efficiency power amplifier based on harmonic tuning according to claim 9, characterized in that, The thirteenth microstrip line T 13 Point A , Complex impedance under , Transformed into a pair of conjugate complex admittances , ,in, for The real part of the complex impedance, for The imaginary part of the complex impedance, for The real part of the complex impedance, for The imaginary part of the complex impedance, and the characteristic impedance Z of the thirteenth microstrip line. 13 and electrical length satisfy: ； ； in, express , The ratio, It can be any integer; Then, using the eighteenth microstrip line T 18 offset , Lower conjugate complex admittance , imaginary part The eighteenth microstrip line T 18 exist , The input impedance must meet the following requirements. : ； ； By solving the above two equations, the eighteenth microstrip line T can be obtained. 18 electrical length and characteristic impedance Z 18 : ； ； Finally, after passing through the thirteenth microstrip line T 13 and the eighteenth microstrip line T 18 Impedance transformation to determine point B , The impedance of the lower amplifier is ;in, Point B , The susceptance value of the lower amplifier; through the fourteenth microstrip line T in series 14 and the fifteenth microstrip line T 15 This is a dual-frequency quarter-wavelength impedance converter that converts the real impedance... exist , Matching to load R L ; Fourteenth microstrip line T 14 and the fifteenth microstrip line T 15 Characteristic impedance Z 14 Z 15 and electrical length , satisfy: ； ； ； in, Given the load impedance, point B is located on the thirteenth microstrip line T. 13 and the fourteenth microstrip line T 14 On the nodes between.

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