Optical transmission method and device based on heterogeneous signal differentiation processing and photo-electric-optical wavelength conversion

Abstract

The application discloses an optical transmission method and device based on heterogeneous signal differential processing and photo-electric-optical wavelength conversion, and relates to the technical field of communication. The method comprises the following steps: receiving a multi-service heterogeneous input signal containing analog signals and / or digital signals, classifying and routing the signals to corresponding special processing channels according to the physical characteristics of the signals; adopting path processing dominated by an analog circuit for the analog signals routed to the analog processing channel, modulating the processed analog signals to a first group of preset optical wavelengths through a high-precision electro-optical conversion module; performing time division multiplexing integration on the digital signals routed to the digital processing channel to form a high-speed data stream, and modulating the high-speed data stream to a second group of preset optical wavelengths through a standard optical module; and coupling the optical signals carrying the first group of preset optical wavelengths and the second group of preset optical wavelengths to a single optical fiber for transmission through a wavelength division multiplexer. The application can effectively reduce the number of physical cables while losslessly guaranteeing various heterogeneous signals.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication technology, in particular to an optical transmission method and device based on differential processing of heterogeneous signals and optical-electrical-optical wavelength conversion. BACKGROUND

[0002] In modern high-reliability communication systems such as radar array and shelter interconnection, industrial automation control network, and remote security monitoring, long-distance and high-fidelity transmission of multi-service signals is a key requirement. Traditional solutions usually adopt an independent wiring architecture of "one cable for one signal", i.e., assigning a dedicated physical cable for each type of signal, such as Ethernet, RS422 control instructions, analog video, and RF local oscillator clock. Although this mode can ensure the independence of each signal link, its drawbacks become increasingly prominent with the increase in the number of service types.

[0003] Firstly, the sharp increase in the number of cables leads to a significant increase in system complexity and weight. In scenarios where space is limited or rotation is required, such as radar antenna connections, a large number of cables not only make it difficult to lay and maintain, but also degrade signal quality due to mutual crosstalk, severely restricting the deployability and long-term stability of the system.

[0004] Secondly, to solve the above problems, the industry attempts to unify and digitize multiple signals and then transmit them through a single high-speed link. However, such "one-size-fits-all" all-digital solutions face fundamental challenges when dealing with high-fidelity analog signals such as precision clocks, wideband RF, or standard analog video. The analog-to-digital conversion process inevitably introduces quantization noise, clock jitter, and bandwidth limitations, resulting in a significant loss of signal phase synchronization accuracy, linearity, or dynamic range, which cannot meet the stringent requirements of military or high-end industrial applications for "transparent" signal transmission.

[0005] Therefore, how to effectively reduce the number of physical cables while ensuring the lossless transmission of various heterogeneous signals has become a technical bottleneck that needs to be broken through in the field of multi-service optical transmission. SUMMARY

[0006] To solve the defects of the prior art, while effectively reducing the number of physical cables, the present application provides an optical transmission method and device based on differential processing of heterogeneous signals and optical-electrical-optical wavelength conversion.

[0007] In the first aspect, the technical scheme adopted by the present application to achieve the purpose of the invention is as follows:

[0008] The optical transmission method based on differential processing of heterogeneous signals and optical-electrical-optical wavelength conversion comprises:

[0009] The multi-service heterogeneous input signal containing analog signals and / or digital signals is received and classified according to the physical characteristics of each signal, and the classified multi-service heterogeneous input signal is routed to the corresponding dedicated processing channel; wherein the physical characteristics include signal type, synchronization requirement and linearity requirement; the dedicated processing channel includes an analog processing channel and a digital processing channel;

[0010] For the analog signals routed to the analog processing channel, a path dominated by analog circuits is used for processing, and the processed analog signals are modulated onto a first set of preset optical wavelengths through a high-precision electro-optical conversion module;

[0011] For the digital signals routed to the digital processing channel, time division multiplexing is used with a programmable logic device to integrate into a high-speed data stream, and the high-speed data stream is modulated onto a second set of preset optical wavelengths through a standard optical module;

[0012] The optical signals carrying the first set of preset optical wavelengths and the second set of preset optical wavelengths are coupled into a single optical fiber for transmission through a wavelength division multiplexer.

[0013] By adopting the technical scheme, the analog signal at least includes a clock signal and a radio frequency signal which have high fidelity requirements for synchronization or linearity; the digital signal includes RS232, RS422, TTL, pulse signal and low-speed control signal; the application provides a signal "transparent" transmission method based on multiple services and multiple signals; not only the number of optical fiber cables required for signal transmission is reduced, but also the system anti-interference capability is improved, and the transmission quality target of lossless transparent transmission of multiple types of signals (especially high-fidelity analog signals) is realized; specifically, unlike the traditional single processing paradigm of full digitalization or full analog, the application classifies and routes multiple service heterogeneous input signals according to physical characteristics, and differentiates the processing based on the internal physical property differences of different signals, such as the extreme requirement of clock signal for phase synchronization, the sensitivity of radio frequency signal to linearity, and the emphasis of digital control signal on real-time. And the differentiated processing is carried out: the differentiated processing mode is formed by "analog circuit dominant path and high-precision electro-optical conversion" and "programmable logic device time division multiplexing and standard optical module", the former retains the original continuous domain characteristics of high-fidelity analog signals such as clock, radio frequency and video, avoids the distortion introduced by ADC / DAC, and ensures the "transparent" transmission of signal waveform, phase and amplitude through special analog conditioning circuit (such as phase-locked loop, linear amplifier) and high linearity electro-optical modulator; the latter fully utilizes the parallel processing capability of FPGA, and efficiently aggregates a large number of low-speed and discrete digital control signals (such as RS232, RS422, TTL pulse) into high-speed data stream, greatly improving the optical fiber bandwidth utilization. Then, the first group of preset optical wavelengths and the second group of preset optical wavelengths are subjected to wavelength division multiplexing, realizing physical layer fusion, that is, the two types of signals subjected to differentiated processing are modulated onto different, predefined optical wavelength channels, and then coupled to a single optical fiber by using a wavelength division multiplexer, the application realizes the ultimate integration of "multiple services and single cable" at the physical layer. This not only completely solves the "cable complexity" problem proposed in the background art, but also fundamentally eliminates the electromagnetic interference between different types of signals through wavelength isolation. The application realizes the purpose of greatly reducing the number of physical cables while losslessly protecting various heterogeneous signals.

[0014] In a preferred example of the application, the analog signal at least includes a clock signal and a radio frequency signal; the clock signal is regenerated and synchronized by a circuit containing a phase-locked loop; and the radio frequency signal is processed by a linear amplification circuit to maintain signal bandwidth, linearity and signal-to-noise ratio.

[0015] By adopting the technical scheme, for the two typical high-fidelity analog signals of clock and radio frequency, phase-locked loop regeneration synchronization and clock phase stability are introduced respectively, and linear amplification circuit is adopted to maintain the bandwidth, linearity and signal-to-noise ratio of the radio frequency signal; signal degradation caused by the general processing path is effectively avoided, the integrity and timing accuracy of the key analog signals in the photoelectric conversion and fiber transmission process are ensured, and the strict requirements of radar, industrial control and other scenes on synchronization and spectral fidelity are met.

[0016] In a preferred example of the present application: the first group of preset optical wavelengths and the second group of preset optical wavelengths correspond to a coarse wavelength division multiplexing band and a dense wavelength division multiplexing band respectively, and a multiplexing strategy of mixing coarse wavelength division multiplexing channels and dense wavelength division multiplexing channels is adopted in the unified wavelength division multiplexing transmission step.

[0017] By adopting the technical scheme, the coarse wavelength division multiplexing band is called CWDM (Coarse Wavelength Division Multiplexing), and the dense wavelength division multiplexing is called DWDM (Dense Wavelength Division Multiplexing); the analog signal and the digital signal are mapped to the CWDM and DWDM bands respectively to form a mixed wavelength division multiplexing strategy. The CWDM channel spacing is wide and the cost is low, and it is suitable for analog signals with moderate bandwidth requirements; the DWDM channel is dense and has large capacity, and it is suitable for high-speed multiplexed digital streams. The mixed architecture flexibly balances the system cost and spectral efficiency under the premise of ensuring the transmission quality of various signals.

[0018] In a preferred example of the present application: a network management unit is integrated inside the transmission device; the network management unit monitors key operating parameters of each functional module in real time, and generates a pre-alarm information when the key operating parameters exceed the corresponding preset threshold, the key operating parameters at least including the received optical power, the transmitted optical power, the working temperature, the power supply voltage and the laser bias current of the optical module.

[0019] By adopting the technical scheme, the integrated network management unit monitors key parameters such as optical module transceiving optical power, temperature, voltage and bias current in real time, and triggers a pre-alarm when the parameters exceed the threshold, thereby realizing the active health early warning function.

[0020] In a preferred example of the present application: before the unified wavelength division multiplexing transmission, a wavelength conversion step is further included:

[0021] By the optical-electric-optical wavelength conversion unit, the non-standard wavelength optical signal emitted by the customer side device is converted into a standardized wavelength division multiplexing wavelength in the first group of preset optical wavelengths or the second group of preset optical wavelengths.

[0022] By adopting the technical scheme, the optical-electric-optical wavelength conversion unit is introduced to convert the non-standard wavelength (such as 850 nm) of the customer side into a standardized CWDM / DWDM wavelength, thereby solving the compatibility problem of the multi-source heterogeneous optical signals that cannot be directly accessed to the wavelength division multiplexing system, and enhancing the adaptability of the system to different front-end devices.

[0023] In a preferred example of the present application: the wavelength range of the coarse wavelength division multiplexing band includes 1271.0 nm to 1611.0 nm; the wavelength range of the dense wavelength division multiplexing band includes 1528.77 nm to 1563.86 nm; and the programmable logic device is an FPGA.

[0024] By adopting the technical scheme, the specific ranges of the CWDM band (1271.0-1611.0 nm) and the DWDM band (1528.77-1563.86 nm) are limited, the wavelength allocation conforms to the ITU-T standard, and compatibility with the existing optical network is ensured; and the parallel processing capability of the FPGA provides hardware support for real-time TDM of multiple low-speed signals.

[0025] In a second aspect, the technical scheme for achieving the purpose of the present application is as follows:

[0026] The optical transmission device based on heterogeneous signal differential processing and optical-electric-optical wavelength conversion is used to implement the optical transmission method based on heterogeneous signal differential processing and optical-electric-optical wavelength conversion as described above, and the device includes:

[0027] The signal recognition and routing module is used to classify and channel allocate the input multi-service heterogeneous input signals;

[0028] The analog signal processing unit includes a phase-locked loop circuit for a clock signal and a linear amplification circuit for a radio frequency signal, and is connected to a high-precision electro-optical conversion module;

[0029] The digital signal processing unit includes a programmable logic device and a standard optical module, and the programmable logic device is configured to perform time division multiplexing of multiple low-speed digital signals;

[0030] The wavelength division multiplexing / demultiplexing unit is used to multiplex the multi-wavelength optical signals from different processing units to a single fiber at the sending end, and to demultiplex at the receiving end;

[0031] The network management unit is used to perform device state monitoring and alarm.

[0032] By adopting the technical scheme, a complete heterogeneous signal mixed transmission hardware platform is constructed. The functions of each unit are decoupled, and the interfaces are clear, which supports transparent passage of high-fidelity analog signals and realizes efficient aggregation of digital signals.

[0033] In a preferred example of the present application, the programmable logic device comprises an FPGA chip with model number XC7A35T-1FGG484, which is configured to receive low-speed digital signals from multiple communication interface chips, perform time division multiplexing algorithm internally, and integrate into a high-speed serial data stream.

[0034] By using the above technical solution, the FPGA chip with model number XC7A35T-1FGG484 is used as the digital processing core, its rich I / O resources and high-speed logic units can receive multiple communication interface signals in parallel, and perform time division multiplexing algorithm internally to meet the input rate requirements of the optical module.

[0035] In a preferred example of the present application, the analog signal processing unit comprises:

[0036] An analog-to-digital converter configured to convert the input analog video signal into a parallel digital video signal under the synchronization of the sampling clock provided by the FPGA chip, and transmit it to the FPGA chip;

[0037] A digital-to-analog converter, wherein the parallel data input end of the digital-to-analog converter is connected to the video data output bus of the FPGA chip, and the clock input end receives the video synchronization clock signal from the FPGA, and the analog-to-digital converter is configured to convert the parallel digital video signal into a differential analog current output signal;

[0038] A high-speed operational amplifier, wherein the non-inverting input end of the high-speed operational amplifier is connected to the analog current output end of the digital-to-analog converter to convert the differential analog current signal into a single-ended voltage signal, and perform buffering and gain conditioning operations to output an analog video signal with a peak-to-peak value meeting the preset standard;

[0039] Wherein, the closed-loop gain of the high-speed operational amplifier is set by a resistance feedback network.

[0040] By using the above technical solution, a high-precision video output link is formed, the FPGA provides a synchronous sampling clock and parallel data to realize high-quality reconstruction of digital video to analog signals. The high-speed operational amplifier such as LMH6643 converts the differential current output by the DAC into a single-ended voltage, and sets the closed-loop gain through a precise resistance feedback network to ensure that the output video peak-to-peak value accurately meets the standard.

[0041] In a preferred example of the present application, the communication interface chip comprises an RS232 transceiver with model number MAX3323EEUE and an RS422 transceiver with model number MAX3490EESA, which are used to realize bidirectional conversion between the FPGA logic level and the external standard serial communication level.

[0042] By adopting the technical scheme, MAX3323EEUE (RS232) and MAX3490EESA (RS422) special transceivers are adopted to realize reliable bidirectional conversion between FPGA TTL level and external standard serial level.

[0043] To sum up, the present application includes at least one of the following beneficial technical effects:

[0044] 1. The present application classifies and routes heterogeneous input signals according to their physical characteristics, processes them differently using analog dominant paths and digital time division multiplexing paths, and modulates the results to different preset wavelengths. Finally, single-fiber transmission is achieved through wavelength division multiplexing. The present application breaks through the limitations of traditional "full digitalization" or "independent wiring", significantly reduces the number of cables, and balances the transparent transmission of high-fidelity analog signals and the efficient aggregation of digital signals, achieving performance and efficiency optimization for multi-service converged transmission.

[0045] 2. Precise processing is implemented for different high-fidelity analog signals: a phase-locked loop (PLL) circuit is introduced for clock signals, not only to regenerate the frequency, but also to effectively suppress the phase jitter accumulated during transmission, ensuring system-level synchronization accuracy. For radio frequency signals, a high linearity amplification path is used to maximize the amplitude-phase relationship and spectral integrity, avoiding signal-to-noise ratio degradation caused by nonlinear distortion. The present application uses a "customized" analog front-end design to optimize the conditioning of sensitive signals before photoelectric conversion, ensuring that each service maintains its required signal quality level while sharing the same fiber infrastructure, thus solving the fidelity conflict problem in heterogeneous analog signal transmission. BRIEF DESCRIPTION OF DRAWINGS

[0046] Figure 1 is a flowchart of an optical transmission method based on heterogeneous signal differential processing and optical-electrical-optical wavelength conversion in an embodiment of the present application;

[0047] Figure 2 is a video signal acquisition circuit diagram of an analog signal processing unit in an optical transmission device based on heterogeneous signal differential processing and optical-electrical-optical wavelength conversion in an embodiment of the present application;

[0048] Figure 3 is a video signal output circuit diagram of an analog signal processing unit in an optical transmission device based on heterogeneous signal differential processing and optical-electrical-optical wavelength conversion in an embodiment of the present application;

[0049] Figure 4 is a communication signal circuit diagram in an optical transmission device based on heterogeneous signal differential processing and optical-electrical-optical wavelength conversion in an embodiment of the present application;

[0050] Figure 5 is a Bank0 interface and configuration circuit diagram of an FPGA in an optical transmission device based on heterogeneous signal differential processing and optical-electrical-optical wavelength conversion in an embodiment of the present application;

[0051] Figure 6 is a circuit diagram of an FPGA chip in an optical transmission device based on heterogeneous signal differential processing and optical-electrical-optical wavelength conversion in an embodiment of the present application;

[0052] Figure 7 is an optical-electrical conversion circuit diagram in an optical transmission device based on heterogeneous signal differential processing and optical-electrical-optical wavelength conversion in an embodiment of the present application;

[0053] Figure 8 is a principle block diagram of optical-electrical conversion in an optical transmission device based on heterogeneous signal differential processing and optical-electrical-optical wavelength conversion in an embodiment of the present application;

[0054] Figure 9 is a principle block diagram of wavelength division multiplexing / demultiplexing unit in an optical transmission device based on heterogeneous signal differential processing and optical-electrical-optical wavelength conversion in an embodiment of the present application;

[0055] Figure 10 is a principle block diagram of optical terminal device point-to-point communication in an optical transmission device based on heterogeneous signal differential processing and optical-electrical-optical wavelength conversion in an embodiment of the present application. DETAILED DESCRIPTION

[0056] The present application will be further described in detail below with reference to the accompanying drawings.

[0057] In an embodiment, as shown in Figure 1 the present application discloses an optical transmission method based on heterogeneous signal differential processing and optical-electrical-optical wavelength conversion, specifically comprising the following steps:

[0058] S1: receiving a multi-service heterogeneous input signal containing analog signals and / or digital signals, and classifying according to the physical characteristics of each signal, the classified multi-service heterogeneous input signal being routed to a corresponding dedicated processing channel; wherein the physical characteristics include signal type, synchronization requirement and linearity requirement; the dedicated processing channel includes an analog processing channel and a digital processing channel.

[0059] In the embodiment, the multi-service heterogeneous input signal includes optical signal, analog clock synchronous signal, radio frequency signal, RS232 signal, RS422 signal, video signal, network signal, TTL signal, and pulse signal; the physical characteristic refers to an inherent attribute exhibited by the signal in the time domain, frequency domain, or logic layer, which determines the transmission quality requirement. The signal type refers to whether the signal is a continuously changing analog quantity (such as a sine wave or a video baseband) or a discrete digital level (such as TTL, RS232, or RS422); the synchronization requirement refers to whether the signal carries a system timing reference, and the phase jitter needs to be controlled to the level of picoseconds; the linearity requirement refers to whether the signal amplitude and information content are in a strict linear relationship (such as a radio frequency carrier), and distortion will directly lead to demodulation failure. The dedicated processing channel includes an analog processing channel and a digital processing channel.

[0060] Specifically, a two-level recognition mechanism is adopted to realize signal classification and routing. The first level is hardware pre-judgment: the signal categories are pre-defined through the physical connection mode of the front-end interface circuit. For example, the signal connected to the BNC interface is a radio frequency or clock class high-fidelity analog signal by default; the signal connected to the DB9 or terminal block is a digital control signal such as RS232 / 422 by default. The second level is dynamic feature extraction: for signals that are not explicitly identified, the system starts an online analysis program executed by a microcontroller (MCU); the microcontroller is, for example, STM32H743VI or MSP432P401R. The online analysis program samples the input signal in real time through a high-speed ADC and calculates the spectral main lobe width (judges whether it is a narrowband clock), the peak factor (Crest Factor, distinguishes between pulse and continuous wave), and the zero-crossing rate (Zero-Crossing Rate, assists in judging the digital / analog attribute).

[0061] For example, if the signal center frequency is detected to be 100MHz, the spectral width is <1kHz, and the phase is continuous, it is determined to be a high-stability clock signal, which is routed to the analog channel; if the signal presents obvious high-low level jumping and meets the UART frame format, it is determined to be a digital signal, which is routed to the digital processing channel, also known as the FPGA processing channel.

[0062] Further, the analog signal at least includes a clock signal and a radio frequency signal; the clock signal is regenerated and synchronized by a circuit containing a phase-locked loop; the radio frequency signal is processed by a linear amplification circuit to maintain the signal bandwidth, linearity, and signal-to-noise ratio. The clock signal refers to a periodic reference signal used for system synchronization, such as a 10MHz or 100MHz sine wave or square wave, and the core quality indicators are phase noise and jitter. The phase-locked loop (PLL) is not only used as a frequency synthesizer, but also as a clock regenerator.

[0063] Specifically, take a 100MHz sinusoidal clock signal from the radar antenna array as an example: after the signal is connected through a coaxial cable, it is first shaped into an approximate square wave by a super-low-noise limiting amplifier (such as ZX60-14012L-S+) and the signal-to-noise ratio is improved; then it is sent to a high-performance clock PLL chip (such as ADF4372). The high-performance clock PLL chip integrates a low-noise VCO (voltage-controlled oscillator) and a phase discriminator inside, the reference input end receives the shaped 100MHz signal, and the feedback frequency divider is set to N=1, so that the VCO is locked at 100MHz. The key is that the loop bandwidth of the PLL is carefully set to 10kHz, which is much lower than the clock frequency, which can effectively suppress the random jitter of >10kHz in the input signal while retaining the long-term frequency accuracy. The regenerated 100MHz clock is output from the RFOUT port of the PLL, and its phase noise is better than -130dBc / Hz at a 10kHz offset. The signal directly drives a high-linearity laser driver (such as MAX3273) to control the modulation current of the DFB laser, achieving low-distortion light intensity modulation. The entire regeneration process reduces the cumulative jitter of the original signal from 5ps RMS to <0.5ps RMS, meeting the stringent requirements of radar systems for time synchronization.

[0064] The linear amplification circuit is a single-stage or multi-stage amplification chain composed of high-OIP3 (output third-order intercept point), low-noise, and wide-bandwidth operational amplifiers or special RF amplifiers; take a radar intermediate frequency signal with a center frequency of 1.5GHz and a bandwidth of 200MHz as an example: after the radar intermediate frequency signal is input through an SMA interface, it first enters a 50Ω DC isolation capacitor and impedance matching network, and then is fed into a super-wideband low-distortion amplifier (such as LMH6643 or ADL5542). In this embodiment, LMH6643 is preferred. The amplifier is configured in a fixed gain mode such as 10dB, and the closed-loop gain is set by precise resistors (1% tolerance) to avoid temperature drift introduced by potentiometers. To suppress the influence of power supply noise on linearity, a 22μH ferrite bead is connected in series and a 10μF+100nF ceramic capacitor is connected in parallel at the VCC pin to form a π-type filter. The amplified signal drives a high-linearity electro-optical modulator (such as FTLX1471D3BCL) through an AC coupling capacitor. The module has a built-in DFB laser and a linear TIA, and its spurious-free dynamic range reaches 75dB·Hz² / ³ at 1.5GHz.

[0065] S2: for analog signals routed to the analog processing channel, the path dominated by analog circuits is used for processing, and the processed analog signal is modulated onto the first group of preset wavelengths through a high-precision electro-optical conversion module.

[0066] In the embodiment, the analog circuit dominated path refers to that the analog signal keeps its continuous analog form throughout the whole processing chain without analog-digital conversion or digital signal processing; the high-precision electro-optical conversion module specifically refers to an analog intensity modulator composed of a high-linearity laser such as a DFB laser diode and a precision automatic power control (APC) circuit, and the nonlinear distortion is better than 70 dBc.

[0067] Specifically, taking a 10MHz reference clock signal as an example: after the signal is input through a BNC interface, it first enters an ultra-low noise broadband amplifier (such as LMH6643) for impedance matching and amplitude conditioning, and then drives a dedicated phase-locked loop (PLL) chip (such as HMC833LP6GE) for regeneration. The PLL uses an internal high-Q VCO to lock the phase of the input clock, and outputs a clean clock copy with a jitter of less than 100 fs. The clean clock copy signal is directly fed into a high-precision electro-optical conversion module, the core of which is a DFB laser with a center wavelength of 1311 nm (belonging to the CWDM band). The bias current of the DFB laser is stabilized by the APC loop, and the modulation current is linearly controlled by the clock signal to realize analog intensity modulation (IM). Finally, the 1311 nm optical signal carrying the 10MHz clock information is output to the wavelength division multiplexing unit. The entire path has no digital link.

[0068] S3: For digital signals routed to the digital processing channel, time division multiplexing is used to integrate the low-speed signals into a high-speed data stream using a programmable logic device, and the high-speed data stream is modulated onto a second set of preset optical wavelengths through a standard optical module.

[0069] In the embodiment, the programmable logic device is preferably a field programmable gate array (FPGA), which has a large number of configurable logic units and hard-core transceivers, and is suitable for parallel processing of multiple low-speed signals. Time division multiplexing (TDM) refers to dividing time into frames of fixed length, and each frame is further divided into multiple time slots, and each input signal is allocated a dedicated time slot, so as to be interleaved into a single high-speed serial stream in the time dimension.

[0070] Specifically, taking the 8-channel RS422 control signal as an example: each channel signal is converted into LVTTL level by MAX3490EESA transceiver, and then connected to the special I / O Bank of FPGA (XC7A35T-1FGG484). A TDM scheduler IP core is configured inside the FPGA, and the working process is as follows: first, each channel signal is sampled and buffered under the local clock domain; then, under the driving of the system main clock, the scheduler reads each channel data in the preset order (such as Ch0→Ch1→…→Ch7) and inserts the frame header / check bit to form an 8B / 10B encoded high-speed serial stream with a rate of 1.25 Gbps. The encoded high-speed serial stream drives a standard SFP optical module (central wavelength 1550.12 nm, belonging to DWDM C band) to generate an optical signal through intensity modulation. This process compresses 8 independent control lines into a single DWDM wavelength, greatly improving the utilization rate of optical fiber.

[0071] Further, the first group of preset optical wavelengths and the second group of preset optical wavelengths correspond to a coarse wavelength division multiplexing (CWDM) band and a dense wavelength division multiplexing (DWDM) band, respectively, and a mixing multiplexing strategy of coarse wavelength division multiplexing channels and dense wavelength division multiplexing channels is adopted in the unified wavelength division multiplexing transmission step. Coarse wavelength division multiplexing (CWDM) refers to a wavelength division multiplexing technology with a channel spacing of 20 nm, and its typical wavelength range is 1271 nm to 1611 nm, with a total of 18 ITU-T G.694.2 standard channels. Dense wavelength division multiplexing (DWDM) refers to a wavelength division multiplexing technology with a channel spacing of 0.8 nm (100 GHz) or narrower, which works in the C band and supports dozens to hundreds of channels. This embodiment adopts a commercial 18CH CWDM + 40CH DWDM Hybrid Mux. Its structure includes: all CWDM ports (1271-1611 nm) are combined by a TFF stage; DWDM ports (1528-1565 nm) are combined by a C-band AWG; the two combined optical paths are combined by a broadband coupler in the last stage, and output to a G.652.D single-mode optical fiber from a single common port.

[0072] At the receiving end, the symmetric Hybrid DeMux performs reverse operation: the composite optical signal first enters the broadband optical splitter, and the light >1520 nm is guided to the DWDM AWG demultiplexing, and the light <1520 nm is guided to the CWDM TFF demultiplexing, thereby realizing the non-cross separation of the two types of signals. The wavelength range of the coarse wavelength division multiplexing band of this embodiment includes 1271.0 nm to 1611.0 nm; the wavelength range of the dense wavelength division multiplexing band includes 1528.77 nm to 1563.86 nm; and the programmable logic device is FPGA. The actual measurement shows that the channel isolation of this device between 1311 nm and 1550 nm is better than 40 dB.

[0073] S4: coupling the optical signals carrying the first set of preset optical wavelengths and the second set of preset optical wavelengths into a single optical fiber for transmission through a wavelength division multiplexer.

[0074] In the embodiment, the wavelength division multiplexer is implemented by using thin film filter (TFF) or arrayed waveguide grating (AWG) technology, the channel isolation is better than 30 dB, and the insertion loss is lower than 3 dB. The single optical fiber refers to a standard G.652.D single-mode optical fiber.

[0075] Specifically, the 1311 nm optical signal from the analog channel and the 1550.12 nm optical signal from the digital channel are respectively connected to different ports of a coarse / dense hybrid wavelength division multiplexer. The multiplexer internally integrates a CWDM filter (for 1311 nm) and a DWDM AWG (for C band), combines the two optical signals without loss, and outputs them to a single optical fiber from a common port. At the receiving end, a symmetrical demultiplexer separates the composite optical signal, the 1311 nm signal is sent to the analog receiving channel for photoelectric conversion and PLL recovery, and the 1550.12 nm signal is sent to the digital receiving channel to be demultiplexed by the FPGA to restore the original 8-way RS422 signal, completing end-to-end transparent transmission.

[0076] Further, a network management unit is integrated in the transmission device; the network management unit monitors key operating parameters of each functional module in real time, and generates a pre-alarm information when the key operating parameters exceed the corresponding preset threshold, the key operating parameters at least including the received optical power, the transmitted optical power, the operating temperature, the power supply voltage and the laser bias current of the optical module.

[0077] In the embodiment, the network management unit is an embedded subsystem constructed with a system on chip (SoC) as the core, which is directly integrated in the main control board. The key operating parameters include but are not limited to the received optical power, the transmitted optical power, the internal temperature, the power supply voltage and the laser bias current of the optical module. In the embodiment, an NXP i.MX 6ULL microprocessor is used as the main control chip of the network management unit. An I²C0 bus is connected to an I²C multiplexer such as TI TCA9548A, which expands 8 sub-channels and is connected to the DDM interfaces of 8 SFP / SFP+ optical modules. At the same time, the SoC also monitors the output voltage of the AC / DC power module after resistance voltage division through the ADC pin, and reads the power on signal through the GPIO. The enable and reset signals of all functional modules are also controlled by the system on chip, forming a closed-loop management. The pre-alarm information refers to an early warning triggered when the parameters have deviated from the normal working range but have not yet caused service interruption.

[0078] Different from the traditional alarm, the preset threshold of the embodiment includes a pre-warning threshold and an alarm threshold. In actual application, different preset thresholds can be divided based on actual data types. For example, the pre-warning threshold of the received optical power is set to -20 dBm, and the alarm threshold is set to -25 dBm. Specifically, the network management unit runs a background monitoring task to poll the DDM data of all optical modules at a 1-second cycle. After each reading, the current value is compared with the threshold table stored in the EEPROM to determine whether to trigger a pre-alarm information, and the SoC generates and outputs the pre-alarm information through local indication, serial reporting, network reporting, and storage recording.

[0079] In the embodiment, before the unified wavelength division multiplexing transmission, a wavelength conversion step is further included: through an optical-electric-optical wavelength conversion unit, a non-standard wavelength optical signal emitted by a customer-side device is converted into a standardized wavelength division multiplexing wavelength in the first group of preset optical wavelengths or the second group of preset optical wavelengths.

[0080] Specifically, as shown in Figure 8 The non-standard wavelength optical signal refers to an optical signal that does not conform to the ITU-T G.694.1 (DWDM) or G.694.2 (CWDM) standard, typically such as an 850nm VCSEL multimode signal, a 1310nm FP laser signal, or a private wavelength of a manufacturer. The standardized wavelength division multiplexing wavelength refers to a CWDM (such as 1311nm) or DWDM (such as 1550.12nm) channel. The optical-electric-optical wavelength conversion unit is composed of four levels of optical receiving sub-modules (ROSA), electrical signal conditioning circuits, laser drivers, and optical transmitting sub-modules (TOSA), and realizes transparent relay from the all-optical domain to the electrical domain and then to the standard optical domain.

[0081] For example, taking an 850nm multimode optical signal (rate 1.25Gbps, carrying the data stream after digitalization of analog video) from a customer-side industrial camera as an example, the conversion process is as follows:

[0082] Optical receiving (O→E): After the 850nm optical signal is accessed through the MMF (multimode optical fiber), it enters the 850nm dedicated ROSA (such as Broadcom AFBR-703SDZ-F2). The ROSA has a built-in PIN photodiode and a transimpedance amplifier (TIA) to convert the optical signal into a differential electrical signal (CML level) and output it to the limiting amplifier through an AC coupling capacitor.

[0083] Electrical signal shaping and decision (E-domain processing): The differential electrical signal is sent to a limiting amplifier (e.g. Semtech GN1060), which functions to shape the input signal with large amplitude fluctuations into a digital signal with constant swing, and to complete clock data recovery (CDR). The output is a standard LVPECL or CML logic level, representing the original data stream. This step realizes signal regeneration (Re-amplifying, Re-shaping, Re-timing—3R), eliminating transmission damage.

[0084] Wavelength mapping and driving (E→O): The regenerated electrical signal drives a configurable laser driver (e.g. Maxim MAX3273), and the output current of the driver is connected to a standardized TOSA. According to the type of service, the system pre-configures the TOSA wavelength: if the video stream belongs to digital services, a DWDM TOSA (center wavelength 1550.12 nm, with TEC temperature control) is selected; if the analog characteristics need to be preserved (such as uncompressed baseband video), a CWDM TOSA (e.g. 1351 nm, without TEC) is selected.

[0085] In this embodiment, since the video has been digitized, a 1550.12 nm DWDM TOSA (model: Lumentum LTR155012-10-SFA) is selected. The TOSA modulates the electrical signal onto a 1550.12 nm DFB laser, outputting a single-mode optical signal that meets the SFF-8472 standard, with an SMSR>45 dB. The entire optical-electrical-optical wavelength conversion unit is packaged as a hot-pluggable SFP+ module, which is inserted into the general optical port slot of the host device. In addition, for analog optical signals, the optical-electrical-optical wavelength conversion unit needs to use linear mode: skip the limiting amplifier and CDR, and directly drive the linear TOSA with the analog electrical signal output by the ROSA through a wideband amplifier (e.g. LMH6643), to ensure minimal AM / PM distortion. At this time, the output wavelength is mapped to the CWDM channel.

[0086] Further, to support the transparent transmission of analog optical signals, the optical-electrical-optical wavelength conversion unit also includes an analog / digital mode switching switch circuit. The switching switch circuit is driven by the control signal MODE_SEL output by the FPGA, and is specifically implemented as two groups of high-speed analog switches, such as TI TS5A23157. When MODE_SEL=0 (digital mode), the differential signal output by the ROSA is processed by the limiting amplifier and CDR circuit; when MODE_SEL=1 (analog mode), the switch directly routes the ROSA output to the wideband linear amplifier (e.g. LMH6643), bypassing all decision regeneration circuits, thereby preserving the amplitude and phase information of the signal. This design ensures that the same hardware platform can handle both digital and analog optical services, improving the versatility of the device.

[0087] In an embodiment, as shown in Figures 2-10 The heterogeneous signal differential processing and electro-optical wavelength conversion based optical transmission device is used to implement the heterogeneous signal differential processing and electro-optical wavelength conversion based optical transmission method as shown above. The heterogeneous signal differential processing and electro-optical wavelength conversion based optical transmission device comprises a signal recognition and routing module, an analog signal processing unit, a digital signal processing unit, a wavelength division multiplexing / demultiplexing unit and a network management unit.

[0088] The signal recognition and routing module is used for classification and channel allocation of the input multi-service heterogeneous input signal. The signal recognition and routing module is embodied in hardware as physical interface partitioning and FPGA I / O Bank allocation, without the need for a separate chip. All external signals are accessed to the equipment backplane through aviation plugs or BNC / RJ45 interfaces. Different types of signals are guided to corresponding dedicated processing sub-boards: analog signals (clock signals, radio frequency signals, video signals) are guided to the analog signal processing unit; digital signals (RS232 signals / RS422 signals / RS485 signals / TTL / network) are guided to the digital signal processing unit; optical signals are guided to the electro-optical wavelength conversion unit (external SFP slot). The FPGA automatically recognizes the signal type through the I / O pin level state or protocol features.

[0089] The analog signal processing unit contains a phase-locked loop circuit for clock signals and a linear amplification circuit for radio frequency signals, and is connected to a high-precision electro-optical conversion module; the phase-locked loop circuit is, for example, LMK04828, and the high-precision electro-optical conversion module is, for example, a high-linearity DFB laser. The analog signal processing unit includes an analog-to-digital converter, a digital-to-analog converter and a high-speed operational amplifier. The analog-to-digital converter is configured to convert the input analog video signal into a parallel digital video signal under the synchronization of the sampling clock provided by the FPGA chip, and transmit it to the FPGA chip; the digital-to-analog converter is, for example, AD9708ARUZ, the parallel data input end of the digital-to-analog converter is connected to the video data output bus of the FPGA chip, the clock input end receives the video synchronization clock signal from the FPGA, and the analog-to-digital converter is configured to convert the parallel digital video signal into a differential analog current output signal; the high-speed operational amplifier is, for example, LMH6643, the non-inverting input end of the high-speed operational amplifier is connected to the analog current output end of the digital-to-analog converter, so as to convert the differential analog current signal into a single-ended voltage signal, and perform buffering and gain conditioning operations to output an analog video signal with a peak-to-peak value meeting a preset standard; wherein the closed-loop gain of the high-speed operational amplifier is set through a resistance feedback network.

[0090] As shown in Figures 2 to 3As shown, the analog signal processing unit is divided into the video signal acquisition circuit of the input path and the video signal output circuit of the output path. The analog-to-digital converter AD9280ARZ is U32 in the figure, the CLK pin is the sampling clock input pin; the D[0:7] pin is used for 8-bit digital output, and the REFIN pin inputs the reference voltage. Figure 2 The U10A and U10B in the figure are operational amplifiers of model LM358, wherein the operational amplifier U10A is configured as a voltage follower, and the U10B and resistors R61 and R62 constitute a non-inverting amplifier with a gain of 1+R62 / R61; the +IN / -IN pins are positive and negative input terminals. Figure 3 The video signal output circuit in the figure includes a digital-to-analog converter AD9708ARUZ (U44) and two high-speed operational amplifiers LMH6643 (U48A, U48B); the FPGA drives the AD9708 through the 8-bit parallel bus DA_D[7:0] and the synchronization clock DA_CLK to output the digital video stream; the AD9708 outputs a differential analog current signal (IOUTA / IOUTB); the differential analog current signal is filtered to remove the image frequency through a π-type LC reconstruction filter (L38-L43, C260-C267); the filtered signal enters the non-inverting input terminal of the LMH6643, which is configured as a non-inverting amplifier; the closed-loop gain of the U48A is set by R262 and R275, and the closed-loop gain of the U48B is set by R278 and R279; the operational amplifier U48A is used for common-mode rejection, and the U48B is used for single-ended output, and the feedback network R278 / R279 sets the closed-loop gain to 0.64 times.

[0091] The digital signal processing unit includes a programmable logic device and a standard optical module, and the programmable logic device is configured to perform time division multiplexing of multiple low-speed digital signals; the programmable logic device includes an FPGA chip of model XC7A35T-1FGG484, which is configured to receive low-speed digital signals from multiple communication interface chips, perform a time division multiplexing algorithm internally, and integrate into one high-speed serial data stream. The time division multiplexing algorithm adopts a fixed-length frame structure, each frame includes N time slots, and each time slot is allocated to one low-speed digital signal. The FPGA is internally configured with a multi-channel flexible buffer for absorbing the frequency offset of each signal. The system main clock (125 MHz) is divided by the MMCM to generate each sampling clock, and the phase consistency of the TDM frames among multiple nodes is ensured through the frame synchronization signal, wherein the frame synchronization signal is provided by the network management unit to align the 1 PPS second pulse. The high-speed serial stream after multiplexing adopts 8b / 10b encoding, and the rate matches the 1.25 Gbps interface standard of the SFP+ optical module.

[0092] As shown in Figure 4 , taking the circuit diagram shown in Figure 4 as an example, Figure 4RS422 communication signal circuit and RS232 communication signal circuit, RS422 communication signal circuit adopts MAX3490EESA (U11, U12, U15, U16, U27) transceiver; Each road is equipped with 120Ω terminal resistance (such as U11's R139, U12's R140, U15's R143) matching impedance; TTL signal FPGA_RXDn / FPGA_TXDn is directly connected with FPGAI / O. RS232 interface adopts MAX3323EEUE (U29); Four 100nF charge pump capacitors (C143, C145, C148, C149) are externally connected, and the output is ±10V standard RS232 level.

[0093] As shown in Figures 5 to 7 , taking the circuit diagram as shown in Figures 5 to 7 as an example, Figure 5 Bank0 interface and configuration circuit of FPGA (XC7A35T) and QSPI Flash memory interface circuit; U1A is Xilinx Artix-7 series FPGA; CLKIN pin receives external master clock input; PROG_B, INIT_B, DONE pins are used to display JTAG configuration signal or configuration state; MCS[1:0] is mode selection pin, which determines the configuration mode; D[0:3], C[0:3], W[0:3], WE, OE, CE pins output QSPI interface signal. U31 is QSPI Flash memory, which is used to store FPGA configuration bitstream, boot program, user data and the like.

[0094] As shown in Figure 6 , taking the circuit diagram as shown in Figure 6 as an example, Figure 6 FPGA clock and reset circuit, Figure 6 which shows the core clock source of FPGA; U2 is the clock management chip of AT93C66, which is suitable for application scenarios requiring extremely low jitter.

[0095] As shown in Figure 7 , taking the circuit diagram as shown in Figure 7 as an example, Figure 7 FPGA signal processing chip electric connection circuit, which shows the connection of FPGA (XC7A35T) and external high-speed serial interface, Figure 7In the SFP / SFP+ optical module, U3B and U3A are SFP / SFP+ optical modules. The TX1_P / N pin transmits differential signals, and the RX1_P / N pin receives differential signals. The CLK_125P / N pin is the reference clock input. The MOD_DEF pin receives the module detection signal. When the SFP / SFP+ optical module transmits optical signals: the SP1_TX_P / N pin of the FPGA outputs a differential signal, which is filtered and then input to the TX1_P / N pin of the SFP module. The SFP module internally converts the electrical signal into an optical signal and transmits it through the optical fiber. When the SFP / SFP+ optical module receives optical signals, the optical signal in the optical fiber enters the SFP module. The SFP module internally converts the optical signal into an electrical signal and outputs it to the RX1_P / N pin. After filtering, the signal is sent to the SP1_RX_P / N pin of the FPGA. The CDR (Clock Data Recovery) circuit inside the FPGA extracts the clock and data from the signal. The clock signal generated by an external crystal oscillator or clock generator is input to the FPGA through CLK_125P / N. The clock signal is used to synchronize the transmission and reception of the SFP module.

[0096] like Figure 9 As shown, Figure 9 This diagram illustrates the principle of converting customer-side optical wavelengths to line-side optical wavelengths in SFP / SFP+ optical modules. It utilizes photoelectric conversion technology to convert 850nm wavelength optical signals from the customer side into wavelength division multiplexing (WDM) wavelength optical signals from the line side, or vice versa. The 850nm optical signal is first converted into an electrical signal by the Optical Receiving Submodule (ROSA), then a large, constant amplitude is output by a limiting amplifier as the input to the laser driver. The laser driver then converts the electrical signal into a specific wavelength optical signal via the Optical Transmitting Submodule (TOSA), thus completing the wavelength conversion. Conversely, to convert a WDM optical signal to an 850nm optical signal, the signal must pass through the ROSA, limiting amplifier, laser driver, and TOSA sequentially.

[0097] A wavelength division multiplexing / demultiplexing unit is used to multiplex multi-wavelength optical signals from different processing units onto a single fiber at the transmitting end, and to demultiplex them at the receiving end. This device is equipped with a Hybrid WDM Mux / DeMux. The wavelength division multiplexing scheme is as follows: Figure 9 As shown, the optical signal at the transmitting end undergoes optical-electrical-optical wavelength conversion, then is multiplexed by an optical multiplexer before being transmitted to the receiving end. The receiving end uses an optical demultiplexer to demultiplex the signal, and then performs wavelength conversion again via an optical-electrical-optical wavelength conversion unit to restore the original wavelength optical signal. The network management unit is used to perform device status monitoring and alarms.

[0098] like Figure 10As shown, taking a point-to-point duplex transmission system formed by two functionally symmetrical optical transceivers connected by an optical fiber as an example, the optical transceiver 1 and the optical transceiver 2 are respectively located at the user side and the opposite end. The wavelength division multiplexer combines optical signals of different wavelengths into an optical fiber at the sending end; and separates the composite optical signal into each wavelength channel at the receiving end. The optical-electric conversion module converts electrical signals into optical signals or converts optical signals into electrical signals; the optical-electric conversion module includes a receiver optical sub-assembly (ROSA) and a transmitter optical sub-assembly (TOSA). The working process of the sending end (optical transceiver 1) includes: a plurality of heterogeneous signals are accessed to the optical transceiver 1 from external devices, including analog signals, digital signals, and optical signals; the signal preprocessing includes: the analog signals are digitized by an analog-to-digital converter and sent to the FPGA; the digital signals are converted into TTL level by a communication interface chip (MAX3490 / MAX3323) and sent to the FPGA; the optical signals enter the optical-electric-optical wavelength conversion unit, are first received by the ROSA into electrical signals, then are regenerated by the limiting amplifier and the CDR, and finally are modulated to the standardized wavelength by the TOSA. The FPGA performs a time division multiplexing (TDM) algorithm: a plurality of low-speed digital signals are integrated into a high-speed serial data stream; the high-speed serial data stream drives the SFP+ optical module and is modulated to the DWDM wavelength; the analog video signal is reconstructed by the DAC and is modulated to the CWDM wavelength; and all the wavelength optical signals are sent to the wavelength division multiplexer. The wavelength division multiplexer combines all the wavelength optical signals and couples them into a single optical fiber to send to the optical transceiver 2.

[0099] The working process of the receiving end (optical transceiver 2) includes: the optical transceiver 2 receives the composite optical signal transmitted from the optical fiber, and the wavelength division multiplexer separates the composite optical signal into each wavelength channel; the signal restoration step includes: signal restoration: the analog signal such as the 1351 nm optical signal enters the optical-electric-optical wavelength conversion unit, is received by the ROSA into an electrical signal, and is recovered into an analog video signal by the wideband amplifier (LMH6643); the digital signal such as the 1550.12 nm optical signal enters the SFP+ optical module, is received by the TOSA into an electrical signal, and is recovered into the original RS422 / RS232 / network signal by the FPGA demultiplexing; the optical signal is directly output after being processed by the optical-electric-optical wavelength conversion unit if it needs to be transmitted; and various signals are output to the terminal device through the corresponding interface. The heterogeneous signals in the embodiment are differentially processed: the analog signal goes through a high linearity analog link (ADC / DAC); the digital signal goes through a FPGA TDM link; and the optical signal goes through an optical-electric-optical wavelength conversion link.

[0100] The specific limitations of the optical transmission device based on heterogeneous signal differential processing and optical-electric-optical wavelength conversion can be referred to the limitations of the optical transmission method based on heterogeneous signal differential processing and optical-electric-optical wavelength conversion in the foregoing, which will not be repeated here; each unit or module in the optical transmission device based on heterogeneous signal differential processing and optical-electric-optical wavelength conversion can be realized by software, hardware, and combinations thereof, in whole or in part; each module can be embedded in or independent of the processor in the computer device in hardware form, or can be stored in the memory in the computer device in software form, so as to be called and executed by the processor to perform the operations corresponding to each module.

[0101] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above functional units and modules is exemplified, and in actual application, the above functions can be completed by different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above.

[0102] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that; it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. Optical transmission method based on heterogeneous signal differential processing and opto-electro-optical wavelength conversion, characterized in that, The method comprises: receiving a multi-service heterogeneous input signal containing analog signals and / or digital signals, and classifying the signals according to their physical characteristics, and routing the classified multi-service heterogeneous input signal to corresponding dedicated processing channels; wherein the physical characteristics include signal type, synchronization requirement and linearity requirement; the dedicated processing channels include analog processing channels and digital processing channels; for the analog signals routed to the analog processing channels, processing the signals by a path dominated by analog circuits, and modulating the processed analog signals onto a first set of preset optical wavelengths by a high-precision electro-optical conversion module; for the digital signals routed to the digital processing channels, performing time division multiplexing on the signals by a programmable logic device to integrate the signals into a high-speed data stream, and modulating the high-speed data stream onto a second set of preset optical wavelengths by a standard optical module; coupling the optical signals carrying the first set of preset optical wavelengths and the second set of preset optical wavelengths into a single optical fiber for transmission by a wavelength division multiplexer; the analog signals at least include clock signals and radio frequency signals; the clock signals are regenerated and synchronized by a circuit containing a phase-locked loop; the radio frequency signals are processed by a linear amplification circuit to maintain signal bandwidth, linearity and signal-to-noise ratio; the first set of preset optical wavelengths and the second set of preset optical wavelengths correspond to coarse wavelength division multiplexing bands and dense wavelength division multiplexing bands respectively, and a mixed multiplexing strategy of coarse wavelength division multiplexing channels and dense wavelength division multiplexing channels is used in the coupling for transmission step; before the unified wavelength division multiplexing transmission, a wavelength conversion step is further included: by an optical-electrical-optical wavelength conversion unit, converting non-standard wavelength optical signals emitted by customer-side equipment into standardized wavelength division multiplexing wavelengths in the first set of preset optical wavelengths or the second set of preset optical wavelengths.

2. The optical transmission method based on heterogeneous signal differential processing and electro-optical wavelength conversion according to claim 1, characterized in that, integrating a network management unit inside the transmission equipment; the network management unit monitors key operating parameters of each functional module in real time, and generates a pre-warning information when the key operating parameters exceed corresponding preset thresholds, the key operating parameters at least include received optical power, transmitted optical power, working temperature, power supply voltage and laser bias current of the optical module.

3. The optical transmission method based on heterogeneous signal differentiation processing and electro-optical-optical wavelength conversion according to claim 1, characterized in that, the wavelength range of the coarse wavelength division multiplexing bands includes 1271.0nm to 1611.0nm; the wavelength range of the dense wavelength division multiplexing bands includes 1528.77nm to 1563.86nm; the programmable logic device is an FPGA.

4. Optical transmission apparatus based on heterogeneous signal differentiated processing and opto-electro-optical wavelength conversion, characterized in that, The apparatus is used to implement the optical transmission method based on heterogeneous signal differentiation processing and optical-electrical-optical wavelength conversion according to any one of claims 1 to 3, and the apparatus comprises: a signal identification and routing module for classifying and channeling the input multi-service heterogeneous input signal; an analog signal processing unit containing a phase-locked loop circuit for clock signals and a linear amplification circuit for radio frequency signals, and connected to a high-precision electro-optical conversion module; a digital signal processing unit containing a programmable logic device configured to perform time division multiplexing on multiple low-speed digital signals, and a standard optical module. Wavelength division multiplexing / demultiplexing unit, for multiplexing multi-wavelength optical signals from different processing units into a single fiber at the sending end, and demultiplexing at the receiving end; Network management unit, for performing device state monitoring and alarming.

5. The optical transmission apparatus based on heterogeneous signal differentiation processing and O-E-O wavelength conversion according to claim 4, characterized in that, The programmable logic device includes an FPGA chip with model number XC7A35T-1FGG484, which is configured to receive low-speed digital signals from multiple communication interface chips, perform time division multiplexing algorithm internally, and integrate into one high-speed serial data stream.

6. The optical transmission apparatus based on heterogeneous signal differentiation processing and O-E-O wavelength conversion according to claim 5, wherein, The analog signal processing unit includes: Analog-to-digital converter, configured to convert the input analog video signal into a parallel digital video signal under the synchronization of the sampling clock provided by the FPGA chip, and transmit it to the FPGA chip; Digital-to-analog converter, the parallel data input end of the digital-to-analog converter is connected to the video data output bus of the FPGA chip, and the clock input end receives the video synchronization clock signal from the FPGA, the analog-to-digital converter is configured to convert the parallel digital video signal into a differential analog current output signal; High-speed operational amplifier, the non-inverting input end of the high-speed operational amplifier is connected to the analog current output end of the digital-to-analog converter, to convert the differential analog current output signal into a single-ended voltage signal, and perform buffering and gain conditioning operations to output an analog video signal with a peak-to-peak value meeting the preset standard; Wherein, the closed-loop gain of the high-speed operational amplifier is set by a resistance feedback network.

7. The optical transmission apparatus based on heterogeneous signal differentiation processing and opto-electro-optical wavelength conversion according to claim 6, characterized in that, The communication interface chip includes an RS232 transceiver with model number MAX3323EEUE and an RS422 transceiver with model number MAX3490EESA, which are used to realize bidirectional conversion between FPGA logic level and external standard serial communication level.

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