FIFO flow control system, peripheral interface and processor

Abstract

The invention discloses an FIFO (First In First Out) flow control system, a peripheral interface and a processor, and belongs to the technical field of communication. The FIFO flow control system comprises a transmitting end and a receiving end; the receiving end comprises a first FIFO buffer used for receiving external serial data; the receiving end generates and outputs a coding signaling with a flow control state according to the occupancy rate of the first FIFO buffer; the transmitting end comprises a second FIFO buffer; and the sending end determines the selected flow control data according to the coding signaling of the receiving end, and loads the flow control data to the second FIFO buffer for sending. The FIFO flow control system further comprises a connecting line which is connected between the receiving end and the sending end and used for receiving the coding signaling sent by the receiving end and transmitting the coding signaling to the sending end. And the connecting line is a flow control signal line, generates a flow control signal according to the received coding signaling and transmits the flow control signal to the transmitting end. According to the invention, the reliability and real-time performance of the FIFO flow control system can be improved.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a FIFO flow control system, peripheral interface, and processor. Background Technology

[0002] In complex embedded systems requiring point-to-point data transmission, such as automotive ADAS (Advanced Driver Assistance Systems), industrial control, and high-performance computing systems, related technologies commonly employ simple, binary-signal-based FIFO (First In First Out) flow control mechanisms. These include RTS / CTS (Request to Send / Clear to Send) protocols or custom Ready / Busy signal flow control mechanisms. Essentially, these mechanisms act as an "on / off" valve that cannot distinguish data priorities. When processing mixed-criticality data streams, this can lead to a "priority inversion" problem, where high-priority data is blocked by low-priority data, compromising system reliability and real-time performance. Summary of the Invention

[0003] This invention provides a FIFO flow control system, peripheral interface, and processor to improve the reliability and real-time performance of the FIFO flow control system.

[0004] In a first aspect, embodiments of the present invention provide a FIFO flow control system, comprising: a transmitter and a receiver;

[0005] The receiving end includes: a first FIFO buffer for receiving external serial data; the receiving end generates and outputs coded signaling with flow control status based on the occupancy rate of the first FIFO buffer;

[0006] The transmitting end includes: a second FIFO buffer; the transmitting end determines the selected flow control data according to the encoded signaling of the receiving end, and loads the flow control data into the second FIFO buffer for transmission.

[0007] Optionally, the receiver may also include:

[0008] The status determination circuit is connected to the first FIFO buffer and generates the corresponding status code based on the occupancy rate of the first FIFO buffer.

[0009] The signaling generation circuit is connected to the state determination circuit and generates coded signaling with flow control status based on the status code output by the state determination circuit.

[0010] Optionally, the state determination circuit includes:

[0011] Multiple first comparators are connected to a first FIFO buffer, and the occupancy rate of each first comparator is compared with the occupancy rate of the first FIFO buffer to obtain multiple first comparison results;

[0012] The encoder is connected to multiple first comparators, receives multiple first comparison results, and generates corresponding digital codes.

[0013] The multiplexer connects to the encoder and maps digital codes to corresponding duty cycle values ​​as status codes.

[0014] Optionally, multiple first comparators are configured to have different occupancy rates;

[0015] The first comparator is configured to output the valid value of the first comparison result when the occupancy rate of the first FIFO buffer reaches the occupancy rate of the first comparator.

[0016] The encoder is configured to respond to the first comparison result of the first comparator with the highest occupancy rate of the output valid value, and generate a digital code representing the flow control state.

[0017] Optionally, the signaling generation circuit includes a PWM generator, which receives the duty cycle value output by the state determination circuit and generates a PWM signal as coded signaling based on the duty cycle value.

[0018] Optionally, the receiving end may also include: an application data buffer for storing data written to the first FIFO buffer.

[0019] Optionally, the sending end further includes:

[0020] The decoding mapping circuit receives and decodes the received encoded signaling, obtains the flow control status of the encoded signaling, and generates a license level with the flow control status.

[0021] The transmission control module is connected to the decoding mapping circuit and the second FIFO buffer respectively. It obtains the permission level, determines the selected flow control data, and loads the flow control data into the second FIFO buffer for transmission.

[0022] Optionally, the sender may also include multiple data queues with different priorities;

[0023] The transmission control module performs a loop traversal of the data queue according to the permission level, determines the selected flow control data, loads the flow control data into the second FIFO buffer, and transmits it.

[0024] Optionally, the sending control module performs a loop traversal of the data queue according to the permission level to determine the selected flow control data, including: in each sending cycle, the sending control module checks the data queue level by level according to the priority from high to low, and determines the selected flow control data in the first data queue with a priority not lower than the permission level and which is not empty.

[0025] Optionally, the decoding mapping circuit includes:

[0026] The input acquisition unit receives the encoded signaling received by the transmitter and measures the duty cycle value of the encoded signaling as a characteristic parameter of the encoded signaling;

[0027] Multiple second comparators are connected to the input capture unit respectively, and the feature parameters of the encoded signaling are compared with the preset interval threshold of each second comparator to obtain multiple second comparison results;

[0028] The decoder connects to multiple second comparators, receives multiple second comparison results, and generates a license level code that represents the license level.

[0029] Optionally, the decoding mapping circuit further includes: a status register, which is connected to the decoder and the transmission control module respectively, receives the license level code sent by the decoder, and maps the license level code to a license level.

[0030] Optionally, the FIFO flow control system further includes: a connecting line, connected between the receiver and the transmitter, for receiving coded signaling sent by the receiver and transmitting it to the transmitter; the connecting line is a flow control signal line, for generating flow control signals based on the received coded signaling and transmitting them to the transmitter.

[0031] Optionally, the flow control status includes at least four levels, namely, highest priority reception, high priority reception, all priority reception, and stop transmission.

[0032] Secondly, embodiments of the present invention also provide a peripheral interface, including: the FIFO flow control system as provided in any embodiment of the present invention.

[0033] Thirdly, embodiments of the present invention also provide a processor, including: a peripheral interface as provided in any embodiment of the present invention.

[0034] The FIFO flow control system provided in this invention provides a flow control mechanism capable of identifying flow control status and adjusting flow control data accordingly. Specifically, the receiving end provides coded signaling with flow control status based on the occupancy rate of the first FIFO buffer, and the sending end selects matching flow control data based on the coded signaling and loads it into the second FIFO buffer. Thus, selective data transmission between the sending and receiving ends can be achieved based on the occupancy rate of the first FIFO buffer. This invention abandons traditional binary flow control signals and uses coded signaling that represents the flow control status to perform fine-grained flow control on the sending end. The coded signaling accurately transmits the physical state of the first FIFO buffer in the receiving end to the sending end, thereby achieving intelligent scheduling of any FIFO flow control system with multiple priority data sources. Under certain communication pressure, it can prioritize the transmission of critical data, solving the fundamental technical defect of "priority inversion" inevitably caused by a "one-size-fits-all" control method, thereby ensuring the real-time performance, reliability, and overall performance of the entire system.

[0035] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a schematic diagram of the structure of a FIFO flow control system provided in an embodiment of the present invention;

[0038] Figure 2 This is a schematic diagram of another FIFO flow control system provided in an embodiment of the present invention;

[0039] Figure 3 This is a schematic diagram of the structure of a receiving end provided in an embodiment of the present invention;

[0040] Figure 4 This is a schematic diagram of the structure of a transmitting end provided in an embodiment of the present invention;

[0041] Figure 5 This is a schematic diagram of a process for a sending control module to select flow control data, provided in an embodiment of the present invention.

[0042] Figure 6This is a schematic diagram of another FIFO flow control system provided in an embodiment of the present invention;

[0043] Figure 7 This is a schematic diagram of another FIFO flow control system provided in an embodiment of the present invention;

[0044] Figure 8 This is a schematic diagram of the structure of a peripheral interface provided in an embodiment of the present invention;

[0045] Figure 9 This is a schematic diagram of the structure of a processor provided in an embodiment of the present invention. Detailed Implementation

[0046] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0047] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0048] As mentioned in the background section, the FIFO flow control mechanism in related technologies can impair the reliability and real-time performance of the system. The following explanation uses UART (Universal Asynchronous Receiver / Transmitter) communication between ECUs (Electronic Control Units) as an example to illustrate the cause of this technical problem:

[0049] UART is the fundamental interface for serial communication between ECUs. To prevent data loss due to delayed processing at the receiving end during UART communication, the industry commonly employs flow control mechanisms. For example, the widely adopted RTS / CTS protocol, integrated into mainstream automotive-grade MCUs (Micro Control Units), is based on two independent control signal lines, transmitting allow and stop transmission commands separately. In modern high-performance embedded systems, such as automotive electronic control units (ECUs) and industrial automation controllers, advanced systems-on-chips (SoCs) or microcontrollers (MCUs) generally rely on first-in-first-out (FIFO) buffers for data exchange. To prevent FIFO overflow due to excessively fast data producer rates or delayed consumer processing, the industry commonly uses flow control mechanisms based on binary "Ready / Busy" or "CTS / RTS" handshake signals. The working principle is that when the receiver's FIFO waterline exceeds a preset high threshold, it changes the level of a dedicated control signal line, issuing a global "stop transmission" command to the data transmitter, thereby prohibiting the transmitter from sending any data.

[0050] However, as system functions become increasingly complex, data streams transmitted through the same FIFO flow control system often contain different levels of criticality. In such scenarios, traditional binary flow control is a "one-size-fits-all" approach that cannot identify the importance (priority) of data. Once a "stop sending" is triggered, it indiscriminately suspends the transmission of all data, thus causing a "priority inversion" problem. This can lead to high-priority data being blocked by low-priority data, for example, the highest-priority safety-critical data being blocked by the lowest-priority log data. This seriously threatens the reliability, real-time performance, and functional safety of the system, and wastes data link bandwidth.

[0051] To address the aforementioned technical problems, embodiments of the present invention provide a FIFO flow control system. Figure 1 This is a schematic diagram of the structure of a FIFO flow control system provided in an embodiment of the present invention. See also... Figure 1 The FIFO flow control system 100 includes a transmitter 120 and a receiver 110. The receiver 110 includes a first FIFO buffer 111. The first FIFO buffer 111 receives external serial data; the receiver 110 generates and outputs an encoded signaling flow control state (FCL) based on the occupancy rate of the first FIFO buffer 111. The transmitter 120 includes a second FIFO buffer 121; the transmitter 120 determines the selected flow control data based on the encoded signaling flow control state (FCL) from the receiver 110, and loads the flow control data into the second FIFO buffer 121 for transmission.

[0052] The flow control state indicates the data reception capability of the receiver 110 under the occupancy rate of the first FIFO buffer 111. For example, the flow control state may include different states such as highest priority reception, high priority reception, all priority reception, and stop transmission. Furthermore, according to actual application requirements, the flow control state can be further increased, decreased, or adjusted, and the types and portions of data allowed to be received under different flow control states can be set. Specifically, the flow control state may indicate the data priority allowed to be transmitted by the transmitter 120. For example, the "all priority reception" flow control state indicates that all priority data can be transmitted; the "highest priority reception" flow control state indicates that only data with the highest priority can be transmitted; the "high priority reception" flow control state indicates that only data with high priority can be transmitted, where which priorities belong to high priority can be set according to actual needs; the "stop transmission" flow control state indicates that all priority data transmission is prohibited. The encoded signaling FCL differs with different flow control states, for example, manifested as different waveforms, different amplitudes, or different duty cycles, which can be specifically set according to actual needs.

[0053] The transmitter 120 can internally store different types of data, such as data with different priorities. After acquiring the coded signaling FCL, the transmitter 120 can search for data matching the flow control state from the stored data to be transmitted as the selected flow control data, and load the flow control data into the second FIFO buffer 121.

[0054] The FIFO flow control system 100 provided in this embodiment of the invention provides a flow control mechanism that can identify the flow control status and adjust the flow control data accordingly. Specifically, the receiving end 110 provides coded signaling FCL with flow control status according to the occupancy rate of the first FIFO buffer 111, and the transmitting end 120 selects matching flow control data according to the coded signaling FCL and loads it into the second FIFO buffer 121. Accordingly, selective data transmission between the transmitting end 120 and the receiving end 110 can be realized according to the occupancy rate of the first FIFO buffer 111. This invention abandons the traditional binary flow control signal and adopts an encoded signaling FCL that represents the flow control state to perform fine-grained flow control on the transmitting end 120. The encoded signaling FCL accurately transmits the physical state of the first FIFO buffer 111 in the receiving end 110 to the transmitting end 120, thereby realizing intelligent scheduling of any FIFO flow control system 100 with multiple priority data sources. When facing certain communication pressure, it can support the priority protection of the transmission of key data, solve the fundamental technical defect of "priority inversion" that is inevitably caused by the "one-size-fits-all" control method, and thus ensure the real-time performance, reliability and overall performance of the entire system.

[0055] In summary, the embodiments of the present invention provide a universal point-to-point data transmission method and system for any data transmission with a FIFO buffer, and a priority-based flow control method.

[0056] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, a UART communication system with flow control applied in the field of automotive electronics is described in detail below as a specific embodiment of the present invention. It is understood that this embodiment is for illustrative purposes only and is not intended to limit the scope of protection of the present invention. Based on the same inventive concept, it can be applied to other serial buses such as SPI and I2C, or other scenarios such as communication between IP cores within a SoC.

[0057] In this UART embodiment, the FIFO flow control system 100 consists of a receiver 110 and a transmitter 120 at the top-level architecture. They exchange data via a standard TXD / RXD data line. The core technical solution lies in using a dedicated flow control signal line for closed-loop, priority-based flow control. This system is designed to fundamentally solve the "priority inversion" problem that is unavoidable in traditional hardware flow control through sophisticated hardware and software collaboration.

[0058] To achieve fine-grained control of the data flow and completely replace traditional hardware flow control, this embodiment defines a four-level flow control model as the core rule foundation. Specifically, it uses a four-level flow control state as an example, and illustrates this with PWM signals as the encoded signaling, representing different flow control states with different duty cycles. This model encodes different flow control states at the receiver 110 through different duty cycles of the PWM signal, thereby transmitting explicit scheduling instructions to the transmitter 120. A specific embodiment is defined in Table 1 below:

[0059] Table 1

[0060]

[0061] Table 1 shows the four-level flow control model, emphasizing that higher priority values ​​represent higher priorities. Specifically, the data queues in the multi-priority queues are ranked from highest to lowest priority as follows: First data queue (Prio3), priority 3; Second data queue (Prio2), priority 2; Third data queue (Prio1), priority 1; Fourth data queue (Prio0), priority 0. Furthermore, occupancy rates within the same range correspond to the same flow control state. Specifically, occupancy rates within [0%, 50%) correspond to all priority receiving states with a permission level of 0; occupancy rates within [50%, 75%) correspond to high-priority receiving states with a permission level of 2; occupancy rates within [75%, 90%) correspond to the highest-priority receiving state with a permission level of 3; and occupancy rates within [90%, 100%] correspond to a stopped-transmission state, with the permission level set to any value greater than the maximum priority (in this case, any value greater than 3).

[0062] The fundamental difference between this model and traditional RTS / CTS hardware flow control is that traditional flow control has only one trigger point (e.g., 90%), which immediately triggers a "stop transmitting" state. This solution, however, sets multiple intermediate flow control states (such as "high priority reception" and "highest priority reception") before reaching the final "stop transmitting" state. These intermediate flow control states allow the system to prioritize the transmission of critical data when facing communication pressure, rather than abruptly stopping all transmissions. In this model, "stop transmitting" is the final and strongest means of flow control upgrade, fully compatible with and covering the core functions of traditional hardware flow control.

[0063] The following description provides an example of the specific structure that the FIFO flow control system may have, but it is not intended to limit the invention.

[0064] Figure 2 This is a schematic diagram of another FIFO flow control system structure provided in an embodiment of the present invention. See also... Figure 2 In one embodiment, the FIFO flow control system 200 may optionally include a connecting line LF, which is connected between the receiving end 210 and the transmitting end 220. The connecting line LF receives the coded signaling sent by the receiving end 210 and transmits it to the transmitting end 220.

[0065] For example, the connecting line LF may only have the function of information transmission. That is, the receiving end 210 transmits the encoded signaling FCL to the connecting line LF, and then the connecting line LF transmits the encoded signaling to the sending end 220, so that the sending end 220 can directly receive the encoded signaling.

[0066] Alternatively, the LF connection line can be a flow control signal line, which can process the received signal before transmission. For example, the flow control signal line generates a flow control signal based on the received coded signaling and transmits it to the transmitter 220; the transmitter 220 receives the flow control signal and parses it to obtain the coded signaling. That is, the flow control signal transmitted on the flow control signal line contains at least the information of the coded signaling, and may also contain other information required for data transmission.

[0067] See also Figure 2 Based on the above embodiments, the receiving end 210 may optionally further include a status determination circuit 212 and a signaling generation circuit 213. The status determination circuit 212 is connected to the first FIFO buffer 2111, and generates a corresponding status code based on the occupancy rate of the first FIFO buffer 2111. The signaling generation circuit 213 is connected to the status determination circuit 212, and generates coded signaling with flow control status based on the status code output by the status determination circuit 212.

[0068] For example, in the receiver 210, the first FIFO buffer 2111 can be specifically set in the receiver 211, which is, for example, a serial receiver, specifically a basic UART receiver. The first FIFO buffer 2111 can receive data sent by the second FIFO buffer 2211 through the receive terminal RXD.

[0069] In this embodiment, the overall function of the receiver 210 is to receive serial data from the receiver terminal RXD, and the state determination circuit 212 and the signaling generation circuit 213 autonomously generate and output an encoded signaling with a flow control state on the flow control signal line according to the occupancy rate of the first FIFO buffer 2111 inside the receiver 211.

[0070] See also Figure 2 Based on the above embodiments, optionally, the transmitting end 220 further includes a decoding mapping circuit 222 and a transmitting control module 223. The decoding mapping circuit 222 receives and decodes the received encoded signaling, obtains the flow control status of the encoded signaling, and generates a permission level with the flow control status. The transmitting control module 223 is connected to both the decoding mapping circuit 222 and the second FIFO buffer 2211. The transmitting control module 223 obtains the permission level, determines the selected flow control data, and loads the flow control data into the second FIFO buffer 2211 for transmission.

[0071] For example, in the transmitter 220, the second FIFO buffer 2211 can be specifically set in the transmitter 221, which is, for example, a serial transmitter, specifically a basic UART transmitter. The permission level is, for example, the lowest priority allowed for data transmitted by the transmitter 220. The second FIFO buffer 2211 can transmit data externally through the transmit terminal TXD.

[0072] In this embodiment, the overall function of the transmitter 220 is as follows: the decoding mapping circuit 222 receives and decodes the flow control signal from the flow control signal line, and provides the mapped permission level to the transmission control module 223. The transmission control module 223 schedules the data inside the transmitter 220 based on the permission level, and finally writes the selected flow control data into the second FIFO buffer 2211 inside the transmitter 221, and then the second FIFO buffer 2211 serially transmits the data through the transmission terminal TXD. For example, the transmitter 220 can store a multi-priority queue 224, which includes multiple data queues with different priorities. The transmission control module 223 can schedule the multi-priority queue 224 based on the permission level. For example, it can determine the selected flow control data from the data queues with a priority not lower than the permission level, preferably selecting the flow control data from the highest priority non-empty data queue that meets the above requirements, so as to prioritize the transmission of high-priority data.

[0073] In this system, the first FIFO buffer 2111, the second FIFO buffer 2211, the state determination circuit 212, the signaling generation circuit 213, and the decoding mapping circuit 222 are all hardware circuits, while the transmission control module 223 is a software control module integrated into the controller. Thus, in the FIFO flow control system 200 provided by this embodiment of the invention, the hardware layer is responsible for performing high-speed, deterministic tasks, such as physical transmission and reception, state determination, and signal encoding and decoding; the software layer is responsible for more complex, flexible tasks, such as data processing and priority scheduling. Connecting lines (e.g., flow control signal lines), as key channels connecting the transceiver ends, accurately transmit the real-time state of the receiver 210 hardware to the software decision-making core of the transmitter 220, thereby forming a complete closed-loop control system.

[0074] Based on the above embodiments, optionally, the encoded signaling is a PWM signal. For example, the signaling generation circuit 213 includes a PWM generator. The PWM generator receives the duty cycle value output by the state determination circuit 212 and generates a PWM signal as the encoded signaling based on the duty cycle value. By using different duty cycle values ​​to represent different encoded signals, the generation process of the encoded signaling is easy to control, and the encoded signaling is easy to parse. It is understood that the above settings are not intended to limit the present invention. In other embodiments, features such as edge transitions, waveforms, or amplitudes can also be used to identify the differences between different encoded signals, as long as the transmitting end 220 and the receiving end 210 predefine the corresponding encoding and decoding logic.

[0075] In one specific implementation, optionally, the flow control state includes at least four levels: highest priority reception, high priority reception, all priority reception, and stop transmission. Specifically, the multi-priority queue 224 includes data queues with at least four priority levels; then, highest priority reception means that the receiving end 210 is only allowed to receive data with the highest priority; high priority reception means that the receiving end 210 is allowed to receive data of all priorities ≥ a certain priority threshold, which can be selected as a priority between the highest and lowest priorities as needed; all priority reception means that the receiving end 210 is allowed to receive data of all priorities; and stop transmission means that the receiving end 210 is not allowed to receive data of all priorities.

[0076] As mentioned above, the current technological evolution of FIFO flow control mechanisms is limited to the software level. It requires the construction of complex upper-layer protocols and scheduling logic to compensate for hardware deficiencies. This leads to complex software development, verification, and functional safety certification, increasing costs and inevitably introducing software processing latency. Therefore, priority management in related FIFO flow control mechanisms relies entirely on complex upper-layer software, introducing significant latency and uncertainty, fundamentally conflicting with the determinism and low latency required by functional safety and high-performance systems. In contrast, this invention provides an adaptive priority FIFO flow control system and method based on coded signaling. At the hardware level, it requires only a flow control signal line as a connection, and at the software level, only a lightweight driver module needs to be developed. This makes the implementation cost of this invention extremely low, the development cycle short, and allows for rapid deployment across the entire product line using existing resources.

[0077] This invention proposes a general approach that transforms flow control signals from simple "switches" into "encoded channels" carrying multi-level flow control state information. To achieve this, the solution provided by this invention is as follows: abandoning traditional binary flow control signals, a dedicated flow control signal line is used. Encoded signaling representing multiple states is output on this flow control signal line to perform refined, priority-based flow control on the data sender. A key feature of this solution is the use of directly measurable electrical signals. Taking a PWM signal as an example, flow control state information is transmitted on the flow control signal line connecting the two ends through periodic PWM waveforms with variable duty cycles, instead of traditional binary levels. This provides a general, adaptive FIFO flow control method and system that ensures high-priority data receives priority transmission under any data load, thereby ensuring the real-time performance, reliability, and overall performance of the entire system (e.g., an embedded system) using this FIFO flow control system 200. This invention brings the intelligence of priority recognition down from complex upper-level software to the efficient hardware driver level, thereby directly eliminating the priority inversion problem at any FIFO interface.

[0078] The specific structures of each functional circuit are illustrated below. Figure 3 This is a schematic diagram of a receiving end provided in an embodiment of the present invention. See also: Figure 3 In one embodiment, the receiver 300 may optionally include a first FIFO buffer 311, a state determination circuit 320, and a signaling generation circuit 330 to implement the flow control function of the receiver 300. Furthermore, the receiver 300 may further include an application data buffer 340 to buffer the data received by the first FIFO buffer 311. The specific structure and operation of each functional module in the receiver 300 are described below by way of example.

[0079] As mentioned earlier, the first FIFO buffer 311 can be set in the receiver 310, which will not be described again.

[0080] See also Figure 3In one embodiment, the state determination circuit 320 may optionally include: a plurality of first comparators 321 (where 321 represents the collective term for all first comparators), an encoder 322, and a multiplexer 323. The plurality of first comparators are respectively connected to a first FIFO buffer 311, and the plurality of first comparators 321 compare the occupancy rate of each first comparator with the occupancy rate of the first FIFO buffer 311 to obtain a plurality of first comparison results. The encoder 322 is connected to the plurality of first comparators, and the encoder 322 receives the plurality of first comparison results and generates a corresponding digital code D1. The multiplexer 323 is connected to the encoder 322, and the multiplexer 323 maps the digital code D1 to a corresponding duty cycle value as the state code S1. Figure 3 The example provided includes a plurality of first comparators 321, including a first first comparator 3211, a second first comparator 3212, and a third first comparator 3213, but this is not intended to limit the invention.

[0081] For example, each first comparator is configured with a preset occupancy rate. The occupancy rate of the first FIFO buffer 311 is compared with this preset occupancy rate, and the comparison result is used as the first comparison result. That is, the first comparison result is used to indicate whether the occupancy rate of the first FIFO buffer 311 has reached the preset occupancy rate in the first comparator. For example, the occupancy rates configured for the first first comparator 3211, the second first comparator 3212, and the third first comparator 3213 are all different, for example, decreasing sequentially. The encoder 322 can store various combinations of first comparison results and their corresponding digital codes D1, each digital code D1 corresponding to a flow control state. The multiplexer 323 can store the correspondence between each digital code D1 and the duty cycle value, so that the state determination circuit 320 can ultimately generate a state code S1 representing the flow control state based on the occupancy rate of the first FIFO buffer 311.

[0082] It should be noted that the number of first comparators 321 can be determined based on the number of flow control states, as long as the encoder 322 can generate the digital code D1 corresponding to each flow control state based on the first comparison result. For example, the number of first comparators may be one less than the total number of flow control states. For instance, the number of first comparators 321 may be greater than or equal to 3.

[0083] Based on the above embodiments, optionally, multiple first comparators are configured to have different occupancy rates. For any one first comparator, the first comparator is configured to output a valid value of the first comparison result when the occupancy rate of the first FIFO buffer 311 reaches the occupancy rate of the first comparator, and to output an invalid value of the first comparison result when the occupancy rate of the first FIFO buffer 311 does not reach the occupancy rate of the first comparator; wherein the first comparison result is, for example, a one-bit binary result, specifically a level signal, with a valid value of, for example, 1 and an invalid value of, for example, 0.

[0084] Encoder 322 is configured to generate a digital code D1 representing the flow control state in response to the first comparison result of the first comparator with the highest occupancy rate of the output valid value. Specifically, the occupancy rates of different first comparators are used as different waterlines for FIFO flow control. When the occupancy rate of the first FIFO buffer 311 reaches a certain waterline, it must exceed all waterlines below that waterline. Therefore, once the first comparator with the highest occupancy rate of the output valid value is determined, the other first comparators with lower occupancy rates will also output valid values. In this embodiment, by setting encoder 322 to the first comparison result of the first comparator with the highest occupancy rate among the multiple parallel output valid values, it can ensure that a unique decision representing the most urgent situation can be made under any circumstances. The encoder 322 finally converts the judgment result into a unique digital code D1 representing the flow control state. The number of bits in the digital code D1 can be determined according to the number of flow control states, such that the number of combinations between the bits of the digital code D1 is greater than or equal to the number of flow control states.

[0085] See also Figure 3 In one embodiment, optionally, the signaling generation circuit 330 includes a PWM generator 331. The PWM generator 331 receives the duty cycle value output by the state determination circuit 320 and generates a PWM signal as the encoded signaling FCL based on the duty cycle value. In this way, the encoded signaling FCL under different flow control states are PWM signals with different duty cycles, which facilitates the sending end to parse the encoded signaling FCL.

[0086] See also Figure 3 Based on the above embodiments, optionally, the receiving end 300 further includes: an application data buffer 340; the application data buffer 340 stores the data written by the first FIFO buffer 311. In this embodiment, the application data buffer 340 is a software functional module. The first FIFO buffer 311 writes the received data into the application data buffer 340 for caching. Subsequently, when the device where the receiving end 300 is located needs to use data, it can retrieve it from the application data buffer 340.

[0087] The above embodiment illustrates the specific structure of the receiver 300. The state determination circuit 320 is not a single module, but a combinational logic circuit composed of multiple standard digital logic units, which is key to its ability to achieve high-speed autonomous decision-making. This pure hardware pipeline, consisting of multiple first comparators 321, encoders 322, and multiplexers 323, forms the core of the state determination circuit 320. It works in conjunction with the PWM generator 331 (which can specifically be a standard MCU timer peripheral) to form a complete hardware decision-making and execution link in the receiver 300. The application data buffer 340 in the software layer is functionally decoupled from this hardware link and is only responsible for processing the final data.

[0088] Taking the aforementioned four-level flow control model as a specific example, for receiver 300, a specific implementation example is as follows:

[0089] The state determination circuit 320 in the receiver 300 consists of multiple first comparators 321, an encoder 322, and a multiplexer 323. The multiple first comparators 321 include a first first comparator 3211, a second first comparator 3212, and a third first comparator 3213, with defined occupancy rates of 50%, 75%, and 90%, respectively. This is equivalent to comparing the occupancy rate of the first FIFO buffer 311 with the different occupancy rates (50%, 75%, 90%) defined by the four-level flow control model in real time through the multiple first comparators 321. The first first comparator 3211, the second first comparator 3212, and the third first comparator 3213 each output a 1-bit binary first comparison result (denoted as C90, C75, and C50, respectively). These parallel first comparison results are fed into encoder 322. Since when the water level reaches 90%, it must also simultaneously satisfy the conditions of "reaching 75%" and "reaching 50%", at which point multiple first comparators will output 1 (valid value). Encoder 322 is designed to respond only to the input with the highest predefined priority among multiple simultaneously valid inputs (i.e., the priority of each first comparison result is: C90>C75>C50), thereby ensuring that a unique decision representing the most urgent situation can be made under any circumstances. The encoder 322 finally converts the judgment result into a unique 2-bit digital code D1 representing the flow control state. This digital code D1 is mapped to a preset duty cycle value after passing through multiplexer 323, forming a status code S1 representing the flow control state. This status code S1 is then used to drive PWM generator 330 (e.g., a hardware timer module), thereby generating a PWM signal with a precise duty cycle on the flow control signal line as the encoded signaling FCL. The entire "compare-encode-generate PWM" process is completed by hardware within a few clock cycles without any CPU intervention, thus ensuring extremely low latency and absolute determinism in flow control decisions. The correspondence between the outputs of each level in the state determination circuit 320, corresponding to the aforementioned four-level flow control model, can be found in Table 2.

[0090] Table 2

[0091]

[0092] Figure 4 This is a schematic diagram of the structure of a transmitting end provided in an embodiment of the present invention. See also... Figure 4In one embodiment, optionally, the transmitter 400 includes a decoding mapping circuit 420, a transmission control module 430, and a second FIFO buffer 411 to implement the flow control function of the transmitter 400. The transmitter 400 may also store a multi-priority queue 440 to provide multiple data queues with different priorities; for example, the multi-priority queue 440 may include multiple data queues with different priorities, such as a first data queue Prio3 and a second data queue Prio2. The specific structure and operation of each functional module in the transmitter 400 are described below by example.

[0093] As mentioned earlier, the second FIFO buffer 411 can be set in the transmitter 410, and will not be described again.

[0094] See Figure 4 In one embodiment, the decoding mapping circuit 420 may optionally include: an input capture unit 421, a plurality of second comparators 422 (where 422 represents the collective term for all second comparators), and a decoder 423. Further, the decoding mapping circuit 420 may also include a status register 424 for mapping the license level code S2 to a license level and storing it. The decoding mapping circuit 420 will be described in detail below.

[0095] The input capture unit 421 receives the encoded signaling FCL received from the transmitter 400 and measures the duty cycle value of the encoded signaling FCL as a feature parameter of the encoded signaling FCL. Multiple second comparators are connected to the input capture unit 421, and each second comparator compares its feature parameter of the encoded signaling FCL with a preset interval threshold to obtain multiple second comparison results. The decoder 423 is connected to multiple second comparators 422, receives the multiple second comparison results, and generates a license level code S2 representing the license level. Figure 4 The example provided includes a first second comparator 4221, a second second comparator 4222, and a third second comparator 4223, but this is not intended to limit the invention. For example, the number of second comparators 422 is greater than or equal to three.

[0096] In the decoding mapping circuit 420, each second comparator compares the duty cycle value extracted by the input capture unit 421 with its own preset interval threshold, and uses the comparison result as the second comparison result. The second comparison results of each second comparator are provided to the encoder 423 in parallel. Based on the comparison results between the duty cycle value and each preset interval threshold, the duty cycle value interval in which the duty cycle value lies can be determined. Since each duty cycle value interval corresponds one-to-one with the nominal duty cycle value of each encoded signaling FCL, knowing which duty cycle value interval the duty cycle value acquired by the decoding mapping circuit 420 lies in allows us to determine the flow control state represented by the encoded signaling FCL corresponding to that duty cycle value. Thus, even if the actual duty cycle value fluctuates compared to the nominal value due to interference or other reasons during the transmission of the encoded signaling FCL, the fluctuating duty cycle value still falls within the duty cycle range corresponding to the nominal duty cycle value, ensuring the accuracy of the second comparison result. This allows the decoder 423 to generate a license level code S2 that satisfies the license level under the correct flow control state based on multiple parallel second comparison results. For example, the preset interval threshold of each second comparator is set to the median value between every two adjacent nominal duty cycle values ​​to achieve maximum noise tolerance.

[0097] For example, decoder 423 processes multiple parallel second comparison results and generates corresponding permission level codes S2. Each permission level code S2 corresponds to a permission level. The permission level code S2 is, for example, a multi-bit numeric code, the number of bits of which can be determined according to the number of flow control states, at least ensuring that it can indicate the flow control data matching the selected flow control state to the transmission control module 430.

[0098] See Figure 4 Optionally, based on the above embodiments, the decoding mapping circuit 420 further includes a status register 424, which is connected to the decoder 423 and the transmission control module 430 respectively. The status register 424 receives the license level code S2 sent by the decoder 423 and maps the license level code S2 to a license level.

[0099] For example, the transmission control module 430 is integrated into the CPU, and the status register 424 can be a dedicated hardware status register in the flow control mechanism that can be read by the CPU. The task of the software-layer transmission control module 430 is to directly read the pre-calculated permission level in this status register 424, and then execute the scheduling algorithm for the multi-priority queue 440 based on this permission level. This design offloads all computational tasks related to signal parsing and classification from the CPU, minimizing software overhead, and eliminating the need to continuously occupy the CPU waiting for relevant signals from the flow control mechanism. While the relevant hardware is performing priority flow control tasks, the CPU can perform other tasks, making the CPU more efficient and improving the real-time response capability of the system.

[0100] Based on the above embodiments, optionally, the transmitting end 400 further includes multiple data queues with different priorities, each data queue having a different priority, for example, forming a multi-priority queue 440. Specifically, the transmitting control module 430 can perform a loop traversal of the data queues according to the permission level, determine the selected flow control data, and load the flow control data into the second FIFO buffer 411 for transmission. For example, the transmitting control module 430 sequentially determines whether the priority of each data queue meets the permission level requirements, and extracts the selected flow control data from the data queues that meet the requirements.

[0101] Specifically, the transmission control module 430 performs a loop traversal of the data queues according to the permission level to determine the selected flow control data. This includes: in each transmission cycle, the transmission control module 430 checks the data queues level by level according to priority from high to low, and determines the selected flow control data in the first non-empty data queue with a priority not lower than the permission level. In this way, it can ensure that the data in the non-empty data queue with the highest priority is used as flow control data, ensuring that the highest priority data in the non-empty queue is sent first, thus guaranteeing the reliability and timeliness of data transmission.

[0102] More specifically, at the start of a transmission cycle, the transmission control module 430 first performs a single hardware register read operation, directly retrieving the permission level from the status register 424 of the decoding mapping circuit 420. Next, the transmission control module 430 initiates a high-priority traversal loop, starting with the highest-priority data queue and checking downwards level by level. At each step of the loop, it performs a double condition check: first, it checks if the priority of the current data queue is not lower than the acquired permission level; second, if the first condition is met, it checks if the current data queue is not empty. If the current data queue is empty, the loop continues, checking the next lower-priority data queue. Once the first data queue that simultaneously meets both conditions is found, the transmission control module 430 immediately selects and extracts the flow control data from it and loads it into the second FIFO buffer 411.

[0103] The key to this data scheduling process is that once data is successfully extracted and loaded, the algorithm immediately exits the current traversal loop, thus completing a sending cycle. This mechanism ensures that at any given time, the system always prioritizes processing the highest priority data it can handle.

[0104] For example, the transmission period and the selected flow control data can be determined according to the data transmission protocol between the receiver and the transmitter. Taking the UART protocol as an example, the transmission period is the transmission period specified in the UART protocol. Since the UART protocol transmits one data byte at a time, the selected flow control data can also be a data byte in the first data queue that simultaneously meets both conditions. For example, this FIFO flow control process uses a triggering mechanism, for example, triggering the data scheduling of the next transmission period only after the previous transmission period has ended. In this way, since the loading decision occurs between two complete UART data frames, it will never interrupt the byte transmission that is taking place in the hardware, thus ensuring the protocol's compatibility with this FIFO flow control mechanism. The same principle applies to other communication protocols, ensuring the protocol's compatibility with this FIFO flow control mechanism, which will not be elaborated here.

[0105] For example, the number of bytes of flow control data extracted by the sending control module 430 in a single transmission can be determined according to the specific communication protocol, such as the same as the number of bytes that can be sent in one transmission cycle of the communication protocol; it can also be determined according to the current remaining storage capacity of the second FIFO buffer 411, for example, the larger the current remaining storage space of the second FIFO buffer 411, the more bytes are extracted; it can also be determined according to the flow control status, for example, the lower the permission level, the more bytes are extracted. The specific extraction rules can be set according to actual needs.

[0106] Taking the aforementioned four-level flow control model as a specific example, for the transmitter 400, a specific implementation example is as follows:

[0107] The internal structure of the transmitter 400 demonstrates how hardware and software work together to achieve precise responses to multi-level flow control states. The transmitter 400 implements a complete, autonomous license level decoding and mapping pipeline at the hardware layer. The transmitter 400 includes a transmitter 410 (containing a second FIFO buffer 411) and a decoding mapping circuit 420 at the hardware layer. This decoding mapping circuit 420 internally consists of an input capture unit 421, multiple second comparators 422, a decoder 423, and a status register 424. Specifically, the multiple second comparators 422 include three parallel second comparators: a first second comparator 4221, a second second comparator 4222, and a third second comparator 4223. All of these second comparators are hardware range comparators.

[0108] In the transmitter 400, the input capture unit 421 is responsible for measuring the flow control signal and calculating the real-time duty cycle value of the coded signaling FCL. This duty cycle value is then fed in parallel to multiple second comparators 422. Each second comparator is responsible for determining the relationship between the duty cycle value and its own preset interval threshold to determine whether the duty cycle value falls within a preset duty cycle value interval. The 1-bit second comparison result of these second comparators is sent to the decoder 423, which converts the multiple parallel second comparison results into a unique 2-bit license level code S2. This 2-bit license level code S2 is directly written into the status register 424. The 1-bit second comparison result is configured, for example, as follows: 1 is a valid value, representing that the duty cycle value has reached the preset interval threshold; 0 is an invalid value, representing that the duty cycle value has not reached the preset interval threshold. The status register 424 is, for example, a dedicated hardware status register that can be read by the CPU.

[0109] In this embodiment, the preset interval thresholds of each second comparator are set as the midpoint between any two adjacent nominal duty cycle values ​​to achieve maximum noise tolerance. Specifically, the preset interval thresholds in the first second comparator 4221, the second second comparator 4222, and the third second comparator 4223 are 87.5%, 62.5%, and 25%, respectively; correspondingly, the three second comparison results are denoted as C87.5, C62.5, and C25, respectively. The transmission license level mapping model is shown in Table 3 below:

[0110] Table 3

[0111]

[0112] The task of the software-layer transmission control module 430 is to directly read the pre-calculated permission level from the status register 424 and then use this permission level to execute the scheduling algorithm for the multi-priority queue 440. This design offloads all computational tasks related to signal parsing and classification from the CPU, minimizing software overhead and improving the system's real-time responsiveness.

[0113] Specifically, at the start of a transmission cycle, the algorithm first performs a single read operation on the status register 424, directly retrieving the permission level from the status register 424 of the decoding mapping circuit 420. Next, the transmission control module 430 initiates a high-priority traversal loop, starting with the highest-priority data queue (e.g., the first data queue, Prio3) and checking downwards level by level. At each step of the loop, it performs a double condition check: first, it checks if the priority of the current data queue is not lower than the acquired permission level; second, it checks if the data queue is not empty. If the current data queue is not lower than the permission level but is empty, the loop continues, checking the next lower-priority data queue. Once the first data queue that satisfies both conditions is found, the algorithm immediately extracts a data byte from it and loads it into the second FIFO buffer 411. It is important to emphasize that after successful data extraction and loading, the algorithm immediately exits the current traversal loop, thus completing one transmission cycle. This mechanism ensures that at any given time, the system always prioritizes the highest priority data it can process, and because the load decision occurs between two complete UART data frames, it never interrupts the byte transmission that is taking place in the hardware, thus guaranteeing protocol compatibility.

[0114] In one specific implementation, Figure 5 This is a schematic diagram of the process for a transmission control module to select flow control data according to an embodiment of the present invention. See 5. Specifically, in any transmission cycle, the process 500 for the transmission control module to select flow control data includes:

[0115] At box 505, read the license level.

[0116] At box 510, determine if Prio3's priority is not lower than the permission level. If yes, proceed to box 515; otherwise, end the data scheduling for this transmission cycle.

[0117] At box 515, determine if Prio3 is not empty. If yes, execute box 520; otherwise, execute box 525.

[0118] At box 520, extract flow control data from Prio3.

[0119] In one transmission cycle, the transmission control module extracts one byte of flow control data from Prio3 and loads it into the second FIFO buffer.

[0120] At box 525, determine if Prio2's priority is not lower than the permission level. If yes, proceed to box 530; otherwise, end the data scheduling for this transmission cycle.

[0121] At box 530, determine if Prio2 is not empty. If yes, execute box 535; otherwise, execute box 540.

[0122] At box 535, extract flow control data from Prio2.

[0123] In one transmission cycle, the transmission control module extracts one byte of flow control data from Prio2 and loads it into the second FIFO buffer.

[0124] At box 540, determine if Prio1's priority is not lower than the permission level. If yes, proceed to box 545; otherwise, end the data scheduling for this transmission cycle.

[0125] At box 545, determine if Prio1 is not empty. If yes, execute box 550; otherwise, execute box 555.

[0126] At box 550, extract flow control data from Prio1.

[0127] In one transmission cycle, the transmission control module extracts one byte of flow control data from Prio1 and loads it into the second FIFO buffer.

[0128] At box 555, determine if Prio0's priority is not lower than the permission level. If yes, proceed to box 560; otherwise, end the data scheduling for this transmission cycle.

[0129] At box 560, determine if Prio0 is not empty. If yes, proceed to box 565; otherwise, end the data scheduling for this transmission cycle.

[0130] At box 565, extract flow control data from Prio0.

[0131] In one transmission cycle, the transmission control module extracts one byte of flow control data from Prio0 and loads it into the second FIFO buffer.

[0132] At box 570, load flow control data into the second FIFO buffer.

[0133] After executing any one of steps in blocks 520, 535, 550, and 565, block 570 is executed, and then the data scheduling for that transmission cycle ends. It is understood that during the execution of any one of steps in blocks 520, 535, 550, and 565, the transmission control module extracts one byte of flow control data from the corresponding data queue and loads it into the second FIFO buffer.

[0134] Thus, this embodiment realizes a complete software and hardware processing flow of a four-level flow control mechanism.

[0135] In summary, this invention employs a closed-loop control system based on coded signaling, consisting of a receiver and a transmitter. Its core technical solution lies in reconstructing the entire FIFO flow control mechanism using a collaborative hardware and software architecture. This solution contains two key features: First, at the physical layer, coded signaling composed of PWM signals replaces binary signals. This allows the flow control signal line to transmit multi-level flow control states such as "all priority reception," "high priority reception," and "stop transmission," providing the necessary channel foundation for priority awareness. Second, at the logical layer, the final decision point for flow control is shifted from a hardware "master switch" that cannot identify priorities to a transmission control module located in the transmitter's driver software that can identify priorities. Therefore, the technical means of this solution can be summarized as a complete and universal system and method encompassing "state generation (multi-level thresholds based on the occupancy rate of the first FIFO buffer) -> state encoding (PWM signal) -> state decoding -> data queue selection and transmission." It uses the reliable hardware messenger PWM signal to accurately transmit the physical state of the first FIFO buffer at the receiving end to the software decision core at the transmitting end, thereby realizing intelligent scheduling of any FIFO buffer system with multiple priority data sources.

[0136] This invention also provides a FIFO flow control system, in which the receiver can generate coded signaling with flow control status based on the occupancy rate of the first FIFO buffer, thus providing conditions for a multi-level FIFO flow control mechanism.

[0137] Specifically, Figure 6 This is a schematic diagram of another FIFO flow control system provided in an embodiment of the present invention. See also... Figure 6 The FIFO flow control system 600 includes a receiver 610 and a transmitter 620.

[0138] The receiver 610 includes a first FIFO buffer 611, a status determination circuit 612, a signaling generation circuit 613, and an application data buffer 614. The first FIFO buffer 611 is connected to both the status determination circuit 612 and the application data buffer 614, and the status determination circuit 612 is connected to the signaling generation circuit 613. The status determination circuit 612 includes multiple first comparators 6121, an encoder 6122, and a multiplexer 6123. The multiple first comparators compare the occupancy rate of the first FIFO buffer 611 with the occupancy rate of each first comparator, obtaining multiple first comparison results. The encoder 6122 receives the multiple first comparison results and generates a digital code representing the flow control status. The multiplexer 6123 maps the digital code representing the flow control status to a corresponding duty cycle value. The signaling generation circuit 613 generates coded signaling with the flow control status based on the duty cycle value and outputs it to the connection line LF. The flow control status includes at least four levels: highest priority reception, high priority reception, all priority reception, and stop transmission. The plurality of first comparators 6121 may include, for example, a first first comparator 61211, a second first comparator 61212, and a third first comparator 61213, but this is not intended to limit the invention.

[0139] The transmitter 620 includes a second FIFO buffer 621. The transmitter 620 determines the selected flow control data according to the coded signaling of the receiver 610, and loads the flow control data into the second FIFO buffer 621 for transmission.

[0140] It should be noted that a complete and working FIFO flow control system 600 includes both a receiver 610 capable of generating multi-level coded signaling and a transmitter 620 capable of parsing the coded signaling. All the above embodiments are feasible but not intended to limit the present invention. It should be emphasized here that even when using the receiver 610 provided in the embodiments of the present invention, the compatible transmitter 620 still needs to be able to parse the coded signaling. The specific structure of the transmitter 620 is not limited to the solutions given in the above embodiments; any structure capable of parsing the coded signaling is included within the protection scope of this application. "Coded signaling" is a standardized signal that can be generated / parsed by a "compatible receiver / transmitter," and does not depend on a specific receiver / transmitter.

[0141] The FIFO flow control system 600 provided in this embodiment of the invention provides coded signaling with flow control status at the receiving end 610 based on the occupancy rate of the first FIFO buffer 611, so as to achieve selective data transmission with the sending end 620. In the receiving end 610, the status determination circuit 612 is not a single module, but a combinational logic circuit composed of multiple standard digital logic units, which is beneficial for achieving high-speed autonomous decision-making. A pure hardware pipeline composed of multiple first comparators 6121, encoders 6122, and multiplexers 6123 forms the core of the status determination circuit 612. It works in conjunction with the signaling generation circuit 613 to form a complete hardware decision-making and execution link in the receiving end 610. The application data buffer 614 in the software layer is functionally decoupled from this hardware link and is only responsible for processing the final data. Therefore, this embodiment of the invention abandons the traditional binary flow control signal and provides encoded signaling that represents the flow control state to the connection line LF to perform fine-grained flow control on the transmitting end 620. The encoded signaling accurately outputs the physical state of the first FIFO buffer 611 in the receiving end 610, so as to realize intelligent scheduling of any FIFO flow control system 600 with multiple priority data sources. When facing certain communication pressure, it can support the priority protection of the transmission of key data, solve the fundamental technical defect of "priority reversal" that is inevitably caused by the "one-size-fits-all" control method, and thus ensure the real-time performance, reliability and overall performance of the system.

[0142] Furthermore, the connecting line LF is a flow control signal line. The flow control signal line generates a flow control signal based on the received coded signaling and then transmits it. The flow control signal is a signal containing coded signaling information, which is transmitted to the transmitting end 620 via the flow control signal line, thus completing the accurate transmission of the physical state of the first FIFO buffer 611 in the receiving end 610 to the transmitting end 620.

[0143] It should be noted that the structure of the receiver 610 has been described in detail in the above embodiments. For any parts not explained in detail here, please refer to the above embodiments and they will not be repeated here.

[0144] This invention also provides a FIFO flow control system, in which the transmitting end can parse the encoded signaling and provide the flow control signal corresponding to the flow control state of the encoded signaling for transmission, so as to realize a multi-level FIFO flow control mechanism.

[0145] Specifically, Figure 7 This is a schematic diagram of another FIFO flow control system provided in an embodiment of the present invention. See also... Figure 7 The FIFO flow control system 700 includes a receiver 710 and a transmitter 720.

[0146] The transmitter 720 includes a second FIFO buffer 721, a decoding mapping circuit 722, a transmission control module 723, and multiple data queues with different priorities. The decoding mapping circuit 722 is connected to the transmission control module 723, and the transmission control module 723 is connected to both the data queues and the second FIFO buffer 721. The decoding mapping circuit 722 includes an input capture unit 7221, multiple second comparators 7222, a decoder 7223, and a status register 7224. The input capture unit 7221 receives the encoded signaling output from the receiving end via a connection line LF and measures the duty cycle value of the encoded signaling as a characteristic parameter. The multiple second comparators compare the characteristic parameter of the encoded signaling with a preset interval threshold for each second comparator, obtaining multiple second comparison results. The decoder 7223 receives the multiple second comparison results and generates a permission level code. The status register 7224 receives the permission level code and maps it to a permission level. The transmission control module 723 obtains the permission level, performs a loop traversal of the data queue, determines the selected flow control data, and loads the flow control data into the second FIFO buffer 721 for transmission. The multiple second comparators 7222 may include, for example, a first second comparator 72221, a second second comparator 72222, and a third second comparator 72223, but this is not intended to limit the invention. Multiple data queues with different priorities constitute a multi-priority queue 724, which may include a first data queue Prio3, a second data queue Prio2, and other data queues.

[0147] The receiver 710 includes: a first FIFO buffer 711, which receives external serial data; the receiver 710 generates and outputs coded signaling with flow control status according to the occupancy rate of the first FIFO buffer 711.

[0148] It should be noted that a complete and working FIFO flow control system 700 includes both a receiver 710 capable of generating multi-level coded signaling and a transmitter 720 capable of parsing the coded signaling. All the above embodiments are feasible but not intended to limit the present invention. It should be emphasized here that even when using the transmitter 720 provided in the embodiments of the present invention, the compatible receiver 710 still needs to be capable of generating multi-level coded signaling. The specific structure of the receiver 710 is not limited to the solutions given in the above embodiments, and all structures capable of generating the coded signaling are included within the protection scope of this application. "Coded signaling" is a standardized signal that can be generated / parsed by a "compatible receiver / transmitter," and does not depend on a specific receiver / transmitter.

[0149] In the FIFO flow control system 700 provided in this embodiment of the invention, the transmitting end 720 obtains coded signaling from the connection line LF and selects matching flow control data according to the coded signaling, loading it into the second FIFO buffer 721. Accordingly, selective data transmission can be achieved based on the coded signaling with flow control status. In the transmitting end 720, the decoding mapping circuit 722 receives and decodes the coded signaling and provides the mapped permission level to the transmission control module 723. The transmission control module 723 schedules the data inside the transmitting end 720 based on the permission level, and finally writes the selected flow control data into the second FIFO buffer 721, which then transmits it out. Furthermore, the decoding mapping circuit 722 uses a series of hardware structures to decode the flow control signal and provide a permission level code to the status register 7224. The task of the software-layer transmission control module 723 is to directly read the calculated permission level from this status register 7224 and then use this level to perform scheduling of each priority data queue. This design offloads all computational tasks related to signal analysis and classification from the CPU, minimizing software overhead and improving the system's real-time responsiveness. The transmitter 720 provided in this embodiment can intelligently schedule any FIFO flow control system 700 with multiple priority data sources. Under certain communication pressure, it can prioritize the transmission of critical data, resolving the fundamental technical defect of "priority reversal" inevitably caused by a "one-size-fits-all" control method, thereby ensuring the real-time performance, reliability, and overall performance of the system.

[0150] Furthermore, the connecting line LF is a flow control signal line. The flow control signal line generates a flow control signal based on the coded signaling received from the receiving end 710 and transmits it to the transmitting end 720. The transmitting end 720 receives the flow control signal transmitted by the flow control signal line to obtain the coded signaling output by the receiving end. The flow control signal is a signal containing coded signaling information, transmitted to the transmitting end 720 via the flow control signal line, enabling the transmitting end 720 to accurately parse the physical state of the first FIFO buffer 711 in the receiving end.

[0151] It should be noted that the structure of the transmitter 720 has been described in detail in the above embodiments. For any parts not explained in detail here, please refer to the above embodiments and they will not be repeated here.

[0152] This invention also provides a peripheral interface, including: the FIFO flow control system provided in any embodiment of this invention, which has corresponding beneficial effects. Figure 8 This is a schematic diagram of the structure of a peripheral interface provided in an embodiment of the present invention. See also: Figure 8 The peripheral interface 800 includes a FIFO flow control system 810.

[0153] This invention also provides a processor, including: a peripheral interface as provided in any embodiment of this invention, which has corresponding beneficial effects. Figure 9 This is a schematic diagram of the structure of a processor provided in an embodiment of the present invention. See also: Figure 9 The processor 900 includes a peripheral interface 910. Exemplarily, the processor 900 may also include components such as memory for storing data and programs. Exemplarily, the processor 900 can be applied to an embedded system.

[0154] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0155] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A FIFO flow control system, characterized in that, include: Sender and receiver; The receiving end includes: a first FIFO buffer for receiving external serial data; the receiving end generates and outputs coded signaling with flow control status based on the occupancy rate of the first FIFO buffer; The transmitting end includes: a second FIFO buffer; the transmitting end determines the selected flow control data according to the encoded signaling of the receiving end, and loads the flow control data into the second FIFO buffer for transmission.

2. The FIFO flow control system according to claim 1, characterized in that, The receiver also includes: The status determination circuit is connected to the first FIFO buffer and generates the corresponding status code based on the occupancy rate of the first FIFO buffer. The signaling generation circuit is connected to the state determination circuit and generates coded signaling with flow control status based on the status code output by the state determination circuit.

3. The FIFO flow control system according to claim 2, characterized in that, The state determination circuit includes: Multiple first comparators are connected to a first FIFO buffer, and the occupancy rate of each first comparator is compared with the occupancy rate of the first FIFO buffer to obtain multiple first comparison results; The encoder is connected to multiple first comparators, receives multiple first comparison results, and generates corresponding digital codes. The multiplexer connects to the encoder and maps digital codes to corresponding duty cycle values ​​as status codes.

4. The FIFO flow control system according to claim 3, characterized in that, Multiple first comparators are configured to have different occupancy rates; The first comparator is configured to output the valid value of the first comparison result when the occupancy rate of the first FIFO buffer reaches the occupancy rate of the first comparator. The encoder is configured to respond to the first comparison result of the first comparator with the highest occupancy rate of the output valid value, and generate a digital code representing the flow control state.

5. The FIFO flow control system according to claim 3, characterized in that, The signaling generation circuit includes a PWM generator. The PWM generator receives the duty cycle value output by the state determination circuit and generates a PWM signal as coded signaling based on the duty cycle value.

6. The FIFO flow control system according to claim 1, characterized in that, The receiving end also includes an application data buffer, which stores the data written to the first FIFO buffer.

7. The FIFO flow control system according to claim 1, characterized in that, The transmitting end also includes: The decoding mapping circuit receives and decodes the received encoded signaling, obtains the flow control status of the encoded signaling, and generates a license level with the flow control status. The transmission control module is connected to the decoding mapping circuit and the second FIFO buffer respectively. It obtains the permission level, determines the selected flow control data, and loads the flow control data into the second FIFO buffer for transmission.

8. The FIFO flow control system according to claim 7, characterized in that, The sending end also includes multiple data queues with different priorities; The transmission control module performs a loop traversal of the data queue according to the permission level, determines the selected flow control data, loads the flow control data into the second FIFO buffer, and transmits it.

9. The FIFO flow control system according to claim 8, characterized in that, The sending control module performs a loop traversal of the data queue according to the permission level to determine the selected flow control data. This includes: in each sending cycle, the sending control module checks the data queue level by level according to the priority from high to low, and determines the selected flow control data in the first data queue with a priority not lower than the permission level and which is not empty.

10. The FIFO flow control system according to claim 7, characterized in that, The decoding mapping circuit includes: The input acquisition unit receives the encoded signaling received by the transmitter and measures the duty cycle value of the encoded signaling as a characteristic parameter of the encoded signaling. Multiple second comparators are connected to the input capture unit respectively, and the feature parameters of the encoded signaling are compared with the preset interval threshold of each second comparator to obtain multiple second comparison results; The decoder connects to multiple second comparators, receives multiple second comparison results, and generates a license level code that represents the license level.

11. The FIFO flow control system according to claim 10, characterized in that, The decoding mapping circuit also includes a status register, which is connected to the decoder and the transmission control module respectively, receives the license level code sent by the decoder, and maps the license level code to a license level.

12. The FIFO flow control system according to any one of claims 1-11, characterized in that, Also includes: The connecting cable connects the receiving end and the sending end, receiving the encoded signaling sent by the receiving end and transmitting it to the sending end; The connection line is a flow control signal line, which generates flow control signals based on the received coded signaling and transmits them to the sending end.

13. The FIFO flow control system according to any one of claims 1-11, characterized in that, The flow control status includes at least four levels: highest priority reception, high priority reception, all priority reception, and stop transmission.

14. A peripheral interface, characterized in that, include: The FIFO flow control system as described in any one of claims 1-13.

15. A processor, characterized in that, include: The peripheral interface as described in claim 14.

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