Image detection circuit, image sensor, electronic apparatus, and image detection method

Abstract

The invention discloses an image detection circuit, an image sensor, electronic equipment and an image detection method, and relates to the technical field of image detection. The image detection circuit comprises a pixel array, a row driver, a full well judgment circuit and an output circuit. The pixel array comprises pixel units; each pixel unit comprises a pixel module, a probe module, a reading module and an LOFIC module; the LOFIC module, the reading module, the pixel module and the probe module are electrically connected with the row driver respectively; the reading module is electrically connected with the output circuit; the probe module and the LOFIC module are electrically connected with the full well judgment circuit respectively; wherein the full-well judgment circuit is used for judging whether the pixel module is full-well according to a detection signal output by the probe module; the full well judgment circuit is used for conducting electric connection between the LOFIC module and the pixel module under the condition that the pixel module is full in well; and the full well judgment circuit is also used for disconnecting the electric connection between the LOFIC module and the pixel module under the condition that the pixel module is not full of the well.

Description

Technical Field

[0001] This application relates to the field of image detection technology, specifically to an image detection circuit, an image sensor, an electronic device, and an image detection method. Background Technology

[0002] In related technologies, some pixel circuits within image detection circuits may include Lateral Overflow Integration Capacitors (LOFICs). A LOFIC is an independent capacitor embedded within the pixel circuit, primarily used to receive and buffer charge or electrons overflowing from the pixel device (PPD). When the LOFIC switching transistor is closed, charge or electrons freely enter and exit the LOFIC, charging and discharging it. Unlike other capacitors within the pixel, the LOFIC is an independent capacitor with its own positive and negative plates and dielectric filling material. Therefore, the capacitance of a LOFIC is substantial.

[0003] Because the LOFIC capacitor in a pixel continuously receives electrons overflowing from the PPD after it fills the well with strong light during the exposure period of one frame, the LOFIC capacitor already stores a signal at the beginning of the readout period of one frame. This stored signal consists of noise signals and electron signals overflowing from the PPD after it fills the well with strong light. During the readout phase, because the LOFIC capacitor stores the signal generated by the exposure time, it is impossible to use noise reduction techniques such as Correlated Double Sampling (CDS) to remove the noise signals, resulting in a signal with huge noise read from the pixel's LOFIC capacitor. This noise level is more than 500 times that of the noise level after CDS noise reduction from capacitors in other pixels. It is evident that the signal stored in the LOFIC capacitor in the image detection circuit has a large amount of noise in related technologies. Summary of the Invention

[0004] This application provides an image detection circuit, an image sensor, an electronic device, and an image detection method, which can reduce the noise of the signal stored in the LOFIC module of the image detection circuit.

[0005] In one aspect, an image detection circuit is provided, including a pixel array, a row driver, a full-well detection circuit, and an output circuit;

[0006] The pixel array includes multiple pixel units arranged in an array; each pixel unit includes a pixel module, a probe module, a readout module, and a lateral overflow integration capacitor (LOFIC) module; the probe module, the LOFIC module, and the readout module are electrically connected to the pixel module; the readout module is also electrically connected to the LOFIC module; the LOFIC module, the readout module, the pixel module, and the probe module are all electrically connected to the row driver; the readout module is electrically connected to the output circuit.

[0007] The probe module and the LOFIC module are respectively electrically connected to the full-well determination circuit; wherein, the full-well determination circuit is used to determine whether the pixel module is full-well based on the detection signal output by the probe module; the full-well determination circuit is used to connect the electrical connection between the LOFIC module and the pixel module when the pixel module is full-well; the full-well determination circuit is also used to disconnect the electrical connection between the LOFIC module and the pixel module when the pixel module is not full-well.

[0008] In this embodiment, the full-well state of the pixel module is detected by a probe module, and a full-well determination circuit determines whether the pixel module is full based on the probe module's detection results. If the full-well determination circuit determines that the pixel module is full, the electrical connection between the LOFIC module and the pixel module is established. This allows charge or electrons in the pixel module to overflow into the LOFIC module when the pixel module is full, thus storing the overflowing electronic signal in the LOFIC module. Conversely, if the full-well determination circuit determines that the pixel module is not full, the electrical connection between the LOFIC module and the pixel module is disconnected. This avoids the problem of continuous noise accumulation in the LOFIC module when the pixel module is not full, due to the constant electrical connection between the LOFIC module and the pixel module. This reduces the noise of the signal stored in the LOFIC module of the image detection circuit.

[0009] Optionally, the full-well determination circuit includes a comparator and a buffer driver module; the probe module is used to acquire the voltage of the pixel module; the output terminal of the probe module is electrically connected to the first input terminal of the comparator; the second input terminal of the comparator is electrically connected to the threshold voltage signal; the output terminal of the comparator is electrically connected to the input terminal of the buffer driver module; and the output terminal of the buffer driver module is electrically connected to the LOFIC module.

[0010] In this embodiment, the full-well judgment circuit includes a comparator and a buffer driver module; the probe module is used to collect the voltage of the pixel module; the output terminal of the probe module is electrically connected to the first input terminal of the comparator; the second input terminal of the comparator is electrically connected to a threshold voltage signal; the output terminal of the comparator is electrically connected to the input terminal of the buffer driver module; and the output terminal of the buffer driver module is electrically connected to the LOFIC module. Thus, the comparator can compare the voltage values ​​of the voltage signals received from the two input terminals and output a high or low level based on the relative magnitude of the two voltage signals. The buffer driver module can control the LOFIC module according to the output result of the comparator to connect or disconnect the electrical connection between the LOFIC module and the pixel module. This enables the full-well judgment circuit to determine the full-well state of the pixel module and to control the LOFIC module.

[0011] Optionally, if the input voltage at the first input terminal of the comparator is lower than or equal to the input voltage at the second input terminal of the comparator, the comparator is used to determine that the pixel module is full-well.

[0012] Alternatively, if the input voltage at the first input terminal of the comparator is higher than the input voltage at the second input terminal of the comparator, the comparator is used to determine that the pixel module is not full.

[0013] In this embodiment, the comparator determines that the pixel module is full-well when the input voltage at the first input terminal of the comparator is lower than or equal to the input voltage at the second input terminal of the comparator; or, the comparator determines that the pixel module is not full-well when the input voltage at the first input terminal of the comparator is higher than the input voltage at the second input terminal of the comparator. In this way, the process of determining whether the pixel module is full-well by the full-well determination circuit can be realized.

[0014] Optionally, the pixel module includes a clamping photodiode (PPD) device; the input terminal of the PPD device is grounded; the image detection circuit further includes a high-level module; the probe module includes a first switch and a first source follower; the gate of the first source follower is electrically connected to the output terminal of the PPD device; the source of the first source follower is electrically connected to the high-level module; the drain of the first source follower is electrically connected to the first input terminal of the comparator through the first switch; the control terminal of the first switch is electrically connected to the row driver.

[0015] In this embodiment, the pixel module includes a clamping photodiode (PPD) device; the input terminal of the PPD device is grounded; the image detection circuit further includes a high-level module; the probe module includes a first switch and a first source follower; the gate of the first source follower is electrically connected to the output terminal of the PPD device; the source of the first source follower is electrically connected to the high-level module; the drain of the first source follower is electrically connected to the first input terminal of the comparator through the first switch; the control terminal of the first switch is electrically connected to the row driver. Thus, when the probe module needs to probe the pixel module, the row driver can control the first switch to be turned on, thereby enabling the probe module to detect the voltage of the pixel module. When the probe module does not need to probe the pixel module, the row driver can control the first switch to be turned off, thereby preventing electrons in the PPD device from flowing to the probe module and causing electron loss from the PPD device.

[0016] Optionally, the pixel module further includes a second switch; the LOFIC module includes a third switch, a fourth switch, a fifth switch, and a LOFIC capacitor; the output terminal of the PPD device is electrically connected to the input terminal of the second switch; the output terminal of the second switch is grounded sequentially through the third switch and the LOFIC capacitor.

[0017] The control terminal of the second switch is electrically connected to the row driver; the control terminal of the third switch is electrically connected to the row driver through the fourth switch; the control terminal of the fourth switch is electrically connected to the output terminal of the buffer driver module through the fifth switch; and the control terminal of the fifth switch is electrically connected to the row driver.

[0018] In this embodiment, the pixel module further includes a second switching element; the LOFIC module includes a third switching element LOFIC, a fourth switching element, a fifth switching element, and a LOFIC capacitor C. LOFIC The output terminal of the PPD device is electrically connected to the input terminal of the second switch; the output terminal of the second switch is sequentially connected to the third switch LOBIC and the LOBIC capacitor C. LOFIC Grounded; the control terminal of the second switch is electrically connected to the row driver; the control terminal of the third switch (LOFIC) is electrically connected to the row driver through the fourth switch; the control terminal of the fourth switch is electrically connected to the output terminal of the buffer driver module through the fifth switch; the control terminal of the fifth switch is electrically connected to the row driver. Thus, when the PPD device is full-well, the second switch can be turned on, and simultaneously, the buffer driver module can be controlled to output a high level, V... LOFICWhen the line outputs a high level, the third, fourth, and fifth switches are all in a conducting state, thus establishing the electrical connection between the LOFIC module and the pixel module. Conversely, when the PPD device is not fully submerged, the buffer driver module can output a low level, causing the fourth switch to deactivate, thereby disconnecting the electrical connection between the LOFIC module and the pixel module. In other words, the buffer driver module and the row driver can control the on / off states of the second, third, fourth, and fifth switches to control the on / off state of the electrical connection between the LOFIC module and the pixel module.

[0019] Optionally, the pixel module is a composite pixel module; the pixel module includes N PPD devices and N second switches; the N PPD devices and the N second switches are connected in a one-to-one correspondence; the gate of the first source follower is electrically connected to the output terminal of at least one of the N PPD devices; wherein, N is an integer greater than 1.

[0020] In this embodiment, since the pixel module is a composite pixel module, the pixel module includes N PPD devices and N second switches. The N PPD devices and the N second switches are connected in a one-to-one correspondence. The gate of the first source follower is electrically connected to the output terminal of at least one of the N PPD devices. Thus, the above image detection circuit can be applied to scenarios where the pixel module is a composite pixel.

[0021] Optionally, the pixel module is a composite pixel module; the pixel module includes N PPD devices and N second switching devices; the pixel unit includes N LOFIC modules, and the N LOFIC modules are connected to the N PPD devices in a one-to-one correspondence; the gate of the first source follower is electrically connected to the output terminal of any one of the N PPD devices; wherein, N is an integer greater than 1;

[0022] The output terminal of the PPD device is electrically connected to the corresponding LOFIC module; the output terminal of the PPD device is electrically connected to the input terminal of the corresponding second switch; the output terminal of the second switch is electrically connected to the reading module; and the control terminal of the second switch is electrically connected to the row driver.

[0023] In this embodiment, the pixel module is configured as a composite pixel module. The pixel module includes N PPD devices and N second switches. The pixel unit includes N LOFIC modules, each corresponding to one of the N PPD devices. The gate of the first source follower is electrically connected to the output of any one of the N PPD devices. The output of each PPD device is electrically connected to its corresponding LOFIC module. The output of each PPD device is electrically connected to the input of its corresponding second switch. The output of the second switch is electrically connected to the readout module. The control terminal of the second switch is electrically connected to the line driver. Thus, during the reading process of the composite pixel module, the signals in each PPD device are read sequentially, and the signals in each LOFIC module are read sequentially, enabling the composite pixel module to implement LOFIC HDR functionality in Binning mode. Alternatively, during the reading of the composite pixel module, all PPD devices can be read simultaneously. After reading all PPD devices, all LOFIC modules can be read at the same time, enabling the composite pixel module to achieve LOFIC HDR functionality in full-size mode.

[0024] Optionally, the LOFIC module includes a third switch, a fourth switch, a fifth switch, and a LOFIC capacitor; the output terminal of the PPD device is grounded sequentially through the third switch and the LOFIC capacitor; the control terminal of the third switch is electrically connected to the row driver through the fourth switch; the control terminal of the fourth switch is electrically connected to the output terminal of the buffer driver module through the fifth switch; and the control terminal of the fifth switch is electrically connected to the row driver.

[0025] In this embodiment, the LOFIC module includes a third switch element (LOFIC), a fourth switch element, a fifth switch element, and a LOFIC capacitor (C). LOFIC The output terminal of the PPD device is sequentially connected to the third switching element Lofficer (LOFIC) and the Lofficer (LOFIC) capacitor C. LOFIC Grounded; the control terminal of the third switch (LOFIC) is electrically connected to the row driver via the fourth switch; the control terminal of the fourth switch is electrically connected to the output terminal of the buffer driver module via the fifth switch; the control terminal of the fifth switch is electrically connected to the row driver. Thus, when the PPD device is full-well, the buffer driver module can be controlled to output a high level, V... LOFICWhen the line outputs a high level, the third, fourth, and fifth switching devices are all in a conducting state, thus establishing the electrical connection between the LOFIC module and the pixel module. Conversely, when the PPD device is not fully submerged, the buffer driver module can output a low level, causing the fourth switching device to disconnect, thereby disconnecting the electrical connection between the LOFIC module and the pixel module. In other words, the buffer driver module and the row driver can control the on / off states of the third, fourth, and fifth switching devices to control the on / off state of the electrical connection between the LOFIC module and the pixel module.

[0026] Optionally, the reading module includes a second source follower, a sixth switch, and a seventh switch; the input terminal of the sixth switch is electrically connected to the high-level module; the output terminal of the sixth switch is electrically connected to the output terminal of the second switch; and the control terminal of the sixth switch is electrically connected to the row driver.

[0027] The gate of the second source follower is electrically connected to the output terminal of the second switch; the source of the second source follower is electrically connected to the high-level module; the drain of the second source follower is electrically connected to the output circuit through the seventh switch; the control terminal of the seventh switch is electrically connected to the row driver.

[0028] In this embodiment, the read module includes a second source follower, a sixth switch, and a seventh switch. The input terminal of the sixth switch is electrically connected to the high-level module. The output terminal of the sixth switch is electrically connected to the output terminal of the second switch. The control terminal of the sixth switch is electrically connected to the row driver. The gate of the second source follower is electrically connected to the output terminal of the second switch. The source of the second source follower is electrically connected to the high-level module. The drain of the second source follower is electrically connected to the output circuit through the seventh switch. The control terminal of the seventh switch is electrically connected to the row driver. Thus, when signal reading is required, the seventh switch can be turned on by controlling the row driver. After signal reading is completed, the sixth switch can be turned on by controlling the driver. At this time, the high-level module can connect the PPD device and the LOFIC capacitor C. LOFIC The charge in the middle is cleared and reset.

[0029] In a second aspect, an image sensor is provided, including the image detection circuit described in the first aspect.

[0030] In this embodiment, since the image sensor includes the image detection circuit described above, the image sensor can implement each process of the image detection circuit in the above embodiments and has the same beneficial effects. To avoid repetition, it will not be described again here.

[0031] Thirdly, an electronic device is provided, including the image sensor described in the second aspect.

[0032] In this embodiment, since the electronic device includes the image sensor described above, the electronic device can implement all the processes of the image sensor in the above embodiments and has the same beneficial effects. To avoid repetition, it will not be described again here.

[0033] Fourthly, an image detection method is provided, performed by the electronic device described in the third aspect, the image detection method comprising:

[0034] During the exposure period of the first pixel unit, the probe module in the first pixel unit is used to detect the pixel module in the first pixel unit to obtain a first detection signal. The first pixel unit is any pixel unit in the pixel array.

[0035] When the full-well determination circuit in the first pixel unit determines that the pixel module is full based on the first detection signal, the full-well determination circuit outputs a first control signal to the LOFIC module in the first pixel unit, wherein the first control signal is used to connect the electrical connection between the LOFIC module and the pixel module.

[0036] Alternatively, if the full-well determination circuit in the first pixel unit determines that the pixel module is not full based on the first detection signal, the full-well determination circuit outputs a second control signal to the LOFIC module in the first pixel unit; wherein the second control signal is used to disconnect the electrical connection between the LOFIC module and the pixel module.

[0037] In this embodiment, the full-well state of the pixel module is detected by a probe module, and a full-well determination circuit determines whether the pixel module is full based on the probe module's detection results. If the full-well determination circuit determines that the pixel module is full, the electrical connection between the LOFIC module and the pixel module is established. This allows charge or electrons in the pixel module to overflow into the LOFIC module when the pixel module is full, thus storing the overflowing electronic signal in the LOFIC module. Conversely, if the full-well determination circuit determines that the pixel module is not full, the electrical connection between the LOFIC module and the pixel module is disconnected. This avoids the problem of continuous noise accumulation in the LOFIC module when the pixel module is not full, due to the constant electrical connection between the LOFIC module and the pixel module. This reduces the noise of the signal stored in the LOFIC module of the image detection circuit.

[0038] Optionally, the exposure period includes multiple exposure sub-periods and multiple detection sub-periods, wherein any two adjacent exposure sub-periods are separated by a detection sub-period;

[0039] During the exposure period of the first pixel unit, the first pixel unit is probed by a probe module to obtain a first detection signal, including:

[0040] During each detection sub-period, the pixel module in the first pixel unit is detected by the probe module in the first pixel unit to obtain the first detection signal;

[0041] The image detection method further includes:

[0042] During the exposure sub-period, the exposure of the pixel module is controlled by the line driver.

[0043] In this embodiment, the exposure period includes multiple exposure sub-periods and multiple detection sub-periods. Each pair of adjacent exposure sub-periods is separated by a detection sub-period. Within each detection sub-period, the probe module in the first pixel unit detects the pixel module to obtain a first detection signal. Within the exposure sub-period, the row driver controls the exposure of the pixel module. This allows for alternating detection and exposure during the exposure period, ensuring that the probe module can promptly detect the full-well state of the pixel module when it is full, thus improving the real-time performance of the full-well detection by the probe module.

[0044] Optionally, the method further includes:

[0045] During the signal reading period of the first pixel unit, the pixel module is probed by the probe module to obtain a second detection signal;

[0046] When the full-well determination circuit determines that the pixel module is full based on the second detection signal, the LOFIC module is read from the signal during the signal reading period.

[0047] Alternatively, when the full-well determination circuit determines, based on the second detection signal, that the pixel module is not full, the signal reading of the LOFIC module is skipped during the signal reading period.

[0048] In this implementation, electrons can only flow into the LOFIC module when the pixel module is full-well; that is, the LOFIC module only stores a valid signal when the pixel module is full-well. Therefore, before reading the LOFIC module, it can be determined whether the pixel module is full-well. Reading is only performed when the pixel module is full-well. If the pixel module is not full-well, signal reading from the LOFIC module is skipped. In other words, the decision to perform LOFIC capacitor C can be adaptively made based on the full-well status of the PPD within the pixel. LOFIC The reading and analog-to-digital conversion can significantly reduce power consumption during the LOFIC HDR process.

[0049] In this embodiment, the full-well state of the pixel module is detected by a probe module, and a full-well determination circuit determines whether the pixel module is full based on the probe module's detection result. If the full-well determination circuit determines that the pixel module is full, the electrical connection between the LOFIC module and the pixel module is established. This allows charge or electrons in the pixel module to overflow into the LOFIC module when the pixel module is full, thus storing the overflowing electronic signal in the LOFIC module. Conversely, if the full-well determination circuit determines that the pixel module is not full, the electrical connection between the LOFIC module and the pixel module is disconnected. This avoids the problem of continuous noise accumulation in the LOFIC module when the pixel module is not full, due to the constant electrical connection between the LOFIC module and the pixel module. This reduces the noise of the signal stored in the LOFIC module of the image detection circuit.

[0050] The second, third, and fourth aspects mentioned above all have various possible circuit structure designs similar to the first aspect and any possible implementation of the first aspect, and can produce corresponding technical effects, which will not be elaborated here. Attached Figure Description

[0051] Figure 1This is a schematic diagram of the structure of an image detection circuit provided in some embodiments of this application;

[0052] Figure 2 This is a schematic diagram of the full-well detection circuit provided in some embodiments of this application;

[0053] Figure 3 This is one of the structural schematic diagrams of a pixel unit provided in some embodiments of this application;

[0054] Figure 4 This is a timing diagram of a frame of adaptive LOFIC HDR provided by some embodiments of this application for pixel-by-pixel full-well monitoring;

[0055] Figure 5 This is a second schematic diagram of the structure of a pixel unit provided in some embodiments of this application;

[0056] Figure 6 Based on Figure 3 Timing diagram of the pixel-by-pixel full-well monitoring implementation of adaptive LOFIC HDR in the illustrated embodiment;

[0057] Figure 7 This is the third of several schematic diagrams illustrating the structure of pixel units provided in some embodiments of this application;

[0058] Figure 8 This is the fourth schematic diagram of the structure of a pixel unit provided in some embodiments of this application;

[0059] Figure 9 This is a flowchart illustrating an image detection method provided in some embodiments of this application. Detailed Implementation

[0060] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0061] The terms "first," "second," etc., used in this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first" and "second" are generally of the same class, not limited in number; for example, the first object can be one or more. Furthermore, "or" in this application indicates at least one of the connected objects. For example, the scope of protection for "A or B" covers at least three scenarios: Scenario 1: including A but not B; Scenario 2: including B but not A; Scenario 3: including both A and B. In addition, the terms "A and / or B," "at least one of A and B," and "at least one of A or B" also cover at least the above three scenarios. The character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0062] The terminology used in the implementation section of this application is only for explaining specific embodiments of this application and is not intended to limit this application. The terminology involved in the embodiments of this application is explained below.

[0063] Full well: refers to the maximum amount of charge stored in a single pixel.

[0064] Line driver 200: It is a key component in the display driver system, mainly responsible for controlling the scanning and gating operations of pixel lines.

[0065] Pixel array 100: An array consisting of multiple pixel rows and multiple pixel columns.

[0066] PPD device: a photodiode structure used in image sensors.

[0067] Source follower: A common-drain amplifier circuit built around a field-effect transistor. Its main function is to achieve impedance transformation and voltage signal following, and its voltage gain is approximately 1.

[0068] Lateral Overflow Floating Integration Capacitor (LOFIC) is an advanced technology used to improve the dynamic range of image sensors. Its core principle is to integrate a high-density capacitor next to the photodiode of each pixel. When excessive light causes overexposure in traditional sensors, this capacitor collects and stores any overflowing photoelectrons, thus preserving both highlight details and shadow information in the same image.

[0069] LOFIC capacitor: It is an independent capacitor with independent positive and negative plates and dielectric filling material.

[0070] The image detection circuit, image sensor, electronic device, and image detection method provided in this application will be described in detail below with reference to the accompanying drawings and through some embodiments and application scenarios.

[0071] Please see Figures 1 to 3 This application provides an image detection circuit, including a pixel array 100, a row driver 200, a full-well judgment circuit 300, and an output circuit 400.

[0072] The pixel array 100 includes multiple pixel units 110 arranged in an array; each pixel unit 110 includes a pixel module 111, a probe module 112, a read module 113, and a lateral overflow integration capacitor (LOFIC) module 114; the probe module 112, the LOFIC module 114, and the read module 113 are electrically connected to the pixel module 111; the read module 113 is also electrically connected to the LOFIC module 114; the LOFIC module 114, the read module 113, the pixel module 111, and the probe module 112 are electrically connected to the row driver 200; and the read module 113 is electrically connected to the output circuit 400.

[0073] The probe module 112 and the LOFIC module 114 are respectively electrically connected to the full-well determination circuit 300; wherein, the full-well determination circuit 300 is used to determine whether the pixel module 111 is full based on the detection signal output by the probe module 112; the full-well determination circuit 300 is used to connect the electrical connection between the LOFIC module 114 and the pixel module 111 when the pixel module 111 is full; the full-well determination circuit 300 is also used to disconnect the electrical connection between the LOFIC module 114 and the pixel module 111 when the pixel module 111 is not full.

[0074] The image detection circuit described above can serve as a contact image sensor (CIS), or it can be an internal circuit of the image sensor. In some embodiments of this application, the image detection circuit can serve as a complementary metal-oxide semiconductor (CMOS) image sensor.

[0075] In CMOS image sensors, there are two main pixel exposure methods: rolling shutter and global shutter. Due to pixel size and readout speed limitations, rolling shutter is currently the mainstream method. After image processing, the output is sent from the port module to an external chip outside the CIS for further image processing. In some embodiments of this application, the image detection circuit may use rolling shutter exposure, or in some embodiments of this application, the image detection circuit may use global shutter exposure. For ease of understanding, the following explanation will use rolling shutter exposure as an example to further illustrate the image detection circuit.

[0076] During the operation of the image detection circuit, in the acquisition of each frame of image, all pixels in the pixel array 100 undergo three steps: reset, exposure, and readout. However, the operation steps of each row of pixels have a time difference from those of other rows. Driven by the row driver 200, each row of pixels is reset, exposed, and readout row by row after receiving a control signal. The column-parallel analog-to-digital converter (ADC) module 410 receives the output information of one row of pixels each time and performs analog-to-digital conversion. Therefore, the CIS adopts a rolling shutter operation mode, which can perform image acquisition and output at high speed and efficiency. Please refer to... Figure 1 In some embodiments of this application, the output circuit 400 described above may include the column parallel ADC module 410 and the column scanner 420.

[0077] Please see Figure 1 The pixel array 100 described above may include multiple pixel rows and multiple pixel columns. Each pixel row includes multiple pixel units 110, and each pixel column includes multiple pixel units 110. The pixel module 111 described above may include a single pixel, or the pixel module 111 may also include binning.

[0078] Please see Figure 1In some embodiments of this application, the image detection circuit may include multiple line groups corresponding one-to-one with the plurality of pixel rows. The line group may include multiple lines arranged along the row direction of the pixel array 100. Thus, all LOFIC modules 114 in the same row can be electrically connected to the row driver 200 through the same line. Correspondingly, all read modules 113 in the same row can be electrically connected to the row driver 200 through the same line, all pixel modules 111 in the same row can be electrically connected to the row driver 200 through the same line, and all probe modules 112 in the same row can be electrically connected to the row driver 200 through the same line.

[0079] Please see Figures 1 to 3 In some embodiments of this application, the image detection circuit includes multiple full-well judgment circuits 300 corresponding one-to-one with the plurality of pixel columns, and each of the plurality of pixel columns can correspond to the following three column-oriented lines: V PPD Line, V OF Lines and V PIX The circuit, wherein the probe module 112 within each pixel unit 110 in the same pixel column can all be accessed via the corresponding V PPD The circuit is electrically connected to the corresponding full-well detection circuit 300, so that the detection signal detected by the probe module 112 can be transmitted through the corresponding V. PPD The signal is transmitted to the corresponding full-well detection circuit 300. The LOBIC module 114 within each pixel unit 110 of the same pixel column can all be transmitted via the corresponding V... OF The circuit is electrically connected to the corresponding full-well detection circuit 300, so that the full-well detection circuit 300 can detect the full-well condition through the connected V. OF The line sends control signals to the LOFIC modules 114 at each position in the corresponding pixel column to control the electrical connection between the LOFIC module 114 and the pixel module 111 to be disconnected or made on. The readout modules 113 within each pixel unit 110 in the same pixel column can all be accessed via their corresponding V... PIX The line is electrically connected to the output circuit 400, so that the signals read by each reading module 113 in each pixel unit 110 in the same pixel column can be transmitted through V. PIX The data is transmitted to output circuit 400 for output. Please refer to further details. Figure 1 ,exist Figure 1 In the illustrated embodiment, the output circuit 400 includes a column-parallel ADC module 410 and a column scanner 420, wherein the column-parallel ADC module 410 can be coupled with V corresponding to each pixel column. PIX With the circuit electrically connected, the parallel ADC module can process each V... PIXThe signal transmitted through the line is converted from analog to digital and then transmitted to the column scanner 420. The column scanner 420 converts the received signal into image data for output.

[0080] Please see Figure 4 The image detection circuit controls each row of pixels during image acquisition. The row driver 200 synchronously controls all pixel units 110 within the same pixel row. Each pixel unit 110 in the same row undergoes three steps: reset, exposure, and readout. There is a time difference in the control between different rows. Control is performed sequentially from row 1 to row N. Once all rows have completed the reset, exposure, and readout steps, the acquisition of one frame of image is complete. For ease of understanding, this embodiment uses the reset, exposure, and readout process of one pixel unit 110 as an example to further illustrate the image acquisition process of the image detection unit: First, in the reset phase, pixel unit 110 is reset. This process clears the charge in pixel module 111 and the charge in LOFIC module 114. Then, during the exposure stage, the pixel module 111 is exposed under control. The PPD in the pixel module 111 generates charge. Simultaneously, during the exposure stage, the probe module 112 can detect whether the pixel module 111 is full-well. If the pixel module 111 is full-well, the full-well determination circuit 300 controls the electrical connection between the LOFIC module 114 and the pixel module 111 to be connected. At this time, the charge in the pixel module 111 can overflow to the LOFIC module 114 through the electrical connection. During the readout stage, firstly, the pixel module 111 and the C... FD This allows the charge in pixel module 111 to flow to C. FD Then read module 113 in C FD The signal in the data is read, and the read signal is transmitted through V. PIX The signal is transmitted to the output circuit 400. Then, the LOFIC module 114 and the reading module 113 can be controlled to conduct. The reading module 113 reads the signal from the LOFIC module 114 and transmits the read signal through V... PIX The signal is transmitted to the output circuit 400. The output circuit 400 performs analog-to-digital conversion on the received signal and then converts it into an image signal for output, thereby completing the detection process of one pixel unit 110.

[0081] Among them, C FD for Figure 3 C FD The virtual capacitance formed at the location of the object can also be called a floating diffuse capacitance, where C is the virtual capacitance. FDThe inherent capacitance of each device connected to the point, and C FD The virtual capacitance is formed by the equivalent capacitance of the wires connected to the point. For example, in Figure 3 In the illustrated embodiment, C FD For the drain of TX transistor, the gate of SF1, the source of LOFIC, the drain of RST, and C FD The floating diffusion capacitance formed by the wires connected to the point, C FD The capacitance can be C FD The capacitors are the proprietary capacitors of the TX transistor, SF1, LOFIC, RST, and C. FD The sum of the equivalent capacitances of the wires connected to the point. That is, C. FD It is not a physical device, but a capacitor composed of the device connected to that location and the wires.

[0082] In this embodiment, the full-well state of the pixel module 111 is detected by the probe module 112, and the full-well determination circuit 300 determines whether the pixel module 111 is full based on the detection result of the probe module 112. When the full-well determination circuit 300 determines that the pixel module 111 is full, the electrical connection between the LOFIC module 114 and the pixel module 111 is turned on, so that when the pixel module 111 is full, the charge or electrons in the pixel module 111 can overflow to the LOFIC module 114, thereby storing the overflowing electronic signal after the pixel module 111 is full in the LOFIC module 114. Accordingly, when the full-well determination circuit 300 determines that the pixel module 111 is not full, the electrical connection between the LOFIC module 114 and the pixel module 111 is disconnected. This avoids the problem of continuous noise accumulation in the LOFIC module 114 when the pixel module 111 is not full, as the LOFIC module 114 and the pixel module 111 are always electrically connected. This reduces the noise of the signal stored in the LOFIC module 114 in the image detection circuit.

[0083] Optionally, the full-well determination circuit 300 includes a comparator 310 and a buffer driver module 320; the probe module 112 is used to collect the voltage of the pixel module 111; the output terminal of the probe module 112 is electrically connected to the first input terminal of the comparator 310; the second input terminal of the comparator 310 is electrically connected to a threshold voltage signal; the output terminal of the comparator 310 is electrically connected to the input terminal of the buffer driver module 320; and the output terminal of the buffer driver module 320 is electrically connected to the LOFIC module 114.

[0084] The comparator 310 can be any type of comparator 310 or comparator circuit. The comparator 310 can compare the voltage values ​​of the voltage signals received at the two input terminals and output a high level or a low level according to the relative magnitude of the voltage values ​​of the two voltage signals. The buffer driver module 320 can control the LOFIC module 114 according to the output result of the comparator 310 to turn on or off the electrical connection between the LOFIC module 114 and the pixel module 111.

[0085] It is understandable that the aforementioned threshold voltage signal can be a voltage signal whose voltage value always remains unchanged at a certain threshold.

[0086] In this embodiment, the full-well judgment circuit 300 includes a comparator 310 and a buffer driving module 320; the probe module 112 is used to collect the voltage of the pixel module 111; the output terminal of the probe module 112 is electrically connected to the first input terminal of the comparator 310; the second input terminal of the comparator 310 is electrically connected to a threshold voltage signal; the output terminal of the comparator 310 is electrically connected to the input terminal of the buffer driving module 320; and the output terminal of the buffer driving module 320 is electrically connected to the LOFIC module 114. Thus, the comparator 310... The voltage values ​​of the voltage signals received from the two input terminals can be compared, and a high level or a low level can be output according to the relative magnitude of the voltage values ​​of the two voltage signals. The buffer driving module 320 can control the LOFIC module 114 according to the output result of the comparator 310 to conduct or disconnect the electrical connection between the LOFIC module 114 and the pixel module 111. This enables the full-well judgment circuit 300 to judge the full-well state of the pixel module 111, and also enables the full-well judgment circuit 300 to control the LOFIC module 114.

[0087] Optionally, if the input voltage at the first input terminal of the comparator 310 is lower than or equal to the input voltage at the second input terminal of the comparator 310, the comparator 310 is used to determine that the pixel module 111 is full-well.

[0088] Alternatively, if the input voltage at the first input terminal of the comparator 310 is higher than the input voltage at the second input terminal of the comparator 310, the comparator 310 is used to determine that the pixel module 111 is not full.

[0089] During exposure, the PPD in pixel module 111 continuously generates electrons, which causes a voltage drop at the PPD. When pixel module 111 is exposed to strong light such as sunlight during exposure, the number of electrons at its PPD increases rapidly. When this increase reaches a certain level, the PPD becomes full-well, resulting in a lower voltage at the PPD. Therefore, the voltage of the PPD when it is full-well can be predetermined, and the threshold voltage signal can be determined based on this voltage. For example, the threshold voltage signal can be equal to or slightly greater than the voltage of the PPD when it is full-well. Thus, when the voltage of the PPD drops below the threshold voltage signal, pixel module 111 is considered full-well. Since the output of the probe module 112 is electrically connected to the first input of the comparator 310, and the second input of the comparator 310 is electrically connected to the threshold voltage signal, the comparator 310 determines that the pixel module 111 is full-well when the input voltage at the first input of the comparator 310 is lower than or equal to the input voltage at the second input of the comparator 310. Conversely, the comparator 310 determines that the pixel module 111 is not full-well when the input voltage at the first input of the comparator 310 is higher than the input voltage at the second input of the comparator 310.

[0090] In this embodiment, when the input voltage at the first input terminal of the comparator 310 is lower than or equal to the input voltage at the second input terminal of the comparator 310, the comparator 310 is used to determine that the pixel module 111 is full-well; or, when the input voltage at the first input terminal of the comparator 310 is higher than the input voltage at the second input terminal of the comparator 310, the comparator 310 is used to determine that the pixel module 111 is not full-well. In this way, the process of determining whether the pixel module 111 is full-well by the full-well determination circuit 300 can be realized.

[0091] Optionally, the pixel module 111 includes a pinned-photodiode (PPD) device; the input terminal of the PPD device is grounded; the image detection circuit further includes a high-level module VDD; the probe module 112 includes a first switch SEL2 and a first source follower SF2; the gate of the first source follower SF2 is electrically connected to the output terminal of the PPD device; the source of the first source follower SF2 is electrically connected to the high-level module VDD; the drain of the first source follower SF2 is electrically connected to the first input terminal of the comparator 310 through the first switch SEL2; the control terminal of the first switch SEL2 is electrically connected to the row driver 200.

[0092] The voltage output of the high-level module VDD can be selected according to actual needs. For example, in some embodiments of this application, the output voltage of the high-level module VDD can be 5V or 3.3V, etc.

[0093] The aforementioned PPD device is a photodiode structure used in image sensors.

[0094] The first switching element SEL2 mentioned above can be any switching element with a control terminal, and whose switching state can be controlled by the control terminal. For example, please refer to [link to relevant documentation]. Figure 3 In some embodiments of this application, the first switching device SEL2 is an N-type metal-oxide-semiconductor (NMOS) transistor, wherein the control terminal of the first switching device SEL2 is the gate of the first switching device SEL2. Accordingly, one of the input and output terminals of the first switching device SEL2 is the source terminal of the first switching device SEL2, and the other is the drain terminal of the first switching device SEL2.

[0095] The first source follower SF2 mentioned above can be any type of source follower or a related circuit with a function similar to that of a source follower. The first source follower SF2 is a common-drain amplifier circuit built with a field-effect transistor as its core. Its main function is to realize impedance transformation and voltage signal following, and its voltage gain is approximately 1.

[0096] Please see Figure 3 In some embodiments of this application, when the probe module 112 needs to probe the pixel module 111, the row driver 200 can control the first switch SEL2 to be turned on; when the probe module 112 does not need to probe the pixel module 111, the row driver 200 can control the first switch SEL2 to be turned off. For example, in Figure 3 In the illustrated embodiment, the line driver 200 can control the first switch SEL2 to be turned off during the exposure sub-period; the line driver 200 can control the first switch SEL2 to be turned on during the detection sub-period. It is understood that since the drain of the first source follower SF2 can follow the voltage at the output terminal of the PPD device, that is, the voltage output from the drain of the first source follower SF2 can be considered as the voltage at the output terminal of the PPD device, therefore, when the first switch SEL2 is turned on, the input voltage at the first input terminal of the comparator 310 can be considered as the voltage at the output terminal of the PPD device, thereby enabling the detection of the voltage at the output terminal of the PPD device.

[0097] In this embodiment, the pixel module 111 includes a clamping photodiode (PPD) device; the input terminal of the PPD device is grounded; the image detection circuit further includes a high-level module VDD; the probe module 112 includes a first switch SEL2 and a first source follower SF2; the gate of the first source follower SF2 is electrically connected to the output terminal of the PPD device; the source of the first source follower SF2 is electrically connected to the high-level module VDD; the drain of the first source follower SF2 is electrically connected to the first input terminal of the comparator 310 through the first switch SEL2; the control terminal of the first switch SEL2 is electrically connected to the row driver 200. Thus, when the probe module 112 needs to probe the pixel module 111, the row driver 200 can control the first switch SEL2 to turn on, thereby enabling the probe module 112 to detect the voltage of the pixel module 111. When the probe module 112 does not need to probe the pixel module 111, the row driver 200 can control the first switch SEL2 to turn off, thereby preventing electrons in the PPD device from flowing to the probe module 112 and causing electron loss in the PPD device.

[0098] Optionally, the pixel module 111 further includes a second switch element TX; the LOFIC module 114 includes a third switch element LOFIC, a fourth switch element LOFIC_EN, a fifth switch element LOFIC_OF, and a LOFIC capacitor C. LOFIC The output terminal of the PPD device is electrically connected to the input terminal of the second switch TX; the output terminal of the second switch TX is sequentially connected to the third switch LOFIC and the LOFIC capacitor C. LOFIC Grounding.

[0099] The control terminal of the second switch TX is electrically connected to the row driver 200; the control terminal of the third switch LOFIC is electrically connected to the row driver 200 through the fourth switch LOFIC_EN; the control terminal of the fourth switch LOFIC_EN is electrically connected to the output terminal of the cache driver module 320 through the fifth switch LOFIC_OF; and the control terminal of the fifth switch LOFIC_OF is electrically connected to the row driver 200.

[0100] The aforementioned second switching element TX can be any switching element with a control terminal, and whose switching state can be controlled by the control terminal. For example, please refer to [link to relevant documentation]. Figure 3 In some embodiments of this application, the second switching element TX is an NMOS. The control terminal of the second switching element TX is also its gate. Correspondingly, one of the input and output terminals of the second switching element TX is its source, and the other is its drain.

[0101] The aforementioned third switching element (LOFIC) can be any switching element with a control terminal, and whose switching state can be controlled by the control terminal. For example, please refer to [link to relevant documentation]. Figure 5 In some embodiments of this application, the third switching device LOFIC is an NMOS, wherein the control terminal of the third switching device LOFIC is the gate of the third switching device LOFIC. Accordingly, one of the input and output terminals of the third switching device LOFIC is the source terminal of the third switching device LOFIC, and the other is the drain terminal of the third switching device LOFIC.

[0102] The aforementioned fourth switching element LOFIC_EN can be any switching element with a control terminal, whose switching state can be controlled by the control terminal. For example, please refer to [link to relevant documentation]. Figure 5 In some embodiments of this application, the fourth switching element LOFIC_EN is an NMOS, wherein the control terminal of the fourth switching element LOFIC_EN is also the gate of the fourth switching element LOFIC_EN. Accordingly, one of the input and output terminals of the fourth switching element LOFIC_EN is the source of the fourth switching element LOFIC_EN, and the other is the drain of the fourth switching element LOFIC_EN.

[0103] The aforementioned fifth switching element LOFIC_OF can be any switching element with a control terminal, whose switching state can be controlled by the control terminal. For example, please refer to [link to relevant documentation]. Figure 5 In some embodiments of this application, the fifth switching device LOBIC_OF is an NMOS, wherein the control terminal of the fifth switching device LOBIC_OF is also the gate of the fifth switching device LOBIC_OF. Correspondingly, one of the input and output terminals of the fifth switching device LOBIC_OF is the source terminal, and the other is the drain terminal.

[0104] Please see Figure 5 In some embodiments of this application, the control terminals of all second switches TX in the same pixel row can be controlled via V TX The line is electrically connected to the row driver 200. The control terminals of all fifth switches LOFIC_OF in the same pixel row can be connected via V... LOFIC The line is electrically connected to the row driver 200.

[0105] Please see Figure 5The aforementioned second switch TX can be used to control the on / off state between the PPD device and the back-end read module 113. For example, when reading the PPD device is required, the row driver 200 can control the second switch TX to be turned on; while in the non-reading stage, the second switch TX can be in a half-open state. The aforementioned second switch TX, third switch LOFIC, fourth switch LOFIC_EN, and fifth switch LOFIC_OF can be used to jointly control the LOFIC capacitor C. LOFIC The conduction state between the PPD device and the device can be controlled, for example, when the PPD device is full-well, the second switch TX can be turned on, and at the same time, the buffer driver module 320 can be controlled to output a high level and V. LOFIC When the line outputs a high level, the third switch (LOFIC), the fourth switch (LOFIC_EN), and the fifth switch (LOFIC_OF) are all turned on, thus establishing the electrical connection between the LOFIC module 114 and the pixel module 111. Conversely, when the PPD device is not fully charged, the buffer driver module 320 can output a low level, causing the fourth switch (LOFIC_EN) to turn off, thereby disconnecting the electrical connection between the LOFIC module 114 and the pixel module 111.

[0106] In this embodiment, the pixel module 111 further includes a second switch element TX; the LOFIC module 114 includes a third switch element LOFIC, a fourth switch element LOFIC_EN, a fifth switch element LOFIC_OF, and a LOFIC capacitor C. LOFIC The output terminal of the PPD device is electrically connected to the input terminal of the second switch TX; the output terminal of the second switch TX is sequentially connected to the third switch LOFIC and the LOFIC capacitor C. LOFIC Grounded; the control terminal of the second switch TX is electrically connected to the row driver 200; the control terminal of the third switch LOFIC is electrically connected to the row driver 200 through the fourth switch LOFIC_EN; the control terminal of the fourth switch LOFIC_EN is electrically connected to the output terminal of the buffer driver module 320 through the fifth switch LOFIC_OF; the control terminal of the fifth switch LOFIC_OF is electrically connected to the row driver 200. Thus, when the PPD device is full-well, the second switch TX can be turned on, and simultaneously, the buffer driver module 320 can be controlled to output a high level and V. LOFICWhen the line outputs a high level, the third switch (LOFIC), the fourth switch (LOFIC_EN), and the fifth switch (LOFIC_OF) are all in a conducting state, thus enabling the electrical connection between the LOFIC module 114 and the pixel module 111. Conversely, when the PPD device is not fully submerged, the buffer driver module 320 can output a low level, causing the fourth switch (LOFIC_EN) to disconnect, thereby disconnecting the electrical connection between the LOFIC module 114 and the pixel module 111. In other words, the buffer driver module 320 and the row driver 200 can control the on / off states of the second switch (TX), the third switch (LOFIC), the fourth switch (LOFIC_EN), and the fifth switch (LOFIC_OF) to control the on / off state of the electrical connection between the LOFIC module 114 and the pixel module 111.

[0107] Optionally, please see Figure 7 The pixel module 111 is a composite pixel module; the pixel module 111 includes N PPD devices and N second switches TX; the N PPD devices and the N second switches TX are connected in a one-to-one correspondence; the gate of the first source follower SF2 is electrically connected to the output terminal of at least one of the N PPD devices; wherein, N is an integer greater than 1.

[0108] Please see Figure 5 In some embodiments of this application, the pixel module 111 may include only a single PPD device; in this case, the pixel module 111 is a single pixel module. See also... Figure 7 In some embodiments of this application, the pixel module 111 may also include multiple PPD devices; in this case, the pixel module 111 is a composite pixel module. Figure 7 In the illustrated embodiment, the number of PPD devices is 4, and the value of N is 4. It should be noted that when the pixel module 111 is a composite pixel module, the value of N can also be other than 4, for example, 9 or 16.

[0109] Please see Figure 7 In some embodiments of this application, the control terminals of the N second switching elements TX can all be controlled via V TX The line is electrically connected to the row driver 200.

[0110] exist Figure 7In the illustrated embodiment, the gate of the first source follower SF2 is electrically connected to any one of the N PPD devices. At this time, the probe module 112 detects the full-well state of the connected PPD device and uses the detection result as the full-well state of the same pixel module 111.

[0111] It should be noted that the gate of the first source follower SF2 can also be electrically connected to the output terminals of two or more PPD devices in the pixel module 111 simultaneously. In this case, the electrons between all PPD devices connected to the gate of the first source follower SF2 are combined. This electron combination means that electrons can flow between PPD devices, resulting in a relatively balanced number of electrons in each PPD device. This electron combination is equivalent to short-circuiting multiple sub-pixels, merging them into one and activating the Binning mode. At this time, the probe module 112 can detect the voltage after the electron combination of each PPD device and use the detection result as the full-well state of the same pixel module 111.

[0112] In this embodiment, since the pixel module 111 is a composite pixel module, the pixel module 111 includes N PPD devices and N second switches TX; the N PPD devices and the N second switches TX are connected in a one-to-one correspondence; the gate of the first source follower SF2 is electrically connected to the output terminal of at least one of the N PPD devices, thus, the above image detection circuit can be applied to scenarios where the pixel module 111 is a composite pixel.

[0113] Optionally, please see Figure 8 The pixel module 111 is a composite pixel module; the pixel module 111 includes N PPD devices and N second switching devices TX; the pixel unit 110 includes N LOFIC modules 114, and the N LOFIC modules 114 are connected to the N PPD devices one by one; the gate of the first source follower SF2 is electrically connected to the output terminal of any one of the N PPD devices; where N is an integer greater than 1;

[0114] The output terminal of the PPD device is electrically connected to the corresponding LOFIC module 114; the output terminal of the PPD device is electrically connected to the input terminal of the corresponding second switch TX; the output terminal of the second switch TX is electrically connected to the reading module 113; and the control terminal of the second switch TX is electrically connected to the row driver 200.

[0115] Specifically, in Figure 8In the illustrated embodiment, the composite pixel module can implement LOFIC (High Dynamic Range, HDR) functionality in both Binning mode and FullSize mode. The Binning mode refers to: during the reading process of the composite pixel module, sequentially reading the signals from each PPD device individually, and sequentially reading the signals from each LOFIC module 114. Figure 8 In the illustrated embodiment, since there are four PPD devices and four LOFIC modules 114, a total of eight reads are required. Each PPD device includes a corresponding second switch TX for control; therefore, during the read process, one of the second switches TX can be activated simultaneously to sequentially read the signals from each PPD device individually. Correspondingly, only one set of LOFIC modules 114 and the read module 113 can be activated simultaneously to sequentially read the signals from each LOFIC module 114.

[0116] Accordingly, the Full Size mode refers to: simultaneously reading all PPD devices during the reading of the composite pixel module; and after reading all PPD devices, simultaneously reading all LOFIC modules 114. Figure 8 In the illustrated embodiment, a total of two reads are required. It is understood that during the read process, all second switches (TX) can be turned on simultaneously to read signals from all PPD devices at the same time. Correspondingly, all LOFIC modules 114 and the read module 113 can also be turned on simultaneously to read signals from all LOFIC modules 114 at the same time.

[0117] In this embodiment, the pixel module 111 is a composite pixel module. The pixel module 111 includes N PPD devices and N second switches TX. The pixel unit 110 includes N LOFIC modules 114, and the N LOFIC modules 114 are connected to the N PPD devices one by one. The gate of the first source follower SF2 is electrically connected to the output terminal of any one of the N PPD devices. The output terminal of the PPD device is electrically connected to the corresponding LOFIC module 114. The output terminal of the PPD device is electrically connected to the input terminal of the corresponding second switch TX. The output terminal of the second switch TX is electrically connected to the readout module 113. The control terminal of the second switch TX is electrically connected to the line driver 200. Thus, during the reading process of the composite pixel module, the signals in each PPD device are read sequentially, and the signals in each LOFIC module 114 are read sequentially, so that the composite pixel module can realize LOFIC HDR function in Binning mode. Alternatively, during the reading of the composite pixel module, all PPD devices can be read simultaneously. After reading all PPD devices, all LOFIC modules 114 can be read at the same time, so that the composite pixel module can realize LOFIC HDR function in full-size mode.

[0118] Optionally, the LOFIC module 114 includes a third switch LOFIC, a fourth switch LOFIC_EN, a fifth switch LOFIC_OF, and a LOFIC capacitor C. LOFIC The output terminal of the PPD device is sequentially connected to the third switching element Lofficer (LOFIC) and the Lofficer (LOFIC) capacitor C. LOFIC Grounded; the control terminal of the third switch LOFIC is electrically connected to the row driver 200 through the fourth switch LOFIC_EN; the control terminal of the fourth switch LOFIC_EN is electrically connected to the output terminal of the buffer driver module 320 through the fifth switch LOFIC_OF; the control terminal of the fifth switch LOFIC_OF is electrically connected to the row driver 200.

[0119] The aforementioned third switching element (LOFIC) can be any switching element with a control terminal, and whose switching state can be controlled by the control terminal. For example, please refer to [link to relevant documentation]. Figure 8In some embodiments of this application, the third switching device LOFIC is an NMOS, wherein the control terminal of the third switching device LOFIC is the gate of the third switching device LOFIC. Accordingly, one of the input and output terminals of the third switching device LOFIC is the source terminal of the third switching device LOFIC, and the other is the drain terminal of the third switching device LOFIC.

[0120] The aforementioned fourth switching element LOFIC_EN can be any switching element with a control terminal, whose switching state can be controlled by the control terminal. For example, please refer to [link to relevant documentation]. Figure 8 In some embodiments of this application, the fourth switching element LOFIC_EN is an NMOS, wherein the control terminal of the fourth switching element LOFIC_EN is also the gate of the fourth switching element LOFIC_EN. Accordingly, one of the input and output terminals of the fourth switching element LOFIC_EN is the source of the fourth switching element LOFIC_EN, and the other is the drain of the fourth switching element LOFIC_EN.

[0121] The aforementioned fifth switching element LOFIC_OF can be any switching element with a control terminal, whose switching state can be controlled by the control terminal. For example, please refer to [link to relevant documentation]. Figure 8 In some embodiments of this application, the fifth switching device LOBIC_OF is an NMOS, wherein the control terminal of the fifth switching device LOBIC_OF is also the gate of the fifth switching device LOBIC_OF. Correspondingly, one of the input and output terminals of the fifth switching device LOBIC_OF is the source terminal, and the other is the drain terminal.

[0122] Please see Figure 8 In some embodiments of this application, the four PPD devices in the pixel module 111 are arranged in a 2×2 manner, that is, the PPD devices in the pixel module 111 are distributed in two pixel rows, and the control terminals of all second switching devices TX in the same pixel row can be controlled via V TX The line is electrically connected to the row driver 200. The control terminals of all fifth switches LOFIC_OF in the same pixel row can be connected via V... LOFIC The line is electrically connected to the row driver 200.

[0123] Thus, it is possible to achieve this by adjusting V. TX Line, V LOFIC By controlling the signals output by the line and buffer driver module 320, the control process for the aforementioned third switch LOBIC, fourth switch LOBIC_EN, and fifth switch LOBIC_OF can be achieved. Please refer to [link / reference needed]. Figure 8The second switch TX can be used to control the on / off state between the PPD device and the back-end read module 113. For example, when reading the PPD device, the row driver 200 can control the second switch TX to be turned on; while in the non-reading stage, the second switch TX can be in a half-open state. The third switch LOFIC, the fourth switch LOFIC_EN, and the fifth switch LOFIC_OF can be used to jointly control the LOFIC capacitor C. LOFIC The conduction state between the PPD device and the cache driver module 320 can be controlled to output a high level when the PPD device is full-well, for example, when the PPD device is full-well. LOFIC When the line outputs a high level, the third switch (LOFIC), the fourth switch (LOFIC_EN), and the fifth switch (LOFIC_OF) are all turned on, thus establishing the electrical connection between the LOFIC module 114 and the pixel module 111. Conversely, when the PPD device is not fully charged, the buffer driver module 320 can output a low level, causing the fourth switch (LOFIC_EN) to turn off, thereby disconnecting the electrical connection between the LOFIC module 114 and the pixel module 111.

[0124] In this embodiment, the LOFIC module 114 includes a third switch LOFIC, a fourth switch LOFIC_EN, a fifth switch LOFIC_OF, and a LOFIC capacitor C. LOFIC The output terminal of the PPD device is sequentially connected to the third switching element Lofficer (LOFIC) and the Lofficer (LOFIC) capacitor C. LOFIC Grounded; the control terminal of the third switch LOFIC is electrically connected to the row driver 200 through the fourth switch LOFIC_EN; the control terminal of the fourth switch LOFIC_EN is electrically connected to the output terminal of the buffer driver module 320 through the fifth switch LOFIC_OF; the control terminal of the fifth switch LOFIC_OF is electrically connected to the row driver 200. Thus, when the PPD device is full-well, the buffer driver module 320 can be controlled to output a high level, V... LOFICWhen the line outputs a high level, the third switch LOBIC, the fourth switch LOBIC_EN, and the fifth switch LOBIC_OF are all in a conducting state, thus enabling the electrical connection between the LOBIC module 114 and the pixel module 111. Conversely, when the PPD device is not fully submerged, the buffer driver module 320 can output a low level, causing the fourth switch LOBIC_EN to disconnect, thereby disconnecting the electrical connection between the LOBIC module 114 and the pixel module 111. In other words, the buffer driver module 320 and the row driver 200 can control the on / off states of the third switch LOBIC, the fourth switch LOBIC_EN, and the fifth switch LOBIC_OF to control the on / off state of the electrical connection between the LOBIC module 114 and the pixel module 111.

[0125] Optionally, the reading module 113 includes a second source follower SF1, a sixth switch RST, and a seventh switch SEL1; the input terminal of the sixth switch RST is electrically connected to the high-level module VDD; the output terminal of the sixth switch RST is electrically connected to the output terminal of the second switch TX; and the control terminal of the sixth switch RST is electrically connected to the row driver 200.

[0126] The gate of the second source follower SF1 is electrically connected to the output terminal of the second switch TX; the source of the second source follower SF1 is electrically connected to the high-level module VDD; the drain of the second source follower SF1 is electrically connected to the output circuit 400 through the seventh switch SEL1; the control terminal of the seventh switch SEL1 is electrically connected to the row driver 200.

[0127] The aforementioned second source follower SF1 can be any type of source follower or a related circuit with a function similar to that of a source follower. The second source follower SF1 is a common-drain amplifier circuit built with a field-effect transistor as its core. Its main function is to realize impedance transformation and voltage signal following, and its voltage gain is approximately 1.

[0128] The aforementioned sixth switching element RST can be any switching element with a control terminal, and whose switching state can be controlled by the control terminal. For example, please refer to [link to relevant documentation]. Figure 8 In some embodiments of this application, the sixth switching device RST is an NMOS, wherein the control terminal of the sixth switching device RST is the gate of the sixth switching device RST. Accordingly, one of the input and output terminals of the sixth switching device RST is the source of the sixth switching device RST, and the other is the drain of the sixth switching device RST.

[0129] The aforementioned seventh switch SEL1 can be any switch with a control terminal, and the switch state can be controlled by the control terminal. For example, please refer to [link to relevant documentation]. Figure 8 In some embodiments of this application, the seventh switching device SEL1 is an NMOS, wherein the control terminal of the seventh switching device SEL1 is the gate of the seventh switching device SEL1. Accordingly, one of the input and output terminals of the seventh switching device SEL1 is the source of the seventh switching device SEL1, and the other is the drain of the seventh switching device SEL1.

[0130] Please see Figure 8 When signal reading is required, the seventh switch SEL1 can be turned on by the row driver 200. After signal reading is completed, the sixth switch RST can be turned on by the driver. At this time, the high-level module VDD can connect the PPD device and the LOFIC capacitor C. LOFIC The charge in the middle is cleared and reset.

[0131] In this embodiment, the read module 113 includes a second source follower SF1, a sixth switch RST, and a seventh switch SEL1. The input terminal of the sixth switch RST is electrically connected to the high-level module VDD. The output terminal of the sixth switch RST is electrically connected to the output terminal of the second switch TX. The control terminal of the sixth switch RST is electrically connected to the row driver 200. The gate of the second source follower SF1 is electrically connected to the output terminal of the second switch TX. The source of the second source follower SF1 is electrically connected to the high-level module VDD. The drain of the second source follower SF1 is electrically connected to the output circuit 400 through the seventh switch SEL1. The control terminal of the seventh switch SEL1 is electrically connected to the row driver 200. Thus, when signal reading is required, the seventh switch SEL1 can be turned on by the row driver 200. After signal reading is completed, the sixth switch RST can be turned on by the driver. At this time, the high-level module VDD can connect the PPD device and the LOFIC capacitor C. LOFIC The charge in the middle is cleared and reset.

[0132] It should be noted that the above-mentioned LOFIC capacitor C LOFIC Unlike other capacitors in the image detection circuit, the LOFIC capacitor C LOFIC As an independent capacitor, it has independent positive and negative plates and dielectric filling material; therefore, the LOFIC capacitor C LOFIC Its capacity is enormous.

[0133] Using LOFIC capacitor C LOFICThe pixels can achieve HDR technology based on LOFIC. Its basic working principle is as follows: during the exposure time of one frame, if a pixel encounters strong light, the PPD within the pixel will fill its well after a certain period, meaning electrons fill the PPD's built-in capacitance. After the PPD fills its well, it will continue to generate electrons, but excess electrons will flow out of the PPD through a partially closed TX transistor. At this time, if the electrical connection between the LOFIC module 114 and the pixel module 111 is made active, the overflowing charge will be buffered by the CFD and C... LOFIC In a large capacitor formed by parallel connections, during the readout period, electrons from the PPD are introduced into the CFD and read by the SF. Finally, the LOFIC switching transistor closes again, and the SF reads the voltage drop generated by the overflowing electrons in the LOFIC as the signal of the pixel under ultra-strong light.

[0134] The image detection circuit provided in this application embodiment continuously performs pixel-by-pixel full-well monitoring during the exposure period of each frame, and turns on the LOFIC capacitor C based on the full-well status of PPD within the pixel. LOFIC To reduce the capacitance C of the LOOFIC LOFIC Accumulation of internal noise signals. Similarly, pixel-by-pixel full-well monitoring is performed during the readout period of each frame, and the decision on whether to apply LOFIC capacitor C is adaptively made based on the full-well status of the PPD within the pixel. LOFIC The reading and analog-to-digital conversion can significantly reduce power consumption during the LOFIC HDR process.

[0135] To facilitate understanding, the image detection circuit provided in this application embodiment is further explained and described in conjunction with the accompanying drawings:

[0136] Please see Figure 3 In some embodiments of this application, a probe module 112 is embedded in the pixel unit 110 to monitor the PPD voltage change of the pixel during the exposure period and output a corresponding voltage signal V. PPD .

[0137] Two switching transistors, LOBIC_OF and LOBIC_EN, are added within each pixel. The LOBIC_EN transistor controls the on / off state of the LOBIC transistor, while the LOBIC_OF transistor controls the on / off state of LOBIC_EN. The operating principle of LOBIC_EN and LOBIC_OF is as follows: When a horizontal pixel is selected, the VLOFIC voltage for that horizontal row goes high, causing the LOBIC_OF transistor to close and conduct. The VLOFIC voltage output by the full-well detection module... OF The signal then reaches LOBIC_EN through the closed LOBIC_OF transistor and is processed according to V. OF The signal indicates that the LOFIC_EN transistor is on or off, where V OFThe signal can be 0 or 1, when V OF When the signal is 1, the LOFIC_EN transistor is closed; when V OF When the signal is 0, the LOFIC_EN transistor is off. It should be noted that when both LOFIC_EN and the LOFIC transistor are closed, electrons in the PPD after it has filled its well can be transferred to the LOFIC capacitor C through the TX transistor and the LOFIC transistor. LOFIC Inside.

[0138] A new pixel full-well detection module is added to the CIS architecture. This module contains column-parallel full-well detection submodules. Each full-well detection submodule corresponds to a pixel column and receives the V signal transmitted from the pixels in that column through a shared wire. PPD Signal. Each full-well judgment module has a built-in comparator 310 for comparing V. PPD Signal and custom threshold signal V TH The relative magnitudes between them are compared by comparator 310, and the result is cached in the cache driver circuit and used as the lateral overflow start signal V. TH Returns to the specified pixel in this column.

[0139] Figure 3 The image detection circuit shown can scan the voltage change of PPD in each pixel line by line within the exposure time of one frame and determine whether the full well has been reached. If the full well has been reached, V is pulled high. OF The signal is used to turn on the LOBIC_EN and LOBIC switching transistors, allowing electrons in the PPD in the full-well state to overflow laterally to the corresponding C. LOFIC In addition, this architecture can determine whether a pixel is full within a frame's read interval, in order to decide whether C is needed. LOFIC The reading and analog-to-digital conversion. A specific frame's timing diagram is shown below. Figure 6 As shown:

[0140] The exposure period during the acquisition of one frame of an image is divided into M sub-periods, and each sub-period includes a sub-exposure period and a full-well judgment period. During the sub-exposure period, the PPD within the pixel generates electrons and stores them in its own capacitance. In the subsequent full-well judgment period, the PPD probe circuit within the pixel outputs the instantaneous voltage value of the PPD as V. PPD The signal is transmitted to the column-parallel full-well judgment module for judgment. The judgment result signal V OF This will guide whether pixels within a pixel row will experience PPD lateral overflow. For example, if the PPD probe circuit detects an instantaneous PPD voltage of 1.5V (VPPD = 1.5V), then this V... PPD The signal is transmitted to the column-parallel full-well detection module for full-well detection. If it is related to V... THIf the full-well detection module determines that the full-well is not full after comparison, it outputs 0 or a low level. If the full-well detection module determines that the full-well is full after comparison with VTH, it outputs 1 or a high level.

[0141] There is a time difference between the exposure time of each row of pixels and the exposure time of other rows of pixels, and this time difference is exactly the same as the time difference when the pixel array 100 is reset and read from the rolling shutter.

[0142] During the reading period of an image frame acquisition process, before electrons in the PPD are transferred to the reading circuit for reading, a full-well check is first performed. After the check is completed, the PPD reading operation is performed, that is, electrons are transferred from the PPD to the buffer capacitor C of the reading circuit via TX. FD In the middle, SF will then take C FD The electrons in the electrons are converted into pixel output signals, and then, by V PIX The pixel output signal is output outside the pixel. Then, based on the full-well determination result, it is decided whether this pixel needs to be read using LOFIC. For example, if V... OF If the value is 1 or high, then LOFIC is read. At this time, the LOFIC transistor is closed, and the LOFIC capacitor C... LOFIC Electrons in the SF are converted into pixel output signals V. PIX The output goes beyond the pixel and undergoes analog-to-digital conversion via an ADC and subsequent image processing via an ISP, such as noise reduction, dead pixel removal, and HDR synthesis. Conversely, if V OF If the value is 0 or low, there is no need to read LOFIC.

[0143] Please see Figure 3 , Figure 7 and Figure 8 This is a specific embodiment of the image detection circuit provided in this application. By including the above-mentioned image detection circuit in a mobile terminal device such as a mobile phone, the CIS chip with LOFIC HDR function in the camera of the mobile terminal device has the following capabilities: the ability to determine the timing of lateral overflow activation by detecting the full-well status of pixels during a single frame exposure time, thereby reducing LOFIC noise; and the ability to adaptively implement LOFIC capacitor C based on the full-well status during a single frame readout time. LOFIC The ability to read data to reduce processing time and power consumption.

[0144] The image detection circuit in this embodiment can be applied to HDR video imaging applications based on LOFIC HDR technology.

[0145] Please see Figure 3In the pixel array 100 within the CIS architecture, each LOFIC pixel contains a probe module 112 composed of two NMOS transistors. SF2 is used to monitor voltage changes on the PPD and outputs the corresponding voltage signal as V. PPD When the row driver 200 outputs a row signal to close the SEL2 transistor, V PPD The signal is transmitted to the full-well detection module via a column of wires. This probe design minimizes the number of transistors inside the pixel, which is beneficial for pixel miniaturization. Based on this LOFIC pixel design, the CIS runtime steps during the acquisition of one frame of image are as follows: Figure 6 As shown, the specific steps include:

[0146] Step 1: During the reset period, the pixel array 100 closes the RST, TX and LOFIC switches row by row under the control of the row controller to reset and clear all residual electrons in the pixels.

[0147] Step 2: When entering the exposure period, proceed as follows Figure 6 The timing control of the 100-pixel array is performed row-by-row in an arc, with all switches open during each sub-exposure period. When the full-well detection period begins, the SEL2 switch closes, and the probe outputs V. PPD The signal is sent to the full-well detection module, which will then determine the V signal. PPD Signal and V TH Compare and generate V based on the comparison results. OF Signal. Based on the returned V OF The state of the signal determines whether the pixel is currently full of its well. For example, in Figure 6 In the illustrated embodiment, the pixel in Row 1 is V during the second full-well determination. OF If the signal feedback is "1" or high, then RST within this pixel will close at the beginning of the third sub-exposure period to clear C. LOFIC All accumulated noise signals within. Then, during the transverse overflow phase, LOFIC closes and TX partially closes to allow excess electrons in PPD to overflow and flow into C. LOFIC Since this pixel is already full, LOFIC needs to be closed and TX partially closed during subsequent sub-exposure periods to allow excess electrons in PPD to overflow and flow into C. LOFIC However, it is not necessary to close RST to clear the well. If no pixel is judged to be about to fill the well, for example, in... Figure 6 In Row 2 of the illustrated embodiment, SEL2 closes periodically during the full-well judgment period to output V. PPD Signal to full trap judgment module.

[0148] Step 3: Upon entering the reading period, pixel array 100 performs a full-well check row by row before entering the PPD reading period. During the PPD reading period, RST is closed to clear C. FD This is coupled with a buffer capacitor, for example, an LCG capacitor. Then TX closes completely to allow electrons from the PPD to be introduced into C. FD Along with the associated buffer capacitor, SEL1 is simultaneously closed. SF1 generates V. PIX The signal is output to an external ADC module for analog-to-digital conversion. After the PPD readout period ends, the LOFIC readout period begins. Based on the previous full-well determination result, for example, for a pixel on Row 1, when the full-well determination result V... OF When the value is 1 or high, the SEL1 and LOFIC transistors close again, and SF reads C. LOFIC Electrons within the body generate V, which is the output of this stage. PIX The data is then converted from analog to digital by the ADC. For a pixel on Row 2, when the full-well judgment result V... OF When the value is 0 or low, the SEL1 and LOFIC transistors are off. In this case, there is no need to adjust C. LOFIC Perform the reading and subsequent analog-to-digital conversion steps.

[0149] Under the above steps, CIS can divide the exposure time into M sub-exposure periods and a full-well judgment period within one frame to achieve full-well monitoring of each pixel and enable the LOFIC (Lateral Overflow Electron) function. Simultaneously, during the one-frame readout phase, LOFIC readout is adaptively performed based on the full-well status of each pixel, saving unnecessary LOFIC readout time and processing power.

[0150] Figure 3 In the illustrated embodiment, because the probe and readout circuit are physically isolated and operate at different times, pixel miniaturization can be achieved using a simple two-transistor design without affecting image frame quality. By continuously monitoring the pixel fill-well status during the exposure period to enable lateral overflow, the performance of the LOFIC capacitor C is effectively reduced. LOFIC Accumulated noise signal within the cell. By determining the pixel full-well status during the readout phase, the LOFIC capacitor C is adaptively adjusted. LOFIC This reading method effectively reduces signal reading time and lowers the power consumption of the image detection circuit during the reading process.

[0151] Figure 7 and Figure 8 The illustrated embodiments and Figure 3 The illustrated embodiments are consistent in terms of CIS architecture, differing only in the circuit architecture within the pixels. Figure 7 In the illustrated embodiment, the circuit architecture is designed for composite pixels. Figure 7The example listed is a 4-in-1 pixel. Each monochrome pixel cluster consists of 4 sub-pixels. Each sub-pixel contains a PPD and a matching transfer transistor TX. Each TX transistor is responsible for the charge transfer of the corresponding PPD sub-pixel. Since each pixel in this embodiment contains multiple sub-pixel PPDs, for this pixel architecture, the probe module 112 can be connected to one or more sub-pixels. For example, each pixel cluster contains one probe connected to one sub-pixel PPD, or it can be connected to multiple sub-pixel PPDs. Alternatively, each pixel cluster contains 4 probes, each connected to one sub-pixel PPD. By monitoring the voltage of one or more PPDs, the full-well status of each sub-pixel can be determined as a whole. It should be noted that if one probe is used to connect multiple PPDs, the VPPD signal will be correspondingly increased and electronic exchange merging between connected PPDs will occur. This electronic exchange merging is equivalent to short-circuiting multiple sub-pixels, merging multiple sub-pixels into one and activating the Binning mode. In addition, there is another unique LOFIC connection method for composite pixels, such as... Figure 8 As shown. Its LOFIC position is placed next to each PPD. For example, Figure 7 The illustrated embodiment shows the pixel design circuit. The sub-pixel PPD is equipped with a corresponding LOCIC capacitor C. LOFIC The charge overflowing from the PPD during the exposure period is conducted to the C via a LOFIC transistor. LOFIC Mid-buffer. This LOFIC connection method allows these composite pixels to achieve LOFIC HDR functionality in both Binning and Full Size modes. Therefore, for this type of composite pixel, this implementation method can adopt... Figure 8 The method shown integrates a probe to achieve full-well monitoring. A probe is connected to one of the PPDs; when this PPD is determined to be nearing full well, the LOFIC of all PPDs is activated for lateral overflow. This approach requires only one additional probe to achieve the desired functionality while maintaining the pixel pair miniaturization requirement.

[0152] Figure 7 and Figure 8 In the illustrated embodiment, by continuously monitoring the pixel fill-well status during the exposure period to enable the lateral overflow function, the LOFIC capacitance C is effectively reduced in Binning mode and Full Size mode. LOFIC Accumulated noise signal within the cell. By determining the pixel full-well status during the readout phase, the LOFIC capacitor C is adaptively adjusted. LOFIC Reading. Effectively reduces signal readout time in Binning and Full Size modes, and lowers power consumption of the image detection circuit during the reading process.

[0153] This application also provides an image sensor, including the image detection circuit described in the above embodiments.

[0154] In this embodiment, since the image sensor includes the image detection circuit described above, the image sensor can implement each process of the image detection circuit in the above embodiments and has the same beneficial effects. To avoid repetition, it will not be described again here.

[0155] This application also provides an electronic device, including the image sensor described in the above embodiments.

[0156] In this embodiment, since the electronic device includes the image sensor described above, the electronic device can implement all the processes of the image sensor in the above embodiments and has the same beneficial effects. To avoid repetition, it will not be described again here.

[0157] Please see Figure 9 This application also provides an image detection method applied to the image detection circuit described in the above embodiments, the image detection method comprising:

[0158] Step 901: During the exposure period of the first pixel unit, the pixel module 111 in the first pixel unit is detected by the probe module 112 in the first pixel unit to obtain a first detection signal. The first pixel unit is any pixel unit 110 in the pixel array 100.

[0159] Step 902: When the full well determination circuit 300 in the first pixel unit determines that the pixel module 111 is full based on the first detection signal, the full well determination circuit 300 outputs a first control signal to the LOFIC module 114 in the first pixel unit, wherein the first control signal is used to connect the electrical connection between the LOFIC module 114 and the pixel module 111.

[0160] Alternatively, in step 903, if the full-well determination circuit 300 in the first pixel unit determines that the pixel module 111 is not full based on the first detection signal, the full-well determination circuit 300 outputs a second control signal to the LOFIC module 114 in the first pixel unit; wherein the second control signal is used to disconnect the electrical connection between the LOFIC module 114 and the pixel module 111.

[0161] In this embodiment, the full-well state of the pixel module 111 is detected by the probe module 112, and the full-well determination circuit 300 determines whether the pixel module 111 is full based on the detection result of the probe module 112. When the full-well determination circuit 300 determines that the pixel module 111 is full, the electrical connection between the LOFIC module 114 and the pixel module 111 is turned on, so that when the pixel module 111 is full, the charge or electrons in the pixel module 111 can overflow to the LOFIC module 114, thereby storing the overflowing electronic signal after the pixel module 111 is full in the LOFIC module 114. Correspondingly, when the full-well determination circuit 300 determines that the pixel module 111 is not full, the electrical connection between the LOFIC module 114 and the pixel module 111 is disconnected, thereby avoiding the problem of continuous noise accumulation in the LOFIC module 114 when the pixel module 111 is not full because the LOFIC module 114 and the pixel module 111 are always electrically connected. This reduces the noise in the signal stored in the LOFIC module 114 of the image detection circuit.

[0162] Optionally, the exposure period includes multiple exposure sub-periods and multiple detection sub-periods, wherein any two adjacent exposure sub-periods are separated by a detection sub-period;

[0163] During the exposure period of the first pixel unit, the probe module 112 in the first pixel unit detects the pixel module 111 in the first pixel unit to obtain a first detection signal, including:

[0164] During each detection sub-period, the pixel module 111 in the first pixel unit is detected by the probe module 112 in the first pixel unit to obtain the first detection signal;

[0165] The image detection method further includes:

[0166] During the exposure sub-period, the pixel module 111 is exposed via the line driver 200.

[0167] In this embodiment, the exposure period includes multiple exposure sub-periods and multiple detection sub-periods. Each pair of adjacent exposure sub-periods is separated by a detection sub-period. Within each detection sub-period, the probe module 112 in the first pixel unit detects the pixel module 111 to obtain a first detection signal. Within the exposure sub-period, the row driver 200 controls the exposure of the pixel module 111. This allows for alternating detection and exposure during the exposure period, ensuring that the probe module 112 can promptly detect the full-well state of the pixel module 111 when it is full, thus improving the real-time performance of the full-well detection by the probe module 112.

[0168] Optionally, the method further includes:

[0169] During the signal reading period of the first pixel unit, the pixel module 111 is probed by the probe module 112 to obtain a second detection signal;

[0170] When the full-well determination circuit 300 determines that the pixel module 111 is full based on the second detection signal, the LOFIC module 114 performs signal reading during the signal reading period.

[0171] Alternatively, when the full-well determination circuit 300 determines that the pixel module 111 is not full based on the second detection signal, the signal reading of the LOFIC module 114 is skipped during the signal reading period.

[0172] During the reading period of each frame, pixel-by-pixel full-well monitoring is performed, and the decision on whether to perform LOFIC capacitance C is adaptively made based on the full-well status of PPD within the pixel. LOFIC The reading and analog-to-digital conversion can significantly reduce power consumption during the LOFIC HDR process.

[0173] In this embodiment, electrons in pixel module 111 can only flow into LOFIC module 114 when pixel module 111 is full-well; that is, LOFIC module 114 only stores a valid signal when pixel module 111 is full-well. Therefore, before reading LOFIC module 114, it can be determined whether pixel module 111 is full-well. Only when pixel module 111 is full-well is it read. If pixel module 111 is not full-well, the signal reading of LOFIC module 114 is skipped. In other words, the decision to perform LOFIC capacitor C can be adaptively made based on the full-well status of the PPD within the pixel. LOFIC The reading and analog-to-digital conversion can significantly reduce power consumption during the LOFIC HDR process.

[0174] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. An image detection circuit, characterized in that, Includes pixel array, row driver, full-well detection circuit and output circuit; The pixel array includes multiple pixel units arranged in an array; each pixel unit includes a pixel module, a probe module, a readout module, and a lateral overflow integration capacitor (LOFIC) module; the probe module, the LOFIC module, and the readout module are electrically connected to the pixel module; the readout module is also electrically connected to the LOFIC module; the LOFIC module, the readout module, the pixel module, and the probe module are all electrically connected to the row driver; the readout module is electrically connected to the output circuit. The probe module and the LOFIC module are respectively electrically connected to the full-well determination circuit; wherein, the full-well determination circuit is used to determine whether the pixel module is full-well based on the detection signal output by the probe module; the full-well determination circuit is used to connect the electrical connection between the LOFIC module and the pixel module when the pixel module is full-well; the full-well determination circuit is also used to disconnect the electrical connection between the LOFIC module and the pixel module when the pixel module is not full-well.

2. The image detection circuit according to claim 1, characterized in that, The full-well detection circuit includes a comparator and a buffer driver module; the probe module is used to collect the voltage of the pixel module; the output terminal of the probe module is electrically connected to the first input terminal of the comparator; the second input terminal of the comparator is electrically connected to the threshold voltage signal; the output terminal of the comparator is electrically connected to the input terminal of the buffer driver module; and the output terminal of the buffer driver module is electrically connected to the LOFIC module.

3. The image detection circuit according to claim 2, characterized in that, When the input voltage at the first input terminal of the comparator is lower than or equal to the input voltage at the second input terminal of the comparator, the comparator is used to determine that the pixel module is full-well. Alternatively, if the input voltage at the first input terminal of the comparator is higher than the input voltage at the second input terminal of the comparator, the comparator is used to determine that the pixel module is not full.

4. The image detection circuit according to claim 2, characterized in that, The pixel module includes a clamping photodiode (PPD) device; the input terminal of the PPD device is grounded; the image detection circuit further includes a high-level module; the probe module includes a first switch and a first source follower; the gate of the first source follower is electrically connected to the output terminal of the PPD device; the source of the first source follower is electrically connected to the high-level module; the drain of the first source follower is electrically connected to the first input terminal of the comparator through the first switch; the control terminal of the first switch is electrically connected to the row driver.

5. The image detection circuit according to claim 4, characterized in that, The pixel module further includes a second switch; the LOFIC module includes a third switch, a fourth switch, a fifth switch, and a LOFIC capacitor; the output terminal of the PPD device is electrically connected to the input terminal of the second switch; the output terminal of the second switch is grounded through the third switch and the LOFIC capacitor in sequence. The control terminal of the second switch is electrically connected to the row driver; the control terminal of the third switch is electrically connected to the row driver through the fourth switch; the control terminal of the fourth switch is electrically connected to the output terminal of the buffer driver module through the fifth switch; and the control terminal of the fifth switch is electrically connected to the row driver.

6. The image detection circuit according to claim 5, characterized in that, The pixel module is a composite pixel module; the pixel module includes N PPD devices and N second switches; the N PPD devices and the N second switches are connected in a one-to-one correspondence; the gate of the first source follower is electrically connected to the output terminal of at least one of the N PPD devices; wherein, N is an integer greater than 1.

7. The image detection circuit according to claim 4, characterized in that, The pixel module is a composite pixel module; the pixel module includes N PPD devices and N second switching devices; the pixel unit includes N LOFIC modules, and the N LOFIC modules are connected to the N PPD devices in a one-to-one correspondence; the gate of the first source follower is electrically connected to the output terminal of any one of the N PPD devices; where N is an integer greater than 1; The output terminal of the PPD device is electrically connected to the corresponding LOFIC module; the output terminal of the PPD device is electrically connected to the input terminal of the corresponding second switch; the output terminal of the second switch is electrically connected to the reading module; and the control terminal of the second switch is electrically connected to the row driver.

8. The image detection circuit according to claim 7, characterized in that, The LOFIC module includes a third switch, a fourth switch, a fifth switch, and a LOFIC capacitor; the output terminal of the PPD device is grounded sequentially through the third switch and the LOFIC capacitor; the control terminal of the third switch is electrically connected to the row driver through the fourth switch; the control terminal of the fourth switch is electrically connected to the output terminal of the buffer driver module through the fifth switch; and the control terminal of the fifth switch is electrically connected to the row driver.

9. The image detection circuit according to any one of claims 5 to 8, characterized in that, The reading module includes a second source follower, a sixth switch, and a seventh switch; the input terminal of the sixth switch is electrically connected to the high-level module; the output terminal of the sixth switch is electrically connected to the output terminal of the second switch; and the control terminal of the sixth switch is electrically connected to the row driver. The gate of the second source follower is electrically connected to the output terminal of the second switch; the source of the second source follower is electrically connected to the high-level module; the drain of the second source follower is electrically connected to the output circuit through the seventh switch; the control terminal of the seventh switch is electrically connected to the row driver.

10. An image sensor, characterized in that, The image detection circuit includes any one of claims 1 to 9.

11. An electronic device, characterized in that, Including the image sensor of claim 10.

12. An image detection method, performed by the electronic device of claim 11, characterized in that, The image detection method includes: During the exposure period of the first pixel unit, the probe module in the first pixel unit is used to detect the pixel module in the first pixel unit to obtain a first detection signal. The first pixel unit is any pixel unit in the pixel array. When the full-well determination circuit in the first pixel unit determines that the pixel module is full based on the first detection signal, the full-well determination circuit outputs a first control signal to the LOFIC module in the first pixel unit, wherein the first control signal is used to connect the electrical connection between the LOFIC module and the pixel module. Alternatively, if the full-well determination circuit in the first pixel unit determines that the pixel module is not full based on the first detection signal, the full-well determination circuit outputs a second control signal to the LOFIC module in the first pixel unit; wherein the second control signal is used to disconnect the electrical connection between the LOFIC module and the pixel module.

13. The image detection method according to claim 12, characterized in that, The exposure period includes multiple exposure sub-periods and multiple detection sub-periods, wherein any two adjacent exposure sub-periods are separated by a detection sub-period; During the exposure period of the first pixel unit, the first pixel unit is probed by a probe module to obtain a first detection signal, including: During each detection sub-period, the pixel module in the first pixel unit is detected by the probe module in the first pixel unit to obtain the first detection signal; The image detection method further includes: During the exposure sub-period, the exposure of the pixel module is controlled by the line driver.

14. The image detection method according to claim 12, characterized in that, The method further includes: During the signal reading period of the first pixel unit, the pixel module is probed by the probe module to obtain a second detection signal; When the full-well determination circuit determines that the pixel module is full based on the second detection signal, the LOFIC module is read from the signal during the signal reading period. Alternatively, when the full-well determination circuit determines, based on the second detection signal, that the pixel module is not full, the signal reading of the LOFIC module is skipped during the signal reading period.

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