Heterojunction transistor with sub-nano trench length and sub-nano gate width and preparation method thereof

Abstract

The invention discloses a heterojunction transistor with sub-nanometer groove length and sub-nanometer gate width and a preparation method thereof, a PN junction heterojunction is constructed by single-layer CVD graphene and a single-layer CVD two-dimensional material, a vertical PN junction with sub-1nm thickness is used as a device channel, and the length of the channel is equal to the thickness of the heterojunction; the grid structure uses the graphene and the edge of the two-dimensional material layer as a grid electrode, and the grid width is equal to the thickness of the heterojunction and reaches sub-1 nm; a source electrode, a drain electrode and a grid electrode are separated into three independent terminals through gap etching, the Fermi level of graphene is adjusted through grid voltage, the barrier height of a PN junction is changed, and on-off control of the device is achieved. The bottom silicon gate can assist regulation and control to further optimize the setting range of the gate voltage. According to the invention, the problems of short channel effect and grid control of a silicon-based device are solved, the preparation process is simplified, wafer-level mass production is realized, and the development requirement of ultra-miniaturization of an integrated circuit is met.

Description

Technical Field

[0001] This invention relates to semiconductor technology, and more particularly to a heterojunction transistor with sub-nanometer trench length and sub-nanometer gate width and its fabrication method. Background Technology

[0002] Since the advent of the first integrated circuit in the 1960s, silicon (Si) transistors have been continuously shrinking under the guidance of Moore's Law. Apart from the early bipolar junction transistor (BJT), field-effect transistors (FETs) are the core logic devices in silicon-based integrated circuits. Device structures have evolved sequentially from planar metal-oxide-semiconductor field-effect transistors (MOSFETs) to FinFETs and Gate-All-Ring Field-Effect Transistors (GAAFETs). However, when transistor technology moves below 5 nanometers, silicon transistors are approaching their scaling limits. As integrated circuit technology enters the sub-nanometer scale, traditional silicon-based transistors face challenges such as reduced gate control capability and increased short-channel effects. Exploring new structures to further reduce gate width and channel length is crucial.

[0003] Two-dimensional materials (such as molybdenum disulfide and graphene), due to their atomic-level thickness and absence of dangling bonds, exhibit superior electrostatic control capabilities and are considered potential candidates for overcoming the size limitations of silicon-based devices. Low-dimensional transistors achieve stronger gate control through atomic-level channel thickness, unaffected by short-channel effects, offering possibilities for further miniaturization of device dimensions. However, in the three typical transistor structures, further reducing the gate width or channel length to below 1 nanometer is extremely difficult. The design of ultra-small transistor structures has always been a core research topic in the field of microelectronics. Transistor structures with sub-1-nanometer gate widths and novel vertical field-effect transistor structures have achieved breakthroughs in gate width and channel length. However, limited by atomic size, transistor structures with gate widths and channel lengths below sub-nanometer may be the limit of transistor manufacturing processes. This may also be the ultimate development direction for traditional silicon-based transistors or two-dimensional transistors.

[0004] 1. Silicon-based super-scaling transistors: such as gate-all-around field-effect transistors (GAAFETs), which improve the control of the channel through a three-dimensional gate structure. However, due to the physical properties of silicon materials, when the process enters the sub-nanometer scale, the short-channel effect cannot be effectively suppressed, and the gate control capability is significantly reduced (Source: Chau, R). et al ., Integratednanoelectronics for the future. Nat. Mater. 6, 810-812 (2007)).

[0005] 2. Two-dimensional material vertical transistors: such as vertical MoS2 transistors, which achieve sub-1nm gate width, but do not simultaneously solve the sub-1nm scaling problem of channel length, and the fabrication process is complex, making it difficult to achieve wafer-level mass production (Source: Wu, F). et al ., VerticalMoS2transistors with sub-1-nm gate lengths. Nature 603, 259- 264 (2022)).

[0006] 3. Two-dimensional heterojunction transistors: Based on the heterojunction structure of MoS2 and graphene, these transistors are used to improve the electrical performance of devices. However, no integrated structure has been designed that simultaneously satisfies the requirements of sub-1nm gate width and sub-1nm channel length. Furthermore, there is a lack of system-level layout design and mass production process solutions (Source: Liu, Y. et al., Promises and prospects of two-dimensional transistors. Nature 591, 43-53 (2021)).

[0007] 4. Transfer Electrode Transistor: Based on the heterojunction structure of MoS2 and graphene, low-energy van der Waals metal integration technology can be used to fabricate molybdenum disulfide (MoS2) vertical transistors with conductive channel lengths as low as one atomic layer. However, this structure cannot meet the technical requirements of sub-1nm gate width, and there is a lack of system-level layout design for sub-1nm transistors. Two-dimensional materials (such as MoS2) are prone to breakage due to suspension structures during fabrication, affecting device reliability. (Source: Liu, L.) et al ., Transferred van der Waals metal electrodes for sub-1-nmMoS2vertical transistors. Nat Electron 4, 342- 347 (2021). Summary of the Invention

[0008] The purpose of this invention is to address the shortcomings of existing technologies by proposing a heterojunction transistor with sub-nanometer trench length and sub-nanometer gate width, as well as its fabrication method.

[0009] The objective of this invention is achieved through the following technical solution: a heterojunction transistor with sub-nanometer trench length and sub-nanometer gate width, and its fabrication method, comprising: A silicon substrate with an insulating dielectric layer has independent source, drain, and gate terminals, a graphene layer, a two-dimensional material layer, and a gate dielectric layer disposed on the insulating dielectric layer. The source and drain are connected by a vertical heterojunction formed by the two-dimensional material layer and the graphene layer, with the channel length equal to the thickness of the heterojunction. The pattern of the two-dimensional material layer is used to connect the source, and the pattern of the graphene layer is used to connect the drain. The heterojunction has a fracture gap, with one separated end serving as the gate, and the gate width being equal to the thickness of the heterojunction. The gate dielectric layer is located in the fracture gap, and the gate dielectric layer covers the graphene layer, the two-dimensional material layer, and the insulating dielectric layer.

[0010] Furthermore, the graphene layer and the two-dimensional material layer are single-layer structures capable of achieving a heterojunction thickness of sub-1 nm, and the thickness of the two-dimensional material layer is such that it can achieve a heterojunction thickness of sub-1 nm.

[0011] Furthermore, the heterojunction is a PN junction formed by P-type doped graphene and N-type doped two-dimensional materials, or an NP heterojunction is formed by using graphene as N-type doped and other two-dimensional materials as P-type doped, and switching control is achieved by adjusting the Fermi level of graphene through the gate voltage.

[0012] Furthermore, the transistor is a single transistor or a wafer-level transistor unit.

[0013] According to another aspect of the specification, a method for fabricating the transistor is also provided, comprising: A lightly doped N-type silicon substrate is used, a silicon oxide layer is grown on the surface, and source, drain, and gate electrodes are deposited on the substrate. Monolayer graphene is transferred to the metal electrode and the central region of the substrate via a wet process, and patterned into graphene regions corresponding to the drain and gate electrodes. Atomic layer deposition technology is used to deposit a gate dielectric on the graphene surface as a patterning mask, and windows are etched to expose the heterojunction integration area for subsequent processing. The single-layer two-dimensional material is transferred to the graphene region of the mask region, the heterojunction integration region, and the substrate region, and patterned into a heterojunction structure corresponding to the source, drain, and gate. The heterojunction gap is etched to form independent source, drain, and gate terminals; defect compensation is performed, and the gate dielectric layer is deposited again. The gate dielectric on the metal electrode is then etched to expose the metal electrode.

[0014] Furthermore, the defect compensation includes: after etching the heterojunction gap, for the suspension region where the two-dimensional material is prone to breakage, defining the breakage risk location by photolithography, etching the gate dielectric in the region and depositing Cr or Au metal to replace the two-dimensional material to achieve electrical connection, thereby avoiding breakage from affecting device performance.

[0015] Furthermore, in the defect compensation process, after etching the heterojunction gap, for the suspension area of ​​the two-dimensional material that is prone to breakage, the location of the breakage risk is defined by photolithography, and polymer encapsulation is used to replace metal deposition to reinforce the MoS2 suspension area and avoid breakage.

[0016] Furthermore, when fabricating wafer-level transistor units, the metal electrode is selected to deposit Cr / Au metal pads, including gate pads and source / drain pads; when etching the heterojunction gap, the integrated source / drain is placed at one end of the gap and the gate is at the other end of the gap, ensuring that all gate separation is completed in one etching.

[0017] Furthermore, the monolayer graphene and monolayer two-dimensional material are obtained using chemical vapor deposition.

[0018] Furthermore, the etched heterojunction gap is achieved by electron beam lithography to expose the gap region, and by reactive ion etching or inductively coupled plasma etching.

[0019] The beneficial effects of this invention are: 1. Design a novel heterojunction structure to achieve both gate width and channel length at the sub-1nm scale, breaking through the size limitations of existing transistors; 2. Develop a self-aligned integrated fabrication process to simplify the separation steps of the source, drain, and gate, reduce the number of etching operations, and improve fabrication efficiency; 3. The entire system-level transistor fabrication process is compatible with chemical vapor deposition (CVD) low-temperature transfer technology. Furthermore, graphene and molybdenum disulfide have already achieved wafer-level industrial fabrication. This ensures the realization of wafer-level mass production of transistors. 4. Design system-level layout and defect compensation schemes to solve the fracture problem of two-dimensional materials during the fabrication process and improve device reliability; 5. It is expected that the overall structure can be further reduced through advanced photolithography processes, enabling flexible fabrication of P-type and N-type field-effect transistors to meet the needs of integrated circuit systems. Attached Figure Description

[0020] Figure 1 The fabrication process and structure diagram of a single transistor with a sub-1 nanometer channel length and sub-1 nanometer gate width; Figure 2 This is a diagram of the transistor system-level manufacturing process with a sub-1 nanometer channel length and a sub-1 nanometer gate width. Figure 3 Characterization of system-level transistors with sub-1 nanometer channel length and sub-1 nanometer gate width; Figure 4 Raman spectral characterization of MoS2-graphene-SiO2-Si and Raman spectral characterization of MoS2-SiO2-Si; Figure 5 This is a schematic diagram of a sub-1nm transistor multi-view structure based on a MoS2 / graphene heterojunction. Detailed Implementation

[0021] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0022] like Figure 5 As shown, this invention provides a molybdenum disulfide / graphene heterojunction transistor with a sub-nanometer channel length and sub-nanometer gate width. The transistor is a single transistor or a wafer-level transistor unit, comprising: A silicon substrate with an insulating dielectric layer has independent source, drain, and gate terminals, a graphene layer, a two-dimensional material layer, and a gate dielectric layer disposed on the insulating dielectric layer. The source and drain are connected by a vertical heterojunction formed by the two-dimensional material layer and the graphene layer, with the channel length equal to the thickness of the heterojunction. The pattern of the two-dimensional material layer connects to the source, and the pattern of the graphene layer connects to the drain. The heterojunction has a fracture gap, with one separated end serving as the gate, the gate width being equal to the thickness of the heterojunction. A gate dielectric layer is present in the fracture gap, and the gate dielectric layer covers the graphene layer, the two-dimensional material layer, and the insulating dielectric layer. By adjusting the Fermi level of the graphene through the gate voltage, the barrier height of the PN junction is changed, achieving device switching control. If necessary, a bottom silicon gate is used to assist in further optimizing the gate voltage setting range.

[0023] In this embodiment, MoS2 is used as the two-dimensional material layer, but other two-dimensional materials can be used to replace MoS2. The heterojunction thickness is still used as the basis for achieving the sub-1nm gate width / channel length. The graphene layer and the two-dimensional material layer are single-layer structures that can achieve a heterojunction thickness of sub-1 nm. The preferred channel structure is: a vertical PN junction formed by P⁺ type graphene (0.335 nm) / N type MoS2 (0.626 nm) as the device channel, and the channel length is equal to the thickness of the heterojunction (sub-1 nm); the edges of the graphene and MoS2 layers are used as gate electrodes, and the gate width is equal to the thickness of the heterojunction (sub-1 nm).

[0024] In this embodiment, Al2O3 is used as the gate dielectric. Materials with higher dielectric constants, such as HfO2 and ZrO2, can be used to replace Al2O3 as the gate dielectric layer to improve gate control capability. The heterojunction is a PN junction formed by P-type doped graphene and N-type doped two-dimensional materials, or an NP heterojunction formed by using N-type doped graphene and P-type doped other two-dimensional materials, and switching control is achieved by adjusting the Fermi level of graphene through the gate voltage.

[0025] The source and drain of the wafer-level transistor unit are placed at one end of the gap, and the gate is at the other end of the gap, ensuring that all gate separation is completed in one etching.

[0026] like Figure 5 As shown in the attached diagram, this figure clearly illustrates the core structure of the transistor of this invention from three dimensions: top view, bottom view, and perspective view. The following is a detailed explanation. The top view shows the materials and regions of this system-level transistor. The green area represents MoS2, the core semiconductor layer of the transistor. Functional areas are labeled Drain, Source, and Gate, clearly defining the three electrical terminals of the transistor, which respectively realize the functions of current output, input, and regulation. Metal connections are used to connect the electrical signals of the MoS2 and graphene layers to external test / circuit systems, ensuring effective current extraction. The bottom view shows the black area as graphene, another core conductive layer forming a heterojunction with MoS2. The metal pad serves as an interface for external electrical testing or circuit integration, realizing signal input / output. The perspective view shows the three-dimensional structure of the device, combining the MoS2 layer in the top view and the graphene layer in the bottom view to form a MoS2 / graphene heterojunction, which is the core structural foundation for transistors to achieve sub-1nm scale performance. This combination of three perspectives allows for a rapid understanding of the material composition, structural layering, electrical termination layout, and three-dimensional integration method of the transistors in this invention.

[0027] Furthermore, the embodiment also provides a single transistor fabrication process, such as... Figure 1 As shown, it includes: 1. Substrate pretreatment: A 500 μm thick lightly doped N-type silicon (Si) substrate is used, and a 100±5 nm silicon oxide (SiO2) layer is grown on the surface. Cr / Au is deposited on the substrate as the source, drain, and gate metal electrodes. 2. Graphene Transfer and Patterning (with appendix) Figure 1 (a and b in the text): CVD-grown monolayer graphene is transferred to the metal electrode and the central region of the substrate by wet process. After cleaning with PMMA, the graphene is patterned into graphene strips in the drain-gate region by photolithography. 3. Medium layer deposition (with) Figure 1 c): An aluminum oxide (Al2O3) layer is deposited on the graphene surface using atomic layer deposition (ALD) technology as a subsequent patterning mask; 4. Mask window etching (attached) Figure 1 d): A window is prepared on the Al2O3 layer by etching process for subsequent integration of MoS2 / graphene heterostructure and exposure of source pads; 5. MoS2 Transfer and Graphicalization (with appendix) Figure 1 (e and f in the text): The CVD-grown monolayer MoS2 is transferred to the substrate and Al2O3 window region by wet process, and the MoS2 is patterned into a heterojunction structure that matches the graphene by photolithography. 6. Etching of heterojunction gaps (see attached) Figure 1 g): Electron beam lithography (EBL) is used to expose the gap region. Through reactive ion etching (RIE) + O2 plasma etching, a gap of about 100 nanometers is formed in the MoS2 / graphene heterojunction, realizing the synchronous separation of the source, drain and gate. The separated heterojunction serves as the gate. In the figure, the metal electrode first contacts the graphene, and the graphene layer then contacts the MoS2.

[0028] 7. Encapsulation and dielectric layer deposition (attached) Figure 1 h): An Al2O3 layer is deposited again using ALD technology as the dielectric layer for the gate region and the overall device packaging layer; 8. Test pad exposure (see attached) Figure 1 i): Etching the Al2O3 layer on the surface of the metal electrode pads to expose the metal pads for electrical testing; 9. Final Structure (Appendix) Figure 1 In the j) device cross-section, from top to bottom, are Al2O3 dielectric layer, MoS2 layer, Au / Cr metal electrode-graphene layer, SiO2 layer, and Si substrate. The gate width and channel length are determined by the thickness of the MoS2 / graphene heterojunction (sub-1nm).

[0029] Furthermore, the embodiments also provide system-level layout and mass production processes, such as... Figure 2 As shown, it includes: 1. Wafer-level substrate fabrication (with appendix) Figure 2 a): A 500μm thick lightly doped N-type Si substrate (100±5nm SiO2 on the surface) is used. Cr / Au metal pads are deposited on the substrate, with gate pads on the top and bottom and source / drain pads on the left and right. 2. Graphene Integration (with appendix) Figure 2 (b and c in the text): CVD wet transfer of graphene to the metal pads and substrate area, patterned as the graphene regions corresponding to the drain and gate. The drain region is arranged on both sides of the metal, and the gate region is arranged on the top and bottom of the metal; 3. Dielectric layer mask fabrication (see appendix) Figure 2(e and f in the text): ALD deposits Al2O3 as a patterned mask, etches to form Al2O3 windows, and exposes the MoS2 / graphene heterojunction integration region and source metal pads. 4. MoS2 Integration (with appendix) Figure 2 g and h): CVD MoS2 wet transfer to the graphene region, Al2O3 mask region and source pad, patterned into heterojunction structures corresponding to the source, drain and gate; 5. Interval etching and terminal separation (see appendix) Figure 2 i): The heterojunction gap is etched by EBL+RIE to finally form independent source, drain and gate three terminals; inductively coupled plasma (ICP) etching can be used instead of RIE etching, or wet etching can be used to optimize the gap etching steps to maintain the core logic of self-aligned integration. 6. Defect Compensation Process (Appendix) Figure 2 k and l in the image): For the easily fractured suspension region of MoS2, a photolithographic mask (with...) Figure 2 (K in the image represents the pattern after photoresist development) Exposure defines the risky location that is prone to breakage. Al2O3 is etched in this area and Cr / Au metal is deposited to replace MoS2 and achieve electrical connection, thus avoiding breakage that could affect device performance. Polymer encapsulation can be used to replace metal deposition to reinforce the MoS2 suspension area and prevent breakage.

[0030] 7. Wafer-level mass production: Based on CVD technology, graphene and MoS2 growth processes can achieve mass production of 4-inch wafer-level transistor units.

[0031] Appendix Figure 3 Image 'a' in the diagram shows a 3D model of a system-on-a-chip transistor smaller than 1 nanometer, displaying graphene and molybdenum disulfide regions. (See attached image.) Figure 3 Image b shows an optical image of a sub-1 nanometer system-on-a-chip (SoC) at a 4-inch wafer scale. Optical images of key manufacturing processes reveal details of the fabrication process. (Attached) Figure 3 Figure c shows that graphene has been transferred onto a silicon (300 ± 5 nm - silicon dioxide / 500 μm - silicon) substrate. The next step is to pattern the graphene to connect it to the drain, source, and gate electrodes (see attached diagram). Figure 3 (d) Al2O3 deposited via atomic layer deposition (ALD) was used as the pattern for the next step – combined with a mask (attached). Figure 3 (e in the text).

[0032] Then, Al2O3 deposited on the metal pads in the source and intermediate regions of the device is etched to create a pattern mask for the next graphene / molybdenum disulfide bonding pattern. MoS2 obtained by chemical vapor deposition (CVD) has been transferred into the Al2O3 windows (see attached image). Figure 3 f in the figure. The graphene / molybdenum disulfide layer is patterned into a graphene / molybdenum disulfide bond (see attached figure). Figure 3 (g) Molybdenum disulfide stripes in the drain channel are wider than graphene stripes. The source channel contains only molybdenum disulfide stripes. Now, the gate, source, and drain regions are a single component. The notch is fabricated using EBL (electron beam lithography) (see attached). Figure 3 (As shown in h in the image). Reactive ion etching (RIE) and O2 plasma techniques were used to etch the silicon oxide and graphene / molybdenum disulfide stacked structures to create clean gaps. Images of the etched gaps are shown in the image. Figure 3 As shown in i in the diagram. After etching, an Al2O3 layer is deposited in the gap region of the gate region and in the entire device's encapsulation layer by atomic layer deposition (ALD). Figure 3 (j) Patterning of fracture-prone sites in MoS2 for use in subsequent manufacturing processes, including etching and metal deposition (see attached). Figure 3 (k in the original text). To confirm the device structure, representative samples after fabrication were characterized. Raman spectral intensity data at test points 1 and 2 confirmed that the graphene film on silicon oxide and the molybdenum disulfide film on siloxane were both monolayer structures. The graphene / molybdenum disulfide junction has been verified. Figure 4 Raman spectral characterization of MoS2-graphene-SiO2-Si and MoS2-SiO2-Si are shown, with Raman shift and intensity on the horizontal and vertical axes, respectively, which verify monolayer CVD graphene and monolayer CVD MoS2.

[0033] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this application are indicated by the claims.

[0034] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this application. This application is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A heterojunction transistor with a sub-nanometer trench length and a sub-nanometer gate width, characterized in that, include: A silicon substrate with an insulating dielectric layer has independent source, drain, and gate terminals, a graphene layer, a two-dimensional material layer, and a gate dielectric layer disposed on the insulating dielectric layer. The source and drain are connected by a vertical heterojunction formed by the two-dimensional material layer and the graphene layer, with the channel length equal to the thickness of the heterojunction. The pattern of the two-dimensional material layer is used to connect the source, and the pattern of the graphene layer is used to connect the drain. The heterojunction has a fracture gap, with one separated end serving as the gate, and the gate width being equal to the thickness of the heterojunction. The gate dielectric layer is located in the fracture gap, and the gate dielectric layer covers the graphene layer, the two-dimensional material layer, and the insulating dielectric layer.

2. A heterojunction transistor with sub-nanometer trench length and sub-nanometer gate width according to claim 1, characterized in that, The graphene layer and the two-dimensional material layer are single-layer structures that can achieve a heterojunction thickness of sub-1 nm, and the thickness of the two-dimensional material layer is such that it can achieve a heterojunction thickness of sub-1 nm.

3. A heterojunction transistor with sub-nanometer trench length and sub-nanometer gate width according to claim 1, characterized in that, The heterojunction is a PN junction formed by P-type doped graphene and N-type doped two-dimensional materials, or an NP heterojunction formed by using N-type doped graphene and P-type doped other two-dimensional materials, and switching control is achieved by adjusting the Fermi level of graphene through the gate voltage.

4. A heterojunction transistor with sub-nanometer trench length and sub-nanometer gate width according to claim 1, characterized in that, The transistor is a single transistor or a wafer-level transistor unit.

5. A method for fabricating a heterojunction transistor based on the sub-nanometer trench length and sub-nanometer gate width as described in any one of claims 1-4, characterized in that, include: A lightly doped N-type silicon substrate is used, a silicon oxide layer is grown on the surface, and source, drain, and gate electrodes are deposited on the substrate. Monolayer graphene is transferred to the metal electrode and the central region of the substrate via a wet process, and patterned into graphene regions corresponding to the drain and gate electrodes. Atomic layer deposition technology is used to deposit a gate dielectric on the graphene surface as a patterning mask, and windows are etched to expose the heterojunction integration area for subsequent processing. The single-layer two-dimensional material is transferred to the graphene region of the mask region, the heterojunction integration region, and the substrate region, and patterned into a heterojunction structure corresponding to the source, drain, and gate. Etch the gap between heterojunctions to form independent source, drain, and gate terminals; Defect compensation is performed, the gate dielectric layer is deposited again, and the gate dielectric on the metal electrode is etched to expose the metal electrode.

6. The method according to claim 5, characterized in that, The defect compensation includes: after etching the heterojunction gap, for the suspension area where the two-dimensional material is prone to breakage, defining the location of the breakage risk by photolithography, etching the gate dielectric in the area and depositing Cr or Au metal to replace the two-dimensional material to achieve electrical connection, thereby avoiding the impact of breakage on device performance.

7. The method according to claim 5, characterized in that, In the defect compensation process, after etching the heterojunction gap, for the suspension area of ​​the two-dimensional material which is prone to breakage, the location of the breakage risk is defined by photolithography, and polymer encapsulation is used to replace metal deposition to reinforce the MoS2 suspension area and avoid breakage.

8. The method according to claim 5, characterized in that, When fabricating wafer-level transistor units, Cr / Au metal pads are selected for depositing metal electrodes, including gate pads and source / drain pads. When etching the heterojunction gap, the integrated source / drain is placed at one end of the gap, and the gate is at the other end of the gap, ensuring that all gate separation is completed in one etching.

9. The method according to claim 5, characterized in that, The monolayer graphene and monolayer two-dimensional materials were obtained using chemical vapor deposition.

10. The method according to claim 5, characterized in that, The etched heterojunction gap is achieved by electron beam lithography to expose the gap region, and by reactive ion etching or inductively coupled plasma etching.

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