A heterojunction transistor with sub-nanometer channel length and sub-nanometer gate width and a method of fabrication

Abstract

The application discloses a heterojunction transistor with sub-nanometer channel length and sub-nanometer gate width and a preparation method. A PN junction heterojunction is constructed by using a single-layer CVD graphene and a single-layer CVD two-dimensional material. A vertical PN junction with a thickness less than 1 nm is used as a device channel, and the channel length is equal to the thickness of the heterojunction. A gate structure uses the edges of the graphene and the two-dimensional material layer as gate electrodes, and the gate width is equal to the thickness of the heterojunction, reaching sub-1 nm. The source electrode, the drain electrode and the gate electrode are separated into three independent terminals through gap etching. The Fermi energy level of the graphene is adjusted by the gate voltage, the barrier height of the PN junction is changed, and the switching control of the device is realized. The bottom silicon gate can also assist in the regulation to further optimize the setting range of the gate voltage. The application solves the problems of the short channel effect and the gate control of the silicon-based device, simplifies the preparation process, realizes wafer-level mass production, and meets the development needs of the ultra-miniaturization of integrated circuits.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, and in particular to a heterojunction transistor with sub-nanometer channel length and sub-nanometer gate width and a method of fabrication. BACKGROUND

[0002] Since the first integrated circuit was introduced in the 1960s, silicon (Si) transistors have been continuously scaled down under the guidance of Moore’s law. In addition to the early bipolar junction transistors (BJTs), field effect transistors (FETs) are the core logic devices for silicon-based integrated circuits. The device structure has gone through planar metal-oxide-semiconductor field-effect transistors (MOSFETs), fin field-effect transistors (FINFETs), and gate-all-around field-effect transistors (GAAFETs) in sequence. However, when the transistor process is below 5 nanometers, the silicon transistor has approached the scaling limit. As the integrated circuit process enters the sub-nanometer scale, the traditional silicon-based transistor faces problems such as weakened gate control ability and increased short channel effect. It is essential to explore new structures to further reduce the gate width and channel length.

[0003] Two-dimensional materials (such as molybdenum disulfide and graphene) exhibit excellent electrostatic control ability due to their atomic thickness and lack of dangling bonds, and are considered as potential candidate materials to break the size limit of silicon-based devices. Low-dimensional transistors achieve stronger gate control ability through atomic channel thickness and are not affected by short channel effects, providing the possibility for further miniaturization of device size. However, it is very difficult to further reduce the gate width or channel length to below 1 nanometer in the three typical transistor structures. Ultra-size transistor structure design has always been a core research topic in the field of microelectronics. Transistor structures with sub-1 nanometer gate width and new vertical field effect transistor structures have made breakthroughs in gate width and channel length. However, due to the limitation of atomic size, transistor structures with gate width and channel length below sub-nanometer may be the limit of transistor process. This may also be the final development direction of traditional silicon-based transistors or two-dimensional transistors.

[0004] 1. Silicon-based ultra-scaling transistors: such as gate-all-around field-effect transistors (GAAFETs), which improve the control ability of the channel through a three-dimensional gate structure, but are limited by the physical properties of silicon material. When the process enters the sub-nanometer scale, the short channel effect cannot be effectively suppressed, and the gate control ability significantly decays (Chau, R. et al. Integrated nanoelectronics for the future. Nat. Mater. 6, 810-812 (2007)). et al

[0005] ​2. Two-dimensional material vertical transistor: such as vertical MoS2 transistor, realizing sub-1nm gate width, but not solving the problem of sub-1nm scaling of channel length at the same time, and the preparation process is complex, which is difficult to realize wafer-level mass production (Wu, F. et al ., Vertical MoS2 transistors with sub-1-nm gate lengths. Nature 603, 259- 264 (2022) ).

[0006] 3. Two-dimensional material heterojunction transistor: based on the heterojunction structure of MoS2 and graphene, used to improve the electrical performance of the device, but the integrated structure that meets the sub-1nm gate width and sub-1nm channel length at the same time has not been designed, and there is a lack of system-level layout design and mass production process scheme (Liu, Y. et al., Promises and prospects of two-dimensional transistors. Nature 591, 43- 53 (2021) ).

[0007] 4. Transferred electrode type transistor: based on the heterojunction structure of MoS2 and graphene, using low-energy van der Waals metal integration technology to manufacture a molybdenum disulfide (MoS2) vertical transistor with a conductive channel length as low as one atomic layer, but this structure cannot meet the technical requirements of sub-1nm gate width, and lacks a system-level layout design for sub-1nm transistors. Two-dimensional materials such as MoS2 are prone to breakage due to suspended structures during preparation, affecting the reliability of the device. (Liu, L. et al ., Transferred van der Waals metal electrodes for sub-1-nmMoS2vertical transistors. Nat Electron 4, 342- 347 (2021). SUMMARY

[0008] The present application aims to solve the problems of the prior art and provide a heterojunction transistor with sub-nanometer channel length and sub-nanometer gate width and a preparation method.

[0009] The purpose of the present application is achieved by the following technical scheme: a heterojunction transistor with sub-nanometer channel length and sub-nanometer gate width and a preparation method, comprising:

[0010] A silicon substrate provided with an insulating medium layer, the insulating medium layer being provided with independent source, drain and gate three terminals, a graphene layer, a two-dimensional material layer and a gate medium layer, wherein the vertical heterojunction formed by the two-dimensional material layer and the graphene layer between the source and the drain serves as a channel, the channel length is equal to the thickness of the heterojunction, the pattern of the two-dimensional material layer is used to connect the source, and the pattern of the graphene layer is used to connect the drain; the heterojunction is provided with a broken gap, one end separated therefrom serving as a gate, and the gate width is the thickness of the heterojunction; the gate medium is in the broken gap, and the gate medium layer covers the graphene layer, the two-dimensional material layer and the insulating medium layer.

[0011] Further, the graphene layer and the two-dimensional material layer are single-layer structures capable of realizing a heterojunction thickness of sub-1 nm, and the thickness of the two-dimensional material layer is capable of realizing a heterojunction thickness of sub-1 nm.

[0012] Further, the heterojunction is a PN junction formed by P-doped graphene and N-doped two-dimensional material, or an N-P heterojunction formed by N-doped graphene and P-doped two-dimensional material, and the graphene Fermi level is adjusted by the gate voltage to realize switch control.

[0013] Further, the transistor is a single transistor or a wafer-level transistor unit.

[0014] According to another aspect of the specification, a preparation method of the transistor is also provided, comprising:

[0015] A lightly doped N-type silicon substrate is used, a silicon oxide layer is grown on the surface, and electrodes of the source, the drain and the gate are deposited on the substrate;

[0016] The single-layer graphene is transferred to the metal electrode and the central region of the substrate by a wet transfer method, and is patterned into graphene regions corresponding to the drain and the gate;

[0017] The gate medium is deposited on the graphene surface by an atomic layer deposition technique as a patterned mask, and a window is etched to expose the integrated region of the heterojunction for subsequent processing;

[0018] The single-layer two-dimensional material is transferred to the mask region, the graphene region of the integrated region of the heterojunction and the substrate region, and is patterned into a heterojunction structure corresponding to the source, the drain and the gate;

[0019] The heterojunction gap is etched to form independent source, drain and gate three terminals; defect compensation is performed, the gate medium layer is deposited again, and the gate medium on the metal electrode is etched to expose the metal electrode.

[0020] Further, the defect compensation includes: after etching the heterojunction gap, for the suspended area of the two-dimensional material prone to breakage, defining the breakage risk position through photolithography, etching the gate dielectric of the area and depositing Cr or Au metal, replacing the two-dimensional material to realize electrical connection and avoid the breakage affecting the device performance.

[0021] Further, in the defect compensation, after etching the heterojunction gap, for the suspended area of the two-dimensional material prone to breakage, the breakage risk position is defined through photolithography, and a polymer encapsulation is used instead of metal deposition to reinforce the MoS2 suspended area and avoid breakage.

[0022] Further, when preparing the wafer-level transistor unit, the deposition of the metal electrode selects to deposit Cr / Au metal pads, including gate pads and source / drain pads; when etching the heterojunction gap, the integrated source / drain is placed at one end of the gap, and the gate is placed at the other end of the gap, so that all the gate separation is completed at one time.

[0023] Further, the single-layer graphene and the single-layer two-dimensional material are obtained by using a chemical vapor deposition method.

[0024] Further, the etching of the heterojunction gap adopts electron beam lithography to expose the gap area, and the gap etching is completed by reactive ion etching or inductively coupled plasma etching.

[0025] The beneficial effects of the present application are as follows:

[0026] 1. A new heterojunction structure is designed to realize that the gate width and the channel length simultaneously reach sub-1nm size, and the size limitation of the existing transistor is broken through;

[0027] 2. A self-aligned integrated preparation process is developed to simplify the separation steps of the source, the drain and the gate, reduce the etching times and improve the preparation efficiency;

[0028] 3. The whole system-level transistor preparation process is compatible with the chemical vapor deposition (CVD) low-temperature transfer technology, and the graphene and the molybdenum disulfide have realized wafer-level industrial preparation, which ensures the realization of wafer-level mass production of the transistor;

[0029] 4. A system-level layout and defect compensation scheme is designed to solve the breakage problem of the two-dimensional material in the preparation process and improve the device reliability;

[0030] 5. It is expected to further reduce the overall structure through an advanced photolithography process, realize the flexible preparation of P-type and N-type field effect transistors, and adapt to the demand of integrated circuit systems. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 The manufacturing process and structure diagram of a single transistor with sub-1nm channel length and sub-1nm gate width;

[0032] Figure 2 System level fabrication process chart for sub-1nm channel length and sub-1nm gate width transistor;

[0033] Figure 3 System level transistor characterization for sub-1nm channel length and sub-1nm gate width;

[0034] Figure 4 Raman spectrum characterization chart for MoS2-graphene-SiO2-Si and MoS2-SiO2-Si;

[0035] Figure 5 Sub-1nm transistor multi-view structure schematic diagram based on MoS2 / graphene heterojunction. DETAILED DESCRIPTION

[0036] The specific embodiments of the present application are further described in detail below with reference to the accompanying drawings.

[0037] As shown in the drawings, Figure 5 The present application provides a sub-nanometer channel length & sub-nanometer gate width molybdenum disulfide / graphene heterojunction transistor. The transistor is a single transistor or a wafer level transistor unit, comprising:

[0038] A silicon substrate provided with an insulating medium layer, the insulating medium layer is provided with independent source, drain and gate three terminals, a graphene layer, a two-dimensional material layer and a gate dielectric layer, wherein the vertical heterojunction formed by the two-dimensional material layer and the graphene layer between the source and the drain serves as a channel, the channel length is equal to the thickness of the heterojunction, the pattern of the two-dimensional material layer is used to connect the source, and the pattern of the graphene layer is used to connect the drain; the heterojunction is provided with a broken gap, one end separated as a gate, and the gate width is the thickness of the heterojunction; there is a gate dielectric in the broken gap, and the gate dielectric layer covers the graphene layer, the two-dimensional material layer and the insulating medium layer. The Fermi level of graphene is adjusted by gate voltage to change the barrier height of PN junction, and the switching control of the device is realized. If necessary, the bottom silicon gate is used to assist in regulation to further optimize the setting range of the gate voltage.

[0039] In this embodiment, MoS2 is used as the two-dimensional material layer, but other two-dimensional materials can also be used instead of MoS2, and the thickness of the heterojunction is still used as the basis for realizing sub-1nm gate width / channel length

[0040] The graphene layer and the two-dimensional material layer are single-layer structures capable of realizing a heterojunction thickness of sub-1 nm, and the channel structure is preferably a vertical PN junction of P+ type graphene (0.335 nm) / N type MoS2 (0.626 nm) formed as a device channel, and the channel length is equal to the thickness (sub-1 nm) of the heterojunction; the edges of the graphene and MoS2 layers are used as gate electrodes, and the gate width is equal to the thickness (sub-1 nm) of the heterojunction.

[0041] In the embodiment, Al2O3 is used as the gate dielectric, and materials with higher dielectric constants such as HfO2 and ZrO2 can be used to replace Al2O3 as the gate dielectric layer to improve the gate control ability.

[0042] The heterojunction is a PN junction formed by P type doped graphene and N type doped two-dimensional material, or N-P heterojunction is formed by N type doped graphene and P type doped other two-dimensional material, and switch control is realized by adjusting the Fermi level of graphene through gate voltage.

[0043] The source and drain of the wafer-level transistor unit integration are placed at one end of the gap, and the gate is at the other end of the gap, so as to ensure that all the gates are separated by one-time etching.

[0044] For example, the graphene layer and the two-dimensional material layer are single-layer structures capable of realizing a heterojunction thickness of sub-1 nm, and the channel structure is preferably a vertical PN junction of P+ type graphene (0.335 nm) / N type MoS2 (0.626 nm) formed as a device channel, and the channel length is equal to the thickness (sub-1 nm) of the heterojunction; the edges of the graphene and MoS2 layers are used as gate electrodes, and the gate width is equal to the thickness (sub-1 nm) of the heterojunction. Figure 5As shown, the figure clearly shows the core structure of the transistor of the present application through three dimensions of Top View, Bottom View and Perspective View, which are explained in detail as follows. The Top View shows the materials and regions of the system-level transistor. The green region is MoS2, which is the core semiconductor layer of the transistor. The functional regions are labeled as Drain (drain), Source (source) and Gate (gate) to clearly indicate the three electrical terminals of the transistor, which respectively realize the functions of current output, input and control. The Metal connection (metal connection structure) is used to connect the electrical signals of the MoS2 layer and the graphene layer with the external test / circuit to ensure the effective extraction of the current. The Bottom View shows that the black region is graphene, which is another core conductive layer forming a heterojunction with MoS2. The Metal Pad (metal pad) shows the interface for external electrical testing or circuit integration to realize signal input / output. The Perspective View shows the three-dimensional structure of the device, which combines the MoS2 layer of the Top View and the graphene layer of the Bottom View to form a MoS2 / graphene heterojunction, which is the core structural basis for the transistor to realize sub-1nm scale performance. Through the combination of the three perspectives, the material composition, structural layering, electrical terminal layout and three-dimensional integration method of the transistor of the present application can be quickly understood.

[0045] In addition, a single transistor preparation process is also given in the embodiment, as shown in Figure 1 , which includes:

[0046] 1. Substrate pretreatment: a lightly doped N-type silicon (Si) substrate with a thickness of 500 μm is used, a 100±5 nm silicon oxide (SiO2) layer is grown on the surface, and Cr / Au is deposited on the substrate as the metal electrode of the source, drain and gate;

[0047] 2. Graphene transfer and patterning (a and b in Figure 1 ): single-layer graphene grown by CVD is transferred to the metal electrode and the center region of the substrate by wet transfer, after cleaning with PMMA, the graphene is patterned into a graphene strip in the drain-gate region by a photolithography process;

[0048] 3. Dielectric layer deposition (c in Figure 1 ): an aluminum oxide (Al2O3) layer is deposited on the surface of the graphene by atomic layer deposition (ALD) technology, which is used as a subsequent patterning mask;

[0049] 4. Mask window etching (d in Figure 1d): A window is prepared on the Al2O3 layer by etching process for subsequent integration of MoS2 / graphene heterostructure and exposure of source pads;

[0050] 5. MoS2 Transfer and Graphicalization (with appendix) Figure 1 (e and f in the text): The CVD-grown monolayer MoS2 is transferred to the substrate and Al2O3 window region by wet process, and the MoS2 is patterned into a heterojunction structure that matches the graphene by photolithography.

[0051] 6. Etching of heterojunction gaps (see attached) Figure 1 g): Electron beam lithography (EBL) is used to expose the gap region. Through reactive ion etching (RIE) + O2 plasma etching, a gap of about 100 nanometers is formed in the MoS2 / graphene heterojunction, realizing the synchronous separation of the source, drain and gate. The separated heterojunction serves as the gate. In the figure, the metal electrode first contacts the graphene, and the graphene layer then contacts the MoS2.

[0052] 7. Encapsulation and dielectric layer deposition (attached) Figure 1 h): An Al2O3 layer is deposited again using ALD technology as the dielectric layer for the gate region and the overall device packaging layer;

[0053] 8. Test pad exposure (see attached) Figure 1 i): Etching the Al2O3 layer on the surface of the metal electrode pads to expose the metal pads for electrical testing;

[0054] 9. Final Structure (Appendix) Figure 1 In the j) device cross-section, from top to bottom, are Al2O3 dielectric layer, MoS2 layer, Au / Cr metal electrode-graphene layer, SiO2 layer, and Si substrate. The gate width and channel length are determined by the thickness of the MoS2 / graphene heterojunction (sub-1nm).

[0055] Furthermore, the embodiments also provide system-level layout and mass production processes, such as... Figure 2 As shown, it includes:

[0056] 1. Wafer-level substrate fabrication (with appendix) Figure 2 a): A 500μm thick lightly doped N-type Si substrate (100±5nm SiO2 on the surface) is used. Cr / Au metal pads are deposited on the substrate, with gate pads on the top and bottom and source / drain pads on the left and right.

[0057] 2. Graphene Integration (with appendix) Figure 2 (b and c in the text): CVD wet transfer of graphene to the metal pads and substrate area, patterned as the graphene regions corresponding to the drain and gate. The drain region is arranged on both sides of the metal, and the gate region is arranged on the top and bottom of the metal;

[0058] 3. Media layer mask preparation (attached Figure 2 e and f in the figure): ALD deposition of Al2O3 as a patterning mask, etching to form Al2O3 windows, exposing MoS2 / graphene heterojunction integration area and source metal pad;

[0059] 4. MoS2 integration (attached Figure 2 g and h in the figure): CVD MoS2 wet transfer to graphene area, Al2O3 mask area, and source pad, patterning into heterojunction structure corresponding to source, drain, and gate;

[0060] 5. Gap etching and terminal separation (attached Figure 2 i in the figure): etching of heterojunction gap by EBL+RIE, finally forming independent source, drain, and gate terminals; ICP etching can be used instead of RIE etching, or wet etching can be used to optimize the gap etching step, maintaining the core logic of self-aligned integration;

[0061] 6. Defect compensation process (attached Figure 2 k and l in the figure): for the suspended area of MoS2 prone to breakage, define the risk position prone to breakage by exposing the photolithography mask (attached Figure 2 K is the pattern after the development of the photoresist) and etch the Al2O3 in this area and deposit Cr / Au metal to replace MoS2 for electrical connection, avoiding the impact of breakage on device performance; polymer encapsulation can be used instead of metal deposition to reinforce the suspended area of MoS2 and avoid breakage.

[0062] 7. Wafer-level mass production: graphene and MoS2 growth process based on CVD technology can realize batch production of 4-inch wafer-level transistor units.

[0063] Figure 1 Figure 3 a shows a three-dimensional model of a system-level transistor below 1 nanometer, with graphene area and molybdenum disulfide area shown. Figure 1 Figure 3 b shows an optical image of a 4-inch wafer-scale system-level transistor unit below 1 nanometer. The optical image of the key manufacturing process shows the details of the manufacturing process. Figure 1 Figure 3 c shows that graphene has been transferred to a silicon (300 ±5 nm - silicon dioxide / 500 μm - silicon) substrate. The next step is to pattern the graphene to connect with the drain, source, and gate (Figure 1 Figure 3 d). Al2O3 deposited by atomic layer deposition (ALD) is used as the next step of pattern-combination mask (Figure 1 Figure 3 e).

[0064] Then, the Al2O3 deposited on the metal pad in the source and the middle region of the device is etched to make a pattern mask for the next graphene / molybdenum disulfide junction pattern. The MoS2 obtained by chemical vapor deposition (CVD) is transferred into the Al2O3 window (Figure 6f). The graphene layer / molybdenum disulfide layer is patterned into graphene / molybdenum disulfide junction (Figure 6g). The molybdenum disulfide stripe in the drain channel is wider than the graphene stripe. The source channel has only molybdenum disulfide stripe. Now, the gate region, the source region, and the drain region are one component. The notch is made by EBL (electron beam lithography) (Figure 6h). The silicon oxide and the graphene / molybdenum disulfide stack are etched by reactive ion etching (RIE) and O2 plasma to form a clean gap. The image of the gap after etching is shown in Figure 6i. After the etching is completed, an Al2O3 layer is deposited by atomic layer deposition (ALD) in the gap region of the gate region and the encapsulation layer of the whole device (Figure 6j). The easy break location of the MoS2 is patterned for the next fabrication process, including etching and metal deposition (Figure 6k). To confirm the device structure, the representative sample after fabrication is characterized. The Raman spectrum intensity data at test point 1 and test point 2 confirm that the graphene film on the silicon oxide is a single layer structure, and the molybdenum disulfide film on the siloxane is also a single layer structure. The graphene / molybdenum disulfide junction has been verified: Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 4 ​

[0065] Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the application being indicated by the following claims.

[0066] It is understood that the general description above and the detailed description of the specifics below are only exemplary and explanatory and are not restrictive of the application. The application is not limited to the precise construction which has been described above and illustrated in the accompanying drawings, and various modifications and changes can be made by those skilled in the art without departing from the scope of the application. The scope of the application is indicated only by the appended claims.​​​​​​​

Claims

1. A heterojunction transistor with sub-nanometer channel length and sub- nanometer gate width, characterized in that, include: A silicon substrate with an insulating dielectric layer has independent source, drain, and gate terminals, a graphene layer, a two-dimensional material layer, and a gate dielectric layer disposed on the insulating dielectric layer. The source and drain are connected by a vertical heterojunction formed by the two-dimensional material layer and the graphene layer, with the channel length equal to the thickness of the heterojunction. The pattern of the two-dimensional material layer is used to connect the source, and the pattern of the graphene layer is used to connect the drain. The heterojunction has a fracture gap, with one separated end serving as the gate, and the gate width being equal to the thickness of the heterojunction. The gate dielectric layer is located in the fracture gap, and the gate dielectric layer covers the graphene layer, the two-dimensional material layer, and the insulating dielectric layer.

2. The sub-nanoscale channel length and sub-nanoscale gate width heterojunction transistor of claim 1, wherein, The graphene layer and the two-dimensional material layer are single-layer structures that can achieve a heterojunction thickness of sub-1 nm, and the thickness of the two-dimensional material layer is such that it can achieve a heterojunction thickness of sub-1 nm.

3. A heterojunction transistor with sub-nanometer trench length and sub-nanometer gate width according to claim 1, characterized in that, The heterojunction is a PN junction formed by P-type doped graphene and N-type doped two-dimensional materials, or an NP heterojunction formed by using N-type doped graphene and P-type doped other two-dimensional materials, and switching control is achieved by adjusting the Fermi level of graphene through the gate voltage.

4. A heterojunction transistor with sub-nanometer trench length and sub-nanometer gate width according to claim 1, characterized in that, The transistor is a single transistor or a wafer-level transistor unit.

5. A method for fabricating a heterojunction transistor based on the sub-nanometer trench length and sub-nanometer gate width as described in any one of claims 1-4, characterized in that, include: A lightly doped N-type silicon substrate is used, a silicon oxide layer is grown on the surface, and source, drain, and gate electrodes are deposited on the substrate. Monolayer graphene is transferred to the metal electrode and the central region of the substrate via a wet process, and patterned into graphene regions corresponding to the drain and gate electrodes. Atomic layer deposition technology is used to deposit a gate dielectric on the graphene surface as a patterning mask, and windows are etched to expose the heterojunction integration area for subsequent processing. The single-layer two-dimensional material is transferred to the graphene region of the mask region, the heterojunction integration region, and the substrate region, and patterned into a heterojunction structure corresponding to the source, drain, and gate. Etch the gap between heterojunctions to form independent source, drain, and gate terminals; Defect compensation is performed, the gate dielectric layer is deposited again, and the gate dielectric on the metal electrode is etched to expose the metal electrode.

6. The method according to claim 5, characterized in that, The defect compensation includes: after etching the heterojunction gap, for the suspension area where the two-dimensional material is prone to breakage, defining the location of the breakage risk by photolithography, etching the gate dielectric in the area and depositing Cr or Au metal to replace the two-dimensional material to achieve electrical connection, thereby avoiding the impact of breakage on device performance.

7. The method according to claim 5, characterized in that, In the defect compensation process, after etching the heterojunction gap, for the suspension area of ​​the two-dimensional material which is prone to breakage, the location of the breakage risk is defined by photolithography, and polymer encapsulation is used to replace metal deposition to reinforce the MoS2 suspension area and avoid breakage.

8. The method according to claim 5, characterized in that, When fabricating wafer-level transistor units, Cr / Au metal pads are selected for depositing metal electrodes, including gate pads and source / drain pads. When etching the heterojunction gap, the integrated source / drain is placed at one end of the gap, and the gate is at the other end of the gap, ensuring that all gate separation is completed in one etching.

9. The method according to claim 5, characterized in that, The monolayer graphene and monolayer two-dimensional materials were obtained using chemical vapor deposition.

10. The method according to claim 5, characterized in that, The etched heterojunction gap is achieved by electron beam lithography to expose the gap region, and by reactive ion etching or inductively coupled plasma etching.

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