Van der Waals ferroelectric heterojunction device for in-induction calculation, and preparation method and application of Van der Waals ferroelectric heterojunction device

Abstract

The invention relates to a Van der Waals ferroelectric heterojunction device for in-inductance calculation and a preparation method and application thereof. The device comprises a grid-controlled substrate, a two-dimensional metal / semi-metal layer, a two-dimensional ferroelectric insulation ferroelectric layer, a two-dimensional transition metal chalcogenide semiconductor compound semiconductor layer, a source electrode and a drain electrode, wherein an adjustable Schottky barrier is formed in an overlapping region of the ferroelectric layer and the semiconductor layer, and a top gate dielectric layer and a top gate can be further overlapped to enhance the regulation and control capability. According to the structure, carrier injection and transportation can be regulated and controlled through ferroelectric polarization, and nonlinear electrical response and fusion processing and feature extraction of multi-mode optical / acoustic signals are achieved. Compared with the prior art, the device prepared in the invention has the functions of low power consumption, multi-modal perception and intra-sensory calculation, also has reconfigurable logic operation and parallel information processing capabilities, can be used as a multifunctional image processing unit, and has wide application prospects in intelligent edge calculation and neuromorphic systems.

Description

Technical Field

[0001] This invention relates to the fields of semiconductor devices and neuromorphic computing technology, and in particular to a van der Waals ferroelectric heterojunction for inductive computing, its fabrication method, and its application. Background Technology

[0002] In-sensor computing is a novel computing paradigm proposed in recent years. By directly performing information preprocessing and computation at the sensor layer, it avoids the frequent data transfer problems between sensing, storage, and computation in traditional architectures, thus showing great potential in overcoming the "von Neumann bottleneck" and reducing energy consumption. Multimodal fusion-based in-sensor computing devices can perform parallel processing and feature extraction of information from different physical channels (such as optical signals and acoustic signals) at the hardware level, making them ideal candidate platforms for future intelligent sensing and neuromorphic computing.

[0003] However, traditional silicon-based semiconductor devices face numerous limitations in realizing inductive computing. On the one hand, the carrier transport characteristics of silicon are difficult to control, and devices typically rely on complex circuit architectures to achieve multimodal responses, which is detrimental to reducing power consumption and improving integration. On the other hand, silicon-based devices have an inherent weakness in sensing external signals, making it difficult to achieve efficient fusion of multi-physical field signals such as light and sound. Two-dimensional layered materials, with their atomically thin geometry, tunable band structure, and strong light-matter interactions, have become ideal material systems for overcoming these bottlenecks. In particular, two-dimensional heterojunctions formed through van der Waals stacking are not limited by the lattice matching of traditional material systems. They can introduce conductive, ferroelectric, and semiconductor layers within the same device, achieving tunability of the Schottky barrier at the interface. This endows the device with nonlinear electrical response and rich synaptic plasticity, making it an ideal candidate material system for constructing a new generation of reconfigurable inductive computing circuits.

[0004] Such existing technologies still have obvious limitations. CN110808309A is mainly for the detection optimization of a single physical signal (polarized light). Its device structure and working mechanism focus on the linear enhancement of photoelectric conversion, and do not involve the fusion processing of multi-mode signals (such as light / sound) or inductive computing functions.

[0005] In recent years, two-dimensional ferroelectric materials have become an important candidate material system for next-generation programmable devices and synaptic-like devices due to their stable ferroelectric polarization at room temperature and the ability to control the polarization direction through an applied bias voltage. Ferroelectric layers can achieve non-volatile control of current response and multi-timescale synaptic plasticity by manipulating the interface barrier and carrier injection, which helps devices perform complex signal fusion and learning functions. However, the application of ferroelectric two-dimensional materials in inductive computing heterojunction devices still faces the following problems: First, the coupling mechanism between ferroelectric polarization and carrier transport in the semiconductor layer is not yet perfect, resulting in insufficient response consistency and stability of the devices; second, in multi-modal signal processing scenarios, there is a lack of integrated schemes that simultaneously utilize ferroelectric control and semiconductor optoelectronic properties. Summary of the Invention

[0006] The purpose of this invention is to overcome, on the one hand, the problems of low energy efficiency and poor controllability of existing silicon-based semiconductor devices in the integration of optoelectronic and acousto-optic multimodal technologies, and on the other hand, to solve the problems of single function and lack of inductive computing capability of existing two-dimensional devices, and to provide a van der Waals ferroelectric heterojunction device for inductive computing, its preparation method and application.

[0007] The objective of this invention can be achieved through the following technical solutions: The first aspect of this invention provides a van der Waals ferroelectric heterojunction device for inductive computing, comprising: Gate-controlled substrate; A two-dimensional metal / semi-metal layer disposed on the substrate; A two-dimensional ferroelectric insulating layer disposed on the two-dimensional metal / semi-metal layer; A two-dimensional transition metal chalcogenide semiconductor is disposed on the two-dimensional ferroelectric insulating layer; The source and drain are located on the upper surface of the two-dimensional transition metal chalcogenide semiconductor; The overlapping region between the two-dimensional ferroelectric insulating layer and the two-dimensional transition metal chalcogenide semiconductor forms an tunable Schottky barrier.

[0008] Furthermore, the gate-controlled substrate includes a substrate body and a dielectric layer disposed on the surface of the substrate body; The substrate is primarily composed of highly doped silicon. The dielectric layer is selected from one of silicon dioxide, silicon nitride, aluminum oxide, and hafnium oxide; The two-dimensional metal / semi-metal layer is selected from any one of two-dimensional Dirac metals or semi-metals, including graphene, palladium ditelluride, and zirconium ditelluride.

[0009] Furthermore, the two-dimensional ferroelectric insulating layer is selected from any one of CuInP2S6, CuInP2Se6, CuCrP2S6, and CuCrP2Se6, and the two-dimensional ferroelectric insulating layer has a band gap of >2.6 eV, and the internal ferroelectric polarization direction is easily modulated by an external electric field.

[0010] Furthermore, the two-dimensional transition metal chalcogenide semiconductor is selected from any one of molybdenum disulfide, tungsten disulfide, molybdenum diselenide, tungsten diselenide, and molybdenum distelluride; The source and / or drain metal materials are selected from one or more of cadmium, silver, copper, aluminum, gold, nickel, tungsten, ruthenium, iridium, platinum, and palladium.

[0011] Furthermore, the ferroelectric polarization direction of the two-dimensional ferroelectric insulating layer can be controlled by an external electric field, and its polarization charge forms a built-in electric field at the interface, dynamically adjusting the height of the Schottky barrier between the two-dimensional transition metal chalcogenide semiconductor and the two-dimensional metal / semi-metal layer. When optical or ultrasonic signals act on the device, the ferroelectric polarization direction and the signal polarity work together to achieve multimodal fusion and feature extraction through the following nonlinear process: Optical signals excite the semiconductor layer to generate charge carriers, and ferropolarization accelerates the separation of charge carriers through the built-in electric field, thereby regulating the injection efficiency. Ultrasonic signals modulate ferroelectric polarization intensity through the piezoelectric effect, changing the potential energy distribution of the barrier and realizing dynamic reconstruction of carrier transport paths; The non-volatile polarization reversal of ferroelectric polarization forms a positive feedback with the signal polarity, thereby enabling the weighted summation of optical / acoustic signals, extraction of spatiotemporal correlation, and updating of synaptic weights in a single structure.

[0012] A second aspect of the present invention provides the fabrication of a van der Waals ferroelectric heterojunction device for inductive calculations as described above, comprising the following steps: S1. A two-dimensional metal / semi-metal layer is prepared on the surface of the gate-controlled substrate. Then, the metal / semi-metal channel region is defined by a mask layer, and the material in the non-channel region is etched away. S2. A two-dimensional ferroelectric insulating layer is coated onto the surface of a two-dimensional metal / semi-metal layer using a polymer transfer process; S3. Using a polymer transfer process, a two-dimensional transition metal chalcogenide semiconductor is coated onto the surface of the ferroelectric layer 3001, so that the two-dimensional transition metal chalcogenide semiconductor partially overlaps with the metal / semi-metal layer in the vertical direction. The semiconductor channel region is defined by a mask layer and the non-overlapping part is etched away. S4. Define the source and drain electrode regions on the semiconductor layer using a mask layer, deposit metal electrodes and strip away excess material to form source and drain electrodes.

[0013] Furthermore, in S1, the method for preparing the two-dimensional metal / semi-metal layer is selected from one of mechanical exfoliation, chemical vapor deposition, physical vapor deposition, molecular beam epitaxy, and atomic layer deposition; In S2, the two-dimensional ferroelectric insulating layer is prepared by mechanical peeling.

[0014] Furthermore, in S2 and S3, the polymer transfer process is a polymer-assisted dry transfer or wet transfer, and the polymer is selected from one of polydimethylsiloxane, polymethyl methacrylate, polypropylene carbonate, and polyvinyl alcohol. In S3, the preparation method of the two-dimensional transition metal chalcogenide semiconductor is selected from any one of mechanical exfoliation, chemical vapor deposition, physical vapor deposition, molecular beam epitaxy, and atomic layer deposition.

[0015] Furthermore, in S1 and S3, the etching process used is one of inductively coupled plasma etching, reactive ion etching, and ion sputtering etching. In S4, the specific process of depositing metal electrodes and stripping away excess material includes: after patterning with photoresist or a mask, depositing metal using one of the following methods: thermal evaporation, electron beam evaporation, or magnetron sputtering, and then stripping away uncovered areas using organic solvents.

[0016] A third aspect of the present invention provides an application of the van der Waals ferroelectric heterojunction device for inductive computing as described above, wherein the van der Waals ferroelectric heterojunction device is used for multimodal optical / acoustic signal fusion processing, nonlinear electrical response, low-power image processing, reconfigurable logic operations, and pulse sequence-based feature extraction in neuromorphic computing.

[0017] The core technical principle of this invention lies in the synergistic effect of a vertically integrated two-dimensional metal / semi-metal layer, a two-dimensional ferroelectric insulating layer, and a two-dimensional transition metal chalcogenide semiconductor layer. By utilizing the dynamic response characteristics of the ferroelectric polarization direction to an external electric field, the Schottky barrier height at the interface between the ferroelectric and semiconductor layers can be controlled. Under the influence of an applied bias voltage or optical / acoustic signals, the built-in electric field generated by the ferroelectric polarization can non-volatilely alter the carrier injection efficiency and transport path, achieving nonlinear enhancement of the device's current response and fusion processing of multi-modal signals (optical / acoustic). Through the programmability of ferroelectric polarization, the device can complete signal sensing, feature extraction, and synaptic plasticity simulation within a single structure, thereby realizing inductive computing under low power consumption conditions.

[0018] Compared with the prior art, the present invention has the following beneficial effects: (1) By introducing a ferroelectric layer into a two-dimensional heterojunction, the ability to control the Schottky barrier at the interface is effectively enhanced, thereby achieving nonlinear enhancement and reconfigurability of the current response.

[0019] (2) The device of the present invention can not only sense and integrate multimodal inputs such as optical and acoustic, but also directly perform in-sensory computing functions such as feature extraction and signal classification at the hardware level, reducing the need for external processing circuits.

[0020] (3) The device of this invention has advantages such as low power consumption, scalability, and strong environmental adaptability, and can be widely used in intelligent edge computing, 3D depth perception, image processing, and neuromorphic computing systems. The device of this invention exhibits unique advantages in depth perception applications. The unique multimodal capability of the device of this invention enables the device to simultaneously extract the spatial distance and multimodal features of the target object at the hardware level, thereby achieving high-precision, low-power 3D depth perception. Compared with traditional sensing methods that rely on a single optical or ultrasonic mode, the heterojunction ferroelectric device provided by this invention can improve signal separation and feature extraction capabilities by utilizing the programmability of ferroelectric polarization, and can maintain high recognition accuracy even in noisy environments. Therefore, this invention has broad application prospects in intelligent perception, 3D imaging, and depth detection of autonomous systems. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the ferroelectric van der Waals heterostructure device for inductive calculations according to the present invention.

[0022] Figure 2 This is the transfer characteristic curve of the bottom-gate controlled ferroelectric van der Waals heterostructure device in this invention.

[0023] Figure 3 This is a schematic diagram illustrating the implementation of the carrier tunneling and storage characteristics of the bottom-gate control device in this invention.

[0024] Figure 4 This is a graph showing the changes in multimodal current of the photoresponse of the device in this invention under stimulation by ultrasonic signals of different polarities.

[0025] Figure 5 This is the pulse response diagram of the device under multimodal fusion input of optical and ultrasonic signals.

[0026] Figure 6 This is a schematic diagram of a depth sensing system based on ferroelectric van der Waals heterostructure devices.

[0027] Figure 7 This is a flowchart illustrating the fabrication process of the ferroelectric van der Waals heterostructure device based on this invention.

[0028] The markings in the image are as follows: 1001 is the gate-controlled substrate, 2001 is a two-dimensional metal / semi-metal layer, 3001 is a two-dimensional ferroelectric insulating layer, 4001 is a two-dimensional transition metal chalcogenide semiconductor, 5001 is the source metal electrode, and 5002 is the drain metal electrode. V dsFor channel input control terminal, V g GND is the gate input control terminal, and GND is the ground terminal. Detailed Implementation

[0029] The van der Waals ferroelectric heterojunction device for inductive computing in this invention includes a gate-controlled substrate, a two-dimensional metal / semi-metal, a two-dimensional ferroelectric insulating layer, a two-dimensional transition metal chalcogenide semiconductor, a drain, and a source. The gate-controlled substrate is located at the bottom of the device and has a dielectric layer as an input control terminal; The two-dimensional metal / semi-metal is fabricated on the surface of a gate-controlled substrate to provide a low-resistance conductive channel; The two-dimensional ferroelectric insulating layer covers the two-dimensional metallic / semi-metallic material, and its ferroelectric polarization field can regulate the injection and transport of charge carriers. The two-dimensional transition metal chalcogenide semiconductor is disposed on the ferroelectric layer and overlaps with the two-dimensional metal / semi-metal layer in the vertical direction, and is used to provide a photoelectric response or electrical switching channel. The source and drain metal electrodes are connected to a two-dimensional transition metal chalcogenide semiconductor layer. The overlapping region of the ferroelectric layer and the semiconductor layer forms an adjustable Schottky barrier, which can achieve nonlinear electrical response and multi-timescale synaptic plasticity under the action of an applied electric field and multi-modal signals.

[0030] In some specific embodiments, the dielectric layer of the substrate is selected from silicon dioxide, silicon nitride, aluminum oxide, or hafnium oxide, and the substrate is highly doped silicon.

[0031] In some specific embodiments, the two-dimensional metal / semi-metal layer is any one of a two-dimensional Dirac metal or a semi-metal, including graphene, palladium ditelluride, and zirconium ditelluride.

[0032] In some specific embodiments, the two-dimensional ferroelectric insulating layer is any one of copper indium phosphorus sulfide (CuInP2S6), copper indium phosphorus selenide (CuInP2Se6), copper cadmium phosphorus sulfide (CuCrP2S6), and copper cadmium phosphorus selenide (CuCrP2Se6).

[0033] In some specific embodiments, the two-dimensional transition metal chalcogenide semiconductor layer is selected from any one of molybdenum disulfide, tungsten disulfide, molybdenum diselenide, tungsten diselenide, and molybdenum distelluride.

[0034] In some specific embodiments, the source and drain metal electrodes are selected from one or more of cadmium, silver, copper, aluminum, gold, nickel, tungsten, ruthenium, iridium, platinum, and palladium.

[0035] The device fabrication method as described in one of the above technical solutions includes the following steps: S1: A two-dimensional metal / semi-metal layer is prepared on the surface of the gate-controlled substrate. Then, the metal / semi-metal channel region is defined by a mask layer, and the material outside the metal / semi-metal channel region is removed by etching. S2: A two-dimensional ferroelectric insulating layer is prepared on a substrate, and the ferroelectric layer is transferred using a polymer to completely cover the two-dimensional metal / semi-metal layer; S3: A two-dimensional transition metal chalcogenide semiconductor is prepared on a substrate. The semiconductor compound is transferred using a polymer to completely cover the two-dimensional ferroelectric layer and partially overlap with the two-dimensional metal / semi-metal layer in the vertical direction. Then, the channel region of the semiconductor compound is defined by a mask layer, and the part of the material that does not overlap with the two-dimensional metal / semi-metal layer is removed by etching. S4: The source and drain metal electrode regions of the etched two-dimensional transition metal chalcogenide semiconductor are defined using a mask layer, and metal deposition is performed. The source and drain metal electrodes are then fabricated using a lift-off process to obtain a two-dimensional ferroelectric van der Waals heterojunction device.

[0036] In some specific embodiments, in step S1, the fabrication process of the two-dimensional metal / semi-metal layer is selected from any one of mechanical exfoliation, chemical vapor deposition, physical vapor deposition, molecular beam epitaxy, or atomic layer deposition; In step S2, the fabrication process of the two-dimensional ferroelectric insulating layer is selected from mechanical peeling; In step S3, the fabrication process of the two-dimensional transition metal chalcogenide semiconductor is selected from any one of mechanical exfoliation, chemical vapor deposition, physical vapor deposition, molecular beam epitaxy, or atomic layer deposition.

[0037] In steps S2 and S3, the polymer transfer process for the two-dimensional ferroelectric insulating layer and the two-dimensional transition metal chalcogenide semiconductor is a polymer-assisted dry transfer or a polymer-assisted wet transfer, wherein the polymer is selected from any one of polydimethylsiloxane, polymethyl methacrylate, polypropylene carbonate or polyvinyl alcohol.

[0038] In steps S1 and S3, the etching process is any one of inductively coupled plasma etching, reactive ion etching, or ion sputtering etching.

[0039] In step S4, the fabrication process of the metal electrode includes: using photoresist or a mask as a mask layer, patterning is performed by electron beam exposure or photolithography; then, metal deposition is performed by any one of thermal evaporation, electron beam evaporation or magnetron sputtering, and the uncovered areas are removed by stripping with an organic solvent, thereby obtaining the patterned source and drain electrodes.

[0040] In some specific embodiments, after each stack and electrode deposition is completed, the heterostructure is subjected to low-temperature annealing or vacuum treatment to remove polymer residues and improve the interfacial electrical and photoelectric properties.

[0041] This invention employs a van der Waals stacked structure consisting of a two-dimensional metal / semi-metal layer, a two-dimensional ferroelectric insulating layer, and a two-dimensional transition metal chalcogenide semiconductor layer. By utilizing ferroelectric polarization to control the Schottky barrier height at the heterojunction interface, it achieves nonlinear electrical response and tunable synaptic plasticity, thereby enabling the fusion of multimodal signals such as light and sound and inductive computing functions.

[0042] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. Component models, material names, connection structures, circuit structures, control methods, algorithms, and other features not explicitly described in this technical solution are considered common technical features disclosed in the prior art.

[0043] Example 1 This embodiment provides a van der Waals ferroelectric heterojunction device for inductive computing and its fabrication method.

[0044] like Figure 7 The diagram illustrates a van der Waals ferroelectric heterojunction device for inductive computing and its fabrication method, comprising the following steps: First, in step S1, a two-dimensional metal / semi-metal layer 2001 is fabricated on a gate-controlled substrate 1001. An etching window is defined on the two-dimensional metal / semi-metal layer 2001 using a mask layer and exposed by development. The two-dimensional metal / semi-metal layer 2001 is then etched into a regular rectangle. The gate-controlled substrate 1001 is a commonly used silicon oxide / silicon substrate in the art. The two-dimensional metal / semi-metal layer 2001 is multilayer graphene. The multilayer graphene is fabricated by mechanical exfoliation. The mask layer is a commonly used photoresist in the art, such as polymethyl methacrylate or cyclic olefin polymers. The patterning method of the mask layer is to use photolithography or electron beam exposure processes, and to pattern the photoresist through exposure, development, and other means.

[0045] As a specific example, in this embodiment, polymethyl methacrylate (PMMA) is selected as the photoresist, with a spin-coating thickness of approximately 100 nm. Etching windows are defined on the photoresist surface through exposure, and the shape, size, and other parameters of the pattern are adjusted through layout design. The parameter scale should not be lower than the limit resolution of the selected photoresist. As a specific example, in this embodiment, high-precision electron beam lithography is used to create the etching window pattern on the PMMA photoresist surface, and then the etching window is exposed through development. The etching method can be any one of inductively coupled plasma etching, reactive ion etching, or ion sputtering etching. As a specific example, in this embodiment, reactive ion etching is used to etch away the multilayer graphene 2001 exposed after development on the gate control substrate 1001.

[0046] In step S2, a two-dimensional ferroelectric insulating layer 3001 is prepared on a polymer substrate, and the ferroelectric layer is transferred using a dry transfer process to completely cover the two-dimensional metal / semi-metal layer 2001 (graphene). The two-dimensional ferroelectric insulating layer 3001 is a layered copper indium phosphorus sulfur ferroelectric material. The preparation process is mechanical exfoliation. The polymer substrate is polydimethylsiloxane.

[0047] As a specific example, in this embodiment, the bulk copper indium phosphorus sulfur ferroelectric material is peeled off into a few layers on a polydimethylsiloxane substrate, and the few layers of copper indium phosphorus sulfur 3001 are transferred to the top of graphene 2001 using a self-aligned dry transfer platform, so that it completely covers the graphene.

[0048] In step S3, a two-dimensional transition metal chalcogenide semiconductor 4001 is prepared on a polymer substrate. The semiconductor compound 4001 is transferred using a polymer transfer method to completely cover the two-dimensional ferroelectric layer 3001 (copper indium phosphorus sulfide) and partially overlap with the two-dimensional metal / semi-metal layer 2001 (graphene) in the vertical direction. Subsequently, a mask layer is used to define the channel region of the semiconductor compound 4001, and then etching is used to remove the portion of material that does not overlap with the two-dimensional metal / semi-metal layer 2001 (graphene). The transition metal chalcogenide semiconductor 4001 is 2H-phase molybdenum disulfide. The preparation process is mechanical exfoliation. The polymer substrate is polydimethylsiloxane. As a specific example, in this embodiment, bulk molybdenum disulfide 4001 is exfoliated into a few layers on a polydimethylsiloxane substrate. A self-aligned dry transfer platform is used to transfer the few-layer molybdenum disulfide 4001 over the few-layer copper indium phosphorus sulfide 3001, so that it partially overlaps with the graphene 2001 in the vertical direction. The mask layer exposure and etching processes are consistent with those in step S1. As a specific example, this embodiment uses electron beam lithography to create a few-layer molybdenum disulfide 4001 window pattern on the surface of the photoresist polymethyl methacrylate that does not overlap with the graphene in vertical space. The etched window is then exposed through development. Reactive ion etching is then used to remove the exposed molybdenum disulfide 4001 after development.

[0049] In step S4, the source and drain electrodes of the etched two-dimensional transition metal chalcogenide semiconductor 4001 (molybdenum disulfide) channel are defined using a mask layer, and metal deposition is performed. The source and drain metal electrodes are then fabricated using a lift-off process, resulting in a two-dimensional ferroelectric van der Waals heterojunction device. The mask layer exposure process is consistent with that in steps S1 and S3. The metal deposition process includes any one of vacuum thermal evaporation, electron beam evaporation, or magnetron sputtering. The metal electrode materials include cadmium, silver, copper, aluminum, gold, nickel, tungsten, ruthenium, iridium, platinum, or palladium. As a specific example, in this embodiment, the channel and electrode regions are defined using an electron beam exposure process, and chromium and gold laminated metals are deposited sequentially using electron beam evaporation, with thicknesses of 5 nm and 50 nm for chromium and gold, respectively. Subsequently, the drain 5001 metal electrode and the source 5002 metal electrode are lifted off using an acetone solution.

[0050] The final van der Waals heterostructure device structure obtained in this embodiment is as follows: Figure 1 As shown, it includes a gate-controlled substrate 1001, a graphene conductive layer 2001, a two-dimensional ferroelectric layer 3001 (copper indium phosphorus sulfide), a two-dimensional transition metal chalcogenide semiconductor layer 4001 (molybdenum disulfide), a source electrode 5001, and a drain electrode 5002 metal electrodes.

[0051] Among them, the gate-controlled substrate 1001 serves as the input control terminal. V g The overlapping region of the ferroelectric layer 3001 and the semiconductor layer 4001 forms an adjustable Schottky barrier, and the source 5001 and drain 5002 serve as the device current output ports.

[0052] The ferroelectric van der Waals heterostructure device prepared in this embodiment of the invention is wire-bonded and then placed in a vacuum chamber (pressure below 10). -6 Electrical and optoelectronic characterization was performed using a PDA FS-Pro PX600 semiconductor parameter analyzer. Electrical transport and synaptic-like properties were acquired; pulsed lasers (405 nm, 520 nm, 638 nm) were used as the light source, collimated and illuminating the active region of the device. The light intensity was calibrated using a THORLABS PM 100A power meter. The test results show that the polarization of the ferroelectric layer can effectively control carrier injection in the molybdenum disulfide channel, achieving nonlinear control of the current response. When the device is simultaneously excited by light and sound, the output signal exhibits multimodal fusion characteristics, which can be used for depth sensing and inductive computing.

[0053] Figure 2 The device exhibits bottom-gate controlled ferroelectric van der Waals heterostructure transfer characteristics, demonstrating the memory characteristics of ferroelectric field reversal.

[0054] Figure 3This diagram illustrates the energy band structure of a ferroelectric van der Waals heterostructure device under different gate biases, showing the charge injection and storage process. As shown, when a positive voltage pulse is applied to the gate, the polarization direction of the ferroelectric layer is aligned with the applied electric field, leading to electron accumulation in the semiconductor channel. This electron accumulation causes the Fermi level to shift upwards, thereby reducing the Schottky barrier height at the ferroelectric layer / semiconductor interface and promoting electron injection from the molybdenum disulfide channel and storage in the graphene layer. This non-volatile electron storage causes the channel to exhibit an equivalent p-type doping effect, resulting in decreased conductivity and demonstrating the modulating effect of ferroelectric polarization on electrical transport. Conversely, when a negative voltage is applied to the gate, the ferroelectric polarization flips, the interface energy bands rearrange, the Fermi level shifts downwards, and the interface barrier becomes more favorable for hole transport. At this time, the channel exhibits an equivalent n-type modulation effect, enhancing conductivity. Therefore, by alternating positive and negative gate voltages, the device of this invention can achieve polarization-assisted charge storage and non-volatile memory characteristics in a single structure.

[0055] Figure 4 This diagram illustrates the current variations in a ferroelectric van der Waals heterostructure device under different polarity ultrasonic signal excitations. The left image corresponds to a forward ultrasonic signal, and the right image to a reverse ultrasonic signal. The ultrasonic signals are input to the gate via the transducer in both directions. As shown in the left image, when a forward ultrasonic signal is applied to the gate, a built-in electric field is generated inside the device, pointing from the molybdenum disulfide channel towards the graphene layer. This electric field not only promotes the separation of photogenerated electron-hole pairs but also drives holes to cross the ferroelectric layer barrier and inject into the graphene, thereby gradually weakening the electron depletion effect in the channel. As the signal pressure increases, charge accumulation in the graphene layer further enhances the built-in electric field, causing the photoresponse current (PSC) to gradually decrease, and the device enters the off state. As shown in the right image, when a reverse ultrasonic signal is applied to the gate, the ferroelectric polarization direction is reversed, and the direction of the built-in electric field is opposite, which is beneficial for the accumulation and injection of electrons in the channel. Simultaneously, the accumulation of holes in the graphene enhances the grating control effect. In this state, as the signal pressure increases, the channel current gradually rises and is further enhanced under illumination, exhibiting a regulation characteristic symmetrical to the positive excitation.

[0056] Verification Example 1 Figure 5The diagram illustrates the pulse response of the ferroelectric van der Waals heterostructure device of this invention under fused optical and ultrasonic signal inputs. The left figure shows the photoresponse current (PSC) corresponding to different 4-bit pulse combinations, and the right figure shows the corresponding final steady-state current. As shown, while maintaining a fixed delay relationship between the ultrasonic and optical signals, the input is encoded using a 4-bit pulse sequence, where the first three bits represent the optical pulse and the last bit represents the ultrasonic pulse. Different binary combinations correspond to different input modes. Under this pulse excitation, the device maps the linear binary input into a nonlinear, densely distributed photoresponse current, with a current response range between 0.1 nA and 2.1 nA and good uniformity. This result demonstrates that the device of this invention possesses strong time-series information discrimination capability and multi-modal signal fusion characteristics, and can be used as a dynamic reservoir computing unit for time-series feature extraction and depth sensing tasks.

[0057] Application Example 1 Figure 6 This diagram illustrates an application of the ferroelectric van der Waals heterostructure device proposed in this invention: a depth sensing system and its performance. Figure a shows the depth sensing system, including a multimodal fusion ferroelectric heterojunction device array as the front end and a deep learning model as the back end. Figure 6 As shown, optical and ultrasonic signals enter the device array through optical and acoustic paths, respectively. The optical path converts ambient light into a multi-channel pulse sequence, while the acoustic path provides sparse depth information based on echo signals. Under the combined action of the optical and acoustic signals, the device array outputs a fused current state vector. This state vector, after processing by a back-end neural network model, can reconstruct a depth distribution image of the scene. Figures b and c show the curves of the depth sensing system's training accuracy with the number of training steps and the change in accuracy with the noise of the ferroelectric van der Waals heterostructure device under three different signal combinations, verifying the multimodal fusion capability of the ferroelectric van der Waals heterostructure device and the high accuracy and robustness of in-memory multimodal computation. Therefore, this invention can realize multimodal information fusion and spatial structure perception at the hardware level, providing a new solution for depth sensing and 3D imaging applications.

[0058] This invention achieves effective control over interface band structure and carrier transport characteristics by constructing a ferroelectric van der Waals heterostructure device. The synergistic effect of the ferroelectric polarization field and the applied bias enables the device to exhibit non-volatile memory effects, adjustable nonlinear current response, and multimodal signal fusion characteristics within a single structure. This device not only simulates synaptic plasticity and supports inductive computation at the hardware level, but also serves as a basic unit for multifunctional computing and image processing, significantly reducing system power consumption and circuit complexity. Furthermore, this invention combines optical and acoustic inputs to achieve multimodal signal fusion processing, demonstrating excellent performance in depth sensing and 3D imaging applications, providing a feasible solution for the development of intelligent sensing systems and novel neuromorphic hardware.

[0059] The above description of the embodiments is provided to enable those skilled in the art to understand and use the invention. It will be apparent to those skilled in the art that various modifications can be made to these embodiments, and the general principles described herein can be applied to other embodiments without inventive effort. Therefore, the present invention is not limited to the above embodiments, and any improvements and modifications made by those skilled in the art based on the disclosure of the present invention without departing from the scope of the invention should be within the protection scope of the present invention.

Claims

1. A van der Waals ferroelectric heterojunction device for inductive computing, characterized in that, include: Gate-controlled substrate (1001); A two-dimensional metal / semi-metal layer (2001) is disposed on the substrate (1001). A two-dimensional ferroelectric insulating layer (3001) is disposed on the two-dimensional metal / semi-metal layer (2001). A two-dimensional transition metal chalcogenide semiconductor (4001) is disposed on the two-dimensional ferroelectric insulating layer (3001). Source (5001) and drain (5002) are provided on the upper surface of the two-dimensional transition metal chalcogenide semiconductor (4001). The overlapping region of the two-dimensional ferroelectric insulating layer (3001) and the two-dimensional transition metal chalcogenide semiconductor (4001) forms an tunable Schottky barrier.

2. The van der Waals ferroelectric heterojunction device for inductive computing according to claim 1, characterized in that, The gate-controlled substrate (1001) includes a substrate body and a dielectric layer disposed on the surface of the substrate body; The substrate is primarily composed of highly doped silicon. The dielectric layer is selected from one of silicon dioxide, silicon nitride, aluminum oxide, and hafnium oxide; The two-dimensional metal / semi-metal layer (2001) is selected from any two-dimensional Dirac metal or semi-metal.

3. The van der Waals ferroelectric heterojunction device for inductive computing according to claim 1, characterized in that, The two-dimensional ferroelectric insulating layer (3001) is selected from any one of CuInP2S6, CuInP2Se6, CuCrP2S6, and CuCrP2Se6. The two-dimensional ferroelectric insulating layer (3001) has a band gap of >2.6 eV, and the internal ferroelectric polarization direction is easily modulated by an external electric field.

4. The van der Waals ferroelectric heterojunction device for inductive computing according to claim 1, characterized in that, The two-dimensional transition metal chalcogenide semiconductor (4001) is selected from any one of molybdenum disulfide, tungsten disulfide, molybdenum diselenide, tungsten diselenide, and molybdenum distelluride. The metal material of the source (5001) and / or drain (5002) is selected from one or more of cadmium, silver, copper, aluminum, gold, nickel, tungsten, ruthenium, iridium, platinum, and palladium.

5. A van der Waals ferroelectric heterojunction device for inductive calculation according to claim 1, characterized in that, The ferroelectric polarization direction of the two-dimensional ferroelectric insulating layer (3001) can be controlled by an external electric field. Its polarization charge forms a built-in electric field at the interface, dynamically adjusting the Schottky barrier height between the two-dimensional transition metal chalcogenide semiconductor (4001) and the two-dimensional metal / semi-metal layer (2001). When optical or ultrasonic signals act on the device, the ferroelectric polarization direction and the signal polarity work together to achieve multimodal fusion and feature extraction through the following nonlinear process: Optical signals excite the semiconductor layer to generate charge carriers, and ferropolarization accelerates the separation of charge carriers through the built-in electric field, thereby regulating the injection efficiency. Ultrasonic signals modulate ferroelectric polarization intensity through the piezoelectric effect, changing the potential energy distribution of the barrier and realizing dynamic reconstruction of carrier transport paths; The non-volatile polarization reversal of ferroelectric polarization forms a positive feedback with the signal polarity, thereby enabling the weighted summation of optical / acoustic signals, extraction of spatiotemporal correlation, and updating of synaptic weights in a single structure.

6. The fabrication of a van der Waals ferroelectric heterojunction device for inductive computing as described in any one of claims 1 to 5, characterized in that, Includes the following steps: S1. A two-dimensional metal / semi-metal layer (2001) is prepared on the surface of the gate-controlled substrate (1001). Then, the metal / semi-metal channel region is defined by a mask layer, and the non-channel region material is etched away. S2. A two-dimensional ferroelectric insulating layer (3001) is coated onto the surface of a two-dimensional metal / semi-metal layer (2001) using a polymer transfer process; S3. Using a polymer transfer process, a two-dimensional transition metal chalcogenide semiconductor (4001) is covered on the surface of the ferroelectric layer (3001), so that the two-dimensional transition metal chalcogenide semiconductor (4001) partially overlaps with the metal / semi-metal layer (2001) in the vertical direction. The semiconductor channel region is defined by a mask layer and the non-overlapping part is etched away. S4. Define the source (5001) and drain (5002) electrode regions on the semiconductor layer (4001) through a mask layer, deposit metal electrodes and strip away excess material to form source and drain electrodes.

7. A van der Waals ferroelectric heterojunction device for inductive calculation according to claim 6, characterized in that, In S1, the preparation method of the two-dimensional metal / semi-metal layer (2001) is selected from one of mechanical exfoliation, chemical vapor deposition, physical vapor deposition, molecular beam epitaxy, and atomic layer deposition; In S2, the two-dimensional ferroelectric insulating layer (3001) is prepared by mechanical peeling.

8. A van der Waals ferroelectric heterojunction device for inductive calculation according to claim 6, characterized in that, In S2 and S3, the polymer transfer process is a polymer-assisted dry transfer or wet transfer, and the polymer is selected from one of polydimethylsiloxane, polymethyl methacrylate, polypropylene carbonate, and polyvinyl alcohol. In S3, the preparation method of the two-dimensional transition metal chalcogenide semiconductor (4001) is selected from any one of mechanical exfoliation, chemical vapor deposition, physical vapor deposition, molecular beam epitaxy, and atomic layer deposition.

9. A van der Waals ferroelectric heterojunction device for inductive calculation according to claim 6, characterized in that, In S1 and S3, the etching process is one of inductively coupled plasma etching, reactive ion etching, or ion sputtering etching. In S4, the specific process of depositing metal electrodes and stripping away excess material includes: after patterning with photoresist or a mask, depositing metal using one of the following methods: thermal evaporation, electron beam evaporation, or magnetron sputtering, and then stripping away uncovered areas using organic solvents.

10. An application of the van der Waals ferroelectric heterojunction device for inductive calculation as described in any one of claims 1 to 5, characterized in that, The Dehua ferroelectric heterojunction device is used for multimodal optical / acoustic signal fusion processing, nonlinear electrical response, low-power image processing, reconfigurable logic operations, and pulse sequence-based feature extraction in neuromorphic computing.

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