Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel includes two or more gate layers including a plurality of gate patterns extending in a first direction and one or more source-drain layers including a plurality of source-drain patterns extending in a second direction crossing the first direction. The gate patterns of the two or more gate layers are curled or curved along a hole surrounding region corresponding to the periphery of the hole in the active region. A source-drain pattern of the one or more source-drain layers is curled or curved along a region around the hole. In the hole surrounding area, the gate pattern of at least one of the two or more gate layers overlaps the source-drain pattern of at least one of the one or more source-drain layers in a thickness direction of the display panel.

Description

[0001] This application is a divisional application of the invention filed on September 3, 2020, with application number 202010914851.2 and titled "Display Panel". Technical Field

[0002] The exemplary embodiments of the present invention relate to a display panel and a display device including the display panel. More specifically, the exemplary embodiments of the present invention relate to a display panel including a hole and a display device including the display panel. Background Technology

[0003] The display panel has holes that are arranged in relation to other components such as cameras. Grille lines and data lines arranged in the area surrounding the holes can be coiled or bent to bypass them. These grille lines and data lines may create dead zones in the vicinity of the area surrounding the holes. Summary of the Invention

[0004] An exemplary embodiment of the present invention relates to a display panel capable of reducing dead zones adjacent to the area around holes in the display panel.

[0005] An aspect of the exemplary embodiments of the present invention relates to a display device including the display panel.

[0006] In an example embodiment of a display panel according to the present invention, the display panel includes two or more gate layers and one or more source-drain layers. The two or more gate layers include a plurality of gate patterns extending in a first direction, and the one or more source-drain layers include a plurality of source-drain patterns extending in a second direction intersecting the first direction. The gate patterns of the two or more gate layers are curled or bent along a peri-hole region corresponding to the periphery of a hole in the effective region. The source-drain patterns of the one or more source-drain layers are curled or bent along the peri-hole region. In the peri-hole region, the gate pattern of at least one of the two or more gate layers overlaps with the source-drain pattern of at least one of the one or more source-drain layers in the thickness direction of the display panel.

[0007] In an example embodiment, the display panel may further include a first gate insulating layer, a second gate insulating layer, and a first passivation layer, and two or more gate layers may include a first gate layer, a second gate layer, and a third gate layer. The first gate layer is located on the first gate insulating layer, the second gate insulating layer is located on the first gate layer, the second gate layer is located on the second gate insulating layer, the first passivation layer is located on the second gate layer, and the third gate layer is located on the first passivation layer.

[0008] In the example embodiment, in normal regions that are not around the aperture, the second gate layer may overlap with the third gate layer in the thickness direction. In normal regions, the first gate layer may not overlap with the second and third gate layers in the thickness direction.

[0009] In an example embodiment, the first gate layer, the second gate layer, and the third gate layer may overlap each other in the thickness direction in the region surrounding the aperture.

[0010] In an example embodiment, the display panel may further include an organic insulating layer in the area around the hole and located between the second gate insulating layer and the second gate layer.

[0011] In an example embodiment, in the region surrounding the aperture, the second gate layer may overlap with the third gate layer in the thickness direction. In the region surrounding the aperture, the first gate layer may not overlap with the second and third gate layers in the thickness direction.

[0012] In an example embodiment, the display panel may further include pixels, which include P-type transistors and N-type transistors.

[0013] In an example embodiment, the first gate layer may include a P-type gate line configured to transmit a P-type gate signal to a P-type transistor. The second gate layer may include a back gate electrode of a P-type transistor or an N-type transistor and a connection line for the back gate electrode. The third gate layer may include an N-type gate line configured to transmit an N-type gate signal to an N-type transistor.

[0014] In an example embodiment, the display panel further includes a first organic insulating layer and a second organic insulating layer, and one or more source-drain layers may include the first source-drain layer and the second source-drain layer. The first organic insulating layer is located on the first source-drain layer, the second source-drain layer is located on the first organic insulating layer, and the second organic insulating layer is located on the second source-drain layer.

[0015] In the example embodiment, in a normal region that is not the area around the hole, the first source-drain layer may not overlap with the second source-drain layer in the thickness direction.

[0016] In an example embodiment, in the region surrounding the hole, the first source-drain layer may overlap with the second source-drain layer in the thickness direction.

[0017] In an example embodiment, the display panel may further include a matrix of pixels. Pixels in one column of pixels may be alternately connected to a first data line and a second data line.

[0018] In an example embodiment, the first source-drain layer may include a first data line. The second source-drain layer may include a second data line.

[0019] In an example embodiment, the display panel may include: a first gate layer on a first gate insulating layer, a second gate insulating layer on the first gate layer, a second gate layer on the second gate insulating layer, a first passivation layer on the second gate layer, a third gate layer on the first passivation layer, a second passivation layer on the third gate layer, a first source-drain layer on the second passivation layer, a first organic insulating layer on the first source-drain layer, a second source-drain layer on the first organic insulating layer, and a second organic insulating layer on the second source-drain layer.

[0020] In an example embodiment, in the region surrounding the aperture, the first gate layer, the second gate layer, the third gate layer, the first source-drain layer, and the second source-drain layer may overlap each other in the thickness direction.

[0021] In an example embodiment, the display panel may further include a third organic insulating layer in the area around the hole and located between the second gate insulating layer and the second gate layer.

[0022] In the example embodiment, in the region surrounding the aperture, the second gate layer, the third gate layer, the first source-drain layer, and the second source-drain layer may overlap each other in the thickness direction. In the region surrounding the aperture, the first gate layer may not overlap with the second gate layer in the thickness direction.

[0023] In an example embodiment, the display panel may include: a first gate layer on a first gate insulating layer, a second gate insulating layer on the first gate layer, a second gate layer on the second gate insulating layer, a first passivation layer on the second gate layer, a third gate layer on the first passivation layer, a second passivation layer on the third gate layer, a source-drain layer on the second passivation layer, and an organic insulating layer on the source-drain layer.

[0024] In an example embodiment, the first gate layer, the second gate layer, the third gate layer, and the source-drain layer may overlap each other in the thickness direction in the region surrounding the aperture.

[0025] In an example embodiment of a display device conceived according to the present invention, the display device includes a display panel, a gate driver, a data driver, and a transmit driver. The display panel includes: two or more gate layers comprising a plurality of gate patterns extending in a first direction; one or more source-drain layers comprising a plurality of source-drain patterns extending in a second direction intersecting the first direction; and a plurality of pixels connected to the plurality of gate patterns and the plurality of source-drain patterns. The gate driver is configured to provide a gate signal to the display panel. The data driver is configured to provide a data voltage to the display panel. The transmit driver is configured to provide a transmit signal to the display panel. The gate patterns of the two or more gate layers are curled or bent along a peri-hole region corresponding to the periphery of a hole in the effective area of ​​the display panel. The source-drain patterns of the one or more source-drain layers are curled or bent along the peri-hole region. In the peri-hole region, the gate pattern of at least one of the two or more gate layers overlaps with the source-drain pattern of at least one of the one or more source-drain layers in the thickness direction of the display panel.

[0026] According to embodiments of the display panel and the display device including the display panel, when a hole is formed in the effective area of ​​the display panel, and the patterns on the gate layer and the source-drain layer bypass the hole in the area surrounding the hole, the patterns on the gate layer and the source-drain layer overlap each other in the thickness direction, thereby reducing the dead zone adjacent to the area surrounding the hole. Attached Figure Description

[0027] The above and other features and aspects of the inventive concept will become more apparent from the detailed description of exemplary embodiments of the inventive concept with reference to the accompanying drawings, in which:

[0028] Figure 1 This is a block diagram illustrating an exemplary embodiment of a display device according to a concept of the present invention;

[0029] Figure 2 It is a diagram. Figure 1 The circuit diagram of the pixels of the display panel;

[0030] Figure 3 The diagram is applied to Figure 2 Timing diagram of the input signal of the pixel;

[0031] Figure 4 It is a diagram. Figure 1 A conceptual diagram of the pixel structure of a display panel;

[0032] Figure 5 It is a diagram. Figure 1 A plan view of the holes, the area around the holes, and the normal area of ​​the display panel;

[0033] Figure 6 It is a diagram. Figure 5 Plan view of the aperture, gate layer, and source-drain layer;

[0034] Figure 7 It is shown in the diagram along Figure 6 A cross-sectional view of the display panel taken by line A-A';

[0035] Figure 8 It is shown in the diagram along Figure 6 A cross-sectional view of the display panel taken by line B-B';

[0036] Figure 9 It is shown in the diagram along Figure 6 A cross-sectional view of the display panel taken by line C-C';

[0037] Figure 10 This is a plan view illustrating a hole, a region surrounding the hole, and a normal region of a display panel according to an exemplary embodiment of the present invention.

[0038] Figure 11 It is shown in the diagram along Figure 10 A cross-sectional view of the display panel taken by line C-C';

[0039] Figure 12 This is a cross-sectional view illustrating the area surrounding the holes in a display panel according to an exemplary embodiment of the present invention;

[0040] Figure 13 This is a conceptual diagram illustrating the pixel structure of a display panel according to an exemplary embodiment of the present invention; and

[0041] Figure 14 It is a diagram. Figure 13 A cross-sectional view of the area surrounding the holes in the display panel. Detailed Implementation

[0042] The concept of the invention will be described in detail below with reference to the accompanying drawings.

[0043] Figure 1 This is a block diagram illustrating an example embodiment of a display device according to a concept of the present invention.

[0044] refer to Figure 1 The display device includes a display panel 100 and a display panel driver. The display panel driver includes a drive controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and a transmit driver 600.

[0045] The display panel 100 has a display area on which an image is displayed and a peripheral area adjacent to the display area.

[0046] The display panel 100 includes multiple gate lines GWPL, GWNL, GIL, and GBL, multiple data lines DL, multiple emission lines EL, and multiple pixels electrically connected to the gate lines GWPL, GWNL, GIL, and GBL, the data lines DL, and the emission lines EL. The gate lines GWPL, GWNL, GIL, and GBL may extend in a first direction D1, the data lines DL may extend in a second direction D2 intersecting the first direction D1, and the emission lines EL may extend in the first direction D1.

[0047] The drive controller 200 receives input image data IMG and input control signal CONT from an external device. For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may also include white image data. The input image data IMG may also include magenta image data, cyan image data, and yellow image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may further include a vertical synchronization signal and a horizontal synchronization signal.

[0048] The drive controller 200 generates a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, a fourth control signal CONT4, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0049] The drive controller 200 generates a first control signal CONT1 based on the input control signal CONT for controlling the operation of the gate driver 300, and outputs the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0050] The drive controller 200 generates a second control signal CONT2 based on the input control signal CONT for controlling the operation of the data driver 500, and outputs the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0051] The drive controller 200 generates a data signal DATA based on the input image data IMG. The drive controller 200 outputs the data signal DATA to the data driver 500.

[0052] The drive controller 200 generates a third control signal CONT3 based on the input control signal CONT for controlling the operation of the gamma reference voltage generator 400, and outputs the third control signal CONT3 to the gamma reference voltage generator 400.

[0053] The drive controller 200 generates a fourth control signal CONT4 based on the input control signal CONT for controlling the operation of the transmitter driver 600, and outputs the fourth control signal CONT4 to the transmitter driver 600.

[0054] The gate driver 300 generates gate signals for driving gate lines GWPL, GWNL, GIL, and GBL in response to a first control signal CONT1 received from the drive controller 200. The gate driver 300 can sequentially output the gate signals to the gate lines GWPL, GWNL, GIL, and GBL.

[0055] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to a third control signal CONT3 received from the drive controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to the level of the data signal DATA.

[0056] In an example embodiment, the gamma reference voltage generator 400 may be arranged in the drive controller 200 or the data driver 500.

[0057] The data driver 500 receives a second control signal CONT2 and a data signal DATA from the drive controller 200, and receives a gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 uses the gamma reference voltage VGREF to convert the data signal DATA into a data voltage of analog type. The data driver 500 outputs the data voltage to the data line DL.

[0058] The transmitter driver 600 generates a transmit signal for driving the transmitter line EL in response to a fourth control signal CONT4 received from the drive controller 200. The transmitter driver 600 can output the transmit signal to the transmitter line EL.

[0059] Figure 2 It is a diagram. Figure 1 Circuit diagram of the pixels in the display panel 100. Figure 3 The diagram is applied to Figure 2 The timing diagram of the input signal of the pixel.

[0060] refer to Figures 1 to 3 The display panel 100 includes multiple pixels. Each pixel includes an organic light-emitting element (OLED).

[0061] The pixel receives data written gate signals GWP and GWN, data initialization gate signal GI, organic light-emitting element initialization gate signal GB, data voltage VDATA and emission signal EM, and the pixel's organic light-emitting element OLED emits light corresponding to the level of data voltage VDATA to display an image (e.g., a portion of an image).

[0062] In the illustrated example embodiments, a pixel may include a first type of switching element and a second type of switching element different from the first type. In one or more illustrated embodiments, the first type of switching element may be a polycrystalline silicon thin-film transistor, and the second type of switching element may be an oxide thin-film transistor. In one or more illustrated embodiments, the first type of switching element may be a low-temperature polycrystalline silicon (LTPS) thin-film transistor, and the second type of switching element may be an oxide thin-film transistor. In one or more illustrated embodiments, the first type of switching element may be a P-type transistor, and the second type of switching element may be an N-type transistor. Although different types of transistors are described with respect to the illustrated example embodiments, any suitable type that causes the pixel to include a first type of switching element and a second type of switching element different from the first type may be used.

[0063] In one or more example embodiments, the data write gate signals GWP and GWN may include a first data write gate signal GWP and a second data write gate signal GWN. The first data write gate signal GWP may be applied to a P-type transistor such that it has a low-level start signal corresponding to the data write timing. The second data write gate signal GWN may be applied to an N-type transistor such that it has a high-level start signal corresponding to the data write timing.

[0064] At least one of the pixels may include a first pixel switching element T1 to a seventh pixel switching element T7 (i.e., the first pixel switching element T1, the second pixel switching element T2, the third pixel switching element T3, the fourth pixel switching element T4, the fifth pixel switching element T5, the sixth pixel switching element T6 and the seventh pixel switching element T7), a storage capacitor CST and an organic light-emitting element OLED.

[0065] The first pixel switching element T1 includes a control electrode connected to the first node N1, an input electrode connected to the second node N2, and an output electrode connected to the third node N3.

[0066] In one or more example embodiments, the first pixel switching element T1 may be a polysilicon thin-film transistor. In one or more example embodiments, the first pixel switching element T1 may be a P-type thin-film transistor. The control electrode of the first pixel switching element T1 may be a gate electrode, the input electrode of the first pixel switching element T1 may be a source electrode, and the output electrode of the first pixel switching element T1 may be a drain electrode.

[0067] The second pixel switching element T2 includes a control electrode to which a first data write gate signal GWP is applied, an input electrode to which a data voltage VDATA is applied, and an output electrode connected to the second node N2.

[0068] In one or more example embodiments, the second pixel switching element T2 may be a polysilicon thin-film transistor. In one or more example embodiments, the second pixel switching element T2 may be a P-type thin-film transistor. The control electrode of the second pixel switching element T2 may be a gate electrode, the input electrode of the second pixel switching element T2 may be a source electrode, and the output electrode of the second pixel switching element T2 may be a drain electrode.

[0069] The third pixel switching element T3 includes a control electrode to which a second data write gate signal GWN is applied, an input electrode connected to the first node N1, and an output electrode connected to the third node N3.

[0070] In one or more example embodiments, the third pixel switching element T3 may be an oxide thin-film transistor. In one or more example embodiments, the third pixel switching element T3 may be an N-type thin-film transistor. The control electrode of the third pixel switching element T3 may be a gate electrode, the input electrode of the third pixel switching element T3 may be a source electrode, and the output electrode of the third pixel switching element T3 may be a drain electrode.

[0071] The fourth pixel switching element T4 includes a control electrode to which a data initialization gate signal GI is applied, an input electrode to which an initialization voltage VI is applied, and an output electrode connected to the first node N1.

[0072] In one or more example embodiments, the fourth pixel switching element T4 may be an oxide thin-film transistor. In one or more example embodiments, the fourth pixel switching element T4 may be an N-type thin-film transistor. The control electrode of the fourth pixel switching element T4 may be a gate electrode, the input electrode of the fourth pixel switching element T4 may be a source electrode, and the output electrode of the fourth pixel switching element T4 may be a drain electrode.

[0073] The fifth pixel switching element T5 includes a control electrode to which a transmission signal EM is applied, an input electrode to which a high power voltage ELVDD is applied, and an output electrode connected to the second node N2.

[0074] In one or more example embodiments, the fifth pixel switching element T5 may be a polysilicon thin-film transistor. In one or more example embodiments, the fifth pixel switching element T5 may be a P-type thin-film transistor. The control electrode of the fifth pixel switching element T5 may be a gate electrode, the input electrode of the fifth pixel switching element T5 may be a source electrode, and the output electrode of the fifth pixel switching element T5 may be a drain electrode.

[0075] The sixth pixel switching element T6 includes a control electrode to which an emission signal EM is applied, an input electrode connected to the third node N3, and an output electrode connected to the anode electrode of the organic light-emitting element OLED.

[0076] In one or more example embodiments, the sixth pixel switching element T6 may be a polysilicon thin-film transistor. In one or more example embodiments, the sixth pixel switching element T6 may be a P-type thin-film transistor. The control electrode of the sixth pixel switching element T6 may be a gate electrode, the input electrode of the sixth pixel switching element T6 may be a source electrode, and the output electrode of the sixth pixel switching element T6 may be a drain electrode.

[0077] The seventh pixel switching element T7 includes a control electrode to which an organic light-emitting element initialization gate signal GB is applied, an input electrode to which an initialization voltage VI is applied, and an output electrode connected to the anode electrode of the organic light-emitting element OLED.

[0078] In one or more example embodiments, the seventh pixel switching element T7 may be an oxide thin-film transistor. In one or more example embodiments, the seventh pixel switching element T7 may be an N-type thin-film transistor. The control electrode of the seventh pixel switching element T7 may be a gate electrode, the input electrode of the seventh pixel switching element T7 may be a source electrode, and the output electrode of the seventh pixel switching element T7 may be a drain electrode.

[0079] Although the seventh pixel switching element T7 is an oxide thin-film transistor in the illustrated example embodiment, the inventive concept is not limited thereto. For example, the seventh pixel switching element T7 could be a polysilicon thin-film transistor. Although the seventh pixel switching element T7 is an N-type thin-film transistor in the illustrated example embodiment, the inventive concept is not limited thereto. For example, the seventh pixel switching element T7 could be a P-type thin-film transistor.

[0080] The storage capacitor CST includes a first electrode to which a high electrical voltage ELVDD is applied and a second electrode connected to a first node N1.

[0081] Organic light-emitting elements (OLEDs) include an anode electrode and a cathode electrode to which a low electrical voltage (ELVSS) is applied.

[0082] exist Figure 3 During the first duration DU1, the first node N1 and the storage capacitor CST are initialized in response to the data initialization gate signal GI (e.g., the data initialization gate signal GI is applied high to the control electrode of the fourth pixel switching element T4). During the second duration DU2, the threshold voltage |VTH| of the first pixel switching element T1 is compensated in response to the first data write gate signal GWP and the second data write gate signal GWN (e.g., the first data write gate signal GWP is applied low to the control electrode of the second pixel switching element T2, and the second data write gate signal GWN is applied high to the control electrode of the third pixel switching element T3), and the data voltage VDATA compensated for the threshold voltage |VTH| is written to the first node N1. During the third duration DU3, the anode electrode of the organic light-emitting element OLED is initialized in response to the organic light-emitting element initialization gate signal GB (e.g., the organic light-emitting element initialization gate signal GB is applied high to the control electrode of the seventh pixel switching element T7). During the fourth duration DU4, the organic light-emitting element OLED emits light in response to the emission signal EM (e.g., the emission signal EM is applied at a low level to the control electrode of the fifth pixel switching element T5 and the control electrode of the sixth pixel switching element T6), causing the display panel 100 to display an image.

[0083] Although in the illustrated example embodiment, the transmit-off duration of the transmit signal EM corresponds to the first to third durations (first duration DU1, second duration DU2, and third duration DU3), the inventive concept is not limited thereto. The transmit-off duration of the transmit signal EM may be configured to include the second duration DU2. In one or more example embodiments, the transmit-off duration of the transmit signal EM may be longer than the sum of the first to third durations DU1, DU2, and DU3.

[0084] During the first duration DU1, the data initialization gate signal GI can have an active level. For example, the active level of the data initialization gate signal GI can be a high level. When the data initialization gate signal GI has an active level, the fourth pixel switch element T4 is turned on, allowing the initialization voltage VI to be applied to the first node N1. The current stage's data initialization gate signal GI[N] can be generated based on the previous stage's scan signal SCAN[N-1].

[0085] During the second duration DU2, the first data write gate signal GWP and the second data write gate signal GWN can have active levels. For example, the active level of the first data write gate signal GWP can be low, and the active level of the second data write gate signal GWN can be high. When the first data write gate signal GWP and the second data write gate signal GWN have active levels, the second pixel switch element T2 and the third pixel switch element T3 are turned on. In addition, the first pixel switch element T1 is turned on in response to the initialization voltage VI. The first data write gate signal GWP[N] of the current stage can be generated based on the scan signal SCAN[N] of the current stage. The second data write gate signal GWN[N] of the current stage can be generated based on the scan signal SCAN[N] of the current stage.

[0086] The voltage generated by subtracting the absolute value |VTH| of the threshold voltage of the first pixel switching element T1 from the data voltage VDATA can be charged at the first node N1 along the path generated from the first pixel switching element to the third pixel switching element (i.e., the first pixel switching element T1, the second pixel switching element T2, and the third pixel switching element T3).

[0087] During the third duration DU3, the OLED initialization gate signal GB can have an active level. For example, the active level of the OLED initialization gate signal GB can be a high level. When the OLED initialization gate signal GB has an active level, the seventh pixel switch element T7 is turned on, allowing the initialization voltage VI to be applied to the anode electrode of the OLED. The current stage's OLED initialization gate signal GB[N] can be generated based on the next stage's scan signal SCAN[N+1].

[0088] During the fourth duration DU4, the transmitted signal EM can have an active level. The active level of the transmitted signal EM can be low. When the transmitted signal EM has an active level, the fifth pixel switch element T5 and the sixth pixel switch element T6 are turned on. In addition, the first pixel switch element T1 is turned on by the data voltage VDATA.

[0089] A driving current flows through the fifth pixel switching element T5, the first pixel switching element T1, and the sixth pixel switching element T6 to drive the organic light-emitting element (OLED). The intensity of the driving current can be determined by the level of the data voltage VDATA. The brightness of the OLED is determined by the intensity (e.g., magnitude) of the driving current applied to the OLED.

[0090] In the illustrated example embodiment, when the image displayed on the display panel 100 is a static image or when the display panel 100 operates in normally-on mode, the driving frequency of the display panel 100 can be reduced to lower power consumption. When all the switching elements of the pixels of the display panel 100 are polysilicon thin-film transistors, flicker may occur due to leakage current of the pixel switching elements in low-frequency driving mode. Therefore, oxide thin-film transistors can be used to design some of the pixel switching elements. In the illustrated example embodiment, the third pixel switching element T3, the fourth pixel switching element T4, and the seventh pixel switching element T7 can be oxide thin-film transistors. The first pixel switching element T1, the second pixel switching element T2, the fifth pixel switching element T5, and the sixth pixel switching element T6 can be polysilicon thin-film transistors. Therefore, in the illustrated embodiment, flicker can be reduced or prevented in low-frequency driving mode.

[0091] Although in the illustrated example embodiment, the second data write gate signal GWN is applied to the control electrode of the third pixel switching element T3, and the organic light-emitting element initialization gate signal GB is applied to the control electrode of the seventh pixel switching element T7, the inventive concept is not limited thereto. The control electrode of the third pixel switching element T3 may be connected to the control electrode of the seventh pixel switching element T7, and the second data write gate signal GWN may be applied to both the control electrodes of the third pixel switching element T3 and the seventh pixel switching element T7. Therefore, in one or more example embodiments, the separate organic light-emitting element initialization gate signal GB may be omitted.

[0092] Figure 4 It is a diagram. Figure 1 A conceptual diagram of the pixel structure of the display panel 100.

[0093] refer to Figures 1 to 4 The display panel 100 includes a plurality of pixels arranged in a matrix.

[0094] In the example embodiment shown, pixels in a pixel column can be alternately connected to adjacent data lines (e.g., two adjacent data lines). For example, pixels in this pixel column can be alternately connected to odd-numbered and even-numbered data lines.

[0095] For example, first pixel P11, second pixel P21, third pixel P31, and fourth pixel P41 are arranged sequentially in the first pixel column of the display panel 100, wherein the first pixel P11 and the third pixel P31 are connected to the first data line DL1 (odd-numbered data line), and the second pixel P21 and the fourth pixel P41 are connected to the second data line DL2 (even-numbered data line). In one or more example embodiments, the first pixel P12 and the third pixel P32 arranged in the second pixel column of the display panel 100 may be connected to the third data line DL3, and the second pixel P22 and the fourth pixel P42 arranged in the second pixel column may be connected to the fourth data line DL4. In one or more example embodiments, the first pixel P13 and the third pixel P33 arranged in the third pixel column of the display panel 100 may be connected to the fifth data line DL5, and the second pixel P23 and the fourth pixel P43 arranged in the third pixel column may be connected to the sixth data line DL6. In one or more example embodiments, the first pixel P14 and the third pixel P34 among the pixels arranged in the fourth pixel column of the display panel 100 can be connected to the seventh data line DL7, and the second pixel P24 and the fourth pixel P44 among the pixels arranged in the fourth pixel column can be connected to the eighth data line DL8.

[0096] Figure 5 It is a diagram. Figure 1 A plan view of the hole HL, the area around the hole, and the normal area of ​​the display panel 100. Figure 6 It is a diagram. Figure 5 A plan view of the aperture HL, the first gate layer GAT1, the second gate layer GAT2, the third gate layer GAT3, the first source-drain layer SD1, and the second source-drain layer SD2.

[0097] refer to Figures 1 to 6 The display panel 100 includes an effective area AA for displaying images and a peripheral area PA surrounding the effective area AA.

[0098] A hole HL can be arranged in the effective area AA. The hole HL can be formed to correspond to the position of the camera module of the display device. In one or more example embodiments, the hole HL can overlap with the camera module of the display device. The hole HL can refer to a hole physically formed in the substrate of the display panel 100. In one or more example embodiments, only transparent elements are arranged in the hole HL.

[0099] The display panel 100 may include multiple gate layers GAT1, GAT2 and GAT3 and multiple source-drain layers SD1 and SD2. The multiple gate layers GAT1, GAT2 and GAT3 include gate patterns extending in a first direction D1, and the multiple source-drain layers SD1 and SD2 include source-drain patterns extending in a second direction D2.

[0100] The gate patterns of gate layers GAT1, GAT2, and GAT3, which do not pass through the region where the aperture HL is formed (e.g., the region including the aperture HL), extend linearly in the first direction D1. In one or more example embodiments, when in such... Figure 6 When viewed in the plan view shown, the gate patterns of the second gate layer GAT2 and the third gate layer GAT3, which do not pass through the region where the aperture HL is formed, overlap. In one or more example embodiments, the gate patterns of gate layers GAT1, GAT2, and GAT3, which pass through the region where the aperture HL is formed (i.e., through the region including the aperture HL and the region surrounding the aperture HL), extend linearly in the first direction D1 in the normal region where the aperture HL is not formed, and the gate patterns of gate layers GAT1, GAT2, and GAT3 curl or bend along the periphery (e.g., outer periphery) of the aperture HL in the region surrounding the aperture (i.e., the region surrounding the aperture HL). In one or more example embodiments, the region surrounding the aperture is adjacent to (e.g., directly adjacent to) the aperture HL. In one or more example embodiments, the region surrounding the aperture borders the aperture HL.

[0101] The source-drain patterns of source-drain layers SD1 and SD2 that do not pass through the region where the aperture HL is formed (e.g., the region including the aperture HL) extend linearly in the second direction D2. In one or more example embodiments, the source-drain patterns of source-drain layers SD1 and SD2 that pass through the region where the aperture HL is formed (i.e., the region including the aperture HL and the region surrounding the aperture HL) extend linearly in the second direction D2 in the normal region where the aperture HL is not formed, and the source-drain patterns of source-drain layers SD1 and SD2 curl or bend along the periphery of the aperture HL in the region surrounding the aperture (i.e., the region surrounding the aperture HL).

[0102] In one or more example embodiments, when from Figure 6 When viewed in the plan view shown in the embodiment, the first source-drain layer SD1 and the second source-drain layer SD2 can extend in the normal region along the second direction D2 and be alternately arranged along the first direction D1. In one or more example embodiments, when viewed from... Figure 6 When viewed in the plan view shown in the embodiment, the first gate layer GAT1 and the third gate layer GAT3 can extend in the normal region along the first direction D1 and be alternately arranged along the second direction D2. In one or more example embodiments, when viewed from... Figure 6When viewed in the plan view shown in the embodiment, the first gate layer GAT1 and the second gate layer GAT2 can extend in the normal region in the first direction D1 and be alternately arranged in the second direction D2.

[0103] The portion of the gate patterns of gate layers GAT1, GAT2, and GAT3, or the source-drain patterns of source-drain layers SD1 and SD2, that is curled or bent due to the via HL, can be defined as the area around the via.

[0104] Figure 7 It is shown in the diagram along Figure 6 The cross-sectional view of the display panel 100 taken by line A-A'. Figure 8 It is shown in the diagram along Figure 6 The cross-sectional view of the display panel 100 taken by line B-B'. Figure 9 It is shown in the diagram along Figure 6 The cross-sectional view of the display panel 100 taken by line C-C'.

[0105] Line A-A' represents the cross-sectional structure of source-drain layers SD1 and SD2 in the normal region where the via HL is not formed. Line B-B' represents the cross-sectional structure of gate layers GAT1, GAT2, and GAT3 in the normal region where the via HL is not formed. Line C-C' represents the cross-sectional structure of gate layers GAT1, GAT2, and GAT3, and source-drain layers SD1 and SD2 in the region surrounding the via (i.e., the region around the via HL).

[0106] refer to Figures 1 to 9 The display panel 100 includes: a substrate layer PI, a barrier layer BR disposed on the substrate layer PI, a first gate insulating layer GI1 disposed on the barrier layer BR, a first gate layer GAT1 disposed on the first gate insulating layer GI1, a second gate insulating layer GI2 disposed on the first gate layer GAT1 and / or the first gate insulating layer GI1, a second gate layer GAT2 disposed on the second gate insulating layer GI2, a first passivation layer ILD1 disposed on the second gate layer GAT2 and / or the second gate insulating layer GI2, and a first passivation layer ILD1 disposed on the first passivation layer ILD1. The third gate layer GAT3 on LD1, the second passivation layer ILD2 disposed on the third gate layer GAT3 and / or the first passivation layer ILD1, the first source-drain layer SD1 disposed on the second passivation layer ILD2, the first organic insulating layer VIA1 disposed on the first source-drain layer SD1 and / or the second passivation layer ILD2, the second source-drain layer SD2 disposed on the first organic insulating layer VIA1, and the second organic insulating layer VIA2 disposed on the second source-drain layer SD2 and / or the first organic insulating layer VIA1.

[0107] The substrate layer PI may include polyimide. The barrier layer BR may include inorganic materials. The thickness of the barrier layer BR may be between approximately 800 nm and approximately 900 nm.

[0108] The first gate insulating layer GI1 and the second gate insulating layer GI2 may comprise inorganic materials. The thickness of the first gate insulating layer GI1 may be approximately 150 nm. The thickness of the second gate insulating layer GI2 may be approximately 150 nm.

[0109] The first passivation layer ILD1 and the second passivation layer ILD2 may comprise inorganic materials. The thickness of the first passivation layer ILD1 and the thickness of the second passivation layer ILD2 may be greater than the thickness of the first gate insulating layer GI1 and the thickness of the second gate insulating layer GI2. The thickness of the first passivation layer ILD1 may be between approximately 400 nm and approximately 500 nm. The thickness of the second passivation layer ILD2 may be between approximately 400 nm and approximately 500 nm.

[0110] The first organic insulating layer VIA1 and the second organic insulating layer VIA2 may comprise organic insulating materials. The thickness of the first organic insulating layer VIA1 and the thickness of the second organic insulating layer VIA2 may be greater than the thickness of the first gate insulating layer GI1 and the thickness of the second gate insulating layer GI2. The thickness of the first organic insulating layer VIA1 and the thickness of the second organic insulating layer VIA2 may be greater than the thickness of the first passivation layer ILD1 and the thickness of the second passivation layer ILD2. The thickness of the first organic insulating layer VIA1 may be between approximately 1.5 μm and approximately 2 μm. The thickness of the second organic insulating layer VIA2 may be between approximately 1.5 μm and approximately 2 μm.

[0111] In an example embodiment, the first passivation layer ILD1 can be replaced by a third gate insulating layer. In this document, the third gate insulating layer may comprise an inorganic material. The thickness of the third gate insulating layer may be approximately 150 nm.

[0112] like Figure 7 As shown, in the normal region, the first source-drain layer SD1 and the second source-drain layer SD2 may not overlap in the thickness direction.

[0113] The first source-drain layer SD1 may include Figure 4 The pixel structure includes odd-numbered data lines DL1, DL3, DL5, and DL7. The second source-drain layer SD2 may include... Figure 4 The even-numbered data lines DL2, DL4, DL6, and DL8 in the pixel structure. In the normal region, the odd-numbered data lines DL1, DL3, DL5, and DL7 can not overlap with the even-numbered data lines DL2, DL4, DL6, and DL8, so that the first source-drain layer SD1 and the second source-drain layer SD2 can not overlap in the thickness direction in the normal region.

[0114] On the contrary, such as Figure 9As shown, in the region surrounding the aperture, the first source-drain layer SD1 and the second source-drain layer SD2 may overlap in the thickness direction. In the region surrounding the aperture, the first source-drain layer SD1 and the second source-drain layer SD2 are not connected to pixels. According to one or more example embodiments, the patterns on the first source-drain layer SD1 and the second source-drain layer SD2 are curled or bent in the region surrounding the aperture to bypass the aperture HL.

[0115] In the region surrounding the aperture, the first source-drain layer SD1 and the second source-drain layer SD2 can overlap in the thickness direction, thereby reducing the dead zone caused by (or defined by) the aperture HL.

[0116] The horizontal spacing of adjacent data lines on the first source-drain layer SD1 in the area surrounding the via can be smaller than the horizontal spacing of adjacent data lines on the first source-drain layer SD1 in the normal area. Similarly, the horizontal spacing of adjacent data lines on the second source-drain layer SD2 in the area surrounding the via can be smaller than the horizontal spacing of adjacent data lines on the second source-drain layer SD2 in the normal area. Therefore, the dead zone caused by the via HL can be further reduced in the area surrounding the via.

[0117] like Figure 8 As shown, in the normal region, the second gate layer GAT2 and the third gate layer GAT3 can overlap in the thickness direction, and in the normal region, the first gate layer GAT1 can not overlap with the second gate layer GAT2 and the third gate layer GAT3 in the thickness direction.

[0118] The first gate layer GAT1 may include outputting the P-type gate signal GWP to... Figure 2 The P-type gate line GWPL of the P-type transistor. The second gate layer GAT2 may include the back gate electrode of the P-type or N-type transistor and the connection line of the back gate electrode. The third gate layer GAT3 may include outputting the N-type gate signal GWN to Figure 2 The N-type gate line GWNL of the N-type transistor. In one or more example embodiments, the second gate layer GAT2 may include a memory electrode overlapping the first gate layer GAT1.

[0119] In the normal region, the first gate layer GAT1 and the second gate layer GAT2 can output gate signals with different waveforms. Therefore, it is desirable that the first gate layer GAT1 and the second gate layer GAT2 do not overlap in the thickness direction to prevent or reduce signal coupling. In other words, the first gate layer GAT1 and the second gate layer GAT2 can not overlap in the thickness direction to prevent or reduce the possibility of gate signal coupling.

[0120] On the contrary, such as Figure 9As shown, in the region surrounding the aperture, the first gate layer GAT1, the second gate layer GAT2, and the third gate layer GAT3 may overlap each other in the thickness direction. In the region surrounding the aperture, the patterns on the first gate layer GAT1, the second gate layer GAT2, and the third gate layer GAT3 are curled or bent to bypass the aperture HL.

[0121] In the region surrounding the aperture, the first gate layer GAT1, the second gate layer GAT2, and the third gate layer GAT3 can overlap each other in the thickness direction, thereby reducing the dead zone caused by the aperture HL.

[0122] The horizontal spacing of adjacent gate lines on the first gate layer GAT1 in the peri-hole region can be smaller than the horizontal spacing of adjacent gate lines on the first gate layer GAT1 in the normal region. The horizontal spacing of adjacent connection lines of the back gate electrode on the second gate layer GAT2 in the peri-hole region can be smaller than the horizontal spacing of adjacent connection lines of the back gate electrode on the second gate layer GAT2 in the normal region. The horizontal spacing of adjacent gate lines on the third gate layer GAT3 in the peri-hole region can be smaller than the horizontal spacing of adjacent gate lines on the third gate layer GAT3 in the normal region. Therefore, the dead zone caused by the via HL can be further reduced in the peri-hole region.

[0123] Furthermore, in the illustrated example embodiment, in the region surrounding the via, the first gate layer GAT1, the second gate layer GAT2, the third gate layer GAT3, the first source-drain layer SD1, and the second source-drain layer SD2 may overlap each other in the thickness direction. Therefore, the dead zone caused by the via HL can be further reduced in the region surrounding the via.

[0124] Despite Figure 9 As shown, the first gate layer GAT1, the second gate layer GAT2, the third gate layer GAT3, the first source-drain layer SD1, and the second source-drain layer SD2 may overlap each other in the thickness direction in the region around the via to reduce the dead zone caused by the via HL. However, in one or more example embodiments, one or more of the first gate layer GAT1, the second gate layer GAT2, the third gate layer GAT3, the first source-drain layer SD1, and the second source-drain layer SD2 may not overlap with other layers.

[0125] According to the example embodiment shown, when the hole HL is formed in the effective area AA of the display panel 100, and the patterns on the gate layers GAT1, GAT2 and GAT3 and the source-drain layers SD1 and SD2 bypass the hole HL in the area surrounding the hole, the patterns on the gate layers GAT1, GAT2 and GAT3 and the source-drain layers SD1 and SD2 overlap each other in the thickness direction, so that the dead zone adjacent to the area surrounding the hole can be reduced.

[0126] Figure 10This is a plan view illustrating a hole, a region surrounding the hole, and a normal region in a display panel according to an exemplary embodiment of the present invention. Figure 11 It is shown in the diagram along Figure 10 The cross-sectional view of the display panel is taken by line C-C'.

[0127] A display panel according to the example embodiment shown, and a display device including the display panel and reference. Figures 1 to 9 The display panel and display device including the previously described example embodiment are substantially the same, except for the layer structure of the display panel in the area surrounding the hole. Therefore, the same reference numerals will be used to refer to the same... Figures 1 to 9 The parts described in the previous example embodiments are the same or similar to the parts described above, and any repeated or redundant descriptions of the above elements may be omitted.

[0128] refer to Figures 1 to 5 , Figure 7 , Figure 8 , Figure 10 and Figure 11 The display device includes a display panel 100 and a display panel driver. The display panel driver includes a drive controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and a transmit driver 600.

[0129] The display panel 100 includes an effective area AA for displaying images and a peripheral area PA surrounding the effective area AA. An aperture HL can be arranged within the effective area AA. The aperture HL can be formed to correspond to the position of the camera module of the display device.

[0130] The display panel 100 may include multiple gate layers GAT1, GAT2 and GAT3 and multiple source-drain layers SD1 and SD2. The multiple gate layers GAT1, GAT2 and GAT3 include gate patterns extending in a first direction D1, and the multiple source-drain layers SD1 and SD2 include source-drain patterns extending in a second direction D2.

[0131] The display panel 100 includes: a substrate layer PI, a barrier layer BR disposed on the substrate layer PI, a first gate insulating layer GI1 disposed on the barrier layer BR, a first gate layer GAT1 disposed on the first gate insulating layer GI1, a second gate insulating layer GI2 disposed on the first gate layer GAT1 and / or the first gate insulating layer GI1, a second gate layer GAT2 disposed on the second gate insulating layer GI2, a first passivation layer ILD1 disposed on the second gate layer GAT2 and / or the second gate insulating layer GI2, a third gate layer GAT3 disposed on the first passivation layer ILD1, a second passivation layer ILD2 disposed on the third gate layer GAT3 and / or the first passivation layer ILD1, a first source-drain layer SD1 disposed on the second passivation layer ILD2, a first organic insulating layer VIA1 disposed on the first source-drain layer SD1 and / or the second passivation layer ILD2, a second source-drain layer SD2 disposed on the first organic insulating layer VIA1, and a second organic insulating layer VIA2 disposed on the second source-drain layer SD2 and / or the first organic insulating layer VIA1.

[0132] like Figure 11 As shown, the display panel 100 may further include a third organic insulating layer VIA3 disposed only in the area around the hole and disposed between the second gate insulating layer GI2 and the second gate layer GAT2.

[0133] The first organic insulating layer VIA1, the second organic insulating layer VIA2, and the third organic insulating layer VIA3 may comprise organic insulating materials. The thicknesses of the first organic insulating layer VIA1, the second organic insulating layer VIA2, and the third organic insulating layer VIA3 may be greater than the thicknesses of the first gate insulating layer GI1 and the second gate insulating layer GI2. The thicknesses of the first organic insulating layer VIA1, the second organic insulating layer VIA2, and the third organic insulating layer VIA3 may be greater than the thicknesses of the first passivation layer ILD1 and the second passivation layer ILD2. The thickness of the first organic insulating layer VIA1 may be between approximately 1.5 μm and approximately 2 μm. The thickness of the second organic insulating layer VIA2 may be between approximately 1.5 μm and approximately 2 μm. The thickness of the third organic insulating layer VIA3 may be between approximately 1.5 μm and approximately 2 μm.

[0134] In the illustrated example embodiment, in the region surrounding the via, the first gate layer GAT1, the second gate layer GAT2, the third gate layer GAT3, the first source-drain layer SD1, and the second source-drain layer SD2 may overlap each other in the thickness direction. Therefore, the dead zone caused by the via HL can be reduced in the region surrounding the via.

[0135] The first gate layer GAT1 and the second gate layer GAT2 can output gate signals with different waveforms. In this case, it is desirable to reduce or prevent coupling between the first gate layer GAT1 and the second gate layer GAT2. Therefore, when the first gate layer GAT1 and the second gate layer GAT2 overlap each other in the thickness direction, coupling between the first gate layer GAT1 and the second gate layer GAT2 can occur. Therefore, as... Figure 11 As shown, a third organic insulating layer VIA3 may be formed between the first gate layer GAT1 and the second gate layer GAT2, thereby preventing or reducing coupling between the first gate layer GAT1 and the second gate layer GAT2. In one or more example embodiments, the third organic insulating layer VIA3 has a thickness sufficient to prevent or substantially prevent coupling between the first gate layer GAT1 and the second gate layer GAT2.

[0136] According to the example embodiment shown, when the hole HL is formed in the effective area AA of the display panel 100, and the patterns on the gate layers GAT1, GAT2 and GAT3 and the source-drain layers SD1 and SD2 bypass the hole HL in the area surrounding the hole, the patterns on the gate layers GAT1, GAT2 and GAT3 and the source-drain layers SD1 and SD2 overlap each other in the thickness direction, so that the dead zone adjacent to the area surrounding the hole can be reduced.

[0137] Figure 12 This is a cross-sectional view illustrating the area around the hole in a display panel according to an exemplary embodiment of the present invention.

[0138] A display panel according to the example embodiment shown, and a display device including the display panel and reference. Figures 1 to 9 The display panel and display device including the previously described example embodiment are substantially the same or similar, except for the layer structure of the display panel in the area surrounding the aperture. Therefore, the same reference numerals will be used to refer to... Figures 1 to 9 The parts described in the previous example embodiments are the same or similar to the parts described above, and any repeated or redundant descriptions of the above elements may be omitted.

[0139] refer to Figures 1 to 8 as well as Figure 12 The display device includes a display panel 100 and a display panel driver. The display panel driver includes a drive controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and a transmit driver 600.

[0140] The display panel 100 includes an effective area AA for displaying images and a peripheral area PA surrounding the effective area AA. An aperture HL can be arranged within the effective area AA. The aperture HL can be formed to correspond to the position of the camera module of the display device.

[0141] The display panel 100 may include multiple gate layers GAT1, GAT2 and GAT3 and multiple source-drain layers SD1 and SD2. The multiple gate layers GAT1, GAT2 and GAT3 include gate patterns extending in a first direction D1, and the multiple source-drain layers SD1 and SD2 include source-drain patterns extending in a second direction D2.

[0142] The display panel 100 includes: a substrate layer PI, a barrier layer BR disposed on the substrate layer PI, a first gate insulating layer GI1 disposed on the barrier layer BR, a first gate layer GAT1 disposed on the first gate insulating layer GI1, a second gate insulating layer GI2 disposed on the first gate layer GAT1 and / or the first gate insulating layer GI1, a second gate layer GAT2 disposed on the second gate insulating layer GI2, a first passivation layer ILD1 disposed on the second gate layer GAT2 and / or the second gate insulating layer GI2, a third gate layer GAT3 disposed on the first passivation layer ILD1, a second passivation layer ILD2 disposed on the third gate layer GAT3 and / or the first passivation layer ILD1, a first source-drain layer SD1 disposed on the second passivation layer ILD2, a first organic insulating layer VIA1 disposed on the first source-drain layer SD1 and / or the second passivation layer ILD2, a second source-drain layer SD2 disposed on the first organic insulating layer VIA1, and a second organic insulating layer VIA2 disposed on the second source-drain layer SD2 and / or the first organic insulating layer VIA1.

[0143] like Figure 8 As shown, in the normal region, the second gate layer GAT2 can overlap with the third gate layer GAT3 in the thickness direction, and in the normal region, the first gate layer GAT1 can not overlap with the second gate layer GAT2 and the third gate layer GAT3 in the thickness direction.

[0144] like Figure 12 As shown, in the region around the aperture, the second gate layer GAT2 may overlap with the third gate layer GAT3 in the thickness direction, and in the region around the aperture, the first gate layer GAT1 may not overlap with the second gate layer GAT2 and the third gate layer GAT3 in the thickness direction.

[0145] In the illustrated example embodiment, the second gate layer GAT2, the third gate layer GAT3, the first source-drain layer SD1, and the second source-drain layer SD2 may overlap each other in the thickness direction in the region surrounding the hole. Therefore, the dead zone caused by the hole HL can be reduced in the region surrounding the hole.

[0146] The first gate layer GAT1 and the second gate layer GAT2 output gate signals with different waveforms. In this case, it is desirable to prevent or reduce coupling between the first gate layer GAT1 and the second gate layer GAT2. In the example embodiment shown, the patterns on the first gate layer GAT1 and the second gate layer GAT2 can be arranged alternately, such that the distance between the patterns on the first gate layer GAT1 and the patterns on the second gate layer GAT2 can be greater than [missing information]. Figure 9 The distance between the pattern on the first gate layer GAT1 and the pattern on the second gate layer GAT2 in the vertically overlapping structure is considered. Therefore, coupling between the first gate layer GAT1 and the second gate layer GAT2 can be prevented or reduced.

[0147] According to the example embodiment shown, when the hole HL is formed in the effective area AA of the display panel 100, and the patterns on the gate layers GAT1, GAT2 and GAT3 and the source-drain layers SD1 and SD2 bypass the hole HL in the area around the hole, a portion of the patterns on the gate layers GAT2 and GAT3 and the source-drain layers SD1 and SD2 overlap each other in the thickness direction, thereby reducing the dead zone adjacent to the area around the hole.

[0148] Figure 13 This is a conceptual diagram illustrating the pixel structure of a display panel according to an exemplary embodiment of the present invention. Figure 14 It is a diagram. Figure 13 A cross-sectional view of the area surrounding the holes in the display panel.

[0149] The display surface and display device including the display panel according to the example embodiment shown are referenced. Figures 1 to 9 The display panel and display device including the previously described example embodiment are substantially the same, except for the pixel structure of the display panel and the layer structure of the display panel in the area surrounding the holes. Therefore, the same reference numerals will be used to refer to the same... Figures 1 to 9 The parts described in the previous example embodiments are the same or similar to the parts described above, and any repeated or redundant descriptions of the above elements may be omitted.

[0150] refer to Figures 1 to 3 , Figure 5 , Figure 8 , Figure 13 and Figure 14 The display device includes a display panel 100 and a display panel driver. The display panel driver includes a drive controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and a transmit driver 600.

[0151] The display panel 100 includes an effective area AA for displaying images and a peripheral area PA surrounding the effective area AA. An aperture HL can be arranged within the effective area AA. The aperture HL can be formed to correspond to the position of the camera module of the display device.

[0152] The display panel 100 may include multiple gate layers GAT1, GAT2 and GAT3 and a source-drain layer SD1. The multiple gate layers GAT1, GAT2 and GAT3 include a gate pattern extending in a first direction D1, and the source-drain layer SD1 includes a source-drain pattern extending in a second direction D2.

[0153] The display panel 100 includes: a substrate layer PI, a barrier layer BR disposed on the substrate layer PI, a first gate insulating layer GI1 disposed on the barrier layer BR, a first gate layer GAT1 disposed on the first gate insulating layer GI1, a second gate insulating layer GI2 disposed on the first gate layer GAT1 and / or the first gate insulating layer GI1, a second gate layer GAT2 disposed on the second gate insulating layer GI2, a first passivation layer ILD1 disposed on the second gate layer GAT2 and / or the second gate insulating layer GI2, a third gate layer GAT3 disposed on the first passivation layer ILD1, a second passivation layer ILD2 disposed on the third gate layer GAT3 and / or the first passivation layer ILD1, a source-drain layer SD1 disposed on the second passivation layer ILD2, and an organic insulating layer VIA1 disposed on the source-drain layer SD1 and / or the second passivation layer ILD2.

[0154] like Figure 13 As shown, the display panel 100 includes a plurality of pixels arranged in a matrix.

[0155] In the example embodiment shown, pixels in a pixel column can be connected to a single data line adjacent to that pixel column.

[0156] For example, pixels P11, P21, P31, and P41 arranged in the first pixel column of the display panel 100 can be connected to the first data line DL1. For example, pixels P12, P22, P32, and P42 arranged in the second pixel column of the display panel 100 can be connected to the second data line DL2. For example, pixels P13, P23, P33, and P43 arranged in the third pixel column of the display panel 100 can be connected to the third data line DL3. For example, pixels P14, P24, P34, and P44 arranged in the fourth pixel column of the display panel 100 can be connected to the fourth data line DL4.

[0157] Figure 14 The source-drain layer SD1 may include a first data line DL1, a second data line DL2, a third data line DL3, and a fourth data line DL4.

[0158] In the illustrated example embodiment, the first gate layer GAT1, the second gate layer GAT2, the third gate layer GAT3, and the source-drain layer SD1 may overlap each other in the thickness direction in the region surrounding the via. Therefore, the dead zone caused by the via HL can be reduced in the region surrounding the via.

[0159] According to the example embodiment shown, when the hole HL is formed in the effective area AA of the display panel 100, and the patterns on the gate layers GAT1, GAT2 and GAT3 and the source-drain layer SD1 bypass the hole HL in the area surrounding the hole, the patterns on the gate layers GAT1, GAT2 and GAT3 and the source-drain layer SD1 overlap each other in the thickness direction, so that the dead zone adjacent to the area surrounding the hole can be reduced.

[0160] According to aspects of the exemplary embodiments of the inventive concept described above, the dead zone around the holes in the effective area of ​​the display panel can be reduced.

[0161] The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to limit the example embodiments described herein.

[0162] As used herein, the singular forms “a” and “the (said)” are intended to also include the plural forms, unless the context clearly indicates otherwise.

[0163] It will be further understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the stated features, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups thereof.

[0164] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0165] Furthermore, when describing embodiments of this disclosure, the use of "may" refers to "one or more exemplary embodiments of this disclosure".

[0166] It will be understood that when an element is referred to as being “on,” “connected,” or “coupled” to another element, the element may be directly on, directly connected to, or directly coupled to the other element, or there may be one or more intermediate elements. When an element is referred to as being “directly on,” “directly connected to,” or “directly coupled” to another element, there are no intermediate elements.

[0167] As used herein, the terms “substantially,” “approximately,” and similar terms are used as terms of approximation and not as terms of degree, and are intended to take into account the inherent biases in the measured or calculated values ​​that would be recognized by one of ordinary skill in the art.

[0168] Any numerical range described herein is intended to include all sub-intervals containing the same numerical precision within the described range. For example, the range “between 1.0 and 10.0” is intended to include all sub-intervals between the described minimum value of 1.0 and the described maximum value of 10.0 (and inclusive of both), that is, having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, for example, between 2.4 and 7.6. Any maximum numerical limit described herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit described herein is intended to include all higher numerical limits contained therein. Therefore, the applicant reserves the right to amend this specification (including the claims) to clearly state any sub-intervals contained within the range clearly described herein.

[0169] The term “use” and its variants, as used in this article, can be considered synonymous with the term “utilize” and its variants, respectively.

[0170] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in common dictionaries should be interpreted as having the same meaning as they have in the relevant field and / or the context of this specification, and should not be interpreted in an idealized or overly formal sense, unless expressly so defined herein.

[0171] As used herein, phrases such as “plan view” can refer to a view from the top or from a direction orthogonal to the display surface of the display panel. “Thickness direction” can refer to a direction orthogonal to or perpendicular to the display surface of the display panel.

[0172] The foregoing is illustrative of the inventive concept and is not intended to limit it. Although some exemplary embodiments of the inventive concept have been described, those skilled in the art will readily understand that many modifications are possible to the exemplary embodiments without departing from the novel doctrine and aspects of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. Accordingly, it should be understood that the foregoing is illustrative of the inventive concept and should not be construed as limiting it to the specific exemplary embodiments disclosed, and modifications to the disclosed exemplary embodiments and other exemplary embodiments are intended to be included within the scope of the appended claims. The inventive concept is defined by the following claims, and equivalents of the claims are included within the inventive concept.

Claims

1. A display panel, comprising: Two or more gate layers, including multiple gate patterns extending in a first direction; as well as One or more source-drain layers, comprising a plurality of source-drain patterns extending in a second direction intersecting the first direction. The grid patterns of the two or more grid layers are curled or bent along the area surrounding the holes corresponding to the periphery of the holes in the effective region. The source-drain pattern of one or more source-drain layers curls or bends along the region surrounding the aperture, and In the region surrounding the aperture, the gate pattern of at least one of the two or more gate layers overlaps with the source-drain pattern of at least one of the one or more source-drain layers in the thickness direction of the display panel. The display panel further includes a first gate insulating layer, a second gate insulating layer, a first passivation layer, a second passivation layer, a first organic insulating layer, and a second organic insulating layer. The two or more gate layers further include a first gate layer, a second gate layer, and a third gate layer. The one or more source-drain layers further include a first source-drain layer and a second source-drain layer. The first gate layer is located on the first gate insulating layer; The second gate insulating layer is located on the first gate layer; The second gate layer is located on the second gate insulating layer; The first passivation layer is located on the second gate layer; The third gate layer is located on the first passivation layer; The second passivation layer is located on the third gate layer; The first source-drain layer is located on the second passivation layer; The first organic insulating layer is located on the first source-drain layer; The second source-drain layer is located on the first organic insulating layer; and The second organic insulating layer is located on the second source-drain layer.

2. The display panel according to claim 1, wherein, In the region surrounding the aperture, the first gate layer, the second gate layer, the third gate layer, the first source-drain layer, and the second source-drain layer overlap each other in the thickness direction.

3. The display panel of claim 2, further comprising a third organic insulating layer in the region surrounding the hole and located between the second gate insulating layer and the second gate layer.

4. The display panel according to claim 1, wherein, In the region surrounding the aperture, the second gate layer, the third gate layer, the first source-drain layer, and the second source-drain layer overlap each other in the thickness direction, and In the region surrounding the hole, the first gate layer does not overlap with the second gate layer in the thickness direction.

5. A display panel, comprising: Two or more gate layers, including multiple gate patterns extending in a first direction; as well as One or more source-drain layers, comprising a plurality of source-drain patterns extending in a second direction intersecting the first direction. The grid patterns of the two or more grid layers are curled or bent along the area surrounding the holes corresponding to the periphery of the holes in the effective region. The source-drain pattern of one or more source-drain layers curls or bends along the region surrounding the aperture, and In the region surrounding the aperture, the gate pattern of at least one of the two or more gate layers overlaps with the source-drain pattern of at least one of the one or more source-drain layers in the thickness direction of the display panel. The display panel further includes a first gate insulating layer, a second gate insulating layer, a first passivation layer, a second passivation layer, and an organic insulating layer; the two or more gate layers further include a first gate layer, a second gate layer, and a third gate layer; and the one or more source-drain layers further include a source-drain layer, wherein: The first gate layer is located on the first gate insulating layer; The second gate insulating layer is located on the first gate layer; The second gate layer is located on the second gate insulating layer; The first passivation layer is located on the second gate layer; The third gate layer is located on the first passivation layer; The second passivation layer is located on the third gate layer; The source-drain layer is located on the second passivation layer; and The organic insulating layer is located on the source-drain layer.

6. The display panel according to claim 5, wherein, In the region surrounding the aperture, the first gate layer, the second gate layer, the third gate layer, and the source-drain layer overlap each other in the thickness direction.

7. A display device, comprising: A display panel includes: two or more gate layers, each including a plurality of gate patterns extending in a first direction; one or more source-drain layers, each including a plurality of source-drain patterns extending in a second direction intersecting the first direction; and a plurality of pixels connected to the plurality of gate patterns and the plurality of source-drain patterns. A gate driver is configured to provide gate signals to the display panel; A data driver is configured to provide a data voltage to the display panel; and A transmitter driver is configured to provide a transmit signal to the display panel. The grid patterns of the two or more grid layers are curled or bent along the area surrounding the holes corresponding to the periphery of the holes in the effective area of ​​the display panel. The source-drain pattern of one or more source-drain layers curls or bends along the region surrounding the aperture, and In the region surrounding the hole, the gate pattern of at least one of the two or more gate layers overlaps with the source-drain pattern of at least one of the one or more source-drain layers in the thickness direction of the display panel.

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