Solar cell and manufacturing method thereof

Abstract

The invention discloses a solar cell and a manufacturing method thereof. The solar cell comprises a substrate, an epitaxial structure, a back electrode, an ohmic contact layer, a grid line electrode, a top electrode and a transparent conductive layer. The epitaxial structure is arranged on one side surface of the substrate. The back electrode is arranged on the surface of the side, away from the epitaxial structure, of the substrate. The ohmic contact layer is arranged on the surface, away from the substrate, of the epitaxial structure and provided with a channel exposing part of the surface of the epitaxial structure. The grid line electrode is arranged in the channel, and the top electrode is connected with the grid line electrode. The transparent conducting layer at least covers the ohmic contact layer and the grid line electrode, or the transparent conducting layer at least covers the ohmic contact layer and the grid line electrode, and the surface, away from the substrate, of the grid line electrode is exposed. And the ohmic contact layer, the transparent conductive layer and the grid line electrode form a composite electrode structure, and the three parts act synergistically, so that the effective light receiving area of the cell is maximized.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, and more specifically, to a solar cell and a method for manufacturing the same. Background Technology

[0002] Gallium arsenide (GaAs) solar cells outperform silicon cells in bandgap matching with the solar spectrum, boasting a conversion efficiency approximately twice that of crystalline silicon and greater light sensitivity. Arsenide solar cells (such as GaAs cells) hold an irreplaceable position in space exploration, concentrated photovoltaics (CPV), and certain specialized terrestrial applications due to their high photoelectric conversion efficiency, excellent radiation resistance, and high-temperature resistance. In recent years, with the trend towards higher conversion efficiencies, the highest efficiency of III-V group multijunction solar cells has reached 47%. With high photoelectric conversion efficiency epitaxial technology, conventional chip technology is struggling to match, especially in its integration with grid electrode technology, which has reached a bottleneck. To reduce resistance, the width or thickness of the grid electrodes needs to be increased, but this blocks more incident light, reducing the effective light-absorbing area of ​​the cell and thus decreasing the short-circuit current (Jsc). This is a typical "resistance-shading" trade-off. Existing solutions, such as using thinner grid lines or optimizing grid patterns, are approaching their physical limits. Furthermore, the traditional combination of grid line electrodes and top electrodes can only reduce current congestion by widening the grid line electrodes, but widening the grid line electrodes increases the light-blocking area. Therefore, there is an urgent need for a new electrode structure that can minimize the obstruction of incident light. Summary of the Invention

[0003] In view of this, the present invention provides a solar cell and a method for manufacturing the same, which can minimize the obstruction of incident light.

[0004] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0005] A solar cell comprising

[0006] Substrate;

[0007] An epitaxial structure, wherein the epitaxial structure is disposed on one side surface of the substrate;

[0008] A back electrode is disposed on the surface of the substrate facing away from the epitaxial structure.

[0009] An ohmic contact layer is disposed on the surface of the epitaxial structure opposite to the substrate, and has channels that expose a portion of the surface of the epitaxial structure.

[0010] A grid line electrode, wherein the grid line electrode is disposed within the channel;

[0011] A top electrode, which is connected to the gate line electrode;

[0012] A transparent conductive layer, wherein the transparent conductive layer at least covers the ohmic contact layer and the gate electrode, or the transparent conductive layer at least covers the ohmic contact layer and the gate electrode, and exposes the surface of the gate electrode facing away from the substrate.

[0013] Furthermore, the height of the gate electrode away from the substrate is higher than or does not exceed the height of the ohmic contact layer away from the substrate.

[0014] Further, the gate electrode does not contact the ohmic contact layer; or, at least a portion of the sidewall of the gate electrode contacts the ohmic contact layer; or, a portion of the surface of the gate electrode facing the substrate contacts the ohmic contact layer; or, at least a portion of the sidewall and a portion of the surface of the gate electrode facing the substrate contact the ohmic contact layer.

[0015] Furthermore, the surface of the epitaxial structure facing away from the substrate is a window layer; the material of the ohmic contact layer is the same as that of the window layer; the resistance of the ohmic contact layer is less than that of the window layer; the ohmic contact layer forms an ohmic contact with the transparent conductive layer, or the ohmic contact layer forms an ohmic contact with the transparent conductive layer and the gate electrode; the window layer does not form an ohmic contact with the transparent conductive layer and the gate electrode.

[0016] Furthermore, the window layer and the ohmic contact layer are GaInP layers; the P-type doping concentration of the ohmic contact layer is greater than that of the window layer, and the P-type doping concentration of the ohmic contact layer is greater than 5 × 10⁻⁶. 18 cm -3 ;

[0017] The transparent conductive layer includes one or more of the following: ITO layer, FTO layer, IZO layer, AZO layer, GZO layer, and TCO layer.

[0018] Furthermore, the thickness of the ohmic contact layer is 10nm-50nm, including the endpoint values.

[0019] Furthermore, the top electrode is in contact with the window layer.

[0020] The present invention also provides a method for manufacturing a solar cell, comprising:

[0021] Provide a substrate;

[0022] An epitaxial structure is fabricated on one side surface of the substrate;

[0023] An ohmic contact material layer is grown on an epitaxial structure, and an ohmic contact layer with channels is formed by photolithography and etching steps; the channels expose a portion of the surface of the epitaxial structure.

[0024] Fabricate a top electrode and a gate line electrode; the top electrode is connected to the gate line electrode, and the top electrode and the gate line electrode are disposed within the channel;

[0025] A transparent conductive layer is fabricated, wherein the transparent conductive layer at least covers the ohmic contact layer and the gate electrode, or the transparent conductive layer at least covers the ohmic contact layer and the gate electrode, and exposes the surface of the gate electrode facing away from the substrate;

[0026] A back electrode is fabricated on the side of the substrate away from the epitaxial structure.

[0027] Furthermore, the height of the surface of the gate electrode facing away from the substrate is higher than or does not exceed the height of the surface of the ohmic contact layer facing away from the substrate;

[0028] The surface of the epitaxial structure facing away from the substrate is a window layer;

[0029] The material of the ohmic contact layer is the same as that of the window layer;

[0030] The resistance of the ohmic contact layer is less than the resistance of the window layer;

[0031] The ohmic contact layer forms an ohmic contact with the transparent conductive layer, or the ohmic contact layer forms an ohmic contact with the transparent conductive layer and the gate electrode; the window layer does not form an ohmic contact with the transparent conductive layer and the gate electrode.

[0032] The window layer and the ohmic contact layer are GaInP layers; the P-type doping concentration of the ohmic contact layer is greater than that of the window layer, and the P-type doping concentration of the ohmic contact layer is greater than 5 × 10⁻⁶. 18 cm -3 ;

[0033] The transparent conductive layer includes one or more of the following: ITO layer, FTO layer, IZO layer, AZO layer, GZO layer, and TCO layer.

[0034] Furthermore, after the transparent conductive layer is fabricated, a low-temperature annealing process is performed; the temperature of the low-temperature annealing process does not exceed 400°C.

[0035] Compared with existing technologies, the technical solution provided by this invention has at least the following advantages:

[0036] This application provides a solar cell comprising a substrate, an epitaxial structure, a back electrode, an ohmic contact layer, grid electrodes, a top electrode, and a transparent conductive layer. The epitaxial structure is disposed on one surface of the substrate; the back electrode is disposed on the surface of the substrate opposite to the epitaxial structure; the ohmic contact layer is disposed on the surface of the epitaxial structure opposite to the substrate and has channels exposing a portion of the surface of the epitaxial structure; the grid electrodes are disposed within the channels; the top electrode is connected to the grid electrodes; the transparent conductive layer at least covers the ohmic contact layer and the grid electrodes, or the transparent conductive layer at least covers the ohmic contact layer and the grid electrodes, exposing the surface of the grid electrodes opposite to the substrate. With this configuration, the ohmic contact layer, the transparent conductive layer, and the grid electrodes constitute a composite electrode structure. The ohmic contact layer facilitates better ohmic contact with the transparent conductive layer, and the transparent conductive layer is used for lateral current spreading and light transmission. The transparent conductive layer undertakes part of the current spreading function, preventing excessive current concentration on the lower surface of the grid electrodes. Furthermore, the grid electrodes can be designed to be thinner and more sparse, reducing the light-shielding area of ​​the grid electrodes and increasing the effective light-absorbing area of ​​the solar cell. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0038] Figure 1a This is a schematic diagram of the structure of one embodiment of the solar cell in this application;

[0039] Figure 1b This is a schematic diagram of the structure of one embodiment of the solar cell in this application;

[0040] Figure 2 This is a schematic diagram of another embodiment of the solar cell in this application;

[0041] Figure 3 This is a schematic diagram of another embodiment of the solar cell in this application;

[0042] Figure 4 This is a schematic diagram of another embodiment of the solar cell in this application;

[0043] Figure 5 This is a schematic diagram of another embodiment of the solar cell in this application;

[0044] Figure 6 This is a schematic diagram of another embodiment of the solar cell in this application;

[0045] Figure 7This is a schematic diagram of another embodiment of the solar cell in this application;

[0046] Figure 8 This is a schematic diagram of another embodiment of the solar cell in this application;

[0047] Figure 9 This is a schematic diagram of another embodiment of the solar cell in this application;

[0048] Figure 10 This is a schematic diagram of another embodiment of the solar cell in this application;

[0049] Figure 11 This is a schematic diagram of another embodiment of the solar cell in this application;

[0050] Figure 12 This is a schematic diagram of another embodiment of the solar cell in this application;

[0051] Figure 13 This is a schematic diagram of another embodiment of the solar cell in this application;

[0052] Figure 14 This is a schematic diagram of another embodiment of the solar cell in this application;

[0053] Figure 15 This is a schematic diagram of another embodiment of the solar cell in this application;

[0054] Figure 16 This is a schematic diagram of another embodiment of the solar cell in this application;

[0055] Figure 17 This is a schematic diagram of another embodiment of the solar cell in this application;

[0056] Figure 18 This is a schematic diagram of another embodiment of the solar cell in this application;

[0057] Figure 19 This is a schematic diagram of another embodiment of the solar cell in this application.

[0058] Figure label:

[0059] Substrate 1; Back electrode 2; Ohmic contact layer 3; Gate line electrode 4; Transparent conductive layer 5; Epitaxial structure 100; First subcell 10; Second subcell 20; Third subcell 30; Tunnel junction 50; Buffer layer 60. Detailed Implementation

[0060] To make the content of this invention clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0061] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0062] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included. In this application, unless specifically stated otherwise, all numerical ranges include endpoint values.

[0063] In response to the "resistance-shading" trade-off issue of the grid electrode 4 mentioned in the background art, this application provides a solar cell.

[0064] The solar cell includes a substrate 1, an epitaxial structure 100, a back electrode 2, an ohmic contact layer 3, a grid electrode 4, a top electrode, and a transparent conductive layer 5.

[0065] like Figure 1a , Figure 1b As shown, the epitaxial structure 100 is disposed on one surface of the substrate 1. The back electrode 2 is disposed on the surface of the substrate 1 opposite to the epitaxial structure 100. An ohmic contact layer 3 is disposed on the surface of the epitaxial structure 100 opposite to the substrate 1, and has channels exposing a portion of the surface of the epitaxial structure 100. A gate electrode 4 is disposed within the channels, and a top electrode (not shown) is connected to the gate electrode 4. Figure 1a The transparent conductive layer 5 at least covers the ohmic contact layer 3 and the gate electrode 4. Alternatively, for example... Figure 1bAs shown, the transparent conductive layer 4 at least covers a portion of the surfaces of the ohmic contact layer 3 and the gate electrode 4, exposing the surface of the gate electrode 4 facing away from the substrate 1. The accompanying drawings of this application only illustrate three channels and three gate electrodes; in practical applications, many more can be used. The top electrode has an exposed surface for wiring to achieve current transmission. Optionally, the top electrode can also be disposed within a channel exposing a portion of the surface of the epitaxial structure 100. For example, the top electrode can be disposed in a ring at the upper edge of the surface of the epitaxial structure 100 facing away from the substrate 1, and connected to each gate electrode 4.

[0066] With this configuration, the ohmic contact layer 3, the transparent conductive layer 5, and the grid electrode 4 constitute a composite electrode structure. The ohmic contact layer 3 helps the transparent conductive layer achieve better ohmic contact. The transparent conductive layer 5 is used for lateral current expansion and light transmission. The transparent conductive layer 5 undertakes part of the current expansion function, avoiding excessive current concentration on the lower surface of the grid electrode 4. Furthermore, the grid electrode 4 can be designed to be thinner and more sparse, which can reduce the light-shielding area of ​​the grid electrode 4 and increase the effective light-absorbing area of ​​the solar cell.

[0067] Optionally, the linewidth of the gate electrode 4 can be set to less than 5 micrometers.

[0068] Based on the above embodiments, in a preferred embodiment, the height of the surface of the gate electrode 4 facing away from the substrate 1 is higher than or does not exceed the height of the surface of the ohmic contact layer 3 facing away from the substrate 1. That is, it can be as follows: Figure 1a The surface of the gate electrode 4 facing away from the substrate 1 is higher than the surface of the ohmic contact layer 3 facing away from the substrate 1; or as shown Figure 2 As shown, the surface of the gate electrode 4 facing away from the substrate 1 can be on the same horizontal plane as the surface of the ohmic contact layer 3 facing away from the substrate 1; or, as... Figure 3 As shown, the surface of the gate electrode 4 facing away from the substrate 1 is lower than the surface of the ohmic contact layer 3 facing away from the substrate 1. Specifically, when the height of the surface of the gate electrode 4 facing away from the substrate 1 does not exceed the height of the surface of the ohmic contact layer 3 facing away from the substrate 1, the transparent conductive layer 5 will not bulge after covering the ohmic contact layer 3 and the gate electrode 4, thus avoiding localized breakage of the transparent conductive layer 5 due to bulging, which could lead to poor current transmission and localized current congestion.

[0069] Based on any of the above embodiments, in a preferred embodiment, the gate electrode 4 does not contact the ohmic contact layer 3; or, at least a portion of the sidewall of the gate electrode 4 contacts the ohmic contact layer 3; or, a portion of the surface of the gate electrode 4 facing the substrate 1 contacts the ohmic contact layer 3; or, at least a portion of the sidewall and a portion of the surface of the gate electrode 4 facing the substrate 1 contact the ohmic contact layer 3.

[0070] Figure 4-6 A schematic diagram of a structure is shown where the gate electrode 4 does not contact the ohmic contact layer 3, wherein... Figure 4 The height at which the gate electrode 4 faces away from the surface of the substrate 1 is greater than the height at which the ohmic contact layer 3 faces away from the surface of the substrate 1. Figure 5 The height at which the gate electrode 4 is away from the surface of the substrate 1 is the same as the height at which the ohmic contact layer 3 is away from the surface of the substrate 1. Figure 6 The height of the surface of the gate electrode 4 facing away from the substrate 1 is lower than the height of the surface of the ohmic contact layer 3 facing away from the substrate 1. As shown in the figure, the left and right sidewalls and the top surface of the gate electrode 4 are in contact with the transparent conductive layer 5 structure, and the bottom surface of the gate electrode 4 is in contact with the surface of the epitaxial structure 100 facing away from the substrate 1. Only the left and right sidewalls of the gate electrode 4 are shown in the figure; its front and rear sidewalls can be connected to the top electrode on one side, with the remaining sidewalls in contact with the transparent conductive layer 5, or both the front and rear sidewalls can be connected to the top electrode. In this application, the top surface of the gate electrode 4 is the surface of the gate electrode 4 facing away from the substrate 1, and the bottom surface of the gate electrode 4 is the surface of the gate electrode 4 facing the substrate 1.

[0071] Figure 1a , 2 Figures 3, 7, 8, and 9 show schematic diagrams illustrating the structure in contact between a portion of the sidewall of the gate electrode 4 and the ohmic contact layer 3. Figure 1a , 7 The height at which the gate electrode 4 faces away from the surface of the substrate 1 is greater than the height at which the ohmic contact layer 3 faces away from the surface of the substrate 1. Figure 2 , 8 The height at which the gate electrode 4 is away from the surface of the substrate 1 is the same as the height at which the ohmic contact layer 3 is away from the surface of the substrate 1. Figure 3 , 9 The height at which the surface of the middle gate electrode 4 faces away from the substrate 1 is lower than the height at which the surface of the ohmic contact layer 3 faces away from the substrate 1. From Figure 1a , 2 As shown in Figure 3, the upper surface of the gate electrode 4 is in contact with the transparent conductive layer 5, the lower surface of the gate electrode 4 is in contact with the surface of the epitaxial structure 100 facing away from the substrate 1, and at least part of the left and right sidewalls of the gate electrode 4 are in contact with the ohmic contact layer 3. Figure 1a The middle grid line electrode 4 protrudes above the left and right side walls of the ohmic contact layer 3 and contacts the transparent conductive layer 5. Figure 2 , 3 The left and right sidewalls of the gate electrode 4 are in contact with the ohmic contact layer 3. Only the left and right sidewalls are shown in the diagram; the front and rear sidewalls can be connected to the top electrode on one side and at least in contact with the ohmic contact layer 3 on the other side; or both front and rear sidewalls can be connected to the top electrode; or one front and rear sidewall can be connected to the top electrode on one side and in contact with the transparent conductive layer 5 on the other side. Figure 7 , 8As shown in Figure 9, the left sidewall and upper surface of the gate electrode 4 are in contact with the transparent conductive layer 5, the lower surface of the gate electrode 4 is in contact with the surface of the epitaxial structure 100 facing away from the substrate 1, and at least part of the right sidewall of the gate electrode 4 is in contact with the ohmic contact layer 3. Figure 7 The middle grid line electrode 4 protrudes above the right sidewall of the ohmic contact layer 3 and contacts the transparent conductive layer 5. Figure 8 , 9 The right sidewall of the middle grid electrode 4 is in contact with the ohmic contact layer 3. Only the left and right sidewalls are shown in the sidewall diagram of the grid electrode 4. Its front and rear sidewalls can be connected to the top electrode on one side and at least in contact with the ohmic contact layer 3 on the other side; or both front and rear sidewalls can be connected to the top electrode; or one side of the front and rear sidewalls can be connected to the top electrode and the other side can be in contact with the transparent conductive layer 5.

[0072] Figure 13 , 14 Figure 15 shows a schematic diagram of the structure in which the portion of the surface of the gate electrode 4 facing the substrate 1 contacts the ohmic contact layer 3. Figure 13 The height at which the gate electrode 4 faces away from the surface of the substrate 1 is greater than the height at which the ohmic contact layer 3 faces away from the surface of the substrate 1. Figure 14 The height at which the gate electrode 4 is away from the surface of the substrate 1 is the same as the height at which the ohmic contact layer 3 is away from the surface of the substrate 1. Figure 15 The height of the surface of the gate electrode 4 facing away from the substrate 1 is lower than the height of the surface of the ohmic contact layer 3 facing away from the substrate 1. As shown in the figure, the upper surface and left and right sidewalls of the gate electrode 4 are in contact with the transparent conductive layer 5 structure, and the lower surface of the gate electrode 4 partially contacts the surface of the epitaxial structure 100 facing away from the substrate 1 and partially contacts the ohmic contact layer 3. Only the left and right sidewalls of the gate electrode 4 are shown in the figure; its front and rear sidewalls can be connected to the top electrode on one side and to the transparent conductive layer 5 on the other side; or both front and rear sidewalls can be connected to the top electrode.

[0073] Figure 10 , 11 Figures 12, 16, 17, and 18 show schematic diagrams illustrating the structure in which at least a portion of the sidewalls and the portion of the surface facing the substrate 1 of the gate electrode 4 are in contact with the ohmic contact layer 3. Figure 10 , 16 The height at which the gate electrode 4 faces away from the surface of the substrate 1 is greater than the height at which the ohmic contact layer 3 faces away from the surface of the substrate 1. Figure 11 , 17 The height at which the gate electrode 4 is away from the surface of the substrate 1 is the same as the height at which the ohmic contact layer 3 is away from the surface of the substrate 1. Figure 12 , 18 The height at which the middle gate electrode 4 is away from the surface of the substrate 1 is lower than the height at which the ohmic contact layer 3 is away from the surface of the substrate 1.

[0074] from Figure 10 , 11 As can be seen from Figure 12, at least part of the left and right sidewalls and part of the lower surface of the gate electrode 4 are in contact with the ohmic contact layer 3, part of the lower surface of the gate electrode 4 is in contact with the surface of the epitaxial structure 100 facing away from the substrate 1, and the upper surface of the gate electrode 4 is in contact with the transparent conductive layer 5. Figure 10 The middle grid line electrode 4 protrudes above the left and right side walls of the ohmic contact layer 3 and contacts the transparent conductive layer. Figure 11 , 12 The left and right sidewalls of the middle grid electrode 4 are in contact with the ohmic contact layer 3. Only the left and right sidewalls are shown in the sidewall diagram of the grid electrode 4. Its front and rear sidewalls can be connected to the top electrode on one side and at least in contact with the ohmic contact layer 3 on the other side, or both the front and rear sidewalls can be connected to the top electrode; or the front and rear sidewalls can be connected to the top electrode on one side and in contact with the transparent conductive layer 5 on the other side.

[0075] from Figure 16 , 17 As can be seen from Figure 18, at least a portion of the right sidewall and a portion of the lower surface of the gate electrode 4 are in contact with the ohmic contact layer 3, a portion of the lower surface of the gate electrode 4 is in contact with the surface of the epitaxial structure 100 facing away from the substrate 1, and the upper surface and the left sidewall of the gate electrode 4 are in contact with the transparent conductive layer 5. Figure 16 The middle grid line electrode 4 protrudes above the right side wall of the ohmic contact layer 3 and contacts the transparent conductive layer. Figure 17 , 18 The right sidewall of the middle grid electrode 4 is in contact with the ohmic contact layer 3. Only the left and right sidewalls are shown in the sidewall diagram of the grid electrode 4. Its front and rear sidewalls can be connected to the top electrode on one side and at least in contact with the ohmic contact layer 3 on the other side; or both front and rear sidewalls can be connected to the top electrode; or one side of the front and rear sidewalls can be connected to the top electrode and the other side can be in contact with the transparent conductive layer 5.

[0076] Based on any of the above embodiments, in a preferred embodiment, the surface of the epitaxial structure 100 facing away from the substrate 1 is a window layer; the material of the ohmic contact layer 3 is the same as that of the window layer; the resistance of the ohmic contact layer 3 is less than that of the window layer; the ohmic contact layer 3 forms an ohmic contact with the transparent conductive layer 5, or the ohmic contact layer 3 forms an ohmic contact with the transparent conductive layer 5 and the gate electrode 4; the window layer does not form an ohmic contact with the transparent conductive layer 5 and the gate electrode 4.

[0077] With this configuration, the material of the ohmic contact layer 3 is the same as that of the window layer, which makes the lattice constants of the ohmic contact layer 3 and the window layer match, thus avoiding defects caused by lattice mismatch.

[0078] For example, Figure 4In the example solar cell, the grid electrode 4 does not contact the ohmic contact layer 3; therefore, the ohmic contact layer 3 only forms an ohmic contact with the transparent conductive layer 5. The window layer contacts both the grid electrode 4 and the transparent conductive layer 5; in this case, the window layer does not form an ohmic contact with either the grid electrode 4 or the transparent conductive layer 5. Figure 1a In the example solar cell, the grid electrode 4 is in contact with both the ohmic contact layer 3 and the transparent conductive layer 5. In this case, the ohmic contact layer 3 can form ohmic contacts with both the grid electrode 4 and the transparent conductive layer 5. The window layer is in contact with the grid electrode 4 but not with the transparent conductive layer 5; therefore, the window layer and the grid electrode 4 do not form an ohmic contact.

[0079] More preferably, the window layer and the ohmic contact layer 3 are GaInP layers; the P-type doping concentration of the ohmic contact layer 3 is greater than that of the window layer, and the P-type doping concentration of the ohmic contact layer 3 is greater than 5 × 10⁻⁶. 18 cm -3 The transparent conductive layer 5 includes one or more of the following: ITO layer, FTO layer, IZO layer, AZO layer, GZO layer, and TCO layer.

[0080] In this embodiment, the transparent conductive layer 5 is an ITO layer as an example for illustration; the high light transmittance of the ITO layer ensures that most of the incident light can pass through the ITO layer and enter the battery absorption layer. In this application, the P-type doping concentration of the ohmic contact layer can, for example, be 5 × 10⁻⁶. 19 cm - ³.

[0081] High-temperature alloying processes often lead to the diffusion of metal atoms into the battery interior, forming deep-level recombination centers, increasing carrier recombination, and reducing open-circuit voltage (Voc) and fill factor (FF).

[0082] The ohmic contact layer 3 is a GaInP layer with a P-type doping concentration greater than 5 × 10⁻⁶. 18 cm -3 The lattice constant matching of the window layer avoids defects caused by lattice mismatch, and the extremely high doping concentration ensures good band alignment with the subsequent transparent conductive layer 5, forming a near-ideal heterojunction ohmic contact. This significantly reduces the contact barrier and achieves excellent ohmic contact characteristics. Furthermore, only a low-temperature annealing process is required, eliminating the need for a high-temperature alloying process. This avoids the problem of metal atom diffusion that is easily caused by high-temperature alloying, thereby avoiding the deterioration of the PN junction performance of the battery. This improves the reliability and fabrication yield of the device while ensuring the performance of the solar cell. The ITO uses an antireflection coating design, and the cooperation between ITO, the ohmic contact layer 3, the window layer, and the grid electrode 4 also achieves current equalization, allowing current to flow from the ohmic contact layer 3 into the ITO and to the grid electrode 4, reducing current congestion at the bottom of the grid electrode 4.

[0083] More preferably, the thickness of the ohmic contact layer 3 is 10nm-50nm, including the endpoint values. In the case of high doping, if the GaInP layer 3 is too thick, it will cause roughness on the crystal surface. Furthermore, as the ohmic contact layer 3, its function is to achieve ohmic contact without requiring excessive thickness. Therefore, setting the thickness of the ohmic contact layer to be ultra-thin, i.e., 10nm-50nm, is preferable.

[0084] Among them, the ultrathin, highly doped GaInP layer and ITO layer are both highly transparent materials, and their absorption of incident light is negligible.

[0085] The solar electrode can be a single-junction solar cell or a multi-junction solar cell.

[0086] like Figure 19 As shown, this embodiment takes a multi-junction solar cell as an example, and illustrates the use of an epitaxial structure 100 with three sub-cells. The epitaxial structure 100 includes a buffer layer 60, a first sub-cell 10, a tunnel junction 50, a second sub-cell 20, a tunnel junction 50, and a third sub-cell 30 disposed on the surface of the substrate 1 facing away from the back electrode 2. The surface of the epitaxial structure facing away from the substrate is the window layer of the third sub-cell 30. It should be understood that... Figure 19 The composite electrode structure formed by the medium-ohmic contact layer 3, the grid electrode 4, and the transparent conductive layer 5 is only based on... Figure 1a Taking this as an example, it can also be used as... Figure 2-18 The structure shown in any one of the items.

[0087] Optionally, the first sub-cell 10 can be a Ge cell, the second sub-cell 20 can be an InGaAs cell, and the third sub-cell 30 can be a GaInP cell.

[0088] Optionally, a buffer layer 60 may be disposed between the first sub-cell 10 and the substrate 1.

[0089] Based on any of the above embodiments, in a preferred embodiment, the top electrode is in contact with the window layer; specifically, the top electrode can be disposed within the channel and in contact with the window layer. The surface of the top electrode facing the substrate 1 is the lower surface.

[0090] Based on any of the above embodiments, in a preferred embodiment, the transparent conductive layer 5 also covers part of the surface of the top electrode, so that the current is conducted to the top electrode more evenly and reasonably, avoiding current congestion.

[0091] This application also provides a method for manufacturing a solar cell, which can be used to manufacture the solar cell described in any of the above-mentioned embodiments, and includes the following steps:

[0092] S01: A substrate 1 is provided. Substrate 1 includes, but is not limited to, GaAs substrate 1.

[0093] S02: An epitaxial structure 100 is fabricated on one side surface of the substrate 1. Optionally, the solar electrode can be a single-junction solar cell or a multi-junction solar cell. In this embodiment, a three-junction structure is used as an example. The epitaxial structure 100 includes a first sub-cell 10, a tunnel junction 50, a second sub-cell 20, a tunnel junction 50, and a third sub-cell 30. Optionally, before growing each sub-cell, a buffer layer 60 can be grown on the substrate 1 first, and then each sub-cell can be grown on the buffer layer 60.

[0094] S03: An ohmic contact material layer is grown on the epitaxial structure 100, and an ohmic contact layer 3 with channels is formed through photolithography and etching steps; the channels expose a portion of the surface of the epitaxial structure 100. Specifically, corresponding channels are fabricated according to the required photolithographic pattern through photolithography and etching. The channels may include channels for accommodating the top electrode and channels for accommodating the gate electrode 4. The width of the channel accommodating the gate electrode 4 can be set to less than 5 micrometers, and the spacing between the channels accommodating the gate electrode 4 can be set to 180 micrometers–230 micrometers.

[0095] S04: Fabricate the top electrode and gate electrode 4; the top electrode is connected to the gate electrode 4, and the top electrode and gate electrode 4 are disposed within the channel. Specifically, the electrode material can be deposited using electron beam evaporation, and finally the top electrode and gate electrode 4 are formed by a lift-off process. Optionally, the linewidth of the gate electrode 4 is set to be less than 5 micrometers.

[0096] Optionally, the gate electrode 4 includes a Ti layer, a Pd layer, and an Ag layer, wherein the thickness distribution of the Ti layer, Pd layer, and Ag layer can be 20 nm, 50 nm, and 2000 nm. Alternatively, the gate electrode 4 includes Cu or Au. The material of the gate electrode 4 is not limited to these.

[0097] S05: Fabricate a transparent conductive layer 5, which at least covers the ohmic contact layer 3 and the gate electrode 4. Alternatively, the transparent conductive layer at least covers the ohmic contact layer and the gate electrode, exposing the surface of the gate electrode facing away from the substrate, such as... Figure 1b As shown. Specifically, the transparent conductive layer 5 can be fabricated using magnetron sputtering or electron beam evaporation. The thickness of the transparent conductive layer 5 can be selected from 50-200 nm, for example, 50 nm, 100 nm, 150 nm, or 200 nm. This embodiment uses a transparent conductive layer 5 with a thickness of 100 nm as an example for illustration.

[0098] S06: Fabricate a back electrode 2 on the side of the substrate 1 away from the epitaxial structure 100. Before fabricating the back electrode 2, flip the sample after step S05. The back electrode 2 includes Ge, Au, Ni, and Au.

[0099] Based on the above embodiments, in a preferred embodiment, after the transparent conductive layer 5 is fabricated in step S05, a low-temperature annealing process is performed; the temperature of the low-temperature annealing process does not exceed 400°C. For example, annealing at 350°C for 15 minutes in a nitrogen atmosphere is used to optimize the electrical and optical properties of ITO, so that its sheet resistance is <50Ω / □ and its transmittance in the visible light region is >90%.

[0100] Based on any of the above embodiments, in a preferred embodiment, in step S04, the height of the surface of the gate electrode 4 away from the substrate 1 is higher than or does not exceed the height of the surface of the ohmic contact layer 3 away from the substrate 1.

[0101] Based on any of the above embodiments, in a preferred embodiment, in step S04, the gate electrode 4 does not contact the ohmic contact layer 3; or, at least a portion of the sidewall of the gate electrode 4 contacts the ohmic contact layer 3; or, a portion of the surface of the gate electrode 4 facing the substrate 1 contacts the ohmic contact layer 3; or, at least a portion of the sidewall and a portion of the surface of the gate electrode 4 facing the substrate 1 contact the ohmic contact layer 3.

[0102] Based on any of the above embodiments, in a preferred embodiment, the epitaxial structure 100 has a window layer on the surface facing away from the substrate 1; the material of the ohmic contact layer 3 is the same as that of the window layer; the resistance of the ohmic contact layer 3 is less than that of the window layer; the ohmic contact layer 3 forms an ohmic contact with the transparent conductive layer 5, or the ohmic contact layer 3 forms an ohmic contact with the transparent conductive layer 5 and the grid electrode 4; the window layer does not form an ohmic contact with the transparent conductive layer 5 and the grid electrode 4. Taking the above triple-junction solar cell as an example, the surface of the epitaxial structure 100 facing away from the substrate 1 is the window layer of the third sub-cell.

[0103] More preferably, the window layer and the ohmic contact layer 3 are GaInP layers; the P-type doping concentration of the ohmic contact layer 3 is greater than that of the window layer, and the P-type doping concentration of the ohmic contact layer 3 is greater than 5 × 10⁻⁶. 18 cm -3 The transparent conductive layer 5 includes one or more of the following: ITO layer, FTO layer, IZO layer, AZO layer, GZO layer, and TCO layer.

[0104] More preferably, the thickness of the ohmic contact layer 3 is 10nm-50nm, including the endpoint values. For example, it can be 10nm, 15nm, 20nm, 35nm, 45nm, 50nm, etc.

[0105] Based on any of the above embodiments, in a preferred embodiment, the top electrode is in contact with the window layer.

[0106] Based on any of the above embodiments, in a preferred embodiment, the transparent conductive layer 5 further covers a portion of the surface of the top electrode.

[0107] The above-described method for manufacturing a solar cell can be used to manufacture any of the solar cells described above, and therefore has the beneficial effects mentioned in any of the solar cells described above, which will not be repeated here; for any content not mentioned, please refer to the content of any of the above-described solar cell embodiments.

[0108] Those skilled in the art should understand that, in the disclosure of this invention, the terms "lateral", "longitudinal", "upper", "lower", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the above terms should not be construed as limiting this invention.

[0109] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0110] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A solar cell, characterized in that, include Substrate; An epitaxial structure, wherein the epitaxial structure is disposed on one side surface of the substrate; A back electrode is disposed on the surface of the substrate facing away from the epitaxial structure. An ohmic contact layer is disposed on the surface of the epitaxial structure opposite to the substrate, and has channels that expose a portion of the surface of the epitaxial structure. A grid line electrode, wherein the grid line electrode is disposed within the channel; A top electrode, which is connected to the gate line electrode; A transparent conductive layer, wherein the transparent conductive layer at least covers the ohmic contact layer and the gate electrode, or the transparent conductive layer at least covers the ohmic contact layer and the gate electrode, and exposes the surface of the gate electrode facing away from the substrate.

2. A solar cell as described in claim 1, characterized in that, The height at which the grid electrode faces away from the substrate is higher than or does not exceed the height at which the ohmic contact layer faces away from the substrate.

3. A solar cell as described in claim 1, characterized in that, The gate electrode is not in contact with the ohmic contact layer; or, at least a portion of the sidewall of the gate electrode is in contact with the ohmic contact layer; or, a portion of the surface of the gate electrode facing the substrate is in contact with the ohmic contact layer; or, at least a portion of the sidewall and a portion of the surface of the gate electrode facing the substrate are in contact with the ohmic contact layer.

4. A solar cell according to any one of claims 1-3, characterized in that, The surface of the epitaxial structure facing away from the substrate is a window layer; The material of the ohmic contact layer is the same as that of the window layer; The resistance of the ohmic contact layer is less than the resistance of the window layer; The ohmic contact layer forms an ohmic contact with the transparent conductive layer, or the ohmic contact layer forms an ohmic contact with the transparent conductive layer and the gate electrode; the window layer does not form an ohmic contact with the transparent conductive layer and the gate electrode.

5. A solar cell as described in claim 4, characterized in that, The window layer and the ohmic contact layer are GaInP layers; the P-type doping concentration of the ohmic contact layer is greater than that of the window layer, and the P-type doping concentration of the ohmic contact layer is greater than 5 × 10⁻⁶. 18 cm -3 ; The transparent conductive layer includes one or more of the following: ITO layer, FTO layer, IZO layer, AZO layer, GZO layer, and TCO layer.

6. A solar cell as described in claim 5, characterized in that, The thickness of the ohmic contact layer is 10nm-50nm, including the endpoint values.

7. A solar cell as described in claim 4, characterized in that, The top electrode is in contact with the window layer.

8. A method for manufacturing a solar cell, characterized in that, include: Provide a substrate; An epitaxial structure is fabricated on one side surface of the substrate; An ohmic contact material layer is grown on an epitaxial structure, and an ohmic contact layer with channels is formed by photolithography and etching steps; the channels expose a portion of the surface of the epitaxial structure. Fabricate a top electrode and a gate line electrode; the top electrode is connected to the gate line electrode, and the top electrode and the gate line electrode are disposed within the channel; A transparent conductive layer is fabricated, wherein the transparent conductive layer at least covers the ohmic contact layer and the gate electrode, or the transparent conductive layer at least covers the ohmic contact layer and the gate electrode, and exposes the surface of the gate electrode facing away from the substrate; A back electrode is fabricated on the side of the substrate away from the epitaxial structure.

9. A method for manufacturing a solar cell as described in claim 8, characterized in that, The height of the grid electrode away from the substrate is higher than or does not exceed the height of the ohmic contact layer away from the substrate; The surface of the epitaxial structure facing away from the substrate is a window layer; The material of the ohmic contact layer is the same as that of the window layer; The resistance of the ohmic contact layer is less than the resistance of the window layer; The ohmic contact layer forms an ohmic contact with the transparent conductive layer, or the ohmic contact layer forms an ohmic contact with the transparent conductive layer and the gate electrode; the window layer does not form an ohmic contact with the transparent conductive layer and the gate electrode. The window layer and the ohmic contact layer are GaInP layers; the P-type doping concentration of the ohmic contact layer is greater than that of the window layer, and the P-type doping concentration of the ohmic contact layer is greater than 5 × 10⁻⁶. 18 cm -3 ; The transparent conductive layer includes one or more of the following: ITO layer, FTO layer, IZO layer, AZO layer, GZO layer, and TCO layer.

10. A method for manufacturing a solar cell as described in claim 9, characterized in that, After the transparent conductive layer is fabricated, a low-temperature annealing process is performed; the temperature of the low-temperature annealing process does not exceed 400°C.

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