De-mapping write buffer portions for access during write to memory device

Abstract

Aspects relate to interrupting memory access during background operation of a memory device. In one example, a memory device includes a memory controller to initiate a write buffer refresh operation. A bus interface is coupled to the main memory and the write buffer to receive write commands from a host during a write buffer refresh operation. The memory controller initiates a write buffer refresh operation, suspends the write buffer refresh operation in response to a write command, transfers a last refresh address of the write buffer from the memory device to the host through the bus interface, and uses the last refresh address to unmap a portion of the write buffer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to non-provisional application sequence No. 18 / 364,277, filed August 2, 2023, with the United States Patent and Trademark Office, the entire contents of which are as fully set forth herein and incorporated herein for all applicable purposes. Technical Field

[0003] All aspects of this disclosure relate to write access to the main memory of a memory device via a write buffer, and more specifically to unmapping a refresh portion of the write buffer for access during a later write to the main memory. Background Technology

[0004] Modern computing systems utilize vast amounts of memory resources. Memory can consist of many individual memory cells managed by a memory controller. Each cell can store 1, 2, 3, 5, or another number of bits simultaneously, depending on the cell's physical structure. The memory controller manages the operations of reading data from memory cells and writing external data to cells. The memory controller also manages the use of memory cells and can control logical address mapping. Logical address mapping is used to map logical data addresses to the physical data addresses of specific cells.

[0005] Memory devices with large main storage can use buffers to allow for faster servicing of write operations. The host writes data quickly to the buffer, and then the memory device writes that data to the large main storage as a background operation. The write command queue is emptied into the write buffer faster than it would be emptied into the main storage. The write buffer can be faster than the main storage because it is smaller, but it can also be implemented using faster techniques.

[0006] In some memory devices, flash memory with three-level-cell (TLC), four-level-cell (QLC), or multi-level-cell (MLC) architectures is used to manufacture large main memory devices. Multi-level-cell architecture allows multiple bits to be stored in a single cell, achieving higher storage density and lower cost. TLC and MLC flash memory have significantly lower write performance than single-level-cell (SLC) flash memory because logically defined TLC bits require more programming steps and have a higher error correction probability. TLC and MLC flash memory also tend to tolerate fewer write cycles than SLC flash memory.

[0007] To improve the write performance of multi-level flash memory in primary storage devices (e.g., TLC), write buffers are constructed from faster, more durable, but more expensive SLC flash cells. The memory host writes to the SLC buffer at a higher speed. The memory device then flushes the SLC content to the TLC flash as a background process. For read operations, direct access to a large primary storage device is typically faster than providing a buffer due to the complexity of pre-fetching data as a background process. Summary of the Invention

[0008] The following content presents an overview of one or more embodiments to provide a basic understanding of such embodiments. This overview is not an exhaustive summary of all anticipated embodiments, nor is it intended to identify key or essential elements of all embodiments, nor to depict the scope of any or all embodiments. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed descriptions that follow.

[0009] In one example, a refresh portion of the write buffer is unmapped for access during a later write to main memory. An apparatus includes main memory, a write buffer coupled to the main memory and a bus interface, and a memory controller configured to initiate a write buffer refresh operation. The bus interface is coupled to the main memory and the write buffer to receive write commands from a host during the write buffer refresh operation. The memory controller is configured to initiate the write buffer refresh operation and suspend the write buffer refresh operation in response to a write command. The memory controller transmits the last refresh address of the write buffer from the memory device to the host via the bus interface and uses the last refresh address to unmap a portion of the write buffer.

[0010] In one example, a method includes: initiating a write buffer flush operation; during the write buffer flush operation at a memory device, the memory device having a write buffer coupled to main memory, receiving a write command from a host at the memory device; and pausing the write buffer flush operation in response to the write command. The method includes transferring the last flush address of the write buffer from the memory device to the host, and using the last flush address to unmap a portion of the write buffer from another write command from the host, and using a portion of the write buffer to buffer the other write command.

[0011] In another example, a non-transitory computer-readable medium has instructions stored therein for causing a processor of an interconnect link to perform the operations described above.

[0012] In another example, an apparatus includes a command queue configured to store commands to be transmitted to a memory device having a write buffer coupled to main memory. The apparatus also includes: a write buffer map; a bus interface coupled to the memory device, configured to transmit write commands from a host to the memory device during a write buffer refresh operation at the memory device, and to receive a last refresh address of the write buffer from the memory device; and a host controller configured to determine a refresh portion of the write buffer based on the last refresh address. The bus interface is configured to transmit an unmapping command to the memory device to unmapping a portion of the write buffer and transmit another write command.

[0013] In another example, a method includes transmitting a write command from the host to the memory device, which has a write buffer coupled to main memory, during a write buffer refresh operation at the memory device. The last refresh address of the write buffer is received from the memory device. A refreshed portion of the write buffer is determined based on the last refresh address. An unmapping command is transmitted to the memory device to unmapping a portion of the write buffer, and another write command is transmitted.

[0014] To achieve the foregoing and related objectives, one or more embodiments include the features fully described below and specifically pointed out in the claims. The following description and accompanying figures illustrate certain exemplary aspects of one or more embodiments in detail. However, these aspects are merely indications of a number of ways in which the principles of the various embodiments may be employed, and the described embodiments are intended to cover all such aspects and their equivalents. Attached Figure Description

[0015] Figure 1 This is a diagram of an example computing system including a system-on-a-chip (SoC) coupled to a memory device via a UFS bus suitable for various aspects of this disclosure.

[0016] Figure 2 It is a diagram of signals and operations performed by host and memory devices suitable for all aspects of this disclosure.

[0017] Figure 3 It is a graphical representation of the status and communication of the host and memory device during normal memory access commands, according to various aspects of this disclosure.

[0018] Figure 4 It is a graphical representation of the state and communication of the host and memory devices during a write buffer refresh operation, according to various aspects of this disclosure.

[0019] Figure 5It is a graphical representation of the status and communication between the host and the memory device during a memory write command after a write buffer refresh operation has been paused, according to various aspects of this disclosure.

[0020] Figure 6 It is a graphical representation of the status and communication between the host and the memory device during a memory write command after the write buffer is full, according to various aspects of this disclosure.

[0021] Figure 7 It is a graphical representation of the state and communication of the host and memory devices after the write buffer is flushed, according to various aspects of this disclosure.

[0022] Figure 8 It is a graphical representation of the state and communication between the host and the memory device during a memory write command after a portion of the write buffer has been demapped, according to various aspects of this disclosure.

[0023] Figure 9 It is a block diagram of the host controller according to various aspects of this disclosure.

[0024] Figure 10 This is a flowchart illustrating various aspects of the host-suspended write buffer flush operation according to various aspects of this disclosure.

[0025] Figure 11 This is a block diagram of a memory device according to various aspects of this disclosure.

[0026] Figure 12 This is a flowchart illustrating various aspects of pausing write buffer flushing due to host commands, based on various aspects of this disclosure. Detailed Implementation

[0027] The detailed descriptions following, illustrated with reference to the accompanying drawings, are intended as descriptions of various configurations and are not intended to represent the only configurations in which the concepts described herein can be practiced. To provide a comprehensive understanding of the various concepts, the detailed descriptions include specific details. However, these concepts can be practiced without these specific details. In some instances, to avoid ambiguity regarding such concepts, well-known structures and components are shown in block diagram form.

[0028] When the host receives a memory access command (e.g., to write data to a memory device) from the application layer, it transmits the command and data to the memory device via the memory bus. When the memory device executes a write command through a write buffer, the write command is served faster than a direct write to main memory. However, the data in the write buffer must be flushed to main memory to free up the memory cell blocks in the write buffer for reuse. The flush operation is performed in the background but may be paused due to a new write command. Because the application layer generates write commands independently of the flush operation at the memory device, the write buffer may not be fully flushed when a new write command is received.

[0029] As described herein, a refresh portion of the write buffer is unmapped for access during a later write to main memory. When a write command is received from the host during a write buffer refresh operation, the memory device suspends the write buffer refresh operation and transmits the last refresh address of the write buffer to the host. This allows the host to transmit an unmapped command for a portion of the write buffer using the last refresh address. The unmapped command can be transmitted before the write buffer refresh operation completes. After the refresh portion of the write buffer is unmapped, it can be used again as a write buffer for new write commands from the host. The memory device has write access to the newly unmapped portion of the write buffer for later write commands to be transmitted to main memory. The fast performance of the write buffer can be maintained while a portion of the write buffer is available. The memory device can resume the write buffer refresh operation after servicing a write command that has not yet completed.

[0030] This description is presented in the context of the JEDEC standard Universal Flash Storage 4.0 (referred to herein as UFS); however, the principles described herein can be applied to other memory device standards, operating and data bus configurations. UFS describes the protocols and communication formats used to connect host and memory devices to one device per UFS port. The specification is optimized for external flash memory devices, but target memory devices include external memory cards and embedded devices, including bootable mass storage devices. Expansion to input / output devices, cameras, wireless devices, and other device types is envisioned.

[0031] Unmapping commands are used in a variety of different memory systems. In UFS, the transport protocol supports packets and frames, and many commands are based on the Small Computer System Interface (SCSI), which includes unmapping commands. Unmapping commands are used to erase and discard data in memory cells. Unmapping is the operation of moving data from the mapped address space in a memory map to the unmapped address space in a memory map. As used in this article, an unmapping command releases an unmapped memory cell from use in the write buffer and returns the unmapped memory cell to the pool of available physical memory resources. Any data in the unmapped memory cell is invalid and ignored. The unmapping command is applied to the write buffer mapping after the data in the corresponding memory cell has been copied to main memory.

[0032] Figure 1 This is a diagram of an example computing system 100 including a system-on-a-chip (SOC) coupled to a memory device via a UFS bus. The host SOC 102 includes one or more host processors 104 for performing the main operations of the die, and parameter and configuration registers 106. The host processors execute the application layer and represent higher layers regarding memory and memory operations. The host SOC 102 can be configured to function as any desired computing device, ranging from embedded processors to portable communication devices to desktop workstations to servers. The host processor 104 accesses the memory device 152 (e.g., a UFS memory device) via a memory bus 148 (e.g., a UFS bus) using a host controller 146 (e.g., a UFS host controller).

[0033] According to various aspects of this disclosure, the host processor 104 can be used to implement elements or any portion of elements or any combination of elements. Examples of processors include central processing units, graphics processors, special-purpose processors, memory controllers, and input / output controllers. Examples of host controller 146 include microprocessors, microcontrollers, digital signal processors (DSPs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic components, discrete hardware circuitry, and other suitable hardware configured to control memory bus connections to memory devices. In various examples, the host SOC 102 can be configured to perform any one or more of the functions described herein. The host SOC 102 includes other components (not shown) configured to perform other functions of the module, as applicable to die types.

[0034] The host SOC 102 can be implemented using a bus architecture, which can include any number of interconnect buses and bridges, depending on the specific application of the host SOC 102. The bus architecture can be used to communicatively couple various circuits together, including processors, controllers, timing sources, peripherals, data buffers, modules, power management circuitry, and other processing cores, which will not be further described. Bus interface 108 provides an interface between external bus 110 and other optional external interfaces, such as control interface 112 and data interface 114. Processor 104 can communicate operational, supervisory, or administrative control with the control interface.

[0035] Control interface 112 can be used to provide a communication interface or component for communicating with various other devices and equipment (e.g., other devices housed within the same package or system) via an internal bus or external transmission medium, such as command and control interfaces for power regulation, power-on testing, and other purposes. Data interface 114 can be used to provide data connectivity to other types of components within the package or system. Control interface 112 and data interface 114 can be connected to higher-level and lower-level peripheral devices, sensors, and other components. Multiple different control interfaces and data interfaces coupled to the same bus 110 or additional buses may exist.

[0036] Host processor 104 is coupled to volatile memory controller 142 to communicate with volatile memory 151 (e.g., random access memory (RAM)) via RAM bus 144. Host processor 104 is coupled to host controller 146 to communicate with memory device 152 (e.g., UFS memory device) via memory bus 148. Multiple memory devices may exist, and each device may be coupled via a host controller or a shared host controller. Host controller 146 receives commands from host processor 104, buffers the commands in command queue 132 of host controller 146, and then, when ready, transmits the commands to memory device 152 via memory bus 148 using write buffer mapping 134 as appropriate.

[0037] Memory device 152 (e.g., a UFS memory device) includes a memory controller 153, a write buffer 154, a main storage device 155 containing primary memory cells for storing data, and a write buffer map 156. The memory controller 153 maps logical memory addresses to physical memory addresses of memory cells in the main storage device 155. The mapping may be stored in the write buffer map 156 or another location (not shown). The memory controller 153 manages the operation of the write buffer 154, which provides fast temporary storage for data from the UFS host controller 146. This data is then written from the write buffer 154 to the main storage device 155 using the write buffer map 156. The memory controller 153 performs background operations to maintain and optimize the operation of the write buffer 154, the main storage device 155, the write buffer map 156, and any other components of the memory device 152.

[0038] Various commands can be received from the host processor 104. Common memory access commands write to and read from one or more registers of the main memory device 155 of the memory device 152. Commands that perform background operations also exist. For example, in flash memory, whether in the main memory device 155, write buffer 154, or any other flash memory component, an erase command can be considered a clear and unmapped command. For write buffer 154, a block of memory cells containing the memory cells from write buffer 154 is flashed, and then the memory cells of that block are unmapped from write buffer maps 134, 156; that is, the write buffer maps do not show any data being mapped to those flashed cells of write buffer 154. Write buffer maps 134, 156 map the addresses of the registers in the write buffer to logical addresses in the main memory where the write buffer data will be written. During background operations, data in write buffer 154 is written to the register at the corresponding logical address in the main memory. The corresponding memory cell in the write buffer is then cleared or flashed for reuse. The response from memory device 152 is returned on memory bus 148 and transmitted to host processor 104 or other components suitable for commands.

[0039] The memory controller 153 also acts as an interface to the host controller 146 via the memory bus 148. The memory controller 153 may include an interface layer that serves as the interface to the memory bus 148. The interface layer may include a logical layer and a physical layer connecting to the UFS bus. The interface layer may be integrated into the memory controller 153 as shown, or it may be configured as a separate component. Similarly, the UFS host controller 146 may also include an interface layer (not shown) with logical and physical layers connecting to the UFS bus.

[0040] The UFS bus has multiple upstream and downstream links that operate on differential signaling. Reset and clock channels are also present to support differential channels. The transport protocol supports packets and frames with commands based on the Small Computer System Interface (SCSI). However, UFS is provided only as an example, and the aspects presented herein can be applied to variations of UFS and other memory systems. Memory bus 148 can be a UFS bus.

[0041] The host controller 146 may have additional buffers, controllers, and other components, including read buffers, write buffers, status registers, a physical interface state machine, and other components not shown herein. Similarly, the memory device 152 may also have buffers, controllers, status and control registers, and other components not shown herein.

[0042] The memory controller can be configured to operate various background operations independently of the host (shown above as the host controller). A memory device can be configured to signal to the host, using its memory controller, that a specific background operation needs to be performed. This signaling to the host allows the host to determine the appropriate time for the background operation. For example, the host can check if the command queue is empty, or continue processing commands to the memory device until the command queue is empty. The host responds to the request by setting a background operation enable flag. This is sent to the memory device, which then begins the background process.

[0043] Requests from the memory controller for background operations can take different forms indicating that performance or operation is affected or critical. In one example, the first level is 02h: operation not completed (performance affected), and the second level is 03h: operation not completed (critical). An example of a background operation is a write buffer flush operation. A write buffer flush operation may have a unique request from the memory device for a write buffer flush and a write buffer flush enable flag set by the host. A write buffer flush operation is an operation performed on the write buffer when it is full or nearly full to free up physical blocks of the write buffer for reuse. The write buffer flush operation copies all data from at least a portion of the write buffer and then erases that portion of the write buffer. Other background operations include wipe operations to erase unused blocks of memory cells in the primary storage device, and dynamic device capacity to reset the capacity of the primary storage device after a wipe or other remapping.

[0044] To keep write buffer 154 available for new data from host controller 146, data in write buffer 154 must be flushed from write buffer 154 and written to main storage device 155. In some examples, when host controller 146 issues a write command to storage device 152, the storage device interrupts any current or pending flush operations to receive the new write command. If there is space in write buffer 154, the data for the new write command is stored in the write buffer. If the write buffer is full, the data is bypassed and written directly to main storage device 155. Direct writing to main storage device 155 is much slower than writing to write buffer 154, thus performance is improved by increasing the availability of the write buffer.

[0045] Flushing a flash-based write buffer requires three processes. First, data is copied from the write buffer to main memory. Next, the logical-to-physical address mapping is updated to reflect the new location of the data. Using the flash-based write buffer, each memory cell block is then flashed to allow reuse of that block. Finally, the flashed memory cell block is unmapped from the write buffer mapping. When the write buffer is mapped to receive new data, the unmapped memory cell becomes available to receive the new data. In some implementations, the entire write buffer is flashed before the memory cell is unmapped. In some implementations, the write buffer is partitioned, with each partition serving a different logical address cell in main memory. A partition can then be flushed independently of the other partitions. The flush operation may take longer to complete if write operations are received during the flush operation and the flush operation stops to allow more data to be written to the write buffer. The flush operation may not complete during periods of high usage. This can result in the write buffer being bypassed during periods of heaviest use.

[0046] To perform a background operation, such as a refresh operation, memory device 152 sends a request to host 102. Host controller 146 sets a background operation enable flag but does not initiate or run the background operation. The memory device runs the background operation independently of the host. Meanwhile, the host receives commands from the application layer (e.g., from the host processor), regardless of whether the memory device is running any background operation. Therefore, the host can issue commands to the memory device independently of any background operation state.

[0047] In UFS, the application layer includes the UFS Command Set (UCS), Device Manager, and Task Manager. UCS handles normal commands such as read and write. UFS can support multiple command sets. UFS is designed to be protocol-agnostic. The command set is based on a simplified SCSI command set. UCS also has a UFS native command set that can be used to extend some UFS functionality. The Task Manager, run by the UFS host controller, handles commands for command queue control. The Device Manager, run by the storage controller, provides device-level control, such as query requests and low-level link layer control.

[0048] Figure 2 This is a diagram illustrating the signals and operations performed by the host and memory devices for clearing operations. The host 202 is coupled to the memory device 204 via a bus 200 represented by signals between the host 202 and the memory device 204. The host 202 and memory device 204 have performed boot, configuration, handshake, and other operations not described herein, and are configured to access memory using bus 200.

[0049] In some aspects, after a period of operation, the memory device determines through its memory controller that a write buffer refresh operation is needed to ensure that the write buffer is available to receive new data. Therefore, it sends a request 212 to host 202 requesting a write buffer refresh. For UFS, this request may be in the form of a UFS Protocol Information Unit (UPIU) response, which includes an indication of importance, such as 02h or 03h. The host receives the request and processes it to determine whether the request should be allowed. Depending on the nature of the memory device and any bus protocol, different considerations exist. In some examples, the host checks the command queue 232. If there are important or urgent commands in the command queue, the host waits until these commands have been processed by the memory device. After the command queue is empty or important commands have been processed, and after any other chosen considerations, the host sets the write buffer refresh enable flag 234. The host may also send a notification (e.g., the buffer refresh enable flag 214) to the memory device 204.

[0050] For UFS, this can take the form of a request UPIU. UFS provides an exception event mechanism. One of the defined exception events is flushing the write buffer (known as the write booster). An exception event is initiated by the storage device when the entire write buffer is full or nearly full. The storage device sends a WRITEBOOSTER_FLUSH_NEEDED response UPIU to the host to indicate that the buffer used for WriteBooster needs to be flushed. The host is expected to issue a flush command by setting the enable flag fWriteBoosterBufferFlushEn to "1". This is placed in the request UPIU. In the device information field of the subsequent response UPIU, the storage device will only indicate events enabled by the host via the wExceptionEventControl property in the write request UPIU. When the cleanup condition is met, the device clears the event bits in the wExceptionEventStatus property and the device information field of the response UPIU. In the example, the host could set a flag to allow write booster flushing during a hibernation state at the storage device. The storage device could then initiate a write buffer flush operation immediately after seeing the flag and entering hibernation without an explicit command from the host.

[0051] Memory device 204 detects the write buffer refresh enable flag 214, and after proper preparation, initiates a write buffer refresh operation 236. Ideally, the memory device continues the write buffer refresh operation until it is complete; however, at 238, a memory write command is received at host 202. At 216, the host forwards the memory write command to memory device 204. At 236, the memory device suspends the write buffer refresh operation in response to the memory write command 216. This is to allow new data to be written to the write buffer, or, if the write buffer is full, to be written to the main memory.

[0052] The memory device provides a response UPIU after pausing write buffer flush operations. In UFS, the response UPIU indicates the status of the WriteBooster buffer flush operation. A 00h response UPIU indicates "Idle". The memory device is not flushing the WriteBooster buffer. A 01h response UPIU indicates "Flush operation in progress". The WriteBooster buffer is not empty, and flushing has been initiated. A 02h response UPIU indicates "Flush operation stopped prematurely". The WriteBooster buffer is not empty, and the host has stopped the ongoing flush. A 03h response UPIU indicates "Flush operation completed successfully". A 04h response UPIU indicates "Flush operation generally failed". When the status is "Flush operation in progress" or "stopped prematurely", the device memory can add the last flush address to the response UPIU 218.

[0053] A memory write operation, initiated by memory write command 216, can then proceed normally. Similar processes are used for other memory access commands, such as read, erase, or any other suitable type of operation to access memory. The memory write command is discussed here because it affects the write buffer. The memory device can respond with a Ready to Transfer (RTT) message 220 (e.g., RTT UPIU) from memory device 204 to host 202. The host can then transfer data 222 to memory device 204 to write to a memory cell, such as a data input UPIU. After the transfer is complete, memory device 204 can immediately send a response 224 indicating the end of the memory access command to host 202. This process can then be followed by further memory access commands 228. The specific order and structure of memory accesses can be modified to suit different specific implementations and protocols.

[0054] Even with the write buffer refresh enable flag 234 set, the host can still receive new commands from higher layers of the system, such as the application layer and the host processor. A memory access command is received at 238, but the host knows that a write buffer refresh operation may be initiated. However, the host transmits the memory write command 216 to the memory device 204 to provide a prompt write response to the higher layers.

[0055] When the host receives the last refresh address in the response UPIU 218 from the memory device, it can determine how much of the write buffer has been refreshed. After the memory write command has been processed, the host can then send a write buffer unmapping command 226 to the memory device. This command allows the memory device to unmapping refreshed memory cells, making them available for reuse. This unmapping occurs even if these write buffer memory cells are only a portion of the total write buffer and even if the refresh operation is not yet complete. If the write buffer refresh enable flag is still set, the memory device can continue refreshing the write buffer after servicing the memory write command. Meanwhile, the refreshed portion of the write buffer is available for new write commands.

[0056] consider Figure 2 The message and operation, write buffer unmapping command 226, followed by unmapping write buffer portion 242, releases the write buffer portion for reuse. This allows the use of that portion of the write buffer even before the write buffer flush operation is complete. Without transmitting the last refresh address and unmapping a portion of the write buffer, the write buffer can be filled before the write buffer flush operation is complete. This will result in write operations being performed more slowly. In one example, the host uses the last refresh address to determine the parameters of the write buffer unmapping command. In other words, the host sets the memory address to be unmapped. In another example, the write buffer unmapping command is generalized, and the memory device determines the memory address to be unmapped. In flash memory-based write buffers, the write buffer is unmapped block by block. The last refresh address can be the last address of a block that has already been flushed. In some respects, the host can know the structure of the memory block and determine the last address of the last refreshed block.

[0057] Figure 3 This is a graphical representation of the state and communication between host 302 and memory device 304 during a normal memory write command. Host 302 is coupled to memory device 304 via downstream link 306 and upstream link 308. For a normal memory access command, the host receives a new memory access command 324 from an upstream or higher-level component (e.g., a processor) and stores these commands in command queue 310. The command queue can be at various capacity levels depending on the rate at which commands are received and executed by the memory device. The host transmits data and commands as "data input" on downstream link 306 and receives data and responses as "data output" on upstream link 308. The result from upstream link 308 is received in result queue 312 and reported back as data result 328 to the same higher level that made the request.

[0058] At memory device 304, a write command is applied to write buffer 314 and then copied to main memory 316 of the memory device. A memory processor (not shown) manages the copying process (referred to herein as a refresh operation) and also maintains various address mappings, command queues, and configuration and operation parameters for operations on the memory device. Write buffer 314 can be smaller and faster than main memory 316, making write operations to write buffer 314 much faster than the processing that would occur if it were in main memory 316.

[0059] exist Figure 3 In the example, write buffer 314 has been filled to the level indicated by arrow P1. Arrow P1 indicates that the memory cells in the area below the arrow are full and contain buffered write data. The memory cells in the area above arrow P1 are empty or unmapped. These are available for use.

[0060] Figure 4 This is a graphical representation of the state and communication between host 402 and memory device 404 during a write buffer refresh operation. Host 402 has received a new command 424 in its command queue 410 and has not yet transmitted these commands as memory write commands on downstream link 406. The response on upstream link 408 is received in result queue 412 and transmitted as data result 428 to a higher layer, such as a process on the host processor.

[0061] A write buffer refresh operation can be initiated in response to a flag set by the host. There is a write buffer refresh enable flag in response to a request from the memory device, and there is also a write buffer refresh enable flag initiated when the memory device is in sleep mode. Regardless of how the buffer refresh operation is initiated, data is copied from the write buffer 414 of memory device 404 to the main memory 416 of memory device 404, as indicated by arrow 418. The memory mapping is updated to maintain a record of the physical addresses of the data written to main memory. After the data has been copied from the write buffer 414, no more data is needed in the write buffer. If the write buffer is flash memory, the memory device controller can flash or erase the memory cell block after the entire block of memory cells has been copied. This is a slow, high-power process of writing "1"s to each cell. Later, when a new memory command is received, data can be written to the flash cells. This is called programming the memory cells and is performed by writing "0"s to each cell where "1"s are not needed.

[0062] Write buffer 414 has been filled to the level indicated by arrow P1. In response to this level, in this example, memory device 404 sends a response to host 402 on upstream link 408 requesting a write buffer refresh. The host has either allowed the write buffer refresh operation or the memory device is in sleep mode and has initiated the write buffer refresh operation autonomously. The write buffer refresh operation is indicated by arrow 418 from write buffer 414 to main memory 416. As shown, the write buffer refresh operation has reached multiple memory cell blocks indicated by arrow P2. In the figure, the bottom of the write buffer indicates the lowest physical address, and the top of arrow P2 is the last refresh address. The top of arrow P1 is the last complete address of write buffer 414. A three-part box representing write buffer 414 is provided to illustrate the principle, rather than the memory structure or the arrangement of physical and logical addresses. In an operating system, wear leveling and TRIM operations may also occur, causing the affected blocks to be discontinuous.

[0063] In this example, when a new write command is received, the write buffer flush operation applied to all registers up to P1 only proceeds to level P2. When the flush operation is paused, the memory device sends a response to the host that first indicates the write buffer flush operation is incomplete, and secondly indicates the last flush address. The last flush address corresponds to P2. This can be entirely in the form of a single UPIU response to the host or in another form. The host can infer all flushed memory blocks in the write buffer based on the last flush address. In some examples, the memory device sends a first flush address and a last flush address, allowing the host to determine that all blocks between the last flush address and the first flush address have been flushed.

[0064] Figure 5 This is a graphical representation of the status and communication between host 502 and memory device 504 after the write buffer flush operation has been paused. The host continues to receive new commands 524 from command queue 510 and transmits these commands to memory device 504 via downstream link 506. Results are received from memory device 504 into result queue 512 via upstream link 508, and then the data results 528 are forwarded to higher layers, such as applications on the host processor.

[0065] In write buffer 514, when a write buffer flush operation is initiated, the buffer is filled to the level of arrow P1. The memory device flushes the write buffer to the level of arrow P2. However, the write buffer flush operation is not yet complete, and a new command 524 is being received. Write buffers up to the level of arrow P2 cannot be used because those memory blocks have not yet been unmapped. They are still mapped to previously written data that has been copied to main memory 516. New commands are written to the write buffer from the level of arrow P1 and above (e.g., up to the level of arrow P3). All this data remains in the write buffer until a write buffer flush operation is performed.

[0066] Figure 6 This is a graphical representation of the state and communication between host 602 and memory device 604 after write buffer 614 has been filled. New command 624 continues to be received by host 602 in command queue 610 and then transmitted to memory device 604 via downstream link 606. However, write buffer 614 is filled to the level of arrow P4, which is at or near the last available address of write buffer 614. As a result, write buffer 614 is no longer usable, and new data is written directly to main memory 616, as indicated by downstream link 606 extending into main memory 616. In a real physical system, numerous intermediate buffers, controllers, timers, address mappings, and other components (not shown) may exist between host 602 and main memory 616. The write buffer flushing operation is still interrupted when new command 624 is received and data result 628 is output via upstream link 608 and result queue 612.

[0067] Figure 7 This is a graphical representation of the status and communication between host 702 and memory device 704 after the write buffer refresh operation has been restarted. The host is not receiving new commands, and command queue 710 is empty. Downstream link 706 and upstream link 708 are idle, and there are no results in result queue 712. Memory device 704 is full up to the level of arrow P4, but the refresh operation has been resumed as indicated by write copy arrow 718 from write buffer 714 to main memory 716. Resumption of the write buffer refresh operation starts from the lowest physical address memory cell (in this case, the bottom of arrow P1) and proceeds sequentially through the physical addresses of the write buffer to the end (in this case, the top of arrow P1). The bottom of arrow P1 corresponds to the last refresh address previously sent to the host. The memory device resumes from this address and continues until the remainder of the top of arrow P1 is complete. This is indicated by write copy arrow 718 extending from the remaining top portion of P1. Additionally, the original refresh segment 720 has been demapped and is available for new memory write commands.

[0068] Figure 8 This is a graphical representation of the status and communication between host 802 and memory device 804 after the write buffer flush operation is completed. The host continues to receive new commands 824 from command queue 810 and transmits these commands to memory device 804 via downstream link 806. The results are received from memory device 804 into result queue 812 via upstream link 808, and then the data results 828 are forwarded to higher layers.

[0069] The lower portion 820 of the write buffer 814 has been flushed and unmapped and is available for use by the memory device 804. The upper portion of the write buffer up to the top of arrow P4 is full and awaits flushing in a manner similar to that described above regarding the portion up to the top of arrow P1.

[0070] Figure 9 It is suitable for and Figure 1 This is a block diagram illustrating an example of a hardware implementation of a UFS host controller 146 used with an SOC 102, or a host controller 900 used as a memory host controller in any other system. The memory host controller has a memory bus 910 for memory access and background operations. In this example, the host controller has a host controller processor 904 for performing primary operations of the host controller, a computer-readable medium 905 for providing instructions to the host controller processor 904, and a memory 903 for containing a command queue 934 and other data and instructions. The host controller has a bus interface 920 to support the memory bus 910 to the memory device. The bus interface has a PHY receive block 916 and a PHY transmit block 918 coupled to the memory bus and PHY logic 912. The host controller processor 904 performs the operations described above to servic the memory bus 910 between the host processing component 932 and the memory device (not shown).

[0071] Examples of host controller 900 include microprocessors, microcontrollers, digital signal processors (DSPs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic components, discrete hardware circuitry, and other suitable hardware configured to control the memory bus 910 described herein. In various examples, host controller 900 may be configured to perform any one or more of the functions described herein. The host controller may include other components (not shown) configured to perform other functions of the host controller, as applicable to the type of memory bus.

[0072] In this example, a bus architecture (typically represented by bus 902) can be used to implement the host controller 900. Bus 902 may include any number of interconnect buses and bridges, depending on the specific application of the host controller 900 and overall design constraints. Bus 902 communicatively couples together various circuits including memory 903, host controller processor 904, and a computer-readable medium (typically represented by computer-readable medium 905) on which instructions are stored. Bus 902 may also link various other circuits, such as timing sources, peripherals, data buffers, modules, power management circuitry, and other processing cores, which are not further described. Bus interface 908 provides an interface between bus 902 and host processing component 932 (e.g., other external components of the host SOC, the host processing component, the application layer, and higher layers). Host controller processor 904 can communicate operational, supervisory, or administrative control with host processing component 932 via bus 902. Host processing component 932 can transmit memory access commands to host controller processor 904 and receive results from host controller processor 904.

[0073] PHY transmit block 916 and PHY receive block 918 are coupled to memory bus 910, which corresponds to the aforementioned upstream and downstream links. These upstream and downstream links couple host processing component 932 to a memory device via pins on corresponding connectors on memory bus 910. The module also includes PHY logic 912, which may include link logic to control data applied to each line and state under the control of host controller processor 904. PHY logic 912 may also include a clock generator coupled to a clock source to generate clock signals and other reference signals for the upstream and downstream links.

[0074] The host controller processor 904 is responsible for managing the PHY logic 912 and interface processing, including executing software stored on the computer-readable medium 905. When executed by the host controller processor 904, the software causes the host controller 900 to perform the various functions described below for any particular device. The computer-readable medium 905 and memory 903 can also be used to store data manipulated by the host controller processor 904 during software execution.

[0075] The host controller processor 904 can perform operations by means of a processor core that executes software stored in a computer-readable medium 905. Software should be broadly interpreted as instructions, instruction sets, code, code segments, program code, programs, subroutines, software chips, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description languages, or others. The software may reside on the computer-readable medium 905. The host controller processor 904 controls the operations performed by the PHY logic 912, the command queue 934, and other components of the host controller 900.

[0076] Computer-readable medium 905 may be a non-transitory computer-readable medium. By way of example, non-transitory computer-readable media include magnetic storage devices, flash memory devices, random access memory (RAM), read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), registers, and any other suitable medium for storing software and / or instructions accessible and readable by the controller. Computer-readable medium 905 may reside in host controller processor 904 or another part of host controller 900. Computer-readable medium 905 may be embodied in firmware for the operation of a state machine or parameters of an ASIC. Those skilled in the art will recognize that how best to implement the functionality described throughout this disclosure depends on the specific application and the overall design constraints imposed on the system.

[0077] The host controller 900 may be configured to perform any one or more of the operations described herein. In some aspects of this disclosure, such as the host controller processor 904 utilized in the host controller 900, circuitry configured for various functions may be included. The host controller processor 904 is coupled to a computer-readable medium 905 via a bus 902. The computer-readable medium 905 includes parameter and configuration registers, which may include parameters for responses, requests, flags, and operations.

[0078] The host controller processor 904 may include write buffer refresh operation circuitry 941 to permit a write buffer refresh operation on the memory device and to receive a last refresh address from the memory device when the write buffer refresh operation is interrupted. Write buffer refresh operation circuitry 941 may also be configured to transmit a request and receive a response from the memory device to receive a request for a write buffer refresh, including urgency level, and to set and clear a write buffer refresh enable flag. Write buffer refresh operation circuitry 941 may include one or more hardware components that provide the physical structure to support the refresh operation by performing various processes associated with permitting the write buffer refresh operation and receiving the last refresh address. Write buffer refresh operation circuitry 941 may include functionality for permitting the write buffer refresh operation and for receiving the last refresh address from the memory device. Write buffer refresh operation circuitry 941 may also be configured to execute write buffer refresh operation instructions 951 included on computer-readable medium 905 to implement the write buffer refresh operation support described herein.

[0079] The host controller processor 904 may include memory access command circuitry 942 configured to receive memory access commands and transmit the memory access commands to a memory device in response to a receive operation completion notification. The memory access command circuitry 942 may include functionality for receiving memory access commands and transmitting them to the memory device. Memory access commands may be received from a higher layer (e.g., host processing component 932). The memory access command circuitry 942 may also be configured to execute memory access command instructions 952 included on the computer-readable medium 905 to implement one or more of the functions described herein.

[0080] Module 914, host controller processor 904, may include address mapping management circuitry 943 configured to manage write buffer mapping and, in response to the last refresh address as discussed herein, manage unmapping of blocks in the write buffer. Address mapping management circuitry 943 may include functionality for managing write buffer mapping and unmapping blocks in the write buffer. Address mapping management circuitry 943 may also include functionality for managing write buffer mapping and unmapping blocks in the write buffer. Address mapping management circuitry 943 may also be configured to execute address mapping management instructions 953 included on computer-readable medium 905 to implement one or more of the functions described herein.

[0081] The host controller processor 904 may include data communication circuitry 944 configured to communicate commands and data with a memory device via a memory bus 910, as discussed herein. Data communication circuitry 944 may include functionality for communicating data with the memory device. Data communication circuitry 944 may also be configured to set parameters for communicating via the memory bus. Data communication circuitry 944 may also be configured to execute data communication instructions 954 included on a computer-readable medium 905 to perform one or more of the functions described herein.

[0082] The circuit architecture described in this article can be implemented on one or more ICs, chips, chiplets, modules, interposers, packages, system printed circuit boards (PCBs), etc. The circuit architecture described in this article can also be manufactured using various process technologies, such as complementary metal-oxide-semiconductor (CMOS), NMOS, PMOS, bipolar junction transistors (BJTs), bipolar CMOS (BiCMOS), silicon-germanium (SiGe), gallium arsenide (GaAs), heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs), silicon-on-insulator (SOI), etc.

[0083] Figure 10 This is a process flowchart illustrating an example of a method for unmapping a portion of a write buffer for access during a write to main memory. The method can be found in... Figure 9 The host controller processor 904 or other circuits and such as in Figure 9 The method is executed within the software described in the context of the above. Method 1000 optionally begins at block 1002, wherein a request for a write buffer refresh is received at the host from the memory device before transmitting the write command. Method 1000 continues at block 1004, wherein a write buffer refresh enable flag is transmitted in response to the request for a write buffer refresh or in response to another signal or condition. The enable flag can be used to allow a write buffer refresh when the command queue is empty, or to allow a write buffer refresh operation when the memory device is asleep or at another time.

[0084] At box 1006, during a write buffer refresh operation at the memory device, a write command is transmitted from the host to the memory device. The memory device has a write buffer coupled to main memory. A write command is a memory access command that involves writing data into the main memory of the memory device coupled to the host. Other commands may also be transmitted to the memory device. Box 1008 relates to receiving the last refresh address of the write buffer.

[0085] At box 1010, the refresh portion of the write buffer is determined based on the last refresh address. The refresh portion may be identified as an address range, a specific block, or otherwise. Box 1012 involves sending an unmapping command to the memory device to unmap a portion of the write buffer. This command allows the memory device to unmap the refresh portion of the write buffer, making it available for new write commands. At box 1014, another write command is sent. This other write command may store new data in the unmapped portion of the write buffer. However, due to other memory management considerations, the new data may be stored in another portion of the write buffer.

[0086] Figure 11 This is a block diagram illustrating an example of a hardware implementation of a memory device 1100, such as a memory card, flash memory stick, solid-state drive, embedded memory, random access memory, or any other suitable component having a memory bus 1110 with write buffer operations and write buffer refresh operations. In this example, the memory device has a memory device controller 1104 for performing the main operations of the memory device, a computer-readable medium 1105 for providing instructions to the memory device controller 1104, and a memory 1103 for containing main memory 1134 and write buffer 1136, as well as other components. The memory device 1100 has a bus interface 1120 to support the memory bus 1110 to a host. The bus interface has a PHY receive block 1116 and a PHY transmit block 1118 coupled to the memory bus and PHY logic 1112. The memory device controller 1104 performs the operations described above to service the memory bus 1110 between the memory device 1100 and a host (not shown). A memory device contains other components (not shown) that are configured to perform other functions of the memory device, as is the case with the type of memory bus.

[0087] In this example, a bus architecture (typically represented by bus 1102) can be used to implement memory device 1100. Bus 1102 may include any number of interconnect buses and bridges, depending on the specific application of memory device 1100 and overall design constraints. Bus 1102 communicatively couples together various circuits including memory 1103, memory device controller 1104, and a computer-readable medium (typically represented by computer-readable medium 1105) on which instructions are stored. Bus 1102 may also link various other circuits, such as timing sources, peripherals, data buffers, modules, power management circuitry, and other processing cores, which are not further described. Bus interface 1108 provides an interface between bus 1102 and controller interface 1132 or other interfaces. In some examples, the control interface may be via memory bus 1110. Memory device controller 1104 may communicate operational, supervisory, or administrative controls with control interface 1132 via bus 1102.

[0088] PHY transmit block 1116 and PHY receive block 1118 are coupled to memory bus 1110, which corresponds to the aforementioned upstream and downstream links, which couple the host to memory device 1100 via pins on corresponding connectors for memory bus 1110. The module also includes PHY logic 1112, which may include link logic to control data applied to each line and state under the control of memory device controller 1104. PHY logic 1112 may also include a clock generator coupled to a clock source to generate clock signals and other reference signals for the upstream and downstream links.

[0089] The memory device controller 1104 is responsible for managing the PHY logic unit 1112 and interface processing, including executing software stored on the computer-readable medium 1105. When executed by the memory device controller 1104, the software causes the memory device 1100 to perform the various functions described below for any particular device. The computer-readable medium 1105 and the memory 1103 can also be used to store data manipulated by the memory device controller 1104 during software execution.

[0090] The memory device controller 1104 may include write buffer refresh operation circuitry 1141 for initiating a write buffer refresh operation by the memory device and pausing the write buffer refresh operation in response to receiving a write command from the host. Write buffer refresh operation circuitry 1141 may also be configured to transmit responses and receive requests from the host to transmit a request for a write buffer refresh, including urgency level, and to receive a write buffer refresh enable flag. Write buffer refresh operation circuitry 1141 may include one or more hardware components that provide the physical structure for performing various processes related to initiating and pausing the write buffer refresh operation and transmitting the last refresh address. Write buffer refresh operation circuitry 1141 may include functionality for initiating the write buffer refresh operation, pausing the write buffer refresh operation, and transmitting the last refresh address to the host. Write buffer refresh operation circuitry 1141 may also be configured to execute write buffer refresh operation instructions 1151 included on the computer-readable medium 1105 to implement the write buffer refresh operation support described herein.

[0091] The memory device controller 1104 may include mapping management circuitry 1142 configured to unmap a portion of a write buffer and buffer write commands using the write buffer, as discussed herein. Mapping management circuitry 1142 may include functionality for managing blocks of write buffer mapping and unmapping. Mapping management circuitry 1142 may include functionality for unmapping write buffers and for buffering write commands using a portion of the write buffer. Mapping management circuitry 1142 may also be configured to execute mapping management instructions 1152 included on the computer-readable medium 1105 to implement one or more of the functions described herein.

[0092] The memory device controller 1104 may include memory access circuitry 1143 configured to receive write commands and write to a write buffer and main memory. Memory access circuitry 1143 may include functionality for receiving memory write commands and writing to the write buffer and main memory. Memory access circuitry 1143 may also be configured to execute memory access instructions 1153 included on the computer-readable medium 1105 to perform one or more of the functions described herein.

[0093] The memory device controller 1104 may include data communication circuitry 1144 configured to communicate commands and data with a host via memory bus 1110, as discussed herein. Data communication circuitry 1144 may include functionality for communicating data with the host. Data communication circuitry 1144 may also be configured to set parameters for communicating via the memory bus. Data communication circuitry 1144 may also be configured to execute data communication instructions 1154 included on computer-readable medium 1105 to perform one or more of the functions described herein.

[0094] Figure 12 This is a process flowchart illustrating an example of a method for unmapping a portion of a write buffer for access during a write to main memory. The method can be found in... Figure 11 The memory device controller 1104 or other circuits and such as in Figure 11 The operation is performed within the software described in the context of the above. Method 1200 begins at block 1202, where a write buffer refresh operation is initiated. The operation can be initiated either by command, autonomously, or otherwise. At block 1204, a write command is received from the host at the memory device during the write buffer refresh operation performed at the memory device. The memory device has a write buffer coupled to main memory. At block 1206, the write buffer refresh operation is paused in response to the write command.

[0095] At box 1208, the memory device transmits the last refresh address of the write buffer from the memory device to the host. Method 1200 continues in box 1210, where a portion of the write buffer is unmapped using the last refresh address. After the unmapping at box 1212, another write command is received from the host, and at box 1214, another write command is buffered using a portion of the write buffer.

[0096] As used herein, “or” is intended to be interpreted as inclusive unless otherwise explicitly stated. For example, “a or b” could include only a, only b, or a combination of a and b. As used herein, the phrase “at least one of” or “one or more of” refers to any combination of those items, including a single member. For example, “at least one of a, b, or c” is intended to cover the following examples: only a, only b, only c, a combination of a and b, a combination of a and c, a combination of b and c, and a combination of a, b, and c.

[0097] The various exemplary components, logic elements, logic blocks, modules, circuits, operations, and algorithmic processes described in conjunction with the specific embodiments disclosed herein can be implemented as electronic hardware, firmware, software, or a combination of hardware, firmware, or software, including the structures disclosed in this specification and their structural equivalents. This interchangeability of hardware, firmware, and software has been generally described in terms of its functionality and exemplified in the various exemplary components, blocks, modules, circuits, and processes described above. Whether such functionality is implemented in hardware, firmware, or software depends on the specific application and the design constraints imposed on the overall system.

[0098] The various exemplary logic blocks, modules, and circuits described in conjunction with the exemplary aspects disclosed herein can be implemented or executed using a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic element, discrete hardware component, or any combination thereof. The general-purpose processor may be a microprocessor, but in alternative embodiments, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0099] In one or more exemplary aspects, the described functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functionality may be stored as one or more instructions or code stored on a computer-readable medium or transmitted as one or more instructions or code stored on a computer-readable medium. A computer-readable medium includes both computer storage media and communication media, including any medium that facilitates the transfer of a computer program from one place to another. A storage medium may be any available medium accessible to a computer. By way of example and not limitation, such a computer-readable medium may include RAM, ROM, EEPROM, CD-ROM, or other optical disk storage devices or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and is accessible to a computer. Combinations of the above should also be included within the scope of computer-readable media.

[0100] The following provides an overview of various embodiments of this disclosure.

[0101] Example 1: A memory device comprising: main memory; a write buffer coupled to the main memory and a bus interface; and a memory controller configured to initiate a write buffer refresh operation; the bus interface being coupled to the main memory and the write buffer to receive a write command from a host during the write buffer refresh operation, and the memory controller being configured to: initiate the write buffer refresh operation; suspend the write buffer refresh operation in response to the write command; transmit the last refresh address of the write buffer from the memory device to the host via the bus interface; and use the last refresh address to unmap a portion of the write buffer.

[0102] Example 2: The memory device according to Example 1, wherein pausing the write buffer refresh operation includes pausing the write buffer refresh operation before the write buffer refresh operation is completed.

[0103] Example 3: In the memory device according to Example 1 or 2, the memory controller clears the memory cell block of the write buffer before pausing the write buffer refresh operation.

[0104] Example 4: A memory device according to any one or more of Examples 1 to 3, wherein the write buffer refresh operation includes writing data from the memory cell of the write buffer to the main memory.

[0105] Example 5: A memory device according to any one or more of Examples 1 to 4, wherein a portion of the write buffer comprises a plurality of memory cells, and wherein unmapping the portion comprises modifying the address mapping at the memory device to release the portion of the write buffer.

[0106] Example 6: In a memory device according to any one or more of Examples 1 to 5, the memory controller is configured to: transmit a notification to the host that a write buffer refresh is required; and receive a write buffer refresh enable request from the host before initiating the write buffer refresh operation.

[0107] Example 7: In a memory device according to any one or more of Examples 1 to 6, the memory controller is configured to complete pending write commands to the write buffer before initiating the write buffer refresh operation.

[0108] Example 8: In a memory device according to any one or more of Examples 1 to 7, the memory controller is configured to resume the write buffer refresh operation after completing a pending command on the write buffer.

[0109] Example 9: The memory device according to Example 8, wherein resuming the write buffer refresh operation includes resuming the write buffer refresh operation starting from the lowest physical address memory cell of the write buffer and sequentially advancing through the physical address of the write buffer.

[0110] Example 10: The memory device according to Example 9, wherein the portion of the write buffer includes memory cells from the lowest physical address memory cell of the write buffer to the last refresh address.

[0111] Example 11: In a memory device according to any one or more of Examples 1 to 10, the bus interface is configured to transmit a response to the host indicating that the write buffer refresh operation is paused in response to receiving the write command.

[0112] Example 12: The apparatus according to Example 11, wherein the response includes a general flash memory wExceptionEventControl bit.

[0113] Example 13: In a memory device according to any one or more of Examples 1 to 12, the bus interface is configured to receive a demapping command from the host, and wherein the demapping is in response to the demapping command.

[0114] Example 14: A memory device according to any one or more of Examples 1 to 13, wherein the bus interface is configured to receive another write command from the host; and the memory controller is configured to use a portion of the write buffer to buffer the other write command.

[0115] Example 15: A method comprising: initiating a write buffer refresh operation; during the write buffer refresh operation at a memory device, the memory device having a write buffer coupled to main memory; pausing the write buffer refresh operation in response to the write command; transferring a last refresh address of the write buffer from the memory device to the host; using the last refresh address to unmap a portion of the write buffer; receiving another write command from the host; and using the portion of the write buffer to buffer the other write command.

[0116] Example 16: According to the method of Example 15, the method further includes resuming the write buffer refresh operation after completing the pending command on the write buffer.

[0117] Example 17: The method according to Example 15 or 16, wherein resuming the write buffer refresh operation includes: resuming the write buffer refresh operation starting from the lowest physical address memory cell, and sequentially advancing through the physical address of the write buffer.

[0118] Example 18: The method according to any one or more of Examples 15 to 17, the method further comprising transmitting a response to the host in response to receiving the write command, indicating that the write buffer refresh operation is suspended.

[0119] Example 19: A host comprising: a command queue configured to store commands to be transmitted to a memory device having a write buffer coupled to main memory; a write buffer mapping; a bus interface coupled to the memory device, the bus interface being configured to transmit write commands from the host to the memory device during a write buffer refresh operation at the memory device, and to receive a last refresh address of the write buffer from the memory device; and a host controller configured to determine a refresh portion of the write buffer based on the last refresh address; the bus interface being configured to transmit an unmapping command to the memory device to unmapping the portion of the write buffer and transmit another write command.

[0120] Example 20: According to the host described in Example 19, the bus interface is configured to receive a request for write buffer refresh from the memory device before transmitting the write command; and the host controller is configured to check the command queue and alternately transmit or not transmit a write buffer refresh enable flag to the memory device.

[0121] Example 21: A method comprising: transmitting a write command from a host to the memory device, the memory device having a write buffer coupled to main memory, during a write buffer refresh operation at a memory device; receiving a last refresh address of the write buffer from the memory device; determining a refresh portion of the write buffer based on the last refresh address; transmitting an unmapping command to the memory device to unmapping the portion of the write buffer; and transmitting another write command.

[0122] Example 22: According to the method of Example 21, the method includes: receiving a request for write buffer refresh from the memory device before transmitting the write command; and transmitting a write buffer refresh enable flag in response to the request for write buffer refresh.

[0123] Example 23: The method according to Example 21 or 22, the method includes checking the command queue, and if an appended write command is in the command queue, then the write buffer refresh enable flag is not transmitted.

[0124] Example 24: The method according to any one or more of Examples 21 to 23, the method comprising: receiving a response from the memory device, the response indicating a pause in write buffer refresh operation in response to transmitting the write command.

Claims

1. A memory device, the memory device comprising: Main memory; A write buffer, the write buffer being coupled to the main memory and the bus interface; and A memory controller configured to initiate a write buffer refresh operation; The bus interface is coupled to the main memory and the write buffer to receive write commands from the host during the write buffer refresh operation, and The memory controller is configured to: initiate the write buffer refresh operation, pause the write buffer refresh operation in response to the write command, transmit the last refresh address of the write buffer from the memory device to the host via the bus interface, and use the last refresh address to unmap a portion of the write buffer.

2. The memory device of claim 1, wherein pausing the write buffer refresh operation includes pausing the write buffer refresh operation before the write buffer refresh operation is completed.

3. The memory device of claim 1, wherein the memory controller clears the memory cell block of the write buffer before pausing the write buffer refresh operation.

4. The memory device of claim 1, wherein the write buffer refresh operation comprises writing data from a memory cell of the write buffer to the main memory.

5. The memory device of claim 1, wherein the portion of the write buffer comprises a plurality of memory cells, and wherein unmapping the portion comprises modifying the address mapping at the memory device to release the portion of the write buffer.

6. The apparatus of claim 1, wherein the memory controller is configured to: Send a notification to the host that a write buffer refresh is required; and Before initiating the write buffer refresh operation, a write buffer refresh enable request is received from the host.

7. The memory device of claim 1, wherein the memory controller is configured to complete pending write commands to the write buffer before initiating the write buffer refresh operation.

8. The memory device of claim 1, wherein the memory controller is configured to resume the write buffer refresh operation after completing a pending command on the write buffer.

9. The memory device of claim 8, wherein resuming the write buffer refresh operation comprises resuming the write buffer refresh operation starting from the lowest physical address memory cell of the write buffer and sequentially advancing through the physical addresses of the write buffer.

10. The memory device of claim 9, wherein the portion of the write buffer comprises memory cells from the lowest physical address memory cell of the write buffer to the last refresh address.

11. The memory device of claim 1, wherein the bus interface is configured to transmit a response to the host indicating that the write buffer refresh operation is paused in response to receiving the write command.

12. The memory device of claim 11, wherein the response includes a general flash memory wExceptionEventControl bit.

13. The memory device of claim 1, wherein the bus interface is configured to receive a demapping command from the host, and wherein demapping is in response to the demapping command.

14. The memory device according to claim 1, wherein: The bus interface is configured to receive another write command from the host; and The memory controller is configured to use a portion of the write buffer to buffer the other write command.

15. A method, the method comprising: Initiate a write buffer flush operation; During the write buffer refresh operation at the memory device, a write command is received from the host at the memory device, which has a write buffer coupled to the main memory; The write buffer refresh operation is paused in response to the write command; The last refresh address of the write buffer is transferred from the memory device to the host. Use the last refresh address to unmap a portion of the write buffer; Receive another write command from the host; as well as The other write command is buffered using a portion of the write buffer.

16. The method of claim 15, further comprising resuming the write buffer refresh operation after completing the pending command on the write buffer.

17. The method of claim 16, wherein resuming the write buffer flush operation comprises: The write buffer refresh operation is resumed starting from the lowest physical address memory cell, and the physical addresses of the write buffer are sequentially advanced.

18. The method of claim 15, further comprising transmitting a response to the host in response to receiving the write command, indicating that the write buffer flush operation is paused.

19. A host computer, the host computer comprising: A command queue configured to store commands to be transmitted to a memory device having a write buffer coupled to main memory; Write to the buffer map; A bus interface coupled to the memory device, the bus interface being configured to transmit write commands from the host to the memory device during a write buffer refresh operation at the memory device, and to receive the last refresh address of the write buffer from the memory device; and A host controller configured to determine the refresh portion of the write buffer based on the last refresh address; The bus interface is configured to transmit an unmapping command to the memory device to unmapping the portion of the write buffer and transmit another write command.

20. The host computer according to claim 19, The bus interface is configured to receive a request from the memory device to flush the write buffer before transmitting the write command; and The host controller is configured to check the command queue and alternately send or not send the write buffer refresh enable flag to the memory device.

21. A method, the method comprising: During a write buffer refresh operation at a memory device, a write command is transmitted from the host to the memory device, which has a write buffer coupled to the main memory. Receive the last refresh address of the write buffer from the memory device; The refresh portion of the write buffer is determined based on the last refresh address; A demapping command is sent to the memory device to demapping the portion of the write buffer; as well as Send another write command.

22. The method according to claim 21, wherein the method comprises: Before transmitting the write command, a request to refresh the write buffer is received from the memory device; as well as In response to the request that a write buffer refresh is required, a write buffer refresh enable flag is transmitted.

23. The method of claim 21, the method comprising checking a command queue and, if an appended write command is in the command queue, not transmitting the write buffer refresh enable flag.

24. The method according to claim 21, wherein the method comprises: A response is received from the memory device, the response indicating that the write buffer refresh operation is paused in response to the transmission of the write command.

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