Display device, method of manufacturing display device, and electronic apparatus

Abstract

Provided is a display device capable of suppressing deterioration of characteristics of a second transistor in a process of manufacturing the display device. The display device includes a circuit board provided with a plurality of light emitting elements. The circuit board includes: a first layer including a plurality of first transistors; and a second layer including a plurality of second transistors, electrodes of the plurality of light emitting elements, and a plurality of wirings, the second layer being bonded to the first layer. The plurality of second transistors are provided separately from a junction surface between the first layer and the second layer. The electrode is provided on a surface opposite to the bonding surface of the two surfaces of the second layer.

Description

Technical Field

[0001] This disclosure relates to display devices, methods of manufacturing the same, and electronic devices. Background Technology

[0002] In the field of display device technology, not only the light-emitting element but also the circuit board (backplane) used to drive the light-emitting element has been actively researched. A circuit board having a configuration of a first layer comprising a plurality of first transistors and a second layer comprising a plurality of second transistors stacked sequentially has been proposed.

[0003] For example, Patent Document 1 discloses a circuit board having a configuration in which a first element layer (first layer) including a plurality of first transistors and a second element layer (second layer) including a plurality of second transistors are stacked sequentially, wherein the first transistors have a semiconductor layer in a channel forming region and the second transistors have an oxide semiconductor layer in the channel forming region.

[0004] Reference List

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2020-154323 Summary of the Invention

[0007] The problem to be solved by the present invention

[0008] Each circuit board with the above configuration is formed by sequentially stacking layers from the bottom up using vacuum film formation technology, photolithography, or similar techniques. As a result, the second transistor is affected by subsequent processes (e.g., oxygen, hydrogen, heat, etc.), and its characteristics may deteriorate. In particular, when the second transistor is a thin-film transistor, such as an oxide semiconductor thin-film transistor, there is a possibility of significant degradation in its characteristics.

[0009] The purpose of this disclosure is to provide a display device, a method for manufacturing the display device, and an electronic device capable of suppressing the degradation of the characteristics of a second transistor during the manufacturing process of the display device.

[0010] Solution to the problem

[0011] To solve the above problems, the display device according to this disclosure includes: a circuit board having a plurality of light-emitting elements, wherein the circuit board includes: a first layer having a plurality of first transistors; and a second layer having a plurality of second transistors, electrodes of the plurality of light-emitting elements, and a plurality of wirings, the second layer being bonded to the first layer, the plurality of second transistors being disposed separately from the bonding surface between the first layer and the second layer, and the electrodes being disposed on the surface of the second layer opposite to the bonding surface.

[0012] The method for manufacturing a display device according to the present disclosure includes the following steps: forming a first layer including a plurality of first transistors; forming a second layer on a substrate including a plurality of second transistors, electrodes including a plurality of light-emitting elements, and a plurality of wirings; bonding the first layer and the second layer to each other; and removing the substrate from the second layer, wherein the step of forming the second layer includes: forming a third layer on the substrate including electrodes including a plurality of light-emitting elements, forming a fourth layer on the third layer including a plurality of wirings, and forming the second layer by forming a fifth layer on the fourth layer including a plurality of second transistors. Attached Figure Description

[0013] [ Figure 1 ] Figure 1 This is a schematic diagram of a display device according to a first embodiment of the present disclosure.

[0014] [ Figure 2 ] Figure 2 This is a diagram of a pixel circuit.

[0015] [ Figure 3 ] Figure 3 This is a cross-sectional view of a display device according to a first embodiment of the present disclosure.

[0016] [ Figure 4 ] Figure 4 This is a cross-sectional view of the circuit board.

[0017] [ Figure 5 ] Figure 5 A and Figure 5 B is a cross-sectional view illustrating an embodiment of the process for forming the first layer.

[0018] [ Figure 6 ] Figure 6 A, Figure 6 B and Figure 6 C is a cross-sectional view illustrating an embodiment of the process for forming the second layer.

[0019] [ Figure 7 ] Figure 7 A, Figure 7 B and Figure 7 C is a cross-sectional view of an embodiment used to describe the process of forming the second layer.

[0020] [ Figure 8 ] Figure 8 A and Figure 8 B is a cross-sectional view illustrating an embodiment of the process for forming the second layer.

[0021] [ Figure 9 ] Figure 9 A and Figure 9 B is a cross-sectional view illustrating an embodiment of the process of joining the first and second layers together.

[0022] [ Figure 10 ] Figure 10 This is a schematic diagram of a display device according to a second embodiment of the present disclosure.

[0023] [ Figure 11 ] Figure 11 This is a diagram of a pixel circuit.

[0024] [ Figure 12 ] Figure 12 This is a cross-sectional view of the circuit board.

[0025] [ Figure 13 ] Figure 13 It is a cross-sectional view of the circuit board based on the modified example.

[0026] [ Figure 14 ] Figure 14 It is a cross-sectional view of the circuit board based on the modified example.

[0027] [ Figure 15 ] Figure 15 It is a cross-sectional view of the circuit board based on the modified example.

[0028] [ Figure 16 ] Figure 16 It is a cross-sectional view of the circuit board based on the modified example.

[0029] [ Figure 17 ] Figure 17 This is a cross-sectional view showing a modified example of the circuit board.

[0030] [ Figure 18 ] Figure 18 This is a schematic diagram of a display area unit (pixel array unit).

[0031] [ Figure 19 ] Figure 19 It is a cross-sectional view of the circuit board based on the modified example.

[0032] [ Figure 20 ] Figure 20 This is an enlarged cross-sectional view of the joint between the first and second layers.

[0033] [ Figure 21 ] Figure 21 It is a cross-sectional view of the circuit board based on the modified example.

[0034] [ Figure 22 ] Figure 22 It is a cross-sectional view of the circuit board based on the modified example.

[0035] [ Figure 23 ] Figure 23 A is a plan view of the dummy wiring in the first embodiment. Figure 23 B is a plan view of the dummy wiring in the second embodiment. Figure 23 C is a plan view of the dummy wiring in the third embodiment.

[0036] [ Figure 24 ] Figure 24 This is an enlarged cross-sectional view of the second transistor.

[0037] [ Figure 25 ] Figure 25 This is an enlarged cross-sectional view of the circuit board based on the modified example.

[0038] [ Figure 26 ] Figure 26 This is an enlarged cross-sectional view of the circuit board based on the modified example.

[0039] [ Figure 27 ] Figure 27 A, Figure 27 B. Figure 27 C Figure 27 D and Figure 27 E is a cross-sectional view used to describe a modified example of the process for forming the second layer.

[0040] [ Figure 28 ] Figure 28 This is an enlarged cross-sectional view of the electrode based on the modified example.

[0041] [ Figure 29 ] Figure 29 A and Figure 29 B is a cross-sectional view used to describe a modified example of the process for forming the second layer.

[0042] [ Figure 30 ] Figure 30 A, Figure 30 B and Figure 30 C is a conceptual diagram used to describe the relationship between the normal LN passing through the center of each light-emitting part, the normal LN' passing through the center of each lens component, and the normal LN' passing through the center of each wavelength selection part.

[0043] [ Figure 31 ] Figure 31 It is a conceptual diagram showing the relationship between the normal LN passing through the center of each light-emitting part, the normal LN' passing through the center of each lens component, and the normal LN' passing through the center of each wavelength selection part.

[0044] [ Figure 32 ] Figure 32 A and Figure 32 B is a conceptual diagram showing the relationship between the normal LN passing through the center of each light-emitting part, the normal LN' passing through the center of each lens component, and the normal LN' passing through the center of each wavelength selection part.

[0045] [ Figure 33 ] Figure 33 It is a conceptual diagram showing the relationship between the normal LN passing through the center of each light-emitting part, the normal LN' passing through the center of each lens component, and the normal LN' passing through the center of each wavelength selection part.

[0046] [ Figure 34 ] Figure 34 A is a schematic cross-sectional view used to describe a first embodiment of the resonator structure. Figure 34 B is a schematic cross-sectional view used to describe a second embodiment of the resonator structure.

[0047] [ Figure 35 ] Figure 35 A is a schematic cross-sectional view used to describe a third embodiment of the resonator structure. Figure 35 B is a schematic cross-sectional view used to describe a fourth embodiment of the resonator structure.

[0048] [ Figure 36 ] Figure 36 A is a schematic cross-sectional view illustrating the fifth embodiment of the resonator structure. Figure 36 B is a schematic cross-sectional view used to describe the sixth embodiment of the resonator structure.

[0049] [ Figure 37 ] Figure 37 This is a schematic cross-sectional view used to describe the seventh embodiment of the resonator structure.

[0050] [ Figure 38 ] Figure 38 A is the front view of the digital camera. Figure 38 B is the rear view of the digital camera.

[0051] [ Figure 39 ] Figure 39 It is a stereoscopic image of a head-mounted display.

[0052] [ Figure 40 ] Figure 40 It is a 3D diagram of a television device.

[0053] [ Figure 41 ] Figure 41 It is a stereoscopic image of a see-through head-mounted display.

[0054] [ Figure 42 ] Figure 42 It's a 3D diagram of a smartphone.

[0055] [ Figure 43 ] Figure 43 A is a diagram showing the interior of a vehicle as viewed from the rear to the front. Figure 43 B is a diagram showing the interior of the vehicle as viewed from the rear to the front. Detailed Implementation

[0056] The embodiments of this disclosure will be described in the following order.

[0057] 1. Description of the outline of the display device according to this disclosure

[0058] 2. Background of the creation of the disclosed embodiments

[0059] 3. First Embodiment (Example of a Display Device)

[0060] 4. Second Embodiment (Example of a Display Device)

[0061] 5. Variations

[0062] 6. The relationship between the normals passing through the centers of the light-emitting part, the lens component, and the wavelength selection part.

[0063] 7. Examples of resonator structures

[0064] 8. Application Examples (Examples of Electronic Devices)

[0065] The embodiments described below are preferred specific embodiments of this disclosure, and the content of this disclosure is not limited to these embodiments. Furthermore, in all the accompanying drawings relating to the following embodiments, the same or corresponding parts are labeled with the same reference numerals. Additionally, to prevent the illustrations from becoming overly complex, sometimes only some parts are labeled with reference numerals, and sometimes the illustrations are simplified, enlarged, or reduced.

[0066] <1 Description of the outline of the display device according to this disclosure>

[0067] In the display device according to this disclosure, since the second layer is bonded to the first layer in the circuit board, the circuit board can be manufactured by pre-fabricating the first and second layers separately and then bonding the second layer to the first layer. Therefore, the second layer can be formed in a sequence that can suppress the influence of the second transistor on the formation process of another layer, such as wiring (e.g., factors like oxygen, hydrogen, heat, etc.). Thus, the degradation of the characteristics of the second transistor during the manufacturing of the display device can be suppressed.

[0068] Since the display device of this disclosure includes a plurality of first transistors and a plurality of second transistors in different layers, higher pixel resolution can be achieved compared with a display device in which the plurality of first transistors and a plurality of second transistors are included in the same layer.

[0069] Because the display device according to this disclosure has a configuration in which the first layer and the second layer are bonded together, a plurality of second transistors are disposed separately from the bonding surface between the first layer and the second layer. For example, the plurality of second transistors may be disposed on a layer at least one layer higher than the bonding surface.

[0070] In the display device according to this disclosure, the wiring layer can be a single wiring layer or multiple wiring layers. When the wiring layer is a multiple wiring layer, the second transistor can be disposed below the multiple wiring layers or between the stacked wiring layers.

[0071] In the display device according to this disclosure, the first transistor may be a metal-oxide-semiconductor field-effect transistor (MOSFET), and the second transistor may be a thin-film transistor. The thin-film transistor may be an oxide semiconductor thin-film transistor.

[0072] As described above, when the second transistor is a thin-film transistor, the gate electrode of the second transistor is located on the front side of the thin-film semiconductor layer when viewed from the opposite side surface of the second layer. In this case, light incident on the second transistor from the surface of the circuit board on which multiple light-emitting elements are disposed can be blocked by the gate electrode. Therefore, light can be suppressed from entering the thin-film semiconductor layer, and the degradation of the characteristics of the second transistor can be suppressed.

[0073] As described above, when viewed from the opposite side surface of the second layer, if the gate electrode of the second transistor is disposed on the front side of the thin film semiconductor layer included in the second transistor, the surface of the thin film semiconductor layer on the gate electrode side can be flat.

[0074] Because the display device according to this disclosure has a configuration in which the first layer and the second layer are bonded to each other as described above, the gate electrode, source electrode, and drain electrode of the second transistor can be formed before the thin-film semiconductor layer of the second transistor is formed. Therefore, damage to the thin-film semiconductor layer during the formation of the gate electrode, source electrode, and drain electrode can be prevented. Therefore, a thin-film semiconductor layer having a flat surface as described above can be formed.

[0075] As described above, when the second transistor is a thin-film transistor, the gate electrode of the second transistor can be disposed on the back side of the thin-film semiconductor layer of the second transistor when viewed from the opposite surface of the second layer. In this case, the second layer preferably also includes a light-shielding layer, and the light-shielding layer is preferably disposed between the electrodes of the plurality of second transistors and the plurality of light-emitting elements. As a result, light incident on the second transistor from the surface of the circuit board on which the plurality of light-emitting elements are disposed can be blocked by the light-shielding layer. Therefore, light entering the thin-film semiconductor layer can be suppressed, and the characteristic degradation of the second transistor can be suppressed.

[0076] In the display device according to this disclosure, when the first transistor is a MOSFET and the second transistor is a thin-film transistor, the circuit board can have the following configuration: Multiple pixel circuits can be disposed on the circuit board corresponding to multiple pixels, and at least a subset of the multiple pixel circuits can include at least one of the first transistors and at least one of the second transistors. The leakage current of the thin-film transistor is less than the leakage current of the MOSFET. Therefore, as described above, since at least a subset of the multiple pixel circuits includes at least one of the first transistors and at least one of the second transistors, the power consumption of the display device can be reduced.

[0077] In the display device according to this disclosure, preferably, the first layer further includes a plurality of first bonding electrodes, and the second layer further includes a plurality of second bonding electrodes. The first bonding electrodes and the second bonding electrodes are bonded to each other at a bonding surface to form a bonding portion, and at least one of the bonding portions is provided for each pixel. In this case, the first transistor and the second transistor included in a pixel circuit can be bonded to each other through at least one bonding portion.

[0078] In the display device according to this disclosure, when the first transistor is a MOSFET and the second transistor is a thin-film transistor, the circuit board can have the following configuration: Multiple pixel circuits can be disposed on the circuit board corresponding to multiple pixels, and the pixel circuits included in a predetermined area of ​​the display area can include at least one of the first transistors and at least one of the second transistors. The leakage current of the thin-film transistor is less than the leakage current of the MOSFET. Therefore, as described above, since the pixel circuits included in the predetermined area of ​​the display area include at least one of the first transistors and at least one of the second transistors, the power consumption of the display device can be reduced.

[0079] In the display device according to this disclosure, when the first transistor is a MOSFET and the second transistor is a thin-film transistor, the circuit board may have the following configuration. Multiple pixel circuits may be disposed on the circuit board corresponding to multiple pixels. The multiple pixel circuits may include: multiple first pixel circuits included in a first region of the display area and multiple second pixel circuits included in a second region of the display area. Each first pixel circuit may include at least two of the first transistors, and each second pixel circuit may include at least one of the first transistors and at least one of the second transistors. A first transistor included in each first pixel circuit and a second transistor included in each first pixel circuit may have the same function and be connected to the same wiring.

[0080] The leakage current of a thin-film transistor (TFT) is lower than that of a MOSFET. On the other hand, the driving capability of a MOSFET is higher than that of a TFT, and MOSFETs exhibit less manufacturing performance variation than TFTs. Therefore, in the first region, pixels can be driven at high speed, and variations in pixel characteristics can be suppressed. Conversely, in the second region, pixel power consumption can be reduced. Thus, the characteristics of the pixel can be altered between the first and second regions.

[0081] Furthermore, since a first transistor included in the first pixel circuit and a second transistor included in the second pixel circuit are connected to the same wiring, the number of wirings can be reduced.

[0082] The second region can be a region located outside the first region and can surround the first region. The second region can have, for example, a ring shape in a plan view. Specifically, for example, the first region of the display area can be the central region of the display area, and the second region of the display area can be the peripheral region of the display area.

[0083] A display device including a first pixel circuit and a second pixel circuit is suitable for devices in which foveated rendering is used (e.g., eyeglasses such as head-mounted displays) because the characteristics of the pixels can be changed between the first region and the second region.

[0084] In the display device according to the present disclosure, the circuit board may further include a first insulating film disposed between the first layer and the second layer, the first layer may further include a plurality of first bonding electrodes, the second layer may further include a plurality of second bonding electrodes, and the first bonding electrodes and the second bonding electrodes may be bonded to each other at the bonding surface by breaking the first insulating film.

[0085] Since the first insulating film is disposed between the first layer and the second layer, the bonding strength between the first layer and the second layer can be increased, and the reliability of the display device can be improved.

[0086] Furthermore, the diffusion of oxygen, hydrogen, etc., from the first layer to the second layer can be suppressed by the first insulating film, and the influence of oxygen, hydrogen, etc., on the second transistor can also be suppressed. Therefore, the characteristic degradation of the second transistor can be suppressed. When the second transistor is a thin-film transistor, the circuit board preferably has a first insulating film because the characteristics of thin-film transistors are particularly prone to degradation due to the influence of oxygen, hydrogen, etc.

[0087] In the display device according to this disclosure, one or both of the first layer and the second layer may further include dummy wiring, and the dummy wiring may be disposed adjacent to the junction surface. When the first transistor emits light due to hot carriers, the light can be blocked by the dummy wiring. Therefore, the effect of the light emission of the first transistor on the second transistor can be suppressed. When the second transistor is a thin-film transistor, it is preferable that one or both of the first layer and the second layer include dummy wiring, because the characteristics of thin-film transistors are particularly susceptible to changes caused by light.

[0088] In the method for manufacturing a display device according to this disclosure, the second layer is formed by forming a third layer including electrodes comprising a plurality of light-emitting elements and a fourth layer including a plurality of wirings on a substrate, and then forming a fifth layer including a plurality of second transistors on the fourth layer. As a result, the effects of the processes for forming the third layer including electrodes comprising a plurality of light-emitting elements and the processes for forming the fourth layer including a plurality of wirings (e.g., factors such as oxygen, hydrogen, heat, etc.) on the second transistors can be suppressed. Therefore, the degradation of the characteristics of the second transistors during the manufacturing of the display device can be suppressed.

[0089] In the display device according to this disclosure, the first layer may further include a first dummy wiring, and the second layer may further include a second dummy wiring. The first dummy wiring and the second dummy wiring may be configured as adjacent mating surfaces, and the first dummy wiring and the second dummy wiring may be mated to each other. In this case, the bonding strength between the first layer and the second layer can be improved, and the reliability of the display device can be improved. The dimensions of the first dummy wiring and the second dummy wiring may be the same or different.

[0090] In the display device according to this disclosure, the second layer may include a second insulating film with barrier properties, and the second insulating film may be disposed between the electrodes of a plurality of second transistors and a plurality of light-emitting elements. The second insulating film can suppress the diffusion of oxygen, hydrogen, etc., from above the second transistors to the second transistors, and can suppress the influence of oxygen, hydrogen, etc., on the second transistors. Therefore, the characteristic degradation of the second transistors can be suppressed. When the second transistor is a thin-film transistor, the circuit board preferably has a first insulating film because the characteristics of thin-film transistors are particularly susceptible to degradation by oxygen, hydrogen, etc.

[0091] In the display device according to this disclosure, the portions between electrodes and adjacent electrodes can be flush with each other to form a flat surface. This facilitates the formation of each layer on the circuit board. For example, it can improve the uniformity of the thickness of each layer formed on the circuit board.

[0092] As described above, because the display device according to this disclosure has a configuration in which the first layer and the second layer are bonded to each other, the second layer can be formed by forming electrodes on the substrate and then forming each layer other than the electrodes. Therefore, the portions between the electrodes and adjacent electrodes can be flush with each other to form a flat surface.

[0093] In the method for manufacturing a display device according to the present disclosure, the first layer may further include a plurality of first bonding electrodes, the second layer may further include a plurality of second bonding electrodes, the step of forming the second layer may further include the step of forming a sixth layer including a plurality of second bonding electrodes on the fifth layer, and in the bonding step, the first bonding electrodes and the second bonding electrodes may be bonded to each other. As a result, the first layer and the second layer can be bonded to each other by bonding a plurality of first bonding electrodes and a plurality of second bonding electrodes.

[0094] The method for manufacturing a display device according to this disclosure may further include the step of forming an insulating film on at least one of a first layer and a second layer. In the bonding step, after the first layer and the second layer are stacked such that the insulating film is sandwiched between them, the constituent materials of the first bonding electrode and the second bonding electrode can be grain-grown by heat treatment. The first bonding electrode and the second bonding electrode can be bonded to each other by breaking the portion of the insulating film located between the first bonding electrode and the second bonding electrode. Therefore, the bonding strength between the first layer and the second layer can be improved, and the reliability of the display device can be improved. Furthermore, insulation can be maintained in the portion between the first layer and the second layer, except for the junction between the first bonding electrode and the second bonding electrode.

[0095] In this disclosure, the bonding between the first layer and the second layer includes "direct bonding" and "indirect bonding", wherein "direct bonding" is used to bond the first layer and the second layer to each other without sandwiching a film or layer such as an insulating film, and "indirect bonding" is used to bond the first layer and the second layer to each other in such a way that a film or layer such as an insulating film is interposed therebetween.

[0096] The light-emitting device according to this disclosure can perform color display. When the display device is capable of color display, a pixel (unit pixel / pixel) used as a unit for forming a color image may include multiple sub-pixels. More specifically, for example, in a display device capable of color display, a pixel may include, for example, three sub-pixels (sub-pixels of the three primary colors), namely, a sub-pixel capable of emitting red light, a sub-pixel capable of emitting green light, and a sub-pixel capable of emitting blue light. However, the configuration of a pixel is not limited to a combination of sub-pixels of the three primary colors, and a pixel can be constructed by further adding sub-pixels of one or more colors to the sub-pixels of the three primary colors. More specifically, for example, in a display device, a pixel can be configured to increase brightness by adding a sub-pixel capable of emitting white light, or a pixel can be configured to expand the color reproduction range by adding at least one sub-pixel capable of emitting complementary color light.

[0097] The light-emitting device according to this disclosure can be a display device, a lighting device, or other device. The display device can be an organic light-emitting diode (OLED) display device, an LED display device, or other display device.

[0098] The display device according to this disclosure can be installed in an electronic device. For example, the display device according to this disclosure can be installed in eyeglasses, such as virtual reality (VR) devices, mixed reality (MR) devices, or augmented reality (AR) devices, or it can be installed in an electronic viewfinder (EVF), a small projector, etc.

[0099] In this disclosure, "on object A" in expressions such as "object B is set on object A" indicates the relative positional relationship between object A and object B. The term "on object A" includes not only the state in which object B is directly on object A without any other object inserted between them, but also the state in which object B is on object A with at least one other object inserted between them.

[0100] In this disclosure, the refractive index is the refractive index under light with a wavelength of 589.3 nm (the D line of sodium).

[0101] <2 Background of the Implementation Method Disclosed Herein>

[0102] As described above, in a drive circuit board having a first layer comprising a plurality of first transistors and a second layer comprising a plurality of second transistors arranged in sequence, the second transistors are affected by the process following their formation, and the characteristics of the second transistors may deteriorate.

[0103] In particular, when the second transistor is a thin-film transistor such as an oxide semiconductor thin-film transistor, there is a possibility that the characteristics of the second transistor may deteriorate significantly under the influence of oxygen, hydrogen, heat, etc. Specifically, for example, when a thin-film transistor (such as an oxide semiconductor thin-film transistor) is formed into multiple second transistors and then a wiring layer is formed on the multiple second transistors, there is a possibility that the characteristics of the second transistors may deteriorate significantly due to the influence of oxygen, hydrogen, heat, etc. during the formation of the wiring layer, etc. Because oxygen, hydrogen, heat, etc. are usually used in the process of forming the circuit board, it is difficult to control the deterioration of the characteristics of the second transistors.

[0104] In view of the above problems, the inventors focused their research on display devices capable of suppressing the degradation of the characteristics of the second transistors during the manufacturing process. As a result, the inventors discovered a display device comprising a circuit board in which a second layer including a plurality of second transistors is bonded to a first layer including a plurality of first transistors.

[0105] <3 First Implementation Method>

[0106] [Overall configuration of display device 1]

[0107] Reference Figure 1 An embodiment of the overall configuration of a display device 1 according to a first embodiment of the present disclosure is described. The display device 1 includes a pixel array unit 20 and a driving circuit unit disposed around the pixel array unit 20.

[0108] The pixel array unit 20 includes a plurality of sub-pixels 2R, 2G, and 2B. Sub-pixel 2R is capable of emitting red light (first light). Sub-pixel 2G is capable of emitting green light (second light). Sub-pixel 2B is capable of emitting blue light (third light). In the following description, when sub-pixels 2R, 2G, and 2B are collectively referred to without special distinction from each other, sub-pixels 2R, 2G, and 2B may be simply referred to as sub-pixels 2. The plurality of sub-pixels 2 are arranged in a two-dimensional pattern on the circuit board 10. In the first embodiment, an embodiment in which the prescribed pattern is a striped arrangement is described, but it is not limited to this, and may also be a square arrangement, a mosaic arrangement, a triangular arrangement, or other arrangements.

[0109] In this specification, a first direction and a second direction orthogonal to each other on the display surface of the display device 1 will be referred to as the X-axis direction and the Y-axis direction, respectively, and a third direction perpendicular to the display surface of the display device 1 will be referred to as the Z-axis direction. In the first embodiment, an embodiment in which the X-axis direction is the horizontal direction (row direction) of the display surface and the Y-axis direction is the vertical direction (column direction) of the display surface will be described.

[0110] In the first embodiment, the display device 1 will be described as an embodiment of a top-emitting display device, but the type of display device 1 is not limited to this embodiment. The display device 1 may be a microdisplay.

[0111] In the first embodiment, an embodiment in which the display device 1 is capable of color display will be described. More specifically, an embodiment in which a pixel (unit pixel / pixel) used as a unit for forming a color image comprises three sub-pixels 2R, 2G, and 2B of adjacent primary colors will be described. However, the configuration of a pixel is not limited to this embodiment, and a pixel may be configured by a combination of sub-pixels 2R, 2G, and 2B of the three primary colors and sub-pixels of one or more colors.

[0112] The driving circuit unit drives each sub-pixel 2 of the pixel array unit 20. The driving circuit unit includes a write scan unit 21, a drive scan unit 22, and a signal output unit 23. The write scan unit 21, the drive scan unit 22, and the signal output unit 23 are mounted on the same circuit board 10 as the pixel array unit 20.

[0113] In pixel array unit 20, scan lines 21a (21a1 to 21a2) m ) and drive line 22a (22a1 to 22a) m An array of sub-pixels 2 in m rows and n columns is routed along the row direction (X-axis direction) for the corresponding pixel rows. Additionally, signal lines 23a (23a1 to 23a) are routed along the column direction (Y-axis direction) relative to the array of sub-pixels 2 in m rows and n columns for the corresponding pixel columns.

[0114] Scan lines 21a1 to 21a m Electrically connected to the output terminal of the corresponding row of the write scan unit 21. Drive lines 22a1 to 22a m Electrically connected to the output terminal of the corresponding row of the drive scan unit 22. Signal lines 23a1 to 23a n It is electrically connected to the output terminal of the corresponding column of the signal output section 23.

[0115] The write scan unit 21 includes a shift register circuit, etc. When writing the signal voltage of the video signal to each sub-pixel 2 of the pixel array unit 20, the write scan unit 21 can move the signal voltage of the video signal to the scan lines 21a (21a1 to 21a2). m The write scan signals WS (WS1 to WS2) are provided sequentially. m The sub-pixels 2 of the pixel array unit 20 are scanned line by line in sequence.

[0116] Similar to the write scan unit 21, the drive scan unit 22 includes a shift register circuit, etc. The drive scan unit 22 can synchronously scan the light emission control signals DS (DS1 to DS2) with the line sequence of the write scan unit 21. mSupply to drive line 22a (22a1 to 22a) m The light emission / non-light emission (extinction) of sub-pixel 2 is controlled by a drive scanning unit 22. It should be noted that in the first embodiment, the display device 1 may not be provided with a drive scanning unit 22 capable of controlling the light emission / non-light emission (extinction) of sub-pixel 2.

[0117] The signal output unit 23 selectively outputs the signal voltage (hereinafter referred to as "signal voltage") Vsig of the video signal based on the brightness information supplied from the signal supply source (not shown) and the reference voltage Vofs. Here, the reference voltage Vofs is a voltage corresponding to or near the voltage used as a reference for the signal voltage Vsig of the video signal.

[0118] The signal voltage Vsig / reference voltage Vofs selectively output from the signal output unit 23 is written to each sub-pixel 2 of the pixel array unit 20 via corresponding signal lines in the signal lines 23a (23a1 to 23a) in unit of the pixel columns selected in the line sequence scan of the write scan unit 21. That is, the signal output unit 23 can write the signal voltage Vsig in unit of pixel columns (lines).

[0119] [Configuration of pixel circuit 2a]

[0120] Next, we will refer to Figure 2 An embodiment of the circuit configuration of the pixel circuit 2a of the display device 1 according to the first embodiment of this disclosure is described. It should be noted that... Figure 2 The circuit configuration shown corresponds to the pixel circuit 2a of the display device 1 without providing a drive scanning unit 22 capable of controlling the light emission / non-light emission (extinction) of the sub-pixels 2. Multiple pixel circuits 2a are provided corresponding to multiple sub-pixels 2. That is, one pixel circuit 2a is provided for each sub-pixel 2.

[0121] In the first embodiment, such as Figure 2 As shown, pixel circuit 2a includes a light-emitting element 13 and a driving circuit for driving the light-emitting element. The light-emitting element 13 is a current-driven electro-optic element, wherein the brightness of the emitted light changes according to the value of the current flowing through the device. The cathode electrode of the light-emitting element 13 is electrically connected, for example, to a node Vss for generating current.

[0122] Furthermore, the driving circuit includes a driving transistor Tr1, a writing transistor Tr2, and a capacitor C1. The anode of the light-emitting element 13 is electrically connected to the driving transistor Tr1, and it emits light when current flows through the driving transistor Tr1. Moreover, the driving transistor Tr1 and the writing transistor Tr2 are, for example, field-effect transistors (FETs). More specifically, the driving transistor Tr1 is a P-channel transistor, and the writing transistor Tr2 is an N-channel transistor.

[0123] Specifically, such as Figure 2 As shown, the source and drain of the write transistor Tr2 are electrically connected to the signal line (Vsig) and the gate (control terminal) of the drive transistor Tr1, respectively, and the gate of the write transistor Tr2 is electrically connected to the scan line (WS). The write transistor Tr2 can write to the gate node of the drive transistor Tr1 by sampling the signal voltage Vsig supplied from the signal output section 23. It should be noted that the expression "write" here means that the signal voltage is applied to the gate node, and the potential of the gate node is maintained at a potential based on the signal voltage.

[0124] The source and drain of the driving transistor Tr1 are electrically connected to the power supply voltage V. DD The anode electrode of the light-emitting element 13. The driving transistor Tr1 can drive the light-emitting element 13 by causing a driving current, based on the voltage held by the capacitor element C1 described later, to flow through the light-emitting element 13.

[0125] Capacitor C1 is connected between the gate and source of driving transistor Tr1 and is able to maintain the signal voltage Vsig that is sampled and written by writing transistor Tr2.

[0126] [Layer configuration of display device 1]

[0127] Next, we will refer to Figure 3 and Figure 4 An embodiment of the layer configuration of the display device 1 according to the first embodiment of this disclosure is described. For example... Figure 3 As shown, the display device 1 sequentially includes a circuit board 10, an OLED layer 132, an electrode 133, a protective layer 14, a planarization layer 15, a color filter (color filter layer) 16, a planarization layer 17, a lens array 18, and a sealing resin layer 19. In the first embodiment, an example of providing the protective layer 14, the planarization layer 15, the color filter 16, the planarization layer 17, the lens array 18, and the sealing resin layer 19 will be described; however, these layers are not essential components, and at least one of these layers may or may not be provided.

[0128] In this specification, of the two surfaces constituting each layer of the display device 1, the surface on the display surface side (top side) of the display device 1 may be referred to as the first surface (upper surface), and the surface on the opposite side (bottom side) of the display surface of the display device 1 may be referred to as the second surface (lower surface). In this specification, the peripheral portion of the first surface refers to a region having a predetermined width extending inward from the peripheral edge of the first surface, and the peripheral portion of the second surface refers to a region having a predetermined width extending inward from the peripheral edge of the second surface. In this specification, the plan view represents a plan view when the object is viewed from a direction perpendicular to the first surface or the second surface.

[0129] (Circuit Board 10)

[0130] Multiple light-emitting elements 13 are disposed on the first surface side of the circuit board 10. The light-emitting elements 13 can emit white light under the control of driving circuitry, etc. In the first embodiment, the light-emitting elements 13 are organic light-emitting diode elements (OLED elements). The light-emitting elements 13 are included in sub-pixels 2R, 2G, and 2B of various colors.

[0131] Multiple light-emitting elements 13 are arranged in a two-dimensional pattern on the first surface of the circuit board 10. The specified pattern is described as a specified arrangement of multiple sub-pixels 2. Each light-emitting element 13 includes an electrode 131, an OLED layer 132, and an electrode 133 in sequence.

[0132] like Figure 4 As shown, the circuit board 10 includes a first layer 11 and a second layer 12. The second layer 12 is disposed on a first surface of the first layer 11, and the first surface of the first layer 11 and the second surface of the second layer 12 are bonded to each other. Note that in Figure 4 In this context, the area represented by FEOL represents the area formed by the front-end process (FEOL), and the area represented by BEOL represents the area formed by the back-end process (BEOL). Figure 4 In the accompanying diagrams, FEOL and BEOL represent these regions, respectively.

[0133] (First floor 11)

[0134] The first layer 11 sequentially includes a semiconductor substrate 11a and an electrode and wiring layer (hereinafter referred to as the "electrode / wiring layer") 11b. A plurality of driving transistors (current source transistors) Tr1 are disposed on the first surface side of the semiconductor substrate 11a. More specifically, the semiconductor substrate 11a includes a plurality of source / drain regions (first diffusion regions) 112 and a plurality of source / drain regions (second diffusion regions) 113. The plurality of source / drain regions 112 and the plurality of source / drain regions 113 are separately disposed on the first surface side of the semiconductor substrate 11a. The semiconductor substrate 11a is preferably a silicon substrate. The silicon substrate includes, for example, monocrystalline silicon or polycrystalline silicon. A driving transistor Tr1 is provided for one sub-pixel 2.

[0135] The electrode / wiring layer 11b sequentially includes an electrode layer 11b1, a wiring layer 11b2, and an electrode layer 11b3 on the first surface of the circuit board 10. The electrode layer 11b1 includes a plurality of gate electrodes 111 and a plurality of vias (not shown). The wiring layer 11b2 includes a plurality of wirings 115 and a plurality of vias (not shown). The wiring layer 11b2 can be a multilayer wiring layer in which two or more layers of wirings 115 are stacked, or it can be a single-layer wiring layer in which one layer of wirings 115 is disposed. Figure 4An embodiment of a multilayer wiring layer in which two layers of wiring 115 are stacked is shown. Electrode layer 11b3 includes a plurality of bonding electrodes 114 and a plurality of vias (not shown). Electrode / wiring layer 11b (e.g., electrode layer 11b3) may include capacitor element C1.

[0136] The first layer 11 is formed by stacking multiple insulating layers 110b1, 110b2, and 110b3, which include the aforementioned components. In the following description, where insulating layers 110b1, 110b2, and 110b3 are not specifically distinguished from each other and are collectively referred to, insulating layers 110b1, 110b2, and 110b3 may be simply referred to as insulating layer 110b.

[0137] Figure 4 The locations of the interfaces between insulating layers 110b and the number of insulating layers 110b shown are embodiments and are not limited to these embodiments. Each insulating layer 110b may have a single-layer structure or a stacked structure. The insulating layer 110b serves as an interlayer insulating layer, a planarization layer, etc. For example, the insulating layer 110b contains materials selected from silicon oxide (SiO2). x Silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y At least one of the groups including (e.g.)

[0138] A gate electrode 111 is disposed on the second surface side (semiconductor substrate 11a side) of the electrode / wiring layer 11b, and more specifically, on the second surface side of the electrode layer 11b1. The gate electrode 111 is located above the channel region between the separately disposed source / drain regions 112 and 113, and an insulating layer is sandwiched between the gate electrode 111 and the channel region. In the first embodiment, the channel region is an n-type semiconductor region, and the source / drain regions 112 and 113 are p-type semiconductor regions.

[0139] Each driving transistor Tr1 includes a gate electrode 111 contained in the electrode / wiring layer 11b and source / drain regions 112 and 113 contained in the semiconductor substrate 11a. The driving transistor Tr1 is a P-channel transistor in the first embodiment. The driving transistor Tr1 is a field-effect transistor, more specifically, a metal-oxide-semiconductor field-effect transistor (MOSFET). The driving transistor Tr1 is an embodiment of the first transistor. It should be noted that in the first embodiment, an embodiment of the driving transistor Tr1 as a P-channel transistor will be described, but the driving transistor Tr1 is not limited to this embodiment and may be an N-channel transistor.

[0140] A bonding electrode 114 is disposed on the first surface side of the electrode / wiring layer 11b (the bonding surface side to the second layer 12), more specifically, on the first surface side of the electrode layer 11b3. The bonding electrode 114 is embedded in the electrode / wiring layer 11b with its first surface exposed on the first surface of the electrode / wiring layer 11b. The first surface of the bonding electrode 114 is flush with the first surface of the portion of the electrode / wiring layer 11b other than the portion where the bonding electrode 114 is disposed.

[0141] Wiring 115 includes, for example, a metal layer. For example, the metal layer contains at least one metal selected from the group consisting of tungsten (W), copper (Cu), etc.

[0142] A via connects the drive transistor Tr1 (gate electrode 111, source / drain region 112, and source / drain region 113) and wiring 115. The via connects wiring 115 to each other. The via connects wiring 115 and bonding electrode 114. For example, the via contains at least one metal selected from the group consisting of tungsten (W), copper (Cu), titanium (Ti), etc.

[0143] (Second layer 12)

[0144] The second layer 12 is an electrode / wiring layer, and sequentially includes an electrode layer 12a1, a transistor layer 12a2, a wiring layer 12a3, and an electrode layer 12a4 on the first surface of the first layer 11. The electrode layer 12a1 includes a plurality of bonding electrodes 121 and a plurality of vias (not shown). The transistor layer 12a2 includes a plurality of write transistors Tr2 and a plurality of vias (not shown). The wiring layer 12a3 includes a plurality of wirings 122 and a plurality of vias (not shown). The wiring layer 12a3 can be a multilayer wiring layer in which two or more layers of wirings 122 are stacked, or it can be a single-layer wiring layer in which one layer of wiring 122 is provided. Figure 4 An embodiment of a multilayer wiring layer in which two layers of wiring 122 are stacked is shown. Electrode layer 12a4 includes a plurality of electrodes 131 and a plurality of vias 123. Electrode layer 12a4, wiring layer 12a3, transistor layer 12a2 and electrode layer 12a1 are embodiments of the third, fourth, fifth and sixth layers, respectively.

[0145] The second layer 12 is formed by stacking multiple insulating layers 120a1, 120a2, 120a3, and 120a4, which include the aforementioned components. In the following description, when insulating layers 120a1, 120a2, 120a3, and 120a4 are collectively referred to without particular distinction from one another, insulating layers 120a1, 120a2, 120a3, and 120a4 may be simply referred to as insulating layer 120a.

[0146] Figure 4The locations of the interfaces between insulating layers 120a and the number of insulating layers 120a shown are embodiments, but are not limited to these embodiments. Each insulating layer 120a may have a single-layer structure or a stacked structure. The insulating layer 120a serves as an interlayer insulating layer, a planarization layer, etc. As an embodiment, a material similar to the material of insulating layer 110b can be used as the material of insulating layer 120a.

[0147] A bonding electrode 121 is disposed on the second surface side of the second layer 12 (bonding to the bonding surface side of the first layer 11). The bonding electrode 121 is embedded in the second layer 12 with its second surface exposed on the second surface of the second layer 12. The second surface of the bonding electrode 121 is flush with the second surface of the second layer 12 except for the portion where the bonding electrode 121 is disposed.

[0148] The second surface of the bonding electrode 121 is bonded to the first surface of the bonding electrode 114. Preferably, the bonding electrode 121 and the bonding electrode 114 contain copper (Cu). In this case, the bonding of the bonding electrode 121 and the bonding electrode 114 is preferably a Cu-Cu bonding. One bonding electrode 121 and one bonding electrode 114 are bonded to form a bonding portion 101. One bonding portion 101 is provided for one sub-pixel 2.

[0149] The write transistor Tr2 is disposed separately from the junction between the first layer 11 and the second layer 12 (i.e., the junction between the electrode / wiring layer 11b and the second layer 12). More specifically, the write transistor Tr2 is disposed on a layer at least one layer higher than the junction between the first layer 11 and the second layer 12. Figure 4 An embodiment is shown in which the write transistor Tr2 is disposed on a layer one level above the junction between the first layer 11 and the second layer 12.

[0150] The write transistor Tr2 is disposed within the insulating layer 120a2. The write transistor Tr2 is preferably disposed above the drive transistor Tr1. Arranging the write transistor Tr2 in this manner simplifies the wiring connection between the drive transistor Tr1 and the write transistor Tr2.

[0151] In the first embodiment, the write transistor Tr2 is an N-channel transistor. The write transistor Tr2 is a field-effect transistor, more specifically, a thin-film transistor (TFT). The thin-film transistor is preferably an oxide semiconductor thin-film transistor (oxide semiconductor TFT). The write transistor Tr2 is an embodiment of a second transistor. It should be noted that in the first embodiment, an embodiment where the write transistor Tr2 is an N-channel transistor will be described, but the write transistor Tr2 is not limited to this embodiment and may be a P-channel transistor.

[0152] Each write transistor Tr2 includes a thin-film semiconductor layer 124, a gate electrode 125, a source / drain electrode 126, and a source / drain electrode 127. The gate electrode 125 is located between the separately disposed source / drain electrode 126 and source / drain electrode 127, and an insulating layer is sandwiched between the gate electrode 125 and the thin-film semiconductor layer 124.

[0153] In the first embodiment, each write transistor Tr2 has a top-gate structure in which the gate electrode 224 is located above the thin-film semiconductor layer 124. That is, when viewed from the first surface of the second layer 12 (the surface opposite to the bonding surface of the second layer 12), the gate electrode 125 of the write transistor Tr2 is disposed on the front side of the thin-film semiconductor layer 124 of the write transistor Tr2. However, the structure of each write transistor Tr2 is not limited to a top-gate structure, but may be, for example, a bottom-gate structure in which the gate electrode 125 is located below the thin-film semiconductor layer 124, or a dual-gate structure including two gate electrodes 125. When the structure of each write transistor Tr2 is a bottom-gate structure, when viewed from the first surface of the second layer 12 (the surface opposite to the bonding surface of the second layer 12), the gate electrode 125 of the write transistor Tr2 is disposed on the back side of the thin-film semiconductor layer 124 of the write transistor Tr2.

[0154] Each of the thin-film semiconductor layers 124 has a first surface facing the gate electrode 125, the source / drain electrode 126, and the source / drain electrode 127, and this first surface is flat. The reason the first surface is flat, as described above, is that, as described later in the method for manufacturing the display device 1, the second layer 12 is formed by stacking the electrode layers 12a4 to 12a1 in that order. Therefore, the thin-film semiconductor layer 124 is formed after the gate electrode 125, the source / drain electrode 126, and the source / drain electrode 127 are formed. Therefore, scraping of the thin-film semiconductor layer 124 during the formation of the gate electrode 125, the source / drain electrode 126, and the source / drain electrode 127 can be prevented, and a flat first surface is obtained as described above.

[0155] Each of the thin-film semiconductor layers 124 comprises, for example, a silicon layer or an oxide layer. The silicon layer may comprise, for example, polycrystalline silicon (poly-Si). The oxide layer may comprise, for example, at least one metal selected from the group consisting of aluminum (Al), indium (In), gallium (Ga), and zinc (Zn). More specifically, the oxide layer may comprise, for example, indium oxide (In₂O₃), indium gallium zinc oxide (a material obtained by adding In and Ga as dopants to ZnO₄, e.g., IGZO), aluminum zinc oxide (a material by adding Al as a dopant to ZnO, e.g., AZO), or indium zinc oxide (a material by adding In as a dopant to ZnO, e.g., IZO). Because oxide films such as IGZO have extremely low leakage current and can suppress leakage current written to transistor Tr2, each thin-film semiconductor layer 124 preferably comprises an oxide film such as IGZO. In this way, an increase in the power consumption of the display device 1 can be suppressed.

[0156] Electrode 131 is disposed on the first surface side of the second layer 12 (the surface side on which the light-emitting element 13 is disposed). The first surface of electrode 131 is flat. Electrode 131 is embedded in the second layer 12 with its first surface exposed on the first surface of the insulating layer 120. The first surface of electrode 131 is flush with the first surface of the portion of the second layer 12 except for the portion where electrode 131 is disposed. The first surface of the second layer 12 is a flat surface. More specifically, the portions between electrode 131 and adjacent electrodes 131 are flush with each other to form a flat surface.

[0157] Electrode 131 is disposed on the second surface side of OLED layer 132. Electrode 131 is a separate electrode disposed individually for each of the plurality of light-emitting elements 13. That is, electrode 131 is separated between adjacent light-emitting elements 13 in the in-plane direction of the first surface of circuit board 10. Electrode 131 is an anode electrode. When a voltage is applied between electrode 131 and electrode 133, holes are injected from electrode 131 into OLED layer 132.

[0158] Electrodes 131 may all include, for example, a metal layer, or may include a metal layer and a transparent conductive oxide layer. When electrodes 131 all include a metal layer and a transparent conductive oxide layer, from the viewpoint that a layer with a high work function is adjacent to the OLED layer 132, the transparent conductive oxide layer is preferably disposed on the OLED layer 132 side.

[0159] The metal layer may function as a reflective layer that reflects light emitted from the OLED layer 132. For example, the metal layer may contain at least one metallic element selected from the group consisting of chromium (Cr), gold (Au), platinum (Pt), nickel (Ni), copper (Cu), molybdenum (Mo), titanium (Ti), tantalum (Ta), aluminum (Al), magnesium (Mg), iron (Fe), tungsten (W), and silver (Ag). The metal layer may contain at least one metallic element as a constituent element of an alloy. Specific examples of alloys include aluminum alloys and silver alloys. Specific examples of aluminum alloys include AlNd and AlCu.

[0160] A substrate layer (not shown) may be disposed adjacent to the second surface side of the metal layer. The substrate layer can improve the crystal orientation of the metal layer during its formation. The substrate layer may, for example, contain at least one metallic element selected from the group consisting of titanium (Ti) and tantalum (Ta). The substrate layer may contain at least one metallic element as a constituent element of the alloy.

[0161] The transparent conductive oxide layer comprises a transparent conductive oxide. The transparent conductive oxide comprises, for example, at least one selected from the group consisting of: a transparent conductive oxide containing indium (hereinafter referred to as "indium-based transparent conductive oxide"), a transparent conductive oxide containing tin (hereinafter referred to as "tin-based transparent conductive oxide"), and a transparent conductive oxide containing zinc (hereinafter referred to as "zinc-based transparent conductive oxide").

[0162] Indium-based transparent conductive oxides include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), or fluorine-doped indium oxide (IFO). Among these transparent conductive oxides, indium tin oxide (ITO) is particularly preferred. Indium tin oxide (ITO) has a particularly low barrier for hole injection into the OLED layer 132 in terms of work function, thereby significantly reducing the driving voltage of the display device 1. Tin-based transparent conductive oxides include, for example, tin oxide, antimony-doped tin oxide (ATO), or fluorine-doped tin oxide (FTO). Zinc-based transparent conductive oxides include, for example, zinc oxide, aluminum-doped zinc oxide (AZO), boron-doped zinc oxide, or gallium-doped zinc oxide (GZO).

[0163] Wiring 122 includes, for example, a metal layer. For example, the metal layer contains at least one metal selected from the group consisting of tungsten (W), copper (Cu), etc.

[0164] The number of wiring layers 115 in the first layer 11 and the number of wiring layers 122 in the second layer 12 can be the same or different from each other. To bring the driving transistor Tr1 and the writing transistor Tr2 closer together, the number of wiring layers 115 in the first layer 11 is preferably less than the number of wiring layers 122 in the second layer 12. It should be noted that when the driving transistor Tr1 and the writing transistor Tr2 can be brought close together, the wiring connection between the driving transistor Tr1 and the writing transistor Tr2 becomes easier.

[0165] A via connects the bonding electrode 121 and the wiring 122. A via connects the write transistor Tr2 (gate electrode 125, source / drain electrode 126, and source / drain electrode 127) and the wiring 122. The via connects the wiring 122 to each other. A via 123 connects the wiring 122 to the electrode 131. For example, the via contains at least one metal selected from the group consisting of tungsten (W), copper (Cu), titanium (Ti), etc.

[0166] (OLED layer 132)

[0167] The OLED layer 132 is capable of emitting white light. The OLED layer 132 is an embodiment of an organic layer containing an organic light-emitting layer. The OLED layer 132 is disposed between a plurality of electrodes 131 and an electrode 133. The OLED layer 132 connects adjacent light-emitting elements 13 in the in-plane direction on the first surface of the circuit board 10 and is a layer shared by a plurality of light-emitting elements 13.

[0168] The OLED layer 132 can be configured using a stack including an organic light-emitting layer, and in this case, a subset of the layers of the stack (e.g., an electron injection layer) can be an inorganic layer. The OLED layer 132 can be an OLED layer including a single light-emitting unit, an OLED layer including two light-emitting units (a stacked structure), or an OLED layer having a structure other than these. The OLED layer 132 including a single light-emitting unit has, for example, a hole injection layer, a hole transport layer, a red light-emitting layer, a light-emitting separation layer, a blue light-emitting layer, a green light-emitting layer, an electron transport layer, and an electron injection layer stacked sequentially from electrode 131 toward electrode 133. The OLED layer including two light-emitting units has, for example, a hole injection layer, a hole transport layer, a blue light-emitting layer, an electron transport layer, a charge generation layer, a hole transport layer, a yellow light-emitting layer, an electron transport layer, and an electron injection layer stacked sequentially from electrode 131 toward electrode 133.

[0169] The hole injection layer improves the hole injection efficiency into the emissive layer and suppresses leakage. The hole transport layer improves the hole transport efficiency into the emissive layer. The electron injection layer improves the electron injection efficiency into the emissive layer. The electron transport layer improves the electron transport efficiency into the emissive layer. The light-emitting separation layer is used to regulate carrier injection into the emissive layer and adjusts the light emission balance of each color by injecting electrons or holes into the emissive layer via the light-emitting separation layer. The charge generation layer supplies electrons and holes to the blue and yellow emissive layers, which are sandwiched between the charge generation layer, respectively.

[0170] When an electric field is applied to each of the red, green, blue, and yellow light-emitting layers, recombination occurs between holes injected from electrode 131 or the charge generation layer and electrons injected from electrode 133 or the charge generation layer, and red, green, blue, and yellow light can be emitted.

[0171] (Electrode 133)

[0172] Electrode 133 is disposed on the first surface side of OLED layer 132. Electrode 133 is connected between adjacent light-emitting elements 13 in the in-plane direction of the first surface of circuit board 10, and is a shared electrode of multiple light-emitting elements 13.

[0173] Electrode 133 is a cathode electrode. When a voltage is applied between electrodes 131 and 133, electrons are injected from electrode 133 into the OLED layer 132. Electrode 133 is semi-transparent to white light emitted from the OLED layer 132. Electrode 133 is preferably a transparent electrode that is transparent to visible light. In this specification, visible light refers to light in the wavelength range of 360 nm to 780 nm.

[0174] To improve luminous efficiency, electrode 133 preferably comprises a material with the highest possible translucency and low work function. Electrode 133 comprises at least one of, for example, a metal layer and a transparent conductive oxide layer. More specifically, electrode 133 comprises a single-layer film of a metal layer or a transparent conductive oxide layer, or a laminated film of a metal layer and a transparent conductive oxide layer. When electrode 133 comprises a laminated film, a metal layer or a transparent conductive oxide layer may be disposed on the OLED layer 132 side, but from the viewpoint of adjacent a layer with a low work function to the OLED layer 132, it is preferable to dispose of a metal layer on the OLED layer 132 side.

[0175] For example, the metal layer includes at least one metallic element selected from the group consisting of magnesium (Mg), aluminum (Al), silver (Ag), calcium (Ca), and sodium (Na). The metal layer may contain at least one metallic element as a constituent element of an alloy. Specific examples of alloys include MgAg alloys, MgAl alloys, AlLi alloys, etc. The transparent conductive oxide layer includes a transparent conductive oxide. As an example, the same material as the transparent conductive oxide of electrode 131 can be used as the transparent conductive oxide.

[0176] (Protective layer 14)

[0177] A protective layer 14 is disposed on the first surface of the electrode 133 and covers a plurality of light-emitting elements 13. The protective layer 14 is translucent to white light emitted from the light-emitting elements 13. The protective layer 14 can protect the plurality of light-emitting elements 13, etc. For example, the protective layer 14 can prevent moisture from entering the plurality of light-emitting elements 13, etc. from the external environment. Furthermore, when the electrode 133 includes a metal layer, the protective layer 14 can have the function of inhibiting the oxidation of the metal layer.

[0178] The protective layer 14 comprises at least one of inorganic and organic materials, for example, materials with low hygroscopicity. The protective layer 14 may have a single-layer or multi-layer structure. A multi-layer structure is preferred when the thickness of the protective layer 14 is increased. This is to alleviate internal stress in the protective layer 14. For example, the inorganic material includes materials selected from silicon dioxide (SiO₂). x Silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y Titanium oxide (TiO) x ), aluminum oxide (AlO) x At least one from the group consisting of, etc. For example, the organic material includes a cured product of at least one resin selected from the group consisting of thermosetting resin compositions, photosensitive resin compositions, etc. The photosensitive resin composition includes, for example, an ultraviolet-curable resin composition. Specifically, the organic material includes, for example, at least one selected from the group consisting of acrylic resins, polyimide resins, phenolic varnish resins, epoxy resins, norbornene resins, parylene resins, etc.

[0179] The protective layer 14 preferably comprises a deposited layer obtained by depositing atomic layers. The deposited layer can be an atomic layer deposition (ALD) layer. The protective layer 14 including the deposited layer can enhance the moisture ingress inhibition effect of the protective layer 14. The deposited layer includes, for example, metal oxides or metal nitrides. Metal oxides include, for example, aluminum oxide (Al₂O₃). x ) or titanium dioxide (TiO) x Metal nitrides include, for example, titanium nitride (TiNx).

[0180] (Planarization layer 15)

[0181] A planarization layer 15 is disposed on the first surface of the protective layer 14. The planarization layer 15 is an example of a first resin layer. The planarization layer 15 can fill irregularities in the first surface of the protective layer 14 and forms a flat first surface over the protective layer 14. The planarization layer 15 is translucent to white light emitted from the light-emitting element 13. The planarization layer 15 comprises at least one of, for example, organic and inorganic materials.

[0182] Organic materials include, for example, cured photosensitive resin compositions. The photosensitive resin compositions may include positive or negative photosensitive resin compositions. Specifically, the photosensitive resin compositions include, for example, at least one selected from the group consisting of polyimides, polyimide precursors, polybenzoxazoles, polybenzoxazole precursors, acrylic resins, phenolic resins, siloxane resins, etc. For inorganic materials, as an example, a material similar to the inorganic material of protective layer 14 may be used.

[0183] (Color Filter 16)

[0184] Color filter 16 is a so-called on-chip color filter (OCCF). Color filter 16 is disposed above a plurality of light-emitting elements 13. More specifically, color filter 16 is disposed on a first surface of planarization layer 15. Color filter 16 includes, for example, a plurality of color layers 160R, a plurality of color layers 160G, and a plurality of color layers 160B. Note that in the following description, when color layers 160R, color layers 160G, and color layers 160B are collectively referred to without particular distinction from each other, color layers 160R, color layers 160G, and color layers 160B may be simply referred to as color layer 160.

[0185] Multiple color layers 160 are arranged two-dimensionally on the first surface of the planarization layer 15 in a prescribed pattern. The prescribed pattern describes a prescribed arrangement of multiple sub-pixels 2. Each color layer 160 is disposed above a corresponding light-emitting element 13. Each sub-pixel 2R includes a light-emitting element 13 and a color layer 160R disposed above the light-emitting element 13. Each sub-pixel 2G includes a light-emitting element 13 and a color layer 160G disposed above the light-emitting element 13. Each sub-pixel 2B includes a light-emitting element 13 and a color layer 160B disposed above the light-emitting element 13.

[0186] Color layer 160R is red. Color layer 160R can transmit the red light component of the white light emitted from the light-emitting element 13 and absorb components other than red light. Color layer 160G is green. Color layer 160G can transmit the green light component of the white light emitted from the light-emitting element 13 and absorb components other than green light. Color layer 160B is blue. Color layer 160B can transmit the blue light component of the white light emitted from the light-emitting element 13 and absorb components other than blue light.

[0187] Each coloring layer 160R includes, for example, a red resist. Each coloring layer 160G includes, for example, a green resist. Each coloring layer 160B includes, for example, a blue resist.

[0188] (Planarization layer 17)

[0189] A planarization layer 15 is disposed on the first surface of the color filter 16. Planarization layer 17 is an example of a second resin layer. Planarization layer 17 can fill the irregularities of the first surface of the color filter 16 and form a flat first surface above the color filter 16. Planarization layer 17 is translucent for red, green, and blue light emitted from the color filter 16. As an example, a material similar to that of planarization layer 15 can be used as the material of planarization layer 17.

[0190] (Lens array 18)

[0191] A lens array 18 is disposed on the first surface of the planarization layer 17. The lens array 18 includes a plurality of lenses 181. Each lens 181 can converge light emitted upward from the light-emitting element 13 and incident through the color layer 160 in the frontal direction. The lens 181 is a convex lens having a convex light-gathering surface on the side opposite to the light-emitting element 13. The plurality of lenses 181 are so-called on-chip microlenses (OCL) and are arranged two-dimensionally on the first surface of the planarization layer 17 in a prescribed arrangement pattern. The prescribed arrangement pattern is described as a prescribed arrangement pattern of a plurality of sub-pixels 2. In the planar view, the center of each lens 181 is substantially aligned with the center of the light-emitting area of ​​the light-emitting element 13.

[0192] The focusing surface of each lens 181 preferably has a convex curved surface shape. Examples of convex curved surface shapes include, but are not limited to, for example, approximately parabolic shapes and approximately hemispherical shapes. Here, approximately parabolic or approximately hemispherical shapes are not strictly limited to parabolic or hemispherical shapes, but include shapes that are visually recognized as parabolic or hemispherical shapes. For example, approximately parabolic or approximately hemispherical shapes include parabolic or hemispherical shapes that are distorted or deformed within tolerances, errors, etc.

[0193] The refractive index n1 of lens 181 is higher than the refractive index n2 of sealing resin layer 19. Because the refractive index n1 of lens 181 is higher than the refractive index n2 of sealing resin layer 19, light can be refracted and converged at the interface between lens 181 and sealing resin layer 19. Therefore, the light extraction function can be improved.

[0194] Each lens 181 comprises, for example, an organic or inorganic material that is transparent to visible light. Organic materials include, for example, cured forms of photosensitive resin compositions such as UV-curable resin compositions. Inorganic materials include, for example, materials selected from silicon nitride (SiN). x ), silicon oxynitride (SiO) x N y At least one of the group consisting of, etc. Each lens 181 may include a filler. The refractive index n1 of each lens 181 can be adjusted by adjusting the amount of filler contained in the lens 181. The filler may be a hollow filler. The filler may be an inorganic filler. The inorganic filler comprises, for example, a material selected from aluminum oxide (Al₂O₃). x Titanium oxide (TiO) x Zirconium oxide (ZrO) x At least one of the groups including (e.g.)

[0195] (Sealing resin layer 19)

[0196] A sealing resin layer 19 covers the lens array 18. The sealing resin layer 19 protects components such as the multiple light-emitting elements 13 from moisture, impact, etc. The sealing resin layer 19 contains a cured form of a sealing resin composition. For example, the sealing resin composition contains at least one component selected from the group consisting of thermosetting resin compositions, photosensitive resin compositions, etc. The photosensitive resin composition includes, for example, an ultraviolet-curable resin composition. The sealing resin layer 19 may include a hard coating. In this case, the characteristics of the display device 1, such as scratch resistance and weather resistance, can be improved.

[0197] [Method for manufacturing display device 1]

[0198] The following will refer to Figure 5 A to Figure 9 B describes an embodiment of a method for manufacturing a display device 1 according to the first embodiment.

[0199] (The process used to form the first layer 11)

[0200] First, source / drain regions 112 and source / drain regions 113 are formed in the semiconductor substrate 11a. Next, as... Figure 5 As shown in Figure A, an electrode layer 11b1, including multiple gate electrodes 111, is formed on the first surface of the semiconductor substrate 11a. Next, as... Figure 5As shown in Figure B, a wiring layer 11b2 including multiple wirings 115, etc., and an electrode layer 11b3 including multiple bonding electrodes 114, etc., are sequentially formed on the first surface of the electrode layer 11b1. As a result, a first layer 11 is obtained.

[0201] (Used to form the second layer 12)

[0202] First, a metal oxide layer and a metal layer are sequentially stacked on the second surface of the semiconductor substrate 12b by, for example, vacuum phase deposition or sputtering. As a result, as... Figure 6 As shown in Figure A, electrode 131a is formed on the second surface of semiconductor substrate 12b. Semiconductor substrate 12b may be, for example, a silicon substrate. The silicon substrate includes, for example, monocrystalline silicon or polycrystalline silicon. Next, electrode 131a is patterned using, for example, photolithography, and electrode 131a is divided for each sub-pixel 2. As a result, as... Figure 6 As shown in Figure B, multiple electrodes 131 are formed on the second surface of the semiconductor substrate 12b. Next, as... Figure 6 As shown in Figure C, an insulating layer 120a4 comprising a plurality of through holes 123 is formed on the second surface of the semiconductor substrate 12b. Each through hole 123 is connected to the second surface of the corresponding electrode 131. Thus, an electrode layer 12a4 comprising a plurality of electrodes 131 and a plurality of through holes 123 is formed on the second surface of the semiconductor substrate 12b.

[0203] Next, as Figure 7 As shown in Figure A, a wiring layer 12a3, including multiple wirings 122, is formed on the second surface of the electrode layer 12a4. Next, as... Figure 7 As shown in Figure B, an insulating layer 120a2 is formed, including multiple gate electrodes 125, etc. Next, as... Figure 7 As shown in Figure C, source / drain electrodes 126 and 127 are formed in the insulating layer 120a2 such that the gate electrode 125 is sandwiched between them. Next, as... Figure 8 As shown in Figure A, a thin-film semiconductor layer 124 is formed on the second surface of the insulating layer 120a2. Therefore, a transistor layer 12a2 is formed on the second surface of the wiring layer 12a3. Next, as... Figure 8 As shown in Figure B, an electrode layer 12a1 including a plurality of bonding electrodes 121 is formed on the second surface of the transistor layer 12a2.

[0204] (The process of joining the first layer 11 and the second layer 12)

[0205] First, such as Figure 9As shown in Figure A, the second layer 12 is flipped over, so that the first surface of the first layer 11 and the second surface of the second layer 12 face each other, and the second layer 12 is placed on the first surface of the first layer 11, such that the first surface of the bonding electrode 121 and the second surface of the bonding electrode 114 are in contact with each other. Next, the first layer 11 and the second layer 12 are heat-treated to bond the first surface of the bonding electrode 121 and the second surface of the bonding electrode 114 to each other. Next, as... Figure 9 As shown in Figure B, the semiconductor substrate 12b is removed from the first surface of the second layer 12. As a result, a circuit board 10 is obtained.

[0206] (The process of forming a layer on the circuit board 10)

[0207] An OLED layer 132, an electrode 133, a protective layer 14, a planarization layer 15, a color filter 16, a planarization layer 17, a lens array 18, and a sealing resin layer 19 are sequentially formed on the first surface of the circuit board 10. As a result, a display device 1 according to the first embodiment is obtained.

[0208] [Functions and Effects]

[0209] The display device 1 according to the first embodiment includes a circuit board 10, which includes a first layer 11 and a second layer 12. The first layer 11 and the second layer 12 are joined together by joining the bonding electrodes 114 of the first layer 11 and the bonding electrodes 121 of the second layer 12. Therefore, the circuit board 10 can be formed by sequentially forming an electrode layer 12a4, a wiring layer 12a3, a transistor layer 12a2, and an electrode layer 12a1 on a semiconductor substrate 12b to form the second layer 12, and then joining the bonding electrodes 114 of the first layer 11 and the bonding electrodes 121 of the second layer 12 together by heat treatment or the like. Therefore, in the process of forming the wiring layer 12a3, the process of forming the electrode layer 12a4, etc., the characteristic degradation of the write transistor Tr2 caused by the influence of oxygen, hydrogen, heat, etc. can be suppressed. That is, the characteristic degradation of the write transistor Tr2 during the manufacturing process of the display device 1 can be suppressed.

[0210] As a circuit board capable of suppressing the degradation of the write transistor Tr2's characteristics caused by oxygen, hydrogen, heat, etc., in addition to the circuit board 10 in the first embodiment described above, it is also conceivable that the write transistor Tr2 is arranged as high as possible on the circuit board. More specifically, for example, a circuit board configuration in which the transistor layer 12a2 is formed on the wiring layer 12a3 is conceivable. By arranging the write transistor Tr2 as high as possible, even if the layers constituting the circuit board are stacked sequentially from the bottom using vacuum film formation technology (e.g., chemical vapor deposition (CVD) or photolithography), the write transistor Tr2 is less likely to be affected by processes (e.g., oxygen, hydrogen, heat, etc.) after the formation of the write transistor Tr2. However, in a circuit board with this configuration, the write transistor Tr2 is arranged near the light-emitting element 13, and there is a possibility that the characteristics of the write transistor Tr2 will degrade due to the light emitted by the light-emitting element 13.

[0211] On the other hand, in the display device 1 according to the first embodiment, the characteristic degradation of the write transistor Tr2 caused by oxygen, hydrogen, heat, etc., can be suppressed while maintaining the arrangement of the wiring layer 12a3 and the electrode layer 12a4 stacked on the transistor layer 12a2. Therefore, the characteristic degradation of the write transistor Tr2 caused by oxygen, hydrogen, heat, etc., during the manufacturing process of the display device 1 can be suppressed, and the characteristic degradation of the write transistor Tr2 caused by the emission of light from the light-emitting element 13 can also be suppressed.

[0212] Furthermore, as mentioned above, in a circuit board where the write transistor Tr2 is arranged as high as possible, the distance between the drive transistor Tr1 and the write transistor Tr2 increases, and there is a possibility that the wiring connection between the drive transistor Tr1 and the write transistor Tr2 becomes difficult.

[0213] On the other hand, in the circuit board 10 of the display device 1 according to the first embodiment, since the transistor layer 12a2 is disposed below the wiring layer 12a3, the increase in the distance between the driving transistor Tr1 and the writing transistor Tr2 can be suppressed. Therefore, the wiring connection between the driving transistor Tr1 and the writing transistor Tr2 becomes easier.

[0214] In the display device 1, the first layer 11 includes a driving transistor Tr1 (which is a MOSFET), and the second layer 12 includes a writing transistor Tr2 (which is a thin-film transistor (TFT)). As a result, the layout size of the driving circuit can be reduced, and the display device 1 can be miniaturized.

[0215] In display device 1, when the thin-film semiconductor layer 124 of the write transistor Tr2 all includes an oxide layer containing IGZO or the like, leakage current of the write transistor Tr2 can be suppressed. Therefore, the increase in power consumption of display device 1A can be suppressed.

[0216] In the manufacturing method of the display device 1 according to the first embodiment, the circuit board 10 can be manufactured by pre-manufacturing the first layer 11 and the second layer 12 separately and bonding the first layer 11 and the second layer 12 together. Therefore, compared with the manufacturing method in which the layers constituting the circuit board are stacked sequentially from the bottom, the restrictions on the manufacturing process can be reduced. Therefore, the design freedom of the circuit board 10 can be increased.

[0217] <4 Second Implementation Method>

[0218] [Overall configuration of display device 1A]

[0219] Reference Figure 10 This section describes an embodiment of the overall configuration of the display device 1A according to a second embodiment of the present disclosure. The driving circuit unit of the display device 1A differs from that of the display device 1 according to the first embodiment in that the driving circuit unit of the display device 1A further includes a second driving scan unit 25. It should be noted that the first driving scan unit 24 in the driving circuit unit of the display device 1A corresponds to the driving scan unit 22 in the driving circuit unit of the display device 1. In the second embodiment, the same reference numerals are used for parts that are the same as in the first embodiment, and their descriptions are appropriately omitted.

[0220] First drive line 24a (24a1 to 24a) m ) and the drive line 22a (22a1 to 22a) of the display device 1 m Corresponding to ). Second drive line 25a (25a1 to 25a) m Routing along the row direction for the corresponding pixel rows. Second drive line 25a (25a1 to 25a) m It is connected to the output terminal of the corresponding row of the second drive scanning unit 25.

[0221] Similar to the write scan unit 21, the second drive scan unit 25 includes a shift register circuit, etc. The second drive scan unit 25 can synchronously scan the drive signals AZ (AZ1 to AZ2) with the line sequence of the write scan unit 21. m ) provides to the second drive line 25a (25a1 to 25a) m This controls the way subpixel 2 emits light during non-light-emitting periods.

[0222] [Configuration of pixel circuit 2b]

[0223] Next, we will refer to Figure 11 An embodiment of the circuit configuration of the pixel circuit 2b of the display device 1A according to the second embodiment is described. Note that descriptions of commonalities with the pixel circuit 2a according to the first embodiment described above are omitted here.

[0224] Similarly, in the second embodiment, such as Figure 11 As shown, pixel circuit 2b includes light-emitting element 13 and driving circuit for driving the light-emitting element. The driving circuit includes driving transistor Tr1, writing transistor Tr2, light-emitting control transistor Tr3, switching transistor Tr4, and capacitor elements C1 and C2.

[0225] In the second embodiment, an example will be described where the driving transistor Tr1 and the light-emitting control transistor Tr3 are P-channel transistors. However, the driving transistor Tr1 and the light-emitting control transistor Tr3 are not limited to this embodiment and may be N-channel transistors. Furthermore, in the second embodiment, an example will be described where the write transistor Tr2 and the switching transistor Tr4 are N-channel transistors. However, the write transistor Tr2 and the switching transistor Tr4 are not limited to this embodiment and may be P-channel transistors.

[0226] The cathode electrode of the light-emitting element 13 is electrically connected, for example, to a node Vss used to generate current. The write transistor Tr2 can write to the gate node (gate electrode) of the driving transistor Tr1 by sampling the signal voltage Vsig supplied from the signal output section 23. The light-emitting control transistor Tr3 is connected to the power supply voltage V. DD The power supply node is between the power supply node and the source node (source electrode) of the driving transistor Tr1, and the light-emitting element 13 is controlled to emit light / not emit light under the drive of the light-emitting control signal DS.

[0227] Switching transistor Tr4 is connected between the drain node (drain electrode) of driving transistor Tr1 and the current discharge target node Vss, and, driven by driving signal AZ, controls the light-emitting element 13 so that it does not emit light during non-light-emitting periods. That is, when switching transistor Tr4 enters the on state, it acts as a bypass to form the path of light-emitting element 13 (i.e., a bypass), preventing current from being supplied to light-emitting element 13. In this way, even if current leakage exists between the source and drain of driving transistor Tr1 when it is switched to the off state, switching transistor Tr4 entering the on state prevents current from being supplied to light-emitting element 13. Therefore, according to the second embodiment, the reduction in contrast during black-to-grayscale display can be suppressed.

[0228] Capacitor C1 is connected between the gate and source nodes of driving transistor Tr1 and holds the signal voltage Vsig, which is the result of sampling by writing transistor Tr2. Driving transistor Tr1 drives light-emitting element 13 by causing a driving current based on the holding voltage of capacitor C1 to flow through light-emitting element 13.

[0229] Capacitor C2 is connected between the source node of the driving transistor Tr1 and a node with a fixed potential (e.g., the power supply voltage V). DD Between the power supply nodes. Capacitor element C2 has the function of suppressing the fluctuation of the source voltage of the driving transistor Tr1 when the signal voltage Vsig is written and making the gate-source voltage Vgs of the driving transistor Tr1 the threshold voltage Vth of the driving transistor Tr1.

[0230] [Layer configuration of display device 1A]

[0231] Next, we will refer to Figure 12 An embodiment of the layer configuration of the display device 1A according to the second embodiment will be described. Since the layer configuration of the display device 1A is similar to that of the display device 1 according to the first embodiment, except for the circuit board 10, only the layer configuration of the circuit board 10 will be described below.

[0232] (Circuit Board 10)

[0233] In addition to multiple driving transistors (current source transistors) Tr1, multiple light-emitting control transistors Tr3 are also disposed on the first surface side of the semiconductor substrate 11a. More specifically, the semiconductor substrate 11a includes multiple source / drain regions 112 and multiple source / drain regions 113 constituting the multiple driving transistors Tr1 and the multiple light-emitting control transistors Tr3.

[0234] Similar to the driving transistor Tr1, each light-emitting control transistor Tr3 includes a gate electrode 111 contained in the electrode / wiring layer 11b and source / drain regions 112 and 113 contained in the semiconductor substrate 11a. As described above, in the second embodiment, the driving transistor Tr1 and the light-emitting control transistor Tr3 are P-channel transistors. The light-emitting control transistor Tr3 is a field-effect transistor, more specifically, a MOSFET. The driving transistor Tr1 is a first embodiment of the first transistor, and the light-emitting control transistor Tr3 is a second embodiment of the first transistor.

[0235] In addition to multiple write transistors Tr2 and multiple vias (not shown), transistor layer 12a2 also includes multiple switching transistors Tr4. The multiple switching transistors Tr4 are disposed in insulating layer 120a2. The switching transistors Tr4 may be disposed above the light-emitting control transistor Tr3. As described above, in the second embodiment, the write transistors Tr2 and switching transistors Tr4 are N-channel transistors. The switching transistors Tr4 are field-effect transistors, more specifically, thin-film transistors (TFTs). The thin-film transistors are preferably oxide semiconductor thin-film transistors (oxide semiconductor TFTs). The write transistors Tr2 are a first embodiment of the second transistor, and the switching transistors Tr4 are a second embodiment of the second transistor.

[0236] A driving transistor Tr1, a writing transistor Tr2, a light-emitting control transistor Tr3, and a switching transistor Tr4 are provided for a sub-pixel 2. In addition, two bonding portions 101 (two bonding electrodes 121 and two bonding electrodes 114) are provided in a sub-pixel 2.

[0237] [Functions and Effects]

[0238] In the display device 1A according to the second embodiment, similar to the display device 1 according to the first embodiment, the circuit board 10 is obtained by bonding the bonding electrode 114 of the first layer 11 and the bonding electrode 121 of the second layer 12 to each other. Therefore, it is possible to suppress the degradation of the characteristics of the write transistor Tr2 and the switching transistor Tr4 during the manufacturing process of the display device 1A.

[0239] In the display device 1A, the first layer 11 includes a driving transistor Tr1, which functions as a MOSFET, and a light-emitting control transistor Tr3, and the second layer 12 includes a write transistor Tr2, which functions as a thin-film transistor (TFT), and a switching transistor Tr4. As a result, the layout size of the driving circuit can be reduced, and the size of the display device 1A can be reduced.

[0240] In the display device 1A, when the thin-film semiconductor layer 124 of the write transistor Tr2 and the switch transistor Tr4 includes an oxide layer containing IGZO or the like, leakage current of the write transistor Tr2 and the switch transistor Tr4 can be suppressed. Therefore, the increase in power consumption of the display device 1A can be suppressed. Furthermore, because the leakage current is suppressed, intermittent driving of the switch transistor Tr4 becomes easier, and the increase in power consumption of the display device 1A is suppressed.

[0241] In the display device 1A, since the thin-film semiconductor layer 124a of the switching transistor Tr4 all includes an oxide layer containing IGZO or the like, the switching transistor Tr4 can easily be formed as an N-channel transistor. Therefore, by using the switching transistor Tr4 (which is an N-channel transistor), the voltage between the cathode and anode of the light-emitting element 13 can be stably adjusted to 0V, and current supply to the light-emitting element 13 can be prevented. As a result, the reduction in contrast during black-to-grayscale display can be suppressed.

[0242] <5 Variations>

[0243] [Variation Example 1]

[0244] The number of transistors for a sub-pixel 2 and the number of junctions 101 (junction electrodes 114 and 121) are not limited to the embodiments of the first and second embodiments. For example, the number of transistors for a sub-pixel 2 and the number of junctions 101 may be set to (A), (B) or (C) below.

[0245] (A) such as Figure 13 As shown, a sub-pixel 2 can be provided with a driving transistor Tr1, a writing transistor Tr2, and two junctions 101.

[0246] (B) such as Figure 14 As shown, a sub-pixel 2 can be provided with a driving transistor Tr1, a writing transistor Tr2, a light-emitting control transistor Tr3, and two junctions 101.

[0247] (C) such as Figure 15 As shown, a sub-pixel 2 can be provided with a driving transistor Tr1, a writing transistor Tr2, a switching transistor Tr4, and two junctions 101.

[0248] [Variation Example 2]

[0249] In the first embodiment, such as Figure 4 As shown, an embodiment has been described in which the first layer 11 (more specifically, the electrode / wiring layer 11b) sequentially comprises an electrode layer 11b1, a wiring layer 11b2, and an electrode layer 11b3 on the first surface of the circuit board 10. However, the configuration of the first layer 11 is not limited to this embodiment, and for example, as... Figure 16 As shown, the first layer 11, more specifically, the electrode / wiring layer 11b may sequentially include electrode layers 11b1 and 11b3 on the first surface of the circuit board 10, but does not include wiring layer 11b2. In this case, the number of layers between the driving transistor Tr1 and the writing transistor Tr2 can be reduced, and the distance between the driving transistor Tr1 and the writing transistor Tr2 can be further reduced. Therefore, the wiring connection between the driving transistor Tr1 and the writing transistor Tr2 is further facilitated. It should be noted that the above configuration can be adopted in the display device 1A according to the second embodiment.

[0250] [Variation Example 3]

[0251] In the display device 1 according to the first embodiment, such as Figure 17As shown, the first layer 11 may include a plurality of capacitor elements C1. More specifically, the electrode / wiring layer 11b may further include a capacitor element layer 11b4. The capacitor element layer 11b4 is disposed between the wiring layer 11b2 and the electrode layer 11b3. The capacitor element layer 11b4 includes an insulating layer 110b4, which includes a plurality of capacitor elements C1. A capacitor element C1 is provided for one sub-pixel 2.

[0252] As described above, since the first layer 11 includes multiple capacitor elements C1, it is possible to form the first layer 11 including multiple capacitor elements C1 and the second layer 12 including multiple write transistors Tr2 separately, so that the process for forming the write transistors Tr2 can prevent the capacitor elements C1 from being affected.

[0253] Although not shown, in the display device according to the second embodiment, the first layer 11 may include a plurality of capacitor elements C1 and a plurality of capacitor elements C2. More specifically, the electrode / wiring layer 11b may further include a capacitor element layer 11b4 comprising a plurality of capacitor elements C1 and a plurality of capacitor elements C2. In this case, a capacitor element C1 and a capacitor element C2 may be provided for a sub-pixel 2.

[0254] As described above, since the first layer 11 includes multiple capacitor elements C1 and multiple capacitor elements C2, the first layer 11 including multiple capacitor elements C1 and multiple capacitor elements C2 and the second layer 12 including multiple write transistors Tr2 and multiple switch transistors Tr4 can be formed separately, and thus the process for forming the write transistors Tr2 and switch transistors Tr4 can be prevented from affecting the capacitor elements C1 and C2.

[0255] [Variation Example 4]

[0256] In the first embodiment, an example has been described in which the circuit board 10 includes a pixel circuit 2a of one type, comprising a driving transistor Tr1 as a MOSFET and a TFT as a write transistor Tr2. However, the configuration of the circuit board 10 is not limited to this embodiment, and for example, the circuit board 10 may include two or three or more types of pixel circuits 2a. The circuit board 10 according to Variation 4 is particularly preferably applied to devices in which foveated rendering is used (e.g., eyeglasses devices such as head-mounted displays).

[0257] The following will refer to Figure 18 and Figure 19 The description includes embodiments in which the circuit board 10 includes a first pixel circuit 2a and a second pixel circuit 2a with different configurations. For example... Figure 18As shown, the pixel array unit 20, which serves as a display area unit, includes a central region (first region) RE1 and a peripheral region (second region) RE2. The central region RE1 is disposed in the central portion of the pixel array unit 20. The peripheral region RE2 is disposed outside the central region RE1 along the periphery of the pixel array unit 20. The central region RE1 includes a first pixel circuit 2a, and the peripheral region RE2 includes a second pixel circuit 2a.

[0258] like Figure 19 As shown, the driving transistor Tr1 included in the second pixel circuit 2a is a MOSFET and is disposed on the first surface side of the semiconductor substrate 11a. Furthermore, the write transistor Tr2 included in the second pixel circuit 2a is a TFT and is disposed in the insulating layer 120a2. On the other hand, the driving transistor Tr1 (not shown) included in the first pixel circuit 2a is a MOSFET and is disposed on the first surface side of the semiconductor substrate 11a. Furthermore, the write transistor Tr2 included in the first pixel circuit 2a is also a MOSFET and is disposed on the first surface side of the semiconductor substrate 11a.

[0259] The write transistor (MOSFET) Tr2 included in the first pixel circuit 2a and the write transistor (TFT) Tr2 included in the second pixel circuit 2a are disposed in layers close to each other in the thickness direction of the circuit board 10. Therefore, the signal lines 23a, control lines, etc. of the write transistor (MOSFET) Tr2 included in the first pixel circuit 2a and the write transistor (TFT) Tr2 included in the second pixel circuit 2a can be shared.

[0260] Both the driving transistor Tr1 and the writing transistor Tr2 in the first pixel circuit 2a in the central region RE1 are MOSFETs. Therefore, the sub-pixel 2 in the central region RE1 can be driven at high speed. On the other hand, the driving transistor Tr1 and the writing transistor Tr2 in the second pixel circuit 2a in the peripheral region RE2 are MOSFETs and FETs, respectively. Therefore, the sub-pixel 2 in the peripheral region RE2 can be driven with low power consumption.

[0261] [Variation Example 5]

[0262] In the second embodiment, an embodiment has been described in which the circuit board 10 includes a pixel circuit 2b of one type, comprising a driving transistor Tr1 as a MOSFET and a light-emitting control transistor Tr3, and a TFT as a write transistor Tr2 and a switching transistor Tr4. However, the configuration of the circuit board 10 is not limited to this embodiment, and for example, the circuit board 10 may include two or three or more types of pixel circuits 2b. An embodiment in which the central region RE1 includes a first pixel circuit 2b and the peripheral region RE2 includes a second pixel circuit 2b will be described below.

[0263] Although not shown, the driving transistor Tr1 and the light-emitting control transistor Tr3 included in the second pixel circuit 2b are MOSFETs and are disposed on the first surface side of the semiconductor substrate 11a. Furthermore, the write transistor Tr2 and the switching transistor Tr4 included in the second pixel circuit 2b are TFTs and are disposed in the insulating layer 120a2. On the other hand, the driving transistor Tr1 and the light-emitting control transistor Tr3 included in the first pixel circuit 2b are MOSFETs and are disposed on the first surface side of the semiconductor substrate 11a. Furthermore, the write transistor Tr2 and the switching transistor Tr4 included in the first pixel circuit 2b are also MOSFETs and are disposed on the first surface side of the semiconductor substrate 11a.

[0264] The write transistor (MOSFET) Tr2 included in the first pixel circuit 2b and the write transistor (TFT) Tr2 included in the second pixel circuit 2b are disposed in layers close to each other in the thickness direction of the circuit board 10. Therefore, the signal lines 23a, control lines, etc. of the write transistor (MOSFET) Tr2 included in the first pixel circuit 2b and the write transistor (TFT) Tr2 included in the second pixel circuit 2b can be shared.

[0265] The switching transistor (MOSFET) Tr4 included in the first pixel circuit 2b and the write switching transistor (TFT) Tr4 included in the second pixel circuit 2b are disposed in layers close to each other in the thickness direction of the circuit board 10. Therefore, the signal lines 23a, control lines, etc., of the write switching transistor (MOSFET) Tr4 included in the first pixel circuit 2b and the write switching transistor (TFT) Tr4 included in the second pixel circuit 2b can be shared.

[0266] [Variation Example 6]

[0267] like Figure 20As shown, the circuit board 10 of the display device 1 according to the first embodiment may further include an insulating film 102 between the first layer 11 and the second layer 12. The insulating film 102 is an example of a first insulating film. The insulating film 102 is broken at the bonding electrodes 114 and 121, and the bonding electrodes 114 and 121 are directly bonded to each other. The insulating film 102 preferably has barrier properties. Here, barrier properties refer to properties that can suppress the diffusion of hydrogen, oxygen, etc. When the insulating film 102 has barrier properties, it is possible to suppress the diffusion of hydrogen, oxygen, etc. from the first layer 11 to the second layer 12, and it is possible to suppress the degradation of the properties of the write transistor (TFT) Tr2.

[0268] From the viewpoint of improving barrier properties, the insulating film 102 preferably comprises a deposited layer obtained by depositing atomic layers. The deposited layer may be an atomic layer deposition (ALD) layer. The insulating film 102 may have a single-layer structure or a multi-layer structure. An insulating film with a multi-layer structure may have a stacked structure in which layers comprising the same material are stacked, or it may have a stacked structure in which layers comprising different materials are stacked. For example, the insulating film 102 comprises at least one of an oxide film and a nitride film. For example, the oxide film comprises silicon oxide (SiO₂). x ) and hafnium oxide (HfO) x At least one of the following. The nitride film contains, for example, silicon nitride (SiN). x ).

[0269] An embodiment of a method (bonding method) for forming a circuit board 10 having the above configuration will be described. Here, the case where the bonding electrodes 114 and 121 contain copper (Cu) will be used as an example, but the materials of the bonding electrodes 114 and 121 are not limited to this.

[0270] First, the insulating film 102 is formed on at least one of the first surface of the first layer 11 and the second surface of the second layer 12, for example, by ALD. Next, after the first layer 11 and the second layer 12 are laminated with the insulating film 102 between the first layer 11 and the second layer 12, the first layer 11 and the second layer 12 are heat-treated at a temperature higher than the film-forming temperature of copper (Cu). As a result, the constituent materials of the bonding electrode 114 and the bonding electrode 121 undergo grain growth, the copper (Cu) grains move, and the insulating film 102 is broken. The greater the temperature difference between the heat treatment temperature and the film-forming temperature of copper (Cu), the more effectively the insulating film 102 can be broken. This is because as the temperature difference increases, the copper (Cu) grains grow larger. Furthermore, since the portion of the insulating film 102 between the bonding electrode 114 and the bonding electrode 121 (the portion containing copper (Cu)) is broken, the insulating properties of the portions other than the bonding electrodes 114 and 121 can be maintained.

[0271] The function and effect of the circuit board 10 according to Modification 6 will be described below, and the circuit board 10 in which the first layer 11 and the second layer 12 are directly bonded to each other will be compared with the circuit board 10 according to Modification 6 in which the first layer 11 and the second layer 12 are indirectly bonded to each other with an insulating film 102 between them.

[0272] In a circuit board 10 in which the first surface of the first layer 11 and the second surface of the second layer 12 are directly bonded to each other, gaps may occur at the bonding interface. When gaps occur, there is a possibility that the bonding strength between the first layer 11 and the second layer 12 may be reduced.

[0273] On the other hand, in the circuit board 10 according to Modified Example 6, the first layer 11 and the second layer 12 are bonded to each other with an insulating film 102 between them. Therefore, direct contact between the first surface of the first layer 11 and the second surface of the second layer 12 at locations other than the joint 101 can be suppressed. Therefore, voids at the joint interface between the first layer 11 and the second layer 12 can be suppressed. Therefore, the bonding strength between the first layer 11 and the second layer 12 can be increased, and a display device 1 with improved reliability can be obtained.

[0274] Specifically, when the insulating layer 110b of the first layer 11 and the insulating layer 120a of the second layer 12 include a TEOS layer, many OH groups exist on the surface of the TEOS layer, and therefore voids are likely to be generated at the bonding interface where the insulating layers 110b and 120a including the TEOS layer are directly bonded to each other due to dehydration condensation.

[0275] On the other hand, in the circuit board 10 according to Modified Example 6, since the first layer 11 and the second layer 12 are bonded to each other through the insulating film 102 between them, direct bonding between the TEOS layers is suppressed. As a result, the generation of voids caused by dehydration condensation can be suppressed. Therefore, even when the insulating layers 110b and 120a are TEOS layers, the bonding strength between the first layer 11 and the second layer 12 can be improved, and a display device 1 with improved reliability can be obtained.

[0276] Note that the TEOS layer is a silicon oxide layer formed by CVD using tetraethoxysilane gas (TEOS gas, whose composition is Si(OC2H5)4) as the raw material gas.

[0277] In the display device 1A according to the second embodiment, the configuration and manufacturing method of the above-described modified example 6 can be adopted.

[0278] [Variation Example 7]

[0279] In a first embodiment, the circuit board 10 may include dummy wiring at the junction between the first layer 11 and the second layer 12. Here, the junction between the first layer 11 and the second layer 12 refers to a portion of the circuit board 10 having a predetermined width in the thickness direction based on the junction surface between the first layer 11 and the second layer 12. The dummy wiring 128 is wiring that does not contribute to the operation of the display device 1, that is, wiring other than the wiring constituting the circuit of the display device 1. The dummy wiring may be single-layer wiring or multi-layer wiring. The dummy wiring may be arranged periodically according to the period of the sub-pixels 2.

[0280] Figure 21 This is a cross-sectional view of a circuit board 10 including a single-layer dummy wiring 128. The dummy wiring 128 is positioned adjacent to the interface between the first layer 11 and the second layer 12. The dummy wiring 128 is disposed on the second surface side of the second layer 12 (the interface side that interfaces with the first layer 11), more specifically, on the second surface side of the electrode layer 12a1. However, the arrangement of the dummy wiring 128 is not limited to this, and the dummy wiring 128 may be disposed on the first surface side of the first layer 11 (the interface side that interfaces with the second layer 12), more specifically, on the first surface side of the electrode layer 11b3. The dummy wiring 128 is embedded in the second layer 12 with its second surface exposed on the second surface of the insulating layer 120. The second surface of the dummy wiring 128 is flush with the second surface of the second layer 12 except for the portion where the dummy wiring 128 is disposed. The dummy wiring 128 is positioned to avoid the portion of the interface 101.

[0281] Figure 22 This is a cross-sectional view of a circuit board 10 including multiple layers of dummy wirings 116 and 128. The dummy wirings 116 and 128 are disposed adjacent to the bonding surfaces of the first layer 11 and the second layer 12. Dummy wiring 116 is disposed on the first surface side of the first layer 11 (the bonding surface side that bonds to the second layer 12). On the other hand, dummy wiring 128 is disposed on the second surface side of the second layer 12 (the bonding surface side that bonds to the first layer 11). In the plan view, dummy wiring 116 is disposed in the gap between adjacent dummy wirings 128 and within the opening of dummy wiring 128. In the plan view, dummy wirings 116 and 128 may partially overlap each other. The overlapping portions are preferably bonded in a manner similar to that used for bonding electrodes 114 and 121. In this case, the bonding strength between the first layer 11 and the second layer 12 can be further improved. Dummy wirings 116 and 128 can be bonded to each other in the same process as bonding electrodes 114 and 121. Dummy wiring 116 is an example of the first dummy wiring, and dummy wiring 128 is an example of the second dummy wiring.

[0282] Dummy wirings 116 and 128 can have a strip shape extending in the Y-axis direction (vertical direction), such as... Figure 23As shown in Figure A. In the plan view, dummy wiring 116 is placed in the gap between adjacent dummy wiring 128 in the X-axis direction (horizontal direction), filling the gap between adjacent dummy wiring 128. Note that the direction in which dummy wiring 116 and 128 extend is not limited to the Y-axis direction (vertical direction), and can also be the X-axis direction (horizontal direction), or can be as shown in Figure A. Figure 23 The direction of inclination relative to the Y-axis is shown in B.

[0283] The long sides of the striped dummy wiring 116 and the long sides of the striped dummy wiring 128 can overlap each other. The overlapping sides are preferably joined together. Here, the long sides of the striped dummy wirings 116 and 128 refer to the regions with a predetermined width extending inward from the long sides of the striped dummy wirings 116 and 117.

[0284] Furthermore, the dummy wirings 116 and 128 are not limited to stripes, but can, for example, have geometric patterns. Specifically, for example, such as... Figure 23 As shown in C, the dummy wiring 116 may have a plurality of holes 116a arranged in a two-dimensional pattern such as a matrix shape, and the dummy wiring 128 may have a dot shape filling the holes 116a. However, the dummy wiring 128 may have holes arranged in a two-dimensional pattern such as a matrix shape, and the dummy wiring 116 may have a dot shape filling the holes.

[0285] The holes 116a and 128 of the dummy wiring 116 can, for example, have approximately circular, approximately polygonal, or oval shapes in a plan view. An approximately circular shape is geometrically limited to a circle and includes shapes that are visually perceived as close to a circle. An approximately polygonal shape is not limited to a polygon in a strictly geometric sense and includes shapes that are visually perceived as close to a polygon. For example, approximately polygonal shapes include polygonal shapes with rounded corners and polygonal shapes with truncated corners. An approximately polygonal shape can be an approximately rectangular shape. Here, an approximately rectangular shape includes an approximately square shape. An oval shape includes shapes such as elongated circles, ellipses, and egg shapes.

[0286] The outer periphery of the hole 116a of the dummy wiring 116 and the outer periphery of the dotted dummy wiring 128 may overlap each other. The overlapping outer periphery portions preferably join together. Here, the outer periphery of the hole 116a of the dummy wiring 116 refers to a region with a predetermined width extending outward from the periphery of the hole 116a. The outer periphery of the dotted dummy wiring 128 refers to a region with a predetermined width extending inward from the periphery of the dotted dummy wiring 128.

[0287] Dummy wirings 116 and 128 have light-shielding properties. Dummy wiring 116 may be made of the same material as the bonding electrode 114. In this case, dummy wiring 116 and bonding electrode 114 can be formed through the same process. Dummy wiring 128 may be made of the same material as the bonding electrode 121. In this case, dummy wiring 128 and bonding electrode 121 can be formed through the same process.

[0288] Dummy wirings 116 and 128 may include, for example, copper (Cu). A barrier metal may be disposed on the surface of dummy wirings 116 and 128. The barrier metal may include, for example, tantalum (Ta) or tantalum nitride (TaNx).

[0289] As described above, since the circuit board 10 includes a single-layer dummy wiring 128 or multiple-layer dummy wirings 116 and 128 at the junction between the first layer 11 and the second layer 12, the light emitted by the driving transistor (MOSFET) Tr1 due to hot carriers can be blocked by the single-layer dummy wiring 128 or multiple-layer dummy wirings 116 and 128. Therefore, the effect of the light emitted by the driving transistor Tr1 on the writing transistor (TFT) Tr2 can be suppressed.

[0290] In the above embodiments, an embodiment in which the dummy wiring 128 is disposed at the junction between the first layer 11 and the second layer 12 has been described. However, the arrangement position of the dummy wiring 128 can be any position between the driving transistor Tr1 and the writing transistor Tr2, and is not limited to the junction between the first layer 11 and the second layer 12.

[0291] In the display device 1A according to the second embodiment, the configuration of the above-described variation 7 can be adopted. In this case, the influence of the light emission of the driving transistor (MOSFET) Tr1 and the light-emitting control transistor (MOSFET) Tr3 on the writing transistor (TFT) Tr2 and the switching transistor (TFT) Tr4 can be suppressed.

[0292] [Variation Example 8]

[0293] In the first and second embodiments, the source / drain electrodes 126 included in the circuit board 10 may each include, as in the following embodiments: Figure 24 The contact material 126a and the barrier metal 126b are shown. Similarly, the source electrode / drain electrode 127 included in the circuit board 10 may also each include a contact material 127a and a barrier metal 127b.

[0294] Contact materials 126a and 127a are directly bonded to the first surface of the thin-film semiconductor layer 124. As a result, the connection resistance between contact material 126a and the thin-film semiconductor layer 124, as well as the connection resistance between contact material 127a and the thin-film semiconductor layer 124, can be reduced.

[0295] The barrier metal 126b covers the surface of the contact material 126a except for the portion bonded to the thin-film semiconductor layer 124. The barrier metal 127b covers the surface of the contact material 127a except for the portion bonded to the thin-film semiconductor layer 124.

[0296] [Variation Example 9]

[0297] In the first embodiment, such as Figure 25 As shown, the circuit board 10 may include an insulating film 129a between the write transistor Tr2 and the electrode 131. Figure 25 An embodiment is shown in which the insulating film 129a is disposed between the write transistor Tr2 and the wiring layer 12a3; however, it is sufficient for the insulating film 129a to be disposed between the write transistor Tr2 and the electrode 131, and the arrangement position of the insulating film 129a is not limited thereto. The insulating film 129a is an example of a second insulating film.

[0298] The insulating film 129a has barrier properties. This allows for the suppression of the diffusion of hydrogen, oxygen, etc., from the first surface side of the circuit board 10 (the surface side where the light-emitting element 13 is disposed) to the write transistor (TFT) Tr2. The insulating film 129a contains, for example, a metal oxide or a metal nitride. The metal oxide includes, for example, aluminum oxide (Al₂O₃). x ) or titanium dioxide (TiO) x Metal nitrides include, for example, titanium nitride (TiNx). From the viewpoint of improving barrier properties, the insulating film 129a preferably comprises a deposited layer obtained by depositing atomic layers. The deposited layer may be an atomic layer deposition (ALD) layer.

[0299] Because the circuit board 10 includes an insulating film 129a between the write transistor Tr2 and the electrode 131, the diffusion of hydrogen, oxygen, etc., from the first surface side of the circuit board 10 (the surface side where the light-emitting element 13 is disposed) to the write transistor (TFT) Tr2 can be suppressed. Therefore, the characteristics of the write transistor Tr2 can be stabilized. That is, the degradation of the characteristics of the write transistor Tr2 can be suppressed.

[0300] In the display device 1A according to the second embodiment, the configuration of the modified example 9 described above can be adopted. In this case, the insulating film 129a is disposed between the write transistor Tr2 and the switch transistor Tr4 and the electrode 131. This makes it possible to suppress the diffusion of hydrogen, oxygen, etc. from the first surface side of the circuit board 10 (the surface side on which the light-emitting element 13 is disposed) to the write transistor (TFT) Tr2 and the switch transistor (TFT) Tr4.

[0301] [Variation Example 10]

[0302] In the first embodiment, such as Figure 26 As shown, the circuit board 10 may include a light-shielding layer 129b between the write transistor Tr2 and the electrode 131. Figure 26 An embodiment is shown in which the light-shielding layer 129b is disposed between the write transistor Tr2 and the wiring layer 12a3, but it is sufficient for the light-shielding layer 129b to be disposed between the write transistor Tr2 and the electrode 131, and the arrangement position of the light-shielding layer 129b is not limited thereto.

[0303] like Figure 26 As shown, when the write transistor Tr2 has a bottom-gate structure, the gate electrode 125 is located below the thin-film semiconductor layer 124, making it easier for light from the first surface side of the circuit board 10 to be incident on the thin-film semiconductor layer 124, and the write transistor Tr2 is easily affected by light from the first surface side of the circuit board 10. Therefore, when the write transistor Tr2 has a bottom-gate structure, it is particularly preferred that the circuit board 10 includes a light-shielding layer 129b between the write transistor Tr2 and the electrode 131 as described above. However, the structure of the write transistor Tr2 is not limited to a bottom-gate structure, but can be, for example, a top-gate structure or a dual-gate structure.

[0304] The light-shielding layer 129b is capable of blocking light incident on the write transistor Tr2 from the first surface side of the circuit board 10. Specifically, for example, the light-shielding layer 129b is capable of blocking light emitted from the light-emitting element 13, external light, etc. The light-shielding layer 129b may contain a metal, for example. As a metal, for example, a known metal used for wiring on a circuit board can be used. Specific examples of metals include at least one of aluminum (Al) and copper (Cu). The blocking metal may be disposed on the surface of the light-shielding layer 129b.

[0305] As described above, because the circuit board 10 includes a light-shielding layer 129b located between the write transistor Tr2 and the electrode 131, light incident on the thin-film semiconductor layer 124 from the first surface side of the circuit board 10 (the surface side where the light-emitting element 13 is disposed) can be blocked. Therefore, the influence of light from the first surface side of the circuit board 10 on the write transistor Tr2 can be suppressed.

[0306] With the write transistor Tr2 having a bottom-gate structure, the source / drain electrodes 126 and 127 can be easily connected to the junction electrode 121. Therefore, the clarity of the display device 1 can be easily improved.

[0307] In the display device 1A according to the second embodiment, the configuration of the modified example 10 described above can be adopted. In this case, the light-shielding layer 129b is disposed between the write transistor Tr2 and the switch transistor Tr4 and the electrode 131. Therefore, it is possible to suppress the influence of light from the first surface side of the circuit board 10 on the write transistor (TFT) Tr2 and the switch transistor (TFT) Tr4.

[0308] [Variation Example 11]

[0309] The process for forming the second layer 12 is not limited to the process described in the first embodiment, and for example, the second layer 12 may be formed as follows.

[0310] First, such as Figure 27 As shown in Figure A, an insulating layer 120a is formed on the second surface of the semiconductor substrate 12b by, for example, a CVD method. 41 Next, as Figure 27 As shown in B, the insulating layer 120a is processed using, for example, photolithography. 41 To form an opening 120ah at the position corresponding to each sub-pixel 2. Next, as Figure 27 As shown in C, the insulating layer 120a is deposited by, for example, vacuum phase deposition or sputtering. 41 An electrode 131a is formed on the first surface. At this time, each opening 120ah is filled with the material of the electrode 131a.

[0311] Next, as Figure 27 As shown in D, the surface (first surface) of electrode 131a is polished by, for example, chemical mechanical polishing (CMP) to remove insulating layer 120a. 41 The material of the electrode 131a present on the first surface. As a result, the electrode 131 is formed in each opening 120ah. Next, as Figure 27 As shown in E, in the insulating layer 120a 41 An insulating layer 120a including a plurality of through holes 123 is formed on the first surface and the first surface of electrode 131. 42 Since the subsequent steps are similar to the steps used to form the second layer 12 in the first embodiment, their description is omitted.

[0312] [Variation Example 12]

[0313] In the first and second embodiments, embodiments have been described where the first surface of electrode 131 (the contact surface with OLED layer 132) is flat; however, the shape of electrode 131 is not limited to this. For example, as... Figure 28 As shown, a step may be provided on the peripheral portion of the first surface of each electrode 131. The step is a descending step, wherein the peripheral portion of the first surface of each electrode 131 is lower than the central portion of the first surface of the electrode 131.

[0314] Electrode 131 is embedded in insulating layer 120a with the central portion of its first surface exposed on the first surface of insulating layer 120a. The central portion of the first surface of electrode 131 is flush with the portion of the first surface of insulating layer 120a except for the portion where electrode 131 is disposed.

[0315] The following will refer to Figure 27 A, Figure 27 B. Figure 27 C Figure 29 A and Figure 29 B describes the process for forming a second layer 12 including an electrode 131 having the shape described above.

[0316] First, the process of forming the insulating layer 120a is performed in a manner similar to that used to form the second layer 12 of modified example 11. 41 The steps from the step of forming electrode 131a (see) Figure 27 A, Figure 27 B and Figure 27 C). Next, as... Figure 29 As shown in Figure A, the material of electrode 131a, excluding the portion within opening 120ah and the peripheral portion of opening 120ah, is removed using, for example, photolithography. As a result, electrodes 131 with steps in their respective peripheral portions on their first surface are obtained. Next, as... Figure 29 As shown in B, in insulating layer 120a 41 An insulating layer 120a including a plurality of through holes 123 is formed on the first surface and the first surface of electrode 131. 42 Since the subsequent steps are similar to the steps used to form the second layer 12 in the first embodiment, their description is omitted.

[0317] [Variation Example 13]

[0318] In the first embodiment, an example has been described in which a plurality of write transistors Tr2 are disposed between the electrode layer 12a1 and the wiring layer 12a3; however, the configuration of the circuit board 10 is not limited to this embodiment. For example, a plurality of write transistors Tr2 may be disposed within the wiring layer 12a3. In the case where the wiring layer 12a3 is a multilayer wiring layer, a plurality of write transistors Tr2 may be disposed between stacked wiring layers.

[0319] In the circuit board 10 of the second embodiment, at least one of the plurality of write transistors Tr2 and the plurality of switch transistors Tr4 may be disposed in the wiring layer 12a3. If the wiring layer 12a3 is a multilayer wiring layer, at least one of the plurality of write transistors Tr2 and the plurality of switch transistors Tr4 may be disposed between the stacked wiring layers.

[0320] [Variation Example 14]

[0321] From the viewpoint of improving light extraction efficiency and / or improving color purity, each light-emitting element 13 may have a resonator structure.

[0322] When each electrode 131 is a reflective electrode that functions as a reflective layer, the resonator structure can be configured with electrode 131 and corresponding electrode 133. In this case, the optical distance between electrode 131 and electrode 133 can be set by the thickness of OLED layer 132, by selecting the material of electrode 131, or by a combination of these.

[0323] When each electrode 131 is a transparent electrode, a reflective layer can be disposed below the transparent electrode, and the reflective layer and the corresponding electrode 133 can form a resonator structure. In this case, the optical distance between the reflective layer and the electrode 133 can be set according to the thickness of the OLED layer 132, by selecting the material of the reflective layer, by the thickness of the insulating layer disposed between the electrode 131 (transparent electrode) and the reflective layer, or by a combination of two or more of these.

[0324] [Variation Example 15]

[0325] While embodiments have been described in the first and second embodiments where display devices 1 and 1A include a plurality of light-emitting elements 13 capable of emitting white light and a color filter 16, and color images can be displayed through a combination of these, the methods for enabling display devices 1 and 1A to perform color display are not limited thereto. For example, instead of a plurality of light-emitting elements 13 capable of emitting white light, display devices 1 and 1A may include a plurality of light-emitting elements capable of emitting red light, a plurality of light-emitting elements capable of emitting green light, and a plurality of light-emitting elements capable of emitting blue light. In this case, the color filter is not a necessary component and may or may not be provided.

[0326] A light-emitting element capable of emitting light of a predetermined color (red, green, or blue) is, for example, (1) a light-emitting element comprising a light-emitting layer capable of emitting light of a predetermined color (red); (2) a light-emitting element comprising a light-emitting layer capable of emitting white light and capable of resonating and enhancing light of a predetermined wavelength (red, green, or blue) by a resonator structure, wherein the light of the predetermined wavelength is contained in the white light emitted by the light-emitting layer; or (3) a light-emitting element comprising a light-emitting layer capable of emitting light of a predetermined color (red, green, or blue) and capable of resonating and enhancing light of a predetermined wavelength contained in the light of the predetermined color emitted by the light-emitting layer by a resonator structure.

[0327] [Variation Example 16]

[0328] In the first and second embodiments, embodiments of providing a color filter 16 have been described; however, a quantum dot layer may be provided instead of the color filter 16, or the quantum dot layer may be provided together with the color filter 16. A quantum dot layer is a color conversion layer comprising quantum dots (semiconductor particles) and capable of converting the color of light emitted from multiple light-emitting elements. In this case, the multiple light-emitting elements 13 may be able to emit blue light.

[0329] [Variation Example 17]

[0330] In the first and second embodiments, embodiments in which the light-emitting element 13 is an OLED element have been described. However, the light-emitting element 13 is not limited to this embodiment and can be a self-emissive light-emitting element such as a light-emitting diode (LED) element, an inorganic electroluminescent (IEL) element, a quantum dot light-emitting diode (QLED) element, or a semiconductor laser element. Two or more types of light-emitting elements can be provided in display devices 1 and 1A.

[0331] [Variation Example 18]

[0332] In the first and second embodiments, embodiments in which electrode 131 is an anode electrode and electrode 133 is a cathode electrode have been described. However, electrode 131 and electrode 133 are not limited to these embodiments, and electrode 131 may be a cathode electrode and electrode 133 may be an anode electrode.

[0333] [Other variations]

[0334] Although the first and second embodiments and their variations (hereinafter referred to as "first embodiments, etc.") of this disclosure have been specifically described above, this disclosure is not limited to the first embodiments, etc., and various variations can be made based on the technical concept of this disclosure.

[0335] For example, the configurations, methods, steps, shapes, materials, values, etc. mentioned in the first embodiment are merely examples, and different configurations, methods, steps, shapes, materials, values, etc. may be used as needed.

[0336] Without departing from the spirit of this disclosure, the configuration, method, steps, shape, materials, values, etc. of the first embodiment, etc., can be combined with each other.

[0337] The materials described in the first embodiment and the like can be used alone or in combination of two or more, unless otherwise stated.

[0338] Without departing from the spirit of this disclosure, two or more configurations of the first embodiment, the second embodiment, and variations 1 to 17 may be combined together.

[0339] In addition, the following configurations may also be used in this disclosure.

[0340] (1) A display device, comprising: The circuit board has multiple light-emitting elements, among which... The circuit board includes: The first layer includes multiple first transistors; and The second layer includes multiple second transistors, electrodes for multiple light-emitting elements, and multiple wirings. The second layer is bonded to the first layer. Multiple second transistors are disposed separately from the junction surface between the first and second layers, and The electrode is disposed on the surface of the second layer opposite to the bonding surface.

[0341] (2) According to the display device of (1), wherein, Multiple second transistors are disposed on a layer at least one layer higher than the junction surface.

[0342] (3) The display device according to (1) or (2), wherein, The first transistor is a metal-oxide-semiconductor field-effect transistor (MOSFET), and The second transistor is a thin-film transistor.

[0343] (4) The display device according to (3), wherein, Thin-film transistors are oxide semiconductor thin-film transistors.

[0344] (5) The display device according to (3) or (4), wherein, When viewed from the opposite surface of the second layer, the gate electrode of the second transistor is disposed on the front side of the thin-film semiconductor layer of the second transistor.

[0345] (6) The display device according to (5), wherein, In each thin-film semiconductor layer, the surface on the gate electrode side is flat.

[0346] (7) The display device according to (3) or (4), wherein, When viewed from the opposite surface of the second layer, the gate electrode of the second transistor is disposed on the back side of the thin-film semiconductor layer of the second transistor. The second layer further includes a light-shielding layer, and A light-shielding layer is disposed between multiple second transistors and electrodes.

[0347] (8) The display device according to (3), wherein, Multiple pixel circuits, corresponding to multiple pixels set on a circuit board, and At least a subset of the multiple pixel circuits includes at least one of the first transistors and at least one of the second transistors.

[0348] (9) The display device according to (8), wherein, The first layer further includes a plurality of first bonding electrodes. The second layer further includes a plurality of second bonding electrodes. The first and second bonding electrodes are bonded to each other at the bonding surface to form a bonding portion, and Set at least one junction for each pixel.

[0349] (10) A display device according to any one of (1) to (7), wherein, Multiple pixel circuits, corresponding to multiple pixels set on a circuit board, and The pixel circuitry included in a predetermined area of ​​the display area includes at least one of the first transistors and at least one of the second transistors.

[0350] (11) A display device according to any one of (1) to (7), wherein, Multiple pixel circuits correspond to multiple pixels being arranged on a circuit board. The multiple pixel circuits include: multiple first pixel circuits included in a first region of the display area and multiple second pixel circuits included in a second region of the display area. The first pixel circuit includes at least two first transistors. The second pixel circuits all include at least one of the first transistors and at least one of the second transistors, and One of the first transistors included in each first pixel circuit and one of the second transistors included in each second pixel circuit have the same function and are connected to the same wiring.

[0351] (12) A display device according to any one of (1) to (8), (10) and (11), wherein, The circuit board further includes a first insulating film disposed between the first layer and the second layer. The first layer further includes a plurality of first bonding electrodes. The second layer further includes a plurality of second bonding electrodes, and By breaking the first insulating film, the first bonding electrode and the second bonding electrode are bonded to each other at the bonding surface.

[0352] (13) A display device according to any one of (1) to (12), wherein, One or both of the first and second layers further include dummy wiring, and Dummy wiring is set to be adjacent to the mating surface.

[0353] (14) A display device according to any one of (1) to (12), wherein, The first layer further includes a first dummy wiring. The second layer further includes a second dummy wiring. The first dummy wiring and the second dummy wiring are positioned adjacent to the mating surface, and The first dummy wiring and the second dummy wiring are connected to each other.

[0354] (15) A display device according to any one of (1) to (14), wherein, The second layer includes a second insulating film with barrier properties, and The second insulating film is disposed between the plurality of second transistors and the electrodes.

[0355] (16) A display device according to any one of (1) to (15), wherein, The electrodes and the portions between adjacent electrodes are flush with each other to form a flat surface.

[0356] (17) An electronic device comprising a display device according to any one of (1) to (16).

[0357] (18) A method for manufacturing a display device, comprising the following steps: Forming a first layer comprising multiple first transistors; A second layer comprising electrodes of multiple second transistors, multiple light-emitting elements, and multiple wirings is formed on the substrate; Join the first and second layers together; and Remove the substrate from the second layer, where The steps to form the second layer include: A third layer comprising electrodes with multiple light-emitting elements is formed on the substrate. A fourth layer, comprising multiple wirings, is formed on top of the third layer. The second layer is formed by forming a fifth layer, which includes multiple second transistors, on the fourth layer.

[0358] (19) The method for manufacturing a display device according to (18), wherein

[0359] The first layer further includes a plurality of first bonding electrodes. The second layer further includes a plurality of second bonding electrodes. The step of forming the second layer further includes the step of forming a sixth layer comprising a plurality of second bonding electrodes on the fifth layer, and In the bonding step, the first bonding electrode and the second bonding electrode are bonded to each other.

[0360] (20) The method for manufacturing a display device according to (19) further includes: The step of forming an insulating film on at least one of the first layer and the second layer, wherein In the bonding step, after the first and second layers are stacked in a manner that sandwiches the insulating film, the constituent materials of the first bonding electrode and the constituent materials of the second bonding electrode are subjected to grain growth by heat treatment, and the first bonding electrode and the second bonding electrode are bonded by breaking the portion of the insulating film located between the first bonding electrode and the second bonding electrode.

[0361] <6. Relationship between the normals passing through the centers of the light-emitting part, the lens component, and the wavelength selection part>

[0362] The relationship between the normal LN passing through the center of each light-emitting part, the normal LN' passing through the center of each lens component, and the normal LN' passing through the center of each wavelength selection part will be described below. Here, the light-emitting part is, for example, the light-emitting element 13. The lens component is, for example, the lens 181. The wavelength selection part is, for example, the color filter 16.

[0363] Note that the size of the wavelength selective section can be appropriately changed according to the light emitted from the light-emitting section, or, in the case where the light-absorbing section (e.g., the black matrix section) is located between the wavelength selective sections of adjacent light-emitting sections, the size of the light-absorbing section can be appropriately changed according to the light emitted from the light-emitting section. Furthermore, the size of the wavelength selective section can be appropriately changed according to the distance (offset) d0 between the normal passing through the center of the light-emitting section and the normal passing through the center of the wavelength selective section. The planar shape of the wavelength selective section can be the same as, similar to, or different from the planar shape of the lens component.

[0364] The following will refer to Figure 30 A, Figure 30 B. Figure 30 C and Figure 31 The relationship between the normals passing through the center of each light-emitting part 51, each wavelength selection part 52, and each lens member 53 is described when the light-emitting part 51, each wavelength selection part 52, and each lens member 53 are arranged in this order.

[0365] like Figure 30 As shown in Figure A, the normal LN passing through the center of the light-emitting part 51, the normal LN” passing through the center of the wavelength selection part 52, and the normal LN' passing through the center of the lens member 53 can coincide with each other. That is, D0=0 and d0=0 can be satisfied. Here, D0 represents the distance (offset) between the normal LN passing through the center of the light-emitting part 51 and the normal LN' passing through the center of the lens member 53, and d0 represents the distance (offset) between the normal LN passing through the center of the light-emitting part 51 and the normal LN” passing through the center of the wavelength selection part 52.

[0366] like Figure 30 As shown in B, a configuration can be adopted in which the normal LN passing through the center of the light-emitting part 51 and the normal LN” passing through the center of the wavelength selection part 52 coincide with each other, but the normal LN passing through the center of the light-emitting part 51 and the normal LN” passing through the center of the wavelength selection part 52 do not coincide with the normal LN' passing through the center of the lens member 53. That is, it is possible to satisfy D0>0 and d0=0.

[0367] like Figure 30 As shown in Figure C, a configuration can be adopted in which the normal LN passing through the center of the light-emitting part 51 does not coincide with the normal LN” passing through the center of the wavelength selection part 52 and the normal LN' passing through the center of the lens member 53, but the normal LN” passing through the center of the wavelength selection part 52 and the normal LN' passing through the center of the lens member 53 coincide with each other. That is, D0>0, d0>0 and D0=d0 can be satisfied.

[0368] like Figure 31 As shown, the normal LN passing through the center of the light-emitting part 51, the normal LN” passing through the center of the wavelength selection part 52, and the normal LN' passing through the center of the lens member 53 can be arranged such that they do not coincide. That is, D0>0, d0>0, and D0≠d0 can be satisfied. Here, the center of the wavelength selection part 52 (in Figure 31 The location indicated by the black square is preferably located at the center of the connection between the light-emitting part 51 and the center of the lens member 53. Figure 31 On the straight line LL (indicated by the black circle in the middle). Specifically, assume that in the thickness direction ( Figure 31 The distance between the center of the light-emitting part 51 and the center of the wavelength selection part 52 in the vertical direction is represented by LL1, and the distance between the center of the wavelength selection part 52 and the center of the lens member 53 in the thickness direction is represented by LL2. Preferably, the distance between the center of the wavelength selection part 52 and the center of the lens member 53 in the thickness direction is: Satisfying D0 > d0 > 0, and Taking into account manufacturing variations, the following condition is met: d0:D0=LL1:(LL1+LL2).

[0369] Here, the thickness direction refers to the thickness direction of the light-emitting part 51, the wavelength selection part 52, and the lens member 53.

[0370] The following will refer to Figure 32 A, Figure 32 B and Figure 33 The relationship between the normals passing through the center of each light-emitting part 51, the center of each lens member 53, and the center of each wavelength selection part 52 is described when the light-emitting part 51, the lens member 53, and the wavelength selection part 52 are arranged in this order.

[0371] like Figure 32As shown in Figure A, a configuration can be adopted in which the normal line LN passing through the center of the light-emitting part 51, the normal line LN” passing through the center of the wavelength selection part 52, and the normal line LN' passing through the center of the lens member 53 coincide with each other. That is, it is possible to satisfy D0>0 and d0=0.

[0372] like Figure 32 As shown in Figure B, a configuration can be adopted in which the normal LN passing through the center of the light-emitting part 51 does not coincide with the normal LN” passing through the center of the wavelength selection part 52 and the normal LN' passing through the center of the lens member 53, but the normal LN” passing through the center of the wavelength selection part 52 and the normal LN' passing through the center of the lens member 53 coincide with each other. That is, D0>0, d0>0 and D0=d0 can be satisfied.

[0373] like Figure 33 As shown, a configuration can be adopted in which the normal LN passing through the center of the light-emitting part 51, the normal LN” passing through the center of the wavelength selection part 52, and the normal LN' passing through the center of the lens member 53 do not coincide with each other. Here, the center of the lens member 53 (by...) Figure 33 The position indicated by the black circle in the diagram is preferably located at the center connecting the light-emitting part 51 and the wavelength selection part 52 (by...). Figure 33 On the straight line LL (indicated by the position of the black square in the diagram). Specifically, assume that in the thickness direction ( Figure 33 The distance between the center of the light-emitting portion 51 and the center of the lens member 53 in the vertical direction is represented by LL2, and the distance between the center of the lens member 53 and the center of the wavelength selection portion 52 in the thickness direction is represented by LL1. Preferably, the distance between the center of the light-emitting portion 51 and the center of the lens member 53 in the thickness direction is LL1. Satisfying d0 > D0 > 0, Furthermore, considering manufacturing variations, the following condition is met: D0:d0 = LL2:(LL1 + LL2).

[0374] Here, the thickness direction refers to the thickness direction of the light-emitting part 51, the wavelength selection part 52, and the lens member 53.

[0375] <7 Examples of Resonator Structures>

[0376] The sub-pixels 2 included in the display device 1 according to the first embodiment, the display device 1A according to the second embodiment, and the display devices 1 and 1A according to their variations (hereinafter referred to as "display device 1 according to the first embodiment, etc.") may have a resonator structure that causes the light generated by the light-emitting element 13 to resonate. The resonator structure will be described below with reference to the accompanying drawings. Furthermore, in the following description, the first surface of each layer may be referred to as the upper surface.

[0377] (Resonator structure: First embodiment)

[0378] Figure 34 A is a schematic cross-sectional view illustrating a first embodiment of the resonator structure. In the following description, the light-emitting elements corresponding to sub-pixels 2R, 2G, and 2B are collectively referred to as light-emitting elements 13, unless otherwise distinguished. When the light-emitting elements corresponding to sub-pixels 2R, 2G, and 2B are distinguished from each other, they may be referred to as light-emitting elements 13. R 13 G 、 and 13 B The portions of OLED layer 132 corresponding to sub-pixels 2R, 2G, and 2B can be referred to as OLED layer 132R, OLED layer 132G, and OLED layer 132B, respectively. The light-emitting element is, for example, the light-emitting element in the first embodiment.

[0379] In the first embodiment, electrode 131 has the same film thickness in each light-emitting element 13. The same applies to electrode 133.

[0380] A reflector 71 is disposed below the electrode 131 of the light-emitting element 13, with an optical adjustment layer 72 situated between them. A resonator structure is formed between the reflector 71 and the electrode 133, in which the light generated by the OLED layer 132 resonates. In the following description, the optical adjustment layer 72, which is disposed corresponding to the sub-pixels 2R, 2G, and 2B, may be referred to as the optical adjustment layer 72, respectively. R 72 G 、 and 72 B .

[0381] The reflector 71 is formed in each light-emitting element 13 with the same film thickness. The film thickness of the optical adjustment layer 72 varies according to the color to be displayed by the corresponding sub-pixel. Due to the optical adjustment layer 72... R 72 G 72 B With different film thicknesses, an optical distance can be set that causes optimal resonance for the wavelength of light corresponding to the color to be displayed.

[0382] exist Figure 34 In the embodiment shown in A, the light-emitting element 13 R 13 G and 13 B The upper surfaces of the reflectors 71 are arranged to be aligned with each other. As described above, since the film thickness of the optical adjustment layer 72 changes according to the color displayed by the corresponding sub-pixel, the position of the upper surface of the electrode 133 is determined according to the light-emitting element 13. R 13 G and 13 B It changes according to the type.

[0383] For example, reflector 71 can be formed using metals such as aluminum (Al), silver (Ag), copper (Cu), or alloys containing one of these metals as a main component.

[0384] The optical conditioning layer 72 may include, for example, silicon nitride (SiN). x ), silicon dioxide (SiO) x ) or silicon oxynitride (SiO) x N y The materials used are inorganic insulating materials or organic resin materials such as acrylic resins or polyimide resins. Each optical adjustment layer 72 can be a single layer or a multilayer film comprising multiple materials. Furthermore, the number of layers can vary depending on the type of light-emitting element 13.

[0385] Electrode 131 may include a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO).

[0386] Electrode 133 needs to be used as a semi-transparent reflective film. Electrode 133 can be formed using magnesium (Mg), silver (Ag), magnesium-silver alloys (MgAg) containing these as main components, alloys containing alkali metals or alkaline earth metals, etc.

[0387] (Resonator structure: Second embodiment)

[0388] Figure 34 B is a schematic cross-sectional view used to describe a second embodiment of the resonator structure.

[0389] Similarly, in the second embodiment, electrodes 131 and 133 are formed with the same film thickness in each light-emitting element 13.

[0390] Similarly, in the second embodiment, the reflector 71 is arranged below the electrode 131 of the light-emitting element 13, with the optical adjustment layer 72 interposed therebetween. A resonator structure is formed between the reflector 71 and the electrode 133, in which the light generated by the OLED layer 132 resonates. Similar to the first embodiment, the reflector 71 is formed with the same film thickness in each light-emitting element 13, and the film thickness of the optical adjustment layer 72 varies according to the color to be displayed by the corresponding sub-pixel.

[0391] exist Figure 34 In the first embodiment shown in A, the light-emitting element 13 R 13 G and 13 B The upper surfaces of the reflectors 71 are arranged to be aligned with each other, and the position of the upper surface of the electrodes 133 is determined according to the light-emitting element 13. R 13 G and 13 B Different types.

[0392] On the other hand, Figure 34 In the second embodiment shown in B, the upper surface of electrode 133 is arranged on the light-emitting element 13. R 13 G and 13 B The electrodes 133 are aligned with each other. To align the upper surfaces of the electrodes 133 with each other, the light-emitting element 13... R 13 G and 13 B In the middle, according to the light-emitting element 13 R 13 G and 13 B The upper surface of the reflector 71 is arranged differently depending on the type of the light-emitting element 13. Therefore, the lower surface of the reflector 71 (in other words, the upper surface of the substrate (insulating layer) 73) is formed in a stepped shape according to the type of the light-emitting element 13.

[0393] The materials of reflector 71, optical adjustment layer 72, electrode 131 and electrode 133 are similar to those described in the first embodiment, and their description is omitted.

[0394] (Resonator structure: Third embodiment)

[0395] Figure 35 A is a schematic cross-sectional view illustrating a third embodiment of the resonator structure. In the following description, the reflector 71, which is disposed corresponding to sub-pixels 2R, 2G, and 2B, may be referred to as reflector 71, respectively. R 71 G 、 and 71 B .

[0396] Similarly, in the third embodiment, electrodes 131 and 133 are formed with the same film thickness in each light-emitting element 13.

[0397] Similarly, in the third embodiment, the reflector 71 is arranged below the electrode 131 of the light-emitting element 13, with the optical adjustment layer 72 interposed therebetween. A resonator structure is formed between the reflector 71 and the electrode 133, in which the light generated by the OLED layer 132 resonates. Similar to the first and second embodiments, the film thickness of the optical adjustment layer 72 varies according to the color to be displayed by the corresponding sub-pixel. Similar to the second embodiment, the upper surface of the electrode 133 is positioned above the light-emitting element 13. R 13 G and 13 B They are aligned with each other.

[0398] exist Figure 35 In the second embodiment shown in B, in order to align the upper surfaces of the electrodes 133 with each other, the lower surface of the reflector 71 has a stepped shape depending on the type of light-emitting element 13.

[0399] On the other hand, Figure 35 In the third embodiment shown in A, the film thickness of the reflector 71 is set according to the light-emitting element 13. R 13 G and 13 B The type varies. More specifically, the film thickness is set such that the reflector 71 R 71 G and 71 B The lower surfaces are aligned with each other.

[0400] The materials of reflector 71, optical adjustment layer 72, electrode 131 and electrode 133 are similar to those described in the first embodiment, and their description is omitted.

[0401] (Resonator Structure: Fourth Embodiment)

[0402] Figure 35 B is a schematic cross-sectional view for describing a fourth embodiment of the resonator structure. In the following description, the electrodes 131 disposed corresponding to sub-pixels 2R, 2G, and 2B may be referred to as electrodes 131, respectively. R 131 G 、 and 131 B .

[0403] exist Figure 35 In the first embodiment shown in A, the electrodes 131 and 133 of the light-emitting element 13 are formed to have the same film thickness. The reflector 71 is arranged below the electrode 131 of the light-emitting element 13, and the optical adjustment layer 72 is interposed therebetween.

[0404] On the other hand, Figure 35 In the fourth embodiment shown in B, the optical adjustment layer 72 is omitted, and the film thickness of the electrode 131 is set according to the light-emitting element 13. R 13 G and 13 B Different types.

[0405] The reflector 71 is formed in each light-emitting element 13 with the same film thickness. The film thickness of the electrode 131 varies according to the color to be displayed by the corresponding sub-pixel. Due to the electrode 131... R 131 G and 131 B With different film thicknesses, the optical distance that produces the optimal resonance with the wavelength of light can be set according to the color to be displayed.

[0406] The materials of reflector 71, optical adjustment layer 72, electrode 131 and electrode 133 are similar to those described in the first embodiment, and their description is omitted.

[0407] (Resonator Structure: Fifth Embodiment)

[0408] Figure 35 A is a schematic cross-sectional view used to describe the fifth embodiment of the resonator structure.

[0409] exist Figure 34 In the first embodiment shown in A, electrodes 131 and 133 are formed to have the same film thickness in each light-emitting element 13. A reflector 71 is disposed below the electrode 131 of the light-emitting element 13, and an optical adjustment layer 72 is interposed therebetween.

[0410] On the other hand, Figure 36 In the fifth embodiment shown in A, the optical adjustment layer 72 is omitted, and instead, an oxide film 74 is formed on the surface of the reflector 71. The thickness of the oxide film 74 is set according to the light-emitting element 13. R 13 G and 13 B The type varies. In the following description, the oxide film 74 corresponding to the sub-pixels 2R, 2G, and 2B may be referred to as oxide film 74, respectively. R 74 G and 74 B .

[0411] The thickness of oxide film 74 varies depending on the color that the corresponding sub-pixel should display. Because oxide film 74 R 74 G 74 B Because the film thickness varies, it is possible to set the optical distance that produces the optimal resonance for the wavelength of light corresponding to the displayed color.

[0412] The oxide film 74 is a film obtained by oxidizing the surface of the reflector 71, and includes, for example, aluminum oxide, tantalum oxide, titanium oxide, magnesium oxide, zirconium oxide, etc. The oxide film 74 serves as an insulating film for adjusting the optical path length (optical distance) between the reflector 71 and the electrode 133.

[0413] For example, it can be based on the light-emitting element 13 R 13 G and 13 B The types of oxide films 74 with different film thicknesses are formed, as follows.

[0414] First, an electrolyte is filled into a container, and the substrate on which the reflector 71 is formed is immersed in the electrolyte. Furthermore, the electrodes are arranged to face the reflector 71.

[0415] Then, a positive voltage is applied to reflector 71 with reference to the electrodes to perform anodizing on reflector 71. Since the thickness of the oxide film produced by anodizing is proportional to the voltage applied to the electrodes, the voltage applied to reflector 71... R 71 G and 71 B Anodizing is performed based on the voltage of the light-emitting element 13. This allows for the formation of oxide films 74 with varying thicknesses in a single step.

[0416] The materials of reflector 71, electrode 131 and electrode 133 are similar to those described in the first embodiment, and their description is omitted.

[0417] (Resonator Structure: Sixth Embodiment)

[0418] Figure 36 B is a schematic cross-sectional view used to describe the sixth embodiment of the resonator structure.

[0419] In the sixth embodiment, the light-emitting element 13 is configured by stacking electrodes 131, OLED layer 132, and electrodes 133. However, in the sixth embodiment, electrode 131 is formed to serve as both an electrode and a reflector. The first electrode (also a reflector) 131 includes components according to the light-emitting element 13. R 13 G and 13 B The type of material chosen determines the optical constants. Because the phase shift of the first electrode (which is also a reflector) 131 is different, an optical distance that produces optimal resonance for the wavelength of light corresponding to the color to be displayed can be set.

[0420] The first electrode (also a reflector) 131 may include a single metal such as aluminum (Al), silver (Ag), gold (Au), or copper (Cu), or an alloy containing one of these as a main component. For example, the light-emitting element 13 R The first electrode (also the reflector) 131 R It may include copper (Cu), and light-emitting element 13 G The first electrode (also the reflector) 131 G and light-emitting element 13 B The first electrode (also the reflector) 131 B It may include aluminum.

[0421] The material of electrode 133 is similar to that described in the first embodiment, and its description is omitted.

[0422] (Resonator Structure: Seventh Embodiment)

[0423] Figure 37 This is a schematic cross-sectional view used to describe the seventh embodiment of the resonator structure.

[0424] In the seventh embodiment, the sixth embodiment is essentially applied to the light-emitting element 13. R and 13 G And the first embodiment is applied to the light-emitting element 13 B Furthermore, in this configuration, an optical distance can be set to generate optimal resonance for the wavelength of light corresponding to the color to be displayed.

[0425] Used for light-emitting element 13 R and 13 G The first electrode (also the reflector) 131 R and 131 G It may include a single metal such as aluminum (Al), silver (Ag), gold (Au) or copper (Cu) or an alloy containing one of these as a main component.

[0426] Used for light-emitting element 13 B Reflector 71 B Optical adjustment layer 72B and electrode 131 B The materials, etc., are similar to those described in the first embodiment, and their description is omitted.

[0427] <8 Application Examples>

[0428] (Electronic devices)

[0429] The display device 1 according to the first embodiment, etc., can be installed in various electronic devices. The display device 1 according to the first embodiment, etc., is particularly required to have high resolution, such as an electronic viewfinder or single-lens reflex camera for eyeglasses (such as a head-mounted display) or a camera, and is suitable for those that are magnified and used near the eyes. (Specific Implementation Example 1)

[0431] Figure 38 A and Figure 38 B shows an example of the appearance of the digital camera 310. The digital camera 310 is a single-lens reflex type with interchangeable lenses and includes an interchangeable imaging lens unit (interchangeable lens) 312 located substantially at the center of the front part of the camera body (camera body) 311, and a grip portion 313 held on the left front side by the person taking the image.

[0432] The monitor 314 is positioned offset to the left from the center of the back of the camera body 311. An electronic viewfinder (eyepiece window) 315 is positioned above the monitor 314. By viewing the electronic viewfinder 315, the photographer can determine the composition by visually recognizing the optical image of the subject guided by the imaging lens unit 312. The electronic viewfinder 315 includes any of the display devices 1 according to the first embodiment, etc. (Specific Implementation Example 2)

[0434] Figure 39 An example of the appearance of a head-mounted display 320 is shown. The head-mounted display 320 is an example of an eyeglass device. For example, the head-mounted display 320 includes a display unit 321 having an eyeglass shape, with ear loops 322 on both sides of the display unit for the user to wear the head-mounted display on their head. The display unit 321 includes any of the display devices 1 according to the first embodiment, etc. (Specific Implementation Example 3)

[0436] Figure 40 An example of the appearance of a television device 330 is shown. The television device 330 includes, for example, a video display screen unit 331 including a front panel 332 and a filter glass 333, and the video display screen unit 331 includes any of the display devices 1 according to the first embodiment, etc. (Specific Implementation Example 4)

[0438] Figure 41 An example of the appearance of a see-through head-mounted display 340 is shown. The see-through head-mounted display 340 is an example of an eyeglass device. The see-through head-mounted display 340 includes a main body 341, an arm 342, and a lens barrel 343.

[0439] The main body 341 is connected to the arm 342 and the glasses 350. Specifically, the end of the main body 341 along its long side is connected to the arm 342, and one side of its side surface is connected to the glasses 350 via a connecting member. Note that the main body 341 can be worn directly on the human head.

[0440] The main body 341 includes a control panel and a display unit for controlling the operation of the see-through head-mounted display 340. An arm 342 connects the main body 341 and the lens barrel 343, and supports the lens barrel 343. Specifically, the arm 342 is coupled to both the end of the main body 341 and the end of the lens barrel 343 to fix the lens barrel 343. Furthermore, the arm 342 includes signal lines for communicating data related to the image provided from the main body 341 to the lens barrel 343.

[0441] The lens barrel 343 projects image light provided from the main body 341 via the arm 342 toward the eyes of the user wearing the see-through head-mounted display 340 through the eyepiece 351. In the see-through head-mounted display 340, the display unit of the main body 341 includes any of the display devices 1 according to the first embodiment, etc. (Specific Implementation Example 5)

[0443] Figure 42An example showing the appearance of a smartphone 360 ​​is provided. The smartphone 360 ​​includes a display unit 361 for displaying various information, an operation unit 362 including buttons for receiving operation input from the user, etc. The display unit 361 includes any of the display devices 1 according to the first embodiment, etc. (Specific Implementation Example 6)

[0445] The display device 1 according to the first embodiment, etc., can be installed in various displays installed in a vehicle.

[0446] Figure 43 A and Figure 43 B is a diagram illustrating an example of the interior configuration of a vehicle 500 equipped with various displays. Specifically, Figure 43 A is an example diagram showing the interior of vehicle 500 as viewed from the rear to the front, and... Figure 43 B is an example diagram showing the interior state of vehicle 500 as viewed from the rear to the front.

[0447] Vehicle 500 includes a central display 501, a console display 502, a head-up display 503, a digital rearview mirror 504, a steering wheel display 505, and a rear entertainment display 506. At least one of these displays includes any of the display devices 1 according to the first embodiment, etc. For example, all these displays may include any of the display devices 1 according to the first embodiment, etc.

[0448] The central display 501 is located on the dashboard facing the driver's seat 508 and the passenger seat 509. Figure 43 A and Figure 43 Example B illustrates a central display 501 with a horizontally elongated shape extending from the driver's seat 508 side to the passenger seat 509 side; however, the screen size and arrangement of the central display 501 are arbitrary. The central display 501 is capable of displaying information detected by various sensors. As specific examples, the central display 501 can display images captured by image sensors, images indicating the distance to obstacles present in front of or to the side of the vehicle 500, distances measured by ToF sensors, occupant body temperatures detected by infrared sensors, etc. The central display 501 can be used to display at least one of, for example, safety-related information, operational-related information, survival logs, health-related information, authentication / identification-related information, or entertainment-related information.

[0449] Safety-related information includes information about drowsiness detection, eye-away detection, mischief by children riding together, presence or absence of seatbelts, and occupant departure, and is sensed by sensors, for example, arranged in an overlapping manner on the rear surface of the central display 501. Operation-related information uses sensors to detect gestures associated with actions performed by occupants. Detected gestures may include the operation of various devices in vehicle 500. For example, the operation of the HVAC system, navigation system, AV system, lighting system, etc. A lifelog includes the lifelog of all occupants. For example, the lifelog includes a record of the actions of each occupant in the vehicle. By acquiring and storing the lifelog, the condition of each occupant at the time of the accident can be checked. Health-related information uses sensors such as temperature sensors to detect the occupant's body temperature and estimates the occupant's health condition based on the detected body temperature. Alternatively, the occupant's face can be imaged using an image sensor, and the occupant's health condition can be estimated from the imaged facial expressions. Furthermore, by interacting with occupants via automated voice, the occupant's health status can be estimated based on their responses. Authentication / recognition related information includes keyless entry functions that use sensors to perform facial authentication, and functions that automatically adjust seat height and position via facial recognition. Entertainment related information includes functions that use sensors to detect operational information of AV devices performed by occupants, and functions that use sensors to recognize occupants' faces and provide content suitable for them via AV devices.

[0450] For example, the console display 502 can be used to display rescue log information. The console display 502 is located near the gearshift lever 511 of the center console 510 between the driver's seat 508 and the passenger seat 509. The console display 502 can also display information detected by various sensors. Furthermore, the console display 502 can display images of the vehicle's surroundings captured by image sensors, or it can display images of the distances to obstacles around the vehicle.

[0451] The head-up display 503 is virtually displayed behind the windshield 512 in front of the driver's seat 508. For example, the head-up display 503 can be used to display at least one of safety-related information, operational-related information, emergency logs, health-related information, authentication / identification-related information, or entertainment-related information. Since the head-up display 503 is virtually positioned in front of the driver's seat 508 in many cases, it is suitable for displaying information directly related to the operation of the vehicle 500, such as the vehicle's speed, remaining fuel (battery) level, etc.

[0452] The digital rearview mirror 504 can not only display the rear of the vehicle 500, but also the status of the rear seat occupants. Therefore, for example, it can be used to display life-saving log information by arranging sensors in an overlapping manner on the back side of the digital rearview mirror 504.

[0453] A steering wheel display 505 is disposed near the center of the steering wheel 513 of the vehicle 500. The steering wheel display 505 can be used to display at least one of the following: safety-related information, operation-related information, emergency log, health-related information, authentication / identification-related information, or entertainment-related information. Specifically, a steering wheel display 505 located near the driver's hands is suitable for displaying emergency log information such as the driver's body temperature, or for displaying information about the operation of AV devices, HVAC systems, etc.

[0454] The rear entertainment display 506 is attached to the rear side of the driver's seat 508 or the passenger seat 509 and is used for viewing / listening by the occupants in the rear seats. The rear entertainment display 506 can be used to display at least one of the following: safety-related information, operational-related information, life-saving logs, health-related information, authentication / identification-related information, or entertainment-related information. Specifically, the rear entertainment display 506 located in front of the rear seat occupants displays information relevant to them. For example, it may display information about the operation of AV devices or HVAC systems, or it may display the results of temperature sensor measurements of the occupants' body temperature in the rear seats.

[0455] Sensors can be arranged in an overlapping manner on the back side of the display device 1, etc., and the distance to objects existing in the surrounding environment can be measured. Optical ranging methods are broadly classified into passive and active types. Passive methods measure distance by receiving light from an object without projecting light from the sensor onto the object. Examples of active methods include lens focusing methods, stereo methods, monocular vision methods, etc. Active methods measure distance by projecting light onto an object and receiving reflected light from the object with a sensor. Examples of active methods include optical radar methods, active stereo methods, photometric stereo methods, moiré morphology methods, interferometry methods, etc. The display device 1, etc., according to the first embodiment can be applied to any of these types of distance measurement. By using sensors arranged to overlap with the back side of the display device 1, etc., according to the first embodiment, the above-described passive or active distance measurement can be performed.

[0456] Reference Symbol List

[0457] 1 Display device

[0458] 2R, 2G, 2B subpixels

[0459] 10 Circuit Boards

[0460] 101 Joint

[0461] 102 Insulating film (first insulating film)

[0462] 11 First Floor

[0463] 11a Semiconductor substrate

[0464] 11b Electrode / Wiring Layer

[0465] 11b1 electrode layer

[0466] 11b2 wiring layer

[0467] 11b3 electrode layer

[0468] 11b4 Capacitor Component Layer

[0469] 110b1, 110b2, 110b3, 110b4 insulation layers

[0470] 111 Gate electrode

[0471] 112, 113 Source / Drain Regions

[0472] 114 Bonding Electrode

[0473] 115 wiring

[0474] 116 Dummy Wiring (First Dummy Wiring)

[0475] 12 Second layer

[0476] 12a1 Electrode Layer (Sixth Layer)

[0477] 12a2 Transistor Layer (Fifth Layer)

[0478] 12a3 Wiring layer (fourth layer)

[0479] 12a4 Electrode Layer (Third Layer)

[0480] Insulation layers 120a1, 120a2, 120a3, 120a4

[0481] 121 Bonding electrode

[0482] 122 wiring

[0483] 123 Through Hole

[0484] 124 Thin Film Semiconductor Layer

[0485] 125 gate electrode

[0486] 126 Source / Drain Electrode

[0487] 126a Contact Material

[0488] 126b Barrier Metal

[0489] 127 Source / Drain Electrode

[0490] 127a Contact Materials

[0491] 127b Barrier Metal

[0492] 128 Dummy Wiring (Second Dummy Wiring)

[0493] 129a Insulating film (second insulating film)

[0494] 129b Light-shielding layer

[0495] 13 Light-emitting elements

[0496] 131 electrode

[0497] 132 OLED layers

[0498] 133 electrode

[0499] 14 Protective Layer

[0500] 15 Planarization layer

[0501] 16 Color Filters

[0502] 160R, 160G, 160B coloring layers

[0503] 17 Planarization layer

[0504] 18-lens array

[0505] 181 Lens

[0506] 19. Sealing resin layer

[0507] 20-pixel array unit

[0508] 21 Write to the scanning section

[0509] 21a scan line

[0510] 22 Driving Scanning Unit

[0511] 22a drive line

[0512] 23 Signal Output Section

[0513] 23a signal line

[0514] 24 First drive scanning unit

[0515] 24a First drive line

[0516] 25 Second drive scanning unit

[0517] 25a Second Drive Line

[0518] 310 digital camera

[0519] 320 Head-Mounted Display

[0520] 330 television equipment

[0521] 340° View Head-Mounted Display

[0522] 360 Smart Phone

[0523] 500 vehicles

[0524] Tr1 is the driving transistor (first transistor).

[0525] Tr2 write transistor (second transistor)

[0526] Tr3 Light-emitting control transistor (first transistor)

[0527] Tr4 Switching transistor (second transistor)

[0528] RE1 Central Area (Region 1)

[0529] RE2 Outer Area (Second Area).

Claims

1. A display device, comprising: The circuit board has multiple light-emitting elements, among which... The circuit board includes: The first layer includes multiple first transistors; and The second layer includes multiple second transistors, electrodes of the multiple light-emitting elements, and multiple wirings. The second layer is bonded to the first layer. The plurality of second transistors are disposed separately from the junction surface between the first layer and the second layer, and The electrode is disposed on the surface of the second layer opposite to the bonding surface.

2. The display device according to claim 1, wherein, The plurality of second transistors are disposed on a layer at least one layer higher than the junction surface.

3. The display device according to claim 1, wherein, The first transistor is a metal-oxide-semiconductor field-effect transistor (MOSFET), and The second transistor is a thin-film transistor.

4. The display device according to claim 3, wherein, The thin-film transistor is an oxide semiconductor thin-film transistor.

5. The display device according to claim 3, wherein, When viewed from the opposite surface of the second layer, the gate electrode of the second transistor is disposed on the front side of the thin-film semiconductor layer of the second transistor.

6. The display device according to claim 5, wherein, In each thin-film semiconductor layer, the surface on the gate electrode side is flat.

7. The display device according to claim 3, wherein, When viewed from the opposite surface of the second layer, the gate electrode of the second transistor is disposed on the rear side of the thin-film semiconductor layer of the second transistor. The second layer further includes a light-shielding layer, and The light-shielding layer is disposed between the plurality of second transistors and the electrode.

8. The display device according to claim 3, wherein, Multiple pixel circuits, corresponding to the multiple pixels, are disposed on the circuit board, and At least a subset of the plurality of pixel circuits includes at least one of the first transistors and at least one of the second transistors.

9. The display device according to claim 8, wherein, The first layer further includes a plurality of first bonding electrodes. The second layer further includes a plurality of second bonding electrodes. The first bonding electrode and the second bonding electrode are bonded to each other at the bonding surface to form a bonding portion, and At least one of the aforementioned joints is provided for each pixel.

10. The display device according to claim 1, wherein, Multiple pixel circuits, corresponding to multiple pixels, are disposed on the circuit board, and The pixel circuit included in a predetermined area of ​​the display area includes at least one of the first transistors and at least one of the second transistors.

11. The display device according to claim 1, wherein, Multiple pixel circuits, corresponding to multiple pixels, are disposed on the circuit board. The plurality of pixel circuits includes: a plurality of first pixel circuits included in a first region of the display area and a plurality of second pixel circuits included in a second region of the display area. Each of the first pixel circuits includes at least two of the first transistors. The second pixel circuit includes at least one of the first transistors and at least one of the second transistors, and The first transistor included in each first pixel circuit and the second transistor included in each second pixel circuit have the same function and are connected to the same wiring.

12. The display device according to claim 1, wherein, The circuit board further includes a first insulating film disposed between the first layer and the second layer. The first layer further includes a plurality of first bonding electrodes. The second layer further includes a plurality of second bonding electrodes, and The first bonding electrode and the second bonding electrode are bonded to each other at the bonding surface by breaking the first insulating film.

13. The display device according to claim 1, wherein, One or both of the first layer and the second layer further include dummy wiring, and The dummy wiring is positioned adjacent to the mating surface.

14. The display device according to claim 1, wherein, The first layer further includes a first dummy wiring. The second layer further includes a second dummy wiring. The first dummy wiring and the second dummy wiring are positioned adjacent to the mating surface, and The first dummy wiring and the second dummy wiring are connected to each other.

15. The display device according to claim 1, wherein, The second layer includes a second insulating film with barrier properties, and The second insulating film is disposed between the plurality of second transistors and the electrode.

16. The display device according to claim 1, wherein, The electrodes and portions between adjacent electrodes are flush with each other to form a flat surface.

17. An electronic device comprising the display device according to claim 1.

18. A method of manufacturing a display device, the method comprising the following steps: Forming a first layer comprising multiple first transistors; A second layer comprising electrodes of multiple second transistors, multiple light-emitting elements, and multiple wirings is formed on the substrate; The first layer and the second layer are joined together; as well as Remove the substrate from the second layer, wherein The steps for forming the second layer include: A third layer comprising electrodes of the plurality of light-emitting elements is formed on the substrate. A fourth layer, including the plurality of wirings, is formed on the third layer, and A fifth layer comprising the plurality of second transistors is formed on the fourth layer, thereby forming the second layer.

19. The method of manufacturing a display device according to claim 18, wherein, The first layer further includes a plurality of first bonding electrodes. The second layer further includes a plurality of second bonding electrodes. The step of forming the second layer further includes the step of forming a sixth layer including the plurality of second bonding electrodes on the fifth layer, and In the bonding step, the first bonding electrode and the second bonding electrode are bonded to each other.

20. The method of manufacturing a display device according to claim 19, further comprising: The step of forming an insulating film on at least one of the first layer and the second layer, wherein In the bonding step, after the first layer and the second layer are stacked in such a way that the insulating film is sandwiched, the constituent materials of the first bonding electrode and the constituent materials of the second bonding electrode are subjected to grain growth by heat treatment, and the first bonding electrode and the second bonding electrode are bonded to each other by breaking the portion of the insulating film located between the first bonding electrode and the second bonding electrode.

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