Array substrate, display panel and display device

Abstract

The embodiment of the invention provides an array substrate, a display panel and a display device. The array substrate comprises: a substrate; the plurality of terminals are positioned in the binding area on one side of the substrate; the first common wire is located on one side of the substrate, the first common wire is arranged around the display area, and the first common wire at least comprises a first sub-part which is located in the binding opposite side area and extends in the first direction, and a second sub-part which is located in the binding opposite side area and extends in the first direction; the multiple second common wires are located on one side of the substrate, the multiple second common wires extend in the second direction, extend from the display area to the binding opposite side area and intersect with the first sub-part, and the second direction intersects with the first direction; wherein the first sub-part and the plurality of second common wires are positioned on the same layer, and are directly and electrically connected at the crossed position.

Description

Array substrate, display panel, and display device Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0002] Dual-gate product design can halve the number of data lines required for display panels, thereby reducing the number of source chip-on-film (COF) used, significantly lowering panel production costs. As a result, it has attracted widespread attention in recent years.

[0003] Existing dual-gate display products have a problem where the common wiring in the display area and the common wiring in the non-display area are connected, resulting in high resistance. During high-frequency refresh, the common signal is difficult to recover, resulting in afterimages and crosstalk problems.

[0004] Summary of the Invention

[0005] The present disclosure provides an array substrate, a display panel, and a display device. The array substrate comprises a display area, a binding area located outside the display area, and a binding opposite side area opposite to the binding area, wherein the array substrate comprises:

[0006] substrate;

[0007] a plurality of terminals located in the bonding area on one side of the substrate;

[0008] A first common wiring is located on one side of the substrate, the first common wiring is arranged around the display area, and at least includes: a first sub-portion located in the binding opposite side area and extending along a first direction;

[0009] a plurality of second common lines located on one side of the substrate, the plurality of second common lines extending along a second direction from the display area to the opposite binding area, crossing the first sub-portion, the second direction crossing the first direction;

[0010] The first sub-section and the plurality of second common traces are located on the same layer and are directly electrically connected at the intersection.

[0011] In a possible implementation, the array substrate further includes: a plurality of data lines; the data lines and the second common lines are alternately arranged along the first direction;

[0012] The first sub-portion and the data line are formed in the same layer and made of the same material.

[0013] In a possible implementation, the first common trace further includes: a second sub-portion extending along the second direction, and a third sub-portion extending along the first direction; the second sub-portion is located outside the display area, and the third sub-portion is located in the binding area;

[0014] The second sub-section and the first sub-section are located in the same layer and are electrically connected at an intersection; the third sub-section and the second sub-section are located in different layers and are electrically connected at the intersection through a via.

[0015] In a possible embodiment, the array substrate further includes: a first compensation line; the first compensation line is located on a side of the first common line away from the display area, and one end of the first compensation line is electrically connected to an intersection of the first sub-portion and the second sub-portion;

[0016] The first compensation trace and the first sub-section are formed on the same layer and made of the same material.

[0017] In a possible embodiment, the array substrate further includes: a first lead; the other end of the first compensation trace is electrically connected to one end of the first lead, and the other end of the first lead is electrically connected to the terminal; the first lead and the first compensation trace are located in different layers.

[0018] In a possible embodiment, the first sub-section includes: a first position; a length between the first position and an end portion of the first sub-section is one fifth to one third of the length of the first sub-section in the first direction;

[0019] The array substrate further includes: a second compensation trace; the second compensation trace is located on a side of the first compensation trace away from the display area; one end of the second compensation trace is electrically connected to the first position;

[0020] The second compensation trace is formed on the same layer and made of the same material as the first sub-section.

[0021] In a possible implementation manner, the array substrate further includes: a second lead;

[0022] The other end of the second compensation trace is electrically connected to one end of the second lead; the other end of the second lead is electrically connected to the terminal; the second lead and the second compensation trace are located in different layers.

[0023] In a possible embodiment, the second sub-section includes: a second position; a length between the second position and the end of the second sub-section is one quarter to three quarters of the length of the second sub-section in the second direction;

[0024] The array substrate further includes: a third compensation trace; the third compensation trace is located between the first compensation trace and the first common trace; one end of the third compensation trace is electrically connected to the second position, and the other end of the third compensation trace is electrically connected to the terminal;

[0025] The third compensation trace is formed on the same layer and made of the same material as the first sub-section.

[0026] In a possible embodiment, the array substrate further includes: a fourth compensation trace; one end of the fourth compensation trace is electrically connected to the end of the second sub-section facing the terminal, and the other end is electrically connected to the terminal; the fourth compensation trace is in the same layer and material as the third sub-section.

[0027] In a possible embodiment, the second sub-section includes: a third position; the length between the third position and the end portion of the second sub-section close to the terminal is one seventh to one fifth of the length of the second sub-section in the second direction;

[0028] The array substrate further includes: a first detection line; the first detection line is located between the first compensation line and the third compensation line; one end of the first detection line is electrically connected to the third position;

[0029] The first detection trace and the first sub-unit are formed on the same layer and made of the same material.

[0030] In a possible implementation manner, the array substrate further includes: a third lead;

[0031] One end of the first detection line is electrically connected to one end of the third lead; the other end of the third lead is electrically connected to the terminal; and the third lead and the first detection line are located in different layers.

[0032] In a possible implementation, the array substrate further includes: a plurality of first electrostatic protection units;

[0033] The plurality of first electrostatic protection units are located between the first sub-portion and the display area, and at least one of the plurality of first electrostatic protection units is electrically connected to the second sub-portion.

[0034] In a possible embodiment, the array substrate further includes: a plurality of data lines extending along the second direction, a fan-out lead group located in the binding area, and a plurality of second electrostatic protection units; the fan-out lead group includes a plurality of fan-out leads, and the fan-out leads are electrically connected to the data lines respectively;

[0035] The plurality of second electrostatic protection units are located between the third sub-portion and the fan-out lead group, and at least one second electrostatic protection unit among the plurality of second electrostatic protection units is electrically connected to the third sub-portion.

[0036] An embodiment of the present disclosure further provides a display panel, which includes the array substrate provided by the embodiment of the present disclosure.

[0037] An embodiment of the present disclosure further provides a display device, which includes the display panel provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] FIG1 is a schematic diagram of an array substrate in the related art;

[0039] FIG2 is a schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0040] FIG3A is a specific structure diagram of a display panel corresponding to each position in FIG2 ;

[0041] FIG3B is a schematic diagram of a portion of the film layer at position S1 in FIG3A ;

[0042] FIG. 3C is a schematic diagram of a portion of the film layer at position S3 in FIG. 3A . DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0044] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0045] As used herein, "about" or "approximately the same" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "approximately the same" can mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%.

[0046] In the accompanying drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes of the figures are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Thus, the embodiments described herein should not be construed as limited to the specific shapes of the regions as shown herein, but rather include deviations in shape that result from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. Furthermore, sharp corners illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0047] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0048] As the market demands for screen aperture ratio and transmittance become increasingly higher, while ensuring that the aperture ratio of the Dual Gate product is consistent with that of the single gate structure (Single Gate), as shown in FIG1 , the display panel includes: a transparent metal oxide planar electrode 03 located in the display area AA (for example, the transparent metal oxide may be indium tin oxide), and a vertical common trace 01 located in the display area AA and on the same layer as the data line (SD), and a horizontal common trace 02 located in the non-display area BB, that is, a pixel design of a high-transmittance Dual Gate structure, in which the horizontal metal common trace is eliminated in the display area AA and only the vertical metal common trace is retained. Under this pixel design, the vertical common trace 01 in the display area AA is connected to the planar transparent metal oxide planar electrode 03 through a via K. The planar resistance of the transparent metal oxide planar electrode 03 is relatively large, resulting in poor overall conduction and recovery of the common signal. Moreover, the Dual Gate structure is not suitable for displaying a plurality of pixels. In the pixel design of the Gate structure, the vertical common trace 01 of the display area AA needs to be connected to the horizontal common trace 02 located in the non-display area BB and on a different layer through the via K when it is extended to the top of the panel. For a high-resolution mainstream product, there are about 2880 vertical common traces 01 in the display area AA, which means that 2880 traces need to be additionally punched to connect with the horizontal common trace 02. In addition to the influence of the via resistance, the conductivity of the horizontal common trace 02 is relatively low. Secondly, although the two horizontal common traces 02 are designed on the same layer, an electrostatic short-circuit loop is set between them (not shown in Figure 1). When the two horizontal common traces 02 are connected, they can only be achieved through other film layer structures and via cross-connection conduction, which also affects the overall conductivity performance of the common trace. Furthermore, compared with the Single Gate product, the Dual Gate structure panel without a mesh common trace structure has enough time to recover when the common voltage is disturbed by the coupling capacitor under low frequency conditions, but under high refresh conditions, the Dual Gate structure panel has a mesh common trace structure and can only connect to the non-display area BB and non-display area BB. In a gate-structured panel, the common voltage is extremely difficult to recover within a very short charging time. This means that the common signal cannot be quickly recovered after coupling, resulting in defects such as line afterimages and crosstalk.

[0049] In view of this, in combination with Figures 2 and 3A-3C, Figure 3A may be a specific structural diagram corresponding to each position in Figure 2, wherein S1 in Figure 3A may be a structural diagram corresponding to the position S1 in Figure 2, S2 in Figure 3A may be a structural diagram corresponding to the position S2 in Figure 2, S3 in Figure 3A may be a structural diagram corresponding to the position S3 in Figure 2, S4 in Figure 3A may be a structural diagram corresponding to the position S4 in Figure 2, the dotted box view on the upper right side of the position S2 in Figure 3A may be an enlarged schematic diagram of the lower left side of the position S2, Figure 3B may be a schematic diagram of a portion of the film layer at the position S1 in Figure 3A, and Figure 3C may be a schematic diagram of a portion of the film layer at the position S3 in Figure 3A. An embodiment of the present disclosure provides an array substrate having a display area AA, a binding area DP located outside the display area AA, and a binding opposite side area DPO opposite to the binding area DP, wherein the array substrate includes:

[0050] substrate;

[0051] Multiple terminals P are located in a bonding area DP on one side of the substrate. The multiple terminals are used to electrically connect to pads of a circuit board. The circuit board can be a flexible circuit board or a printed circuit board, etc.

[0052] A first common line 1 is located on one side of the substrate. The first common line 1 surrounds the display area AA and includes at least a first sub-portion 11 located in the opposite binding area DPO and extending along the first direction X.

[0053] A plurality of second common traces 2 are located on one side of the substrate. The plurality of second common traces 2 extend along a second direction Y and extend from the display area AA to the opposite-binding area DPO, intersecting the first sub-portion 11. The second direction Y intersects the first direction X. Specifically, the second common traces 2 may be partially located in the display area AA and partially located in the opposite-binding area DPO. Optionally, the second direction Y may be perpendicular to the first direction X.

[0054] The first sub-section 11 and the plurality of second common traces 2 are located on the same layer and are directly electrically connected at the intersection. That is, the first sub-section 11 and the plurality of second common traces 2 are located on the same layer and do not need to be electrically connected through punching. Their extension directions intersect, and they can be directly electrically connected at the intersection.

[0055] In the disclosed embodiment, the first sub-portion 11 located in the binding opposite side area DPO is located in the same layer as the plurality of second common lines 2 partially located in the display area AA, and the two are directly electrically connected at the intersection without the need for electrical connection through punching, thereby avoiding the overall reduction in resistance of the common lines when conduction is through the vias, thereby reducing the resistance value of the second common lines 2 in the display area AA when they are conducted with the public lines outside the display area AA while ensuring that high transmittance is achieved without setting horizontal public lines in the display area AA, thereby improving the recovery and conduction capabilities of the panel common signal, and improving the problem that in the case of high refresh, the common voltage of the Dual Gate structure panel is extremely difficult to recover within a very short charging time, resulting in problems such as afterimages and crosstalk.

[0056] In one possible embodiment, the array substrate further includes: a plurality of data lines (not shown); the data lines and the second common lines 2 are alternately arranged along the first direction X; and the first sub-portion 11 and the data lines are formed from the same layer and material. That is, the first sub-portion 11 and the second common lines 2 are formed from the same layer and material as the data lines.

[0057] In a possible implementation, in the embodiment of the present disclosure, the display area AA may not be provided with a metal common line extending along the first direction X. Optionally, the array substrate provided in the embodiment of the present disclosure may be a dual gate structure, including two gate lines corresponding to a pixel row, and the two gate lines are respectively arranged on both sides of the pixel row, and the same data line is electrically connected to two adjacent sub-pixels. In the pixel column, the data line and the second common line are alternately arranged in adjacent pixel columns.

[0058] In one possible embodiment, as shown in FIG2 , the display area AA may further be provided with a common electrode 3; in one possible embodiment, the common electrode 3 may be a planar electrode; in another possible embodiment, the common electrode 3 may include a plurality of common electrode strips extending along the first direction X and arranged sequentially along the second direction Y; one common electrode strip may correspond to a row of pixel electrodes, that is, the orthographic projection of one common electrode strip on the substrate may cover the orthographic projection of a row of pixel electrodes on the substrate; in one possible embodiment, the common electrode 3 may also include a plurality of common electrode blocks, and one common electrode block may correspond to a plurality of pixel electrodes, that is, the orthographic projection of one common electrode block on the substrate may cover the orthographic projection of a plurality of pixel electrodes on the substrate.

[0059] In a possible implementation, as shown in FIG. 2 , in the display area AA, the common electrode 3 may be electrically connected to the second common wiring 2 through the first via hole K1 .

[0060] In a possible embodiment, the array substrate may include, sequentially located on one side of the substrate: a pixel electrode layer (the pixel electrode layer may include multiple pixel electrodes), a gate line layer (may include multiple gate lines extending along the first direction X and arranged in sequence along the second direction Y), a gate insulating layer, an active layer, a data line (may include multiple data lines extending along the second direction Y and arranged along one side of the first direction X, and multiple second common lines 2 extending along the second direction Y and arranged along one side of the first direction X, and the data lines and the second common lines 2 may be arranged alternately along the first direction X), a passivation layer, and a common electrode layer (may include a common electrode 3); wherein the material of the pixel electrode layer may be a transparent metal oxide, for example, indium tin oxide; and the material of the common electrode layer may be a transparent metal oxide, for example, indium tin oxide.

[0061] In one possible embodiment, in conjunction with Figures 2 and 3A-3C, the first common trace 1 further includes: a second sub-section 12 extending along the second direction Y, and a third sub-section 13 extending along the first direction X; the second sub-section 12 is located outside the display area AA, for example, as shown in Figure 2, the second sub-section 12 can be located on the left and right sides of the display area AA; the third sub-section 13 is located in the binding area DP; the second sub-section 12 and the first sub-section 11 are located on the same layer and are electrically connected at the intersection; the third sub-section 13 and the second sub-section 12 are located on different layers and are electrically connected at the intersection through a via. Specifically, for example, in conjunction with Figures 3A and 3C, the third sub-section 13 and the second sub-section 12 overlap at the dotted box S6, and the two can be electrically connected at the overlapping position through a via; optionally, for example, they can be electrically connected through a via and a first transition portion, and the first transition portion can be located in the common electrode layer.

[0062] In a possible implementation, as shown in FIG. 2 and FIG. 3A to FIG. 3C , the first common trace 1 may be a closed loop, including a first sub-section 11 , a second sub-section 12 , and a third sub-section 13 that are connected to each other.

[0063] In a possible implementation, the third sub-portion 13 may be located in the gate line layer and made of the same layer and material as the gate lines. Forming the third sub-portion 13 at the same time as forming the gate lines is beneficial for simplifying the manufacturing process of the array substrate.

[0064] In one possible embodiment, as shown in conjunction with Figures 2 and 3A-3C, the array substrate further includes: a fourth compensation trace C4; one end of the fourth compensation trace C4 is electrically connected to the end of the second sub-section 12 facing the terminal P, and the other end is electrically connected to the terminal P; the fourth compensation trace C4 is formed from the same layer and material as the third sub-section 13. In the disclosed embodiment, the fourth compensation trace C4 can be configured as a proximal common compensation trace near the terminal P of the display panel, compensating for the common voltage signal of the common trace near the terminal P to maintain the stability of the common voltage of the display panel.

[0065] In a possible embodiment, in combination with Figures 2 and 3A-3C, the array substrate further includes: a first compensation trace C1; the first compensation trace C1 is located on a side of the first common trace 1 away from the display area AA, and one end is electrically connected to the intersection of the first sub-section 11 and the second sub-section 12; the first compensation trace C1 and the first sub-section 11 are in the same layer and material. In the embodiment of the present disclosure, the array substrate also includes: a first compensation trace C1, one end of the first compensation trace C1 is electrically connected to the intersection of the first sub-section 11 and the second sub-section 12, and can serve as a remote common compensation trace away from the terminal P of the display panel and electrically connected to the top corner of the display panel, to compensate for the common voltage of the common trace away from the terminal P, and maintain the stability of the remote common voltage of the display panel; moreover, the first compensation trace C1 is on the same layer and the same material as the first sub-section 11, that is, it can be located on the same layer as the data line, and is directly electrically connected to the first common trace 1, avoiding the overall reduction of the common trace resistance when electrically connected through a via, thereby improving the recovery and conduction capability of the panel common signal, and improving problems such as afterimage and crosstalk.

[0066] In one possible embodiment, as shown in Figures 3A and 3C , the array substrate further includes: a first lead Y1; the other end of a first compensation trace C1 is electrically connected to one end of the first lead Y1, and the other end of the first lead Y1 is electrically connected to a terminal. The first lead Y1 and the first compensation trace C1 are located on different layers. Specifically, the first compensation trace C1 can be located on the layer where the data lines reside, and the first lead Y1 can be located on the layer where the gate lines reside. That is, the first compensation trace C1 switches layers to the gate line layer to achieve electrical connection with the corresponding terminal, thereby providing a signal to the first compensation trace C1 through the terminal.

[0067] In a possible implementation, the first compensation trace C1 may be directly electrically connected to the first lead Y1 at an overlapping position through a via.

[0068] In a possible embodiment, in combination with Figure 2, the first sub-section 11 includes: a first position E1; a length a1 between the first position E1 and the end of the first sub-section 11 is one-fifth to one-third of the length a2 of the first sub-section 11 in the first direction X; optionally, the length a1 between the first position E1 and the end of the first sub-section 11 is one-quarter of the length a2 of the first sub-section 11 in the first direction X; the array substrate also includes: a second compensation trace C2; ​​the second compensation trace C2 is located on a side of the first compensation trace C1 away from the display area; one end of the second compensation trace C2 is electrically connected to the first position E1; the second compensation trace C2 is on the same layer and material as the first sub-section 11. In the embodiment of the present disclosure, the array substrate further includes: a second compensation trace C2; ​​one end of the second compensation trace C2 is electrically connected to a point one-quarter the length of the first sub-portion 11 (which can also be regarded as a point one-quarter the position of the display panel along the first direction X), and can serve as a remote common compensation trace of the display panel away from the terminal P and at a point one-quarter the position of the display panel in the first direction X, to compensate for the common voltage of the common trace away from the terminal P and maintain the stability of the remote common voltage of the display panel; moreover, the second compensation trace C2 is on the same layer and material as the first sub-portion 11, that is, it can be located on the same layer as the data line, and can be directly electrically connected to the first common trace 1. Compared with the conventional display panel shown in Figure 1, the two horizontal common traces O2 at the upper end of the display area AA need to be conductively connected through vias and a transfer structure. In the embodiment of the present disclosure, the second compensation trace C2 can be directly contacted and electrically connected to the first sub-portion 11, avoiding the overall reduction in resistance of the common trace when electrically connected through vias, thereby improving the recovery and conductivity of the panel common signal, and improving problems such as afterimage and crosstalk.

[0069] In a possible embodiment, in combination with Figures 3A and 3C, the array substrate further includes: a second lead Y2; the other end of the second compensation trace C2 is electrically connected to one end of the second lead Y2; the other end of the second lead Y2 is electrically connected to the terminal P, and the second lead Y2 and the second compensation trace C2 are located in different layers. Specifically, the second compensation trace C2 can be located in the layer where the data line is located, and the second lead Y2 can be located in the layer where the gate line is located, that is, the second compensation trace C2 is electrically connected to the corresponding terminal by changing layers to the gate line layer, so as to provide a signal to the second compensation trace C2 through the terminal.

[0070] In a possible implementation, the second compensation trace C2 may be directly electrically connected to the second lead Y2 at an overlapping position through a via.

[0071] In a possible embodiment, in combination with Figure 2, the second sub-section 12 includes: a second position E2; the length b1 between the second position E2 and the end of the second sub-section 12 is one-quarter to three-quarters of the length b2 of the second sub-section 12 in the second direction Y; optionally, the length b1 between the two positions E2 and the end of the second sub-section 12 is one-half of the length b2 of the second sub-section 12 in the second direction Y; the array substrate also includes: a third compensation trace C3; the third compensation trace C3 is located between the first compensation trace C1 and the first common trace 1; one end of the third compensation trace C3 is electrically connected to the second position E2, and the other end of the third compensation trace C3 is electrically connected to the terminal P; the third compensation trace C3 is on the same layer and material as the first sub-section 11. In the embodiment of the present disclosure, the array substrate also includes: a third compensation trace C3; one end of the third compensation trace C3 is electrically connected to a position half the length of the second sub-section 12 (which can also be regarded as a position half the length of the display panel along the second direction Y), and can serve as a common compensation trace at the center position of the second direction Y of the display panel, compensating for the common voltage of the common trace at the center position of the second direction Y of the display panel, and maintaining the stability of the common voltage at the far end of the display panel; moreover, the third compensation trace C3 is on the same layer and the same material as the first sub-section 11, that is, it can be located on the same layer as the data line, and can be directly electrically connected to the first common trace 1, avoiding the overall reduction of the common trace resistance when electrically connected through a via, thereby improving the recovery and conduction capability of the panel common signal, and improving problems such as afterimage and crosstalk.

[0072] In a possible embodiment, in combination with Figure 2, the second sub-section 12 includes: a third position E3; the length b3 between the third position E3 and the end of the second sub-section 12 close to the terminal side is one-seventh to one-fifth of the length b2 of the second sub-section 12 in the second direction Y; optionally, the length b3 between the third position E3 and the end of the second sub-section 12 close to the terminal side is one-sixth of the length b2 of the second sub-section 12 in the second direction Y; the array substrate also includes: a first detection trace F1; the first detection trace F1 is located between the first compensation trace C1 and the third compensation trace C3; one end of the first detection trace F1 is electrically connected to the third position E3; the first detection trace F1 is on the same layer and made of the same material as the first sub-section 11. In the embodiment of the present disclosure, the array substrate also includes: a first detection trace F1; one end of the first detection trace F1 is electrically connected to one-sixth of the length of the second sub-section 12 (which can also be regarded as one-sixth of the position of the display panel along the second direction Y), which can be used as a display panel detection feedback trace, and can detect the actual common voltage signal of the display panel and feed it back to the processing component of the display panel (for example, IC). After receiving this signal, the processing component will make a corresponding compensation signal (through each common compensation trace) to supply to the display panel to ensure the stability of the common voltage of the entire display panel; moreover, the first detection trace F1 is on the same layer and material as the first sub-section 11, that is, it can be located on the same layer as the data line, and can be directly electrically connected to the first common trace 1, avoiding the overall reduction of the common trace resistance when electrically connected through a via, thereby improving the recovery and conduction capability of the panel common signal, and improving problems such as afterimage and crosstalk.

[0073] In a possible embodiment, in combination with Figures 3A and 3C, the array substrate further includes: a third lead Y3; one end of the first detection trace F1 is electrically connected to one end of the third lead Y3; the other end of the third lead Y3 is electrically connected to the terminal P, and the third lead Y3 and the first detection trace F1 are located on different layers. Specifically, the first detection trace F1 can be located on the layer where the data line is located, and the third lead Y3 can be located on the layer where the gate line is located, that is, the first detection trace F1 is electrically connected to the corresponding terminal by changing layers to the gate line layer.

[0074] It can be understood that the first lead Y1, the second lead Y2, and the third lead Y3 can be electrically connected to different terminals respectively to obtain different signals.

[0075] In one possible embodiment, as shown in Figures 3A-3C , the array substrate further includes a plurality of first electrostatic protection units ESD1 located between the first sub-portion 11 and the display area AA, with at least one of the plurality of first electrostatic protection units ESD1 electrically connected to the second sub-portion 12. This prevents static electricity between the first common trace 1 and the display area AA from affecting traces in the display area AA.

[0076] Specifically, one end of the first electrostatic protection unit ESD1 is electrically connected to the data line of the display area AA, and the other end is electrically connected to the first common wiring 1. A second common wiring 2 portion is provided between two adjacent first electrostatic protection units ESD1 for electrically connecting to the first common wiring 1.

[0077] In one possible embodiment, in combination with Figures 3A-3C, the array substrate further includes: a plurality of data lines extending along the second direction Y (not shown in the figures), a fan-out lead group 4 located in the binding area DP, and a plurality of second electrostatic protection units ESD2; the fan-out lead group 4 includes a plurality of fan-out leads, and the fan-out leads are electrically connected to the data lines accordingly. Specifically, the fan-out leads can be electrically connected to the data lines one by one; the plurality of second electrostatic protection units ESD2 are located between the third sub-section 13 and the fan-out lead group 4, and at least one of the plurality of second electrostatic protection units ESD2 is electrically connected to the third sub-section 13. In this way, static electricity between the first common trace 1 and the display area AA is prevented from affecting the traces of the display area AA.

[0078] Specifically, the second electrostatic protection unit ESD2 is electrically connected to the data line of the display area.

[0079] In one possible embodiment, in combination with what is shown in FIG3A , the display panel provided by the embodiment of the present disclosure may further include a gate drive circuit GOA; in one possible embodiment, the first compensation trace C1, the second compensation trace C2, and the first detection trace F1 may be located on a side of the gate drive circuit GOA away from the display area AA, and the second sub-portion 12 and the third compensation trace C3 may be located on a side of the gate drive circuit GOA close to the display area AA.

[0080] In a possible embodiment, in combination with Figures 3A and 3C, the array substrate may further include a plurality of drive traces G1 extending along the second direction Y and electrically connected to the gate drive circuit GOA, a plurality of fourth leads Y4 extending along the first direction X, and a plurality of third electrostatic protection units ESD3; at least some of the drive traces G1 may be electrically connected to the third electrostatic protection unit ESD3 through the fourth leads Y4 to achieve anti-static protection for the drive traces G1.

[0081] Optionally, the fourth lead line Y4 may be provided in the same layer and material as the common electrode; optionally, the fourth lead line Y4 may also be provided in the same layer and material as the pixel electrode.

[0082] In a possible implementation, at least one of the first compensation trace C1 , the second compensation trace C2 , the third compensation trace C3 , the fourth compensation trace C4 , and the first detection trace F1 may also be electrically connected to the corresponding electrostatic protection unit through the corresponding fourth lead Y4 .

[0083] Based on the same inventive concept, an embodiment of the present disclosure further provides a display panel, which includes the array substrate provided in the public embodiment.

[0084] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which includes a display panel provided by the embodiment of the present disclosure.

[0085] Based on the same inventive concept, an embodiment of the present disclosure further provides a display panel, which includes the array substrate provided in the public embodiment.

[0086] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which includes a display panel provided by the embodiment of the present disclosure.

[0087] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0088] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An array substrate comprising a display area, a binding area located outside the display area, and a binding opposite side area opposite to the binding area, wherein: The array substrate includes: substrate; a plurality of terminals located in the bonding area on one side of the substrate; A first common wiring is located on one side of the substrate, the first common wiring is arranged around the display area, and at least includes: a first sub-portion located in the binding opposite side area and extending along a first direction; a plurality of second common lines located on one side of the substrate, the plurality of second common lines extending along a second direction from the display area to the opposite binding area, crossing the first sub-portion, the second direction crossing the first direction; The first sub-section and the plurality of second common traces are located on the same layer and are directly electrically connected at the intersection.

2. The array substrate according to claim 1, wherein: The array substrate further includes: a plurality of data lines; the data lines and the second common lines are alternately arranged along the first direction; The first sub-portion and the data line are formed in the same layer and made of the same material.

3. The array substrate according to claim 1 or 2, wherein: The first common trace further includes: a second sub-portion extending along the second direction, and a third sub-portion extending along the first direction; the second sub-portion is located outside the display area, and the third sub-portion is located in the binding area; The second sub-section and the first sub-section are located in the same layer and are electrically connected at an intersection; the third sub-section and the second sub-section are located in different layers and are electrically connected at the intersection through a via.

4. The array substrate according to claim 3, wherein: The array substrate further includes: a first compensation line; the first compensation line is located on a side of the first common line away from the display area, and one end of the first compensation line is electrically connected to an intersection of the first sub-section and the second sub-section; The first compensation trace and the first sub-section are formed on the same layer and made of the same material.

5. The array substrate according to claim 4, wherein: The array substrate further includes: a first lead; the other end of the first compensation line is electrically connected to one end of the first lead, and the other end of the first lead is electrically connected to the terminal; the first lead and the first compensation line are located in different layers.

6. The array substrate according to any one of claims 3 to 5, wherein: The first sub-section includes: a first position; a length between the first position and the end of the first sub-section is one fifth to one third of the length of the first sub-section in the first direction; The array substrate further includes: a second compensation trace; the second compensation trace is located on a side of the first compensation trace away from the display area; one end of the second compensation trace is electrically connected to the first position; The second compensation trace is formed on the same layer and made of the same material as the first sub-section.

7. The array substrate according to claim 6, wherein: The array substrate further includes: a second lead; The other end of the second compensation trace is electrically connected to one end of the second lead; the other end of the second lead is electrically connected to the terminal; the second lead and the second compensation trace are located in different layers.

8. The array substrate according to any one of claims 3 to 7, wherein: The second sub-section includes: a second position; a length between the second position and the end of the second sub-section is one quarter to three quarters of the length of the second sub-section in the second direction; The array substrate further includes: a third compensation trace; the third compensation trace is located between the first compensation trace and the first common trace; one end of the third compensation trace is electrically connected to the second position, and the other end of the third compensation trace is electrically connected to the terminal; The third compensation trace is formed on the same layer and made of the same material as the first sub-section.

9. The array substrate according to any one of claims 3 to 7, wherein: The array substrate further includes: a fourth compensation trace; one end of the fourth compensation trace is electrically connected to the end of the second sub-section facing the terminal, and the other end is electrically connected to the terminal; the fourth compensation trace is in the same layer and material as the third sub-section.

10. The array substrate according to claim 8 or 9, wherein: The second sub-section includes: a third position; the length between the third position and the end portion of the second sub-section close to the terminal is one seventh to one fifth of the length of the second sub-section in the second direction; The array substrate further includes: a first detection line; the first detection line is located between the first compensation line and the third compensation line; one end of the first detection line is electrically connected to the third position; The first detection trace and the first sub-unit are formed on the same layer and made of the same material.

11. The array substrate according to claim 10, wherein: The array substrate further includes: a third lead; One end of the first detection line is electrically connected to one end of the third lead; the other end of the third lead is electrically connected to the terminal; and the third lead and the first detection line are located in different layers.

12. The array substrate according to any one of claims 3 to 11, wherein: The array substrate further includes: a plurality of first electrostatic protection units; The plurality of first electrostatic protection units are located between the first sub-portion and the display area, and at least one of the plurality of first electrostatic protection units is electrically connected to the second sub-portion.

13. The array substrate according to any one of claims 3 to 12, wherein: The array substrate further includes: a plurality of data lines extending along the second direction, a fan-out lead group located in the binding area, and a plurality of second electrostatic protection units; the fan-out lead group includes a plurality of fan-out leads, and the fan-out leads are electrically connected to the data lines respectively; The plurality of second electrostatic protection units are located between the third sub-portion and the fan-out lead group, and at least one second electrostatic protection unit among the plurality of second electrostatic protection units is electrically connected to the third sub-portion.

14. A display panel, wherein: The invention comprises an array substrate as described in any one of claims 1 to 13.

15. A display device, wherein: Comprising the display panel as claimed in claim 14.

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