Method for processing surface of cavity on silicon substrate

Abstract

The invention discloses a method for processing the surface of a cavity on a silicon substrate, which belongs to the technical field of semiconductor manufacturing and micro electro mechanical systems, and comprises the following steps of: forming a central hole distribution area and an edge hole-free area on the surface of a silicon wafer by using a hard mask and an etching process; placing the isolation pad between the edge non-hole areas of the two silicon wafers, and aligning the central hole distribution areas of the two silicon wafers to form a silicon wafer-isolation pad-silicon wafer stacked structure; the isolation pad does not shield the central hole flow channel; and placing the stacked silicon wafers and the isolation pad in a hydrogen atmosphere for annealing treatment to form a uniform cavity. According to the invention, the defects of many surface defects, high roughness and poor process stability of the silicon substrate cavity caused by the edge effect of the hydrogen flow field in the existing SON process are overcome, the optimized hydrogen flow channel is formed through wafer stacking, the hydrogen density distribution is improved, the reaction probability of oxygen atoms and silicon atoms is reduced, and the stable preparation of the high-quality and high-consistency cavity is realized.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor manufacturing and microelectromechanical systems (MEMS) technology, and specifically relates to a method for surface treatment of cavities on a silicon substrate. Background Technology

[0002] In the fabrication of semiconductor and micro-electro-mechanical systems (MEMS) devices, uniform cavity structures within silicon substrates are key to achieving lightweight devices, low parasitic capacitance, and high insulation, and are widely used in products such as RF switches, micro-resonators, and pressure sensors. Currently, the technology for fabricating silicon substrate cavities based on the SON (Silicon On Nothing) process has been extensively studied. Its core principle is: after etching dense holes on the silicon wafer surface, it is annealed in a low-pressure, high-temperature pure hydrogen atmosphere. Driven by the surface diffusion and surface tension of silicon atoms at high temperatures, the sidewalls of adjacent holes gradually migrate and merge, ultimately forming a continuous, flat buried cavity. This method avoids the interface defects and thickness unevenness problems caused by the traditional "bonding before thinning" process. Theoretically, large-area cavity fabrication can be completed in one step within a single wafer, thus it is considered the most promising mass production route. However, as the process scales up to 200mm and larger wafers and enters the batch verification stage, the inherent defects of the SON annealing step have gradually become apparent.

[0003] First, the asymmetrical layout of the gas inlet and outlet of the annealing furnace cavity leads to a viscous-transitional flow state of hydrogen under low pressure, which easily creates a flow field distribution of "high-speed zone at the edge and low-speed zone in the center" on the wafer surface. The low hydrogen density at the edge weakens the ability to "scour" and dilute residual oxygen atoms, allowing free oxygen to penetrate the boundary layer and combine with silicon surface atoms to form silicon oxide or silicon-oxygen crystals, resulting in irreparable defects such as pitting and haze within a 3-5mm radius at the edge. Second, these oxygen-induced particles cannot be completely decomposed during subsequent high-temperature migration; instead, they act as pinning points, hindering further diffusion of silicon atoms. This leads to protrusions, pinholes, and irregular grains on the upper and lower surfaces of the cavity, causing the surface roughness Ra of the cavity to generally exceed 50nm, far exceeding the stringent requirement of ≤10nm for interface flatness in devices such as RF switches and resonators. This directly causes increased parasitic resistance, resonant frequency drift, and other deterioration in electrical and mechanical properties. More importantly, the aforementioned edge effects are amplified by minute fluctuations in the hydrogen flow field, resulting in a cavity thickness uniformity deviation of over 15% within a single wafer, batch-to-batch repeatability of less than 60%, and yield that can only be maintained at 60%-70%, which cannot meet the requirements of large-scale mass production and a stable yield of over 90%. Furthermore, once there is a momentary disturbance in the furnace pressure, hydrogen flow rate, or temperature, edge defects will rapidly expand towards the center, causing the entire wafer to be scrapped. The process window is extremely narrow, making it difficult to meet the needs of large-scale mass production. Summary of the Invention

[0004] The purpose of this invention is to provide a method for treating the cavity surface on a silicon substrate to improve the surface quality of the cavity on the silicon substrate.

[0005] The objective of this invention can be achieved through the following technical solutions: This application provides a method for surface treatment of cavities on a silicon substrate, comprising the following steps: Hard masks and etching processes are used to form a central hole distribution area and an edge-free hole area on the surface of a silicon wafer. A spacer is placed between the non-porous areas at the edges of two silicon wafers, and the central hole distribution areas of the two silicon wafers are aligned to form a silicon wafer-spacer-silicon wafer stacked structure; the thickness of the spacer is 1-4mm, and the spacer does not block the flow channel of the central hole; The stacked silicon wafers and spacers are annealed in a hydrogen atmosphere to form uniform cavities.

[0006] In some possible implementations, alignment is achieved using an infrared alignment device, with the positional deviation of the holes in the hole distribution areas of the two silicon wafers ≤1μm.

[0007] In some possible implementations, the septum has a temperature tolerance of ≥1200°C.

[0008] In some possible implementations, the septum is an annular graphite septum.

[0009] In some possible implementations, the aspect ratio of the holes in the central hole distribution area is 3-9.5, and the spacing is 0.5-2μm.

[0010] The shape is circular (diameter 1-5μm) or square (side length 1-5μm).

[0011] In some possible implementations, the silicon wafer is a 6-8 inch P-type monocrystalline silicon wafer; the thickness of the silicon wafer is 500-750 μm.

[0012] In some possible implementations, the etching is performed using an ICP (Inductively Coupled Plasma) etching process, with the etching gas being a mixture of SF6 and C4F8, and the etching depth being 5-20 μm.

[0013] The preferred flow rate ratio of SF6 to C4F8 is 3:1.

[0014] In some possible implementations, the hard mask is silicon oxide or silicon nitride with a thickness of 1-2 μm, deposited using a plasma-enhanced chemical vapor deposition (PECVD) process.

[0015] In some possible implementations, the annealing conditions are: temperature 1150℃, pressure 10 torr, hydrogen flow rate 5 slm-30 slm, and holding time 10 min.

[0016] In some possible implementations, the annealing heating rate is 5-10℃ / min, the cooling rate is 3-5℃ / min, and the annealing furnace is first evacuated to a vacuum of 1×10⁻⁶. -3 For temperatures below torr, hydrogen purity ≥ 99.999% and replacement time ≥ 5 min.

[0017] The beneficial effects of this invention are: The present invention provides a method for surface treatment of cavities on silicon substrates, which is applicable to the fabrication of uniform cavities in high-precision silicon-based devices (such as radio frequency MEMS devices, power devices, sensors, etc.), and can significantly improve the surface quality of cavities to meet the high-performance requirements of devices.

[0018] The process of this invention breaks through the technical bottleneck of the existing SON process by optimizing the hydrogen flow field distribution, reducing oxygen-induced defects, and improving the cavity surface quality. It optimizes the hydrogen flow field and eliminates edge effects: through the 1-4mm narrow flow channel formed by stacking two wafers, the hydrogen gas is transformed from "non-uniform turbulence" to "uniform laminar flow". The influence range of the non-uniform hydrogen flow field is reduced from the 20mm edge area of ​​a single wafer to within 3mm, and the flow field uniformity is improved by more than 80%.

[0019] The process of this invention increases hydrogen density and suppresses oxygen-induced defects: the hydrogen flow rate in the narrow channel increases due to the reduced channel cross-sectional area (the flow rate is increased to 3-5 times that of the single-wafer process), the hydrogen molecule collision frequency increases, and the local hydrogen density increases by 40%-60%, effectively preventing free oxygen atoms from contacting the silicon surface, and reducing the oxygen-induced defect density from 1×10 4 cm -2 Reduced to 5×10 2 cm -2 the following.

[0020] The process of this invention significantly improves the surface roughness of the cavity: after reducing oxygen-induced defects, irregular structures such as protrusions and pinholes on the cavity surface are greatly reduced. Through AFM (atomic force microscopy) testing, the surface roughness (Ra) of the cavity is reduced from 50-80nm in the existing process to below 8nm, which meets the stringent requirements of high-precision devices for surface flatness.

[0021] The process of this invention improves process stability and yield: the improved flow field uniformity and hydrogen protection effect reduce the cavity quality difference in different regions of the same wafer to within 5%, and increase the batch device yield from 60%-70% to over 95%, thereby reducing the cost of large-scale mass production.

[0022] The invention has strong process compatibility: the equipment used (ICP etching machine, high temperature annealing furnace) are all mature equipment in the semiconductor industry, and no new special equipment is required. It can be directly integrated into the existing SON process production line, which is easy to promote industrialization.

[0023] This invention overcomes the shortcomings of existing SON processes, such as numerous defects, high roughness, and poor process stability of silicon substrate cavities caused by the edge effect of hydrogen flow field. By stacking wafers to form optimized hydrogen flow channels, it improves hydrogen density distribution, reduces the probability of reaction between oxygen atoms and silicon atoms, and achieves stable fabrication of high-quality, highly consistent cavities. Attached Figure Description

[0024] The invention will now be further described with reference to the accompanying drawings.

[0025] Figure 1 This is a cross-sectional view of the silicon wafer-spacer-silicon wafer stacked structure in Embodiment 1 of the present invention; Figure 2 This is a cross-sectional view of the cavity in the silicon substrate after annealing in Embodiment 1 of the present invention; Figure 3 This is a surface morphology diagram of the cavity formed after annealing in Embodiment 1 of the present invention; Figure 4 This is a flow field distribution diagram formed on the surface of a single wafer in Comparative Example 1 of the present invention; Figure 5 This is a surface morphology diagram of the cavity formed after annealing in Comparative Example 1 of the present invention.

[0026] Figure 1 In the middle, 1. the area without holes at the edge; 2. the area with holes in the center; 3. the septum. Detailed Implementation

[0027] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0028] Obviously, the following description is merely some examples or embodiments of this application. Those skilled in the art can apply this application to other similar scenarios without any inventive effort. Furthermore, it is understood that although the effort involved in such development may be complex and lengthy, for those skilled in the art related to the content disclosed in this application, any changes to design, manufacturing, or production based on the technical content disclosed in this application are merely conventional technical means and should not be construed as insufficient disclosure of the content of this application.

[0029] However, there may be instances where unnecessary detailed descriptions are omitted. For example, detailed descriptions of well-known matters or repetitive descriptions of essentially the same structure may be omitted. This is to avoid making the following description unnecessarily lengthy and to facilitate understanding by those skilled in the art. Furthermore, the following description is provided to enable those skilled in the art to fully understand this application and is not intended to limit the subject matter of the claims.

[0030] Unless otherwise specified, all embodiments and optional embodiments of this application can be combined to form new technical solutions, and all technical features and optional technical features of this application can be combined to form new technical solutions.

[0031] The following is a detailed description of the embodiments of this application.

[0032] In the embodiments and comparative examples of this invention, the silicon wafers are pretreated before the hard mask and etching processes: the semiconductor industry standard wet cleaning process (RCA standard cleaning process) is used to remove organic matter, metallic impurities and natural oxide layer from the surface of the silicon wafer: SC-1: NH4OH:H2O2:H2O=1:1:5 to 1:2:7, temperature 75℃; SC-2: HCl:H2O2:H2O=1:1:6 to 1:2:8, temperature 75℃.

[0033] This application provides a method for surface treatment of cavities on a silicon substrate, including the following steps: Step 1: Using a hard mask and etching process, a central hole distribution region 2 and an edge hole-free region 1 are formed on the surface of the silicon wafer; The second step is to place the spacer 3 between the non-porous areas 1 at the edges of the two silicon wafers, aligning the central hole distribution areas 2 of the two silicon wafers to form a silicon wafer-spacer-silicon wafer stacked structure; the thickness of the spacer 3 is 1-4mm, and the spacer 3 does not block the flow channel of the central hole; The third step is to place the stacked silicon wafers and spacers 3 in a hydrogen atmosphere for annealing to form a uniform cavity.

[0034] In some possible embodiments, the holes in the central hole distribution area 2 of the two silicon wafers are aligned by an infrared alignment device, and the hole position deviation is ≤1μm.

[0035] In some possible embodiments, the spacer 3 has a temperature resistance ≥1200℃ and is chemically inert, not reacting with silicon or hydrogen. The spacer 3 does not need to completely cover the non-porous area, and the shape of the spacer 3 is not necessarily annular; it can be two or more pieces, and is not necessarily a single piece.

[0036] In some possible embodiments, the septum 3 is an annular graphite septum.

[0037] In some possible embodiments, the aspect ratio of the holes in the central hole distribution area 2 is 3-9.5, and the spacing is 0.5-2μm.

[0038] The holes are circular (diameter 1-5μm) or square (side length 1-5μm), with a depth-to-width ratio (hole depth / hole diameter) controlled between 3 and 9.5, and the hole spacing (center-to-center distance between adjacent holes) between 0.5 and 2μm.

[0039] In some possible embodiments, the silicon wafer is a 6-8 inch P-type monocrystalline silicon wafer; the thickness of the silicon wafer is 500-750 μm.

[0040] In some possible embodiments, the etching employs an ICP (Inductively Coupled Plasma) etching process, using a mixture of SF6 and C4F8 as the etching gas, with an etching depth of 5-20 μm. The radio frequency power is 2000-3000W to ensure that the aperture distribution range perfectly matches the area of ​​the cavity to be formed subsequently.

[0041] The preferred flow rate ratio of SF6 to C4F8 is 3:1.

[0042] In some possible embodiments, the hard mask is silicon oxide or silicon nitride with a thickness of 1-2 μm, deposited using plasma-enhanced chemical vapor deposition (PECVD). The hard mask layer is removed using a wet etching process (HF buffer solution for silicon oxide masks, and hot phosphoric acid solution for silicon nitride masks) to obtain a silicon wafer with densely packed holes on its surface.

[0043] In some possible embodiments, the annealing conditions are: temperature 1150°C, pressure 10 torr, hydrogen flow rate 5-30 slm, and holding time 10 min. The stacked silicon wafers and spacers 3 are placed on a graphite carrier in a silicon epitaxial furnace or high-temperature annealing furnace, ensuring that the stacked structure is centered and avoids proximity to the furnace wall or gas inlet / outlet.

[0044] In some possible embodiments, the annealing heating rate is 5-10°C / min, the cooling rate is 3-5°C / min, and the furnace is first evacuated to a vacuum of 1×10⁻⁶. -3 For temperatures below torr, hydrogen purity ≥ 99.999% and replacement time ≥ 5 min.

[0045] In a high-temperature hydrogen environment, silicon atoms diffuse along the surface of the pores and, driven by surface tension, the dense pores gradually merge. At the same time, the 1-4mm narrow flow channel between the two silicon wafers allows hydrogen to form a stable "laminar flow," uniformly covering all pore areas, ultimately forming a smooth, uniform cavity structure without obvious defects. After annealing, the temperature is reduced to room temperature at a rate of 3-5℃ / min to prevent deformation of the cavity structure.

[0046] The following is a detailed description with reference to specific examples.

[0047] Example 1

[0048] This embodiment provides a method for surface treatment of cavities on a silicon substrate, including the following steps: Step 1: Using a hard mask and etching process, create a central hole distribution area and an edge-free hole area on the silicon wafer surface: An 8-inch P-type monocrystalline silicon wafer with a thickness of 675μm and a resistivity of 0.1-5Ω was selected. cm; Hard mask: PECVD deposition of 1.5μm Si A window is formed by applying adhesive, exposing, and developing the material; ICP etching: The etching gas is a mixture of SF6 and C4F8 with a flow rate ratio of 3:1, a power of 2000-3000W, and an etching depth of 9μm, forming dense circular holes (1-5μm in diameter) with an aspect ratio of 4. Mask removal: using HF:N Si was removed by soaking in a buffer solution with an F=1:6 concentration at room temperature for 5 minutes. Mask, to obtain the silicon wafer to be annealed; The second step involves placing a graphite spacer between the non-porous areas at the edges of two silicon wafers, aligning the central porous areas of the two wafers to form a silicon wafer-spacer-wafer stacked structure. A cross-sectional diagram of this silicon wafer-spacer-wafer stacked structure is shown below. Figure 1 As shown; the thickness of the graphite spacer is 4mm, and the spacer does not block the flow channel of the central hole; the positional deviation of the holes in the hole distribution area of ​​the two silicon wafers is ≤1μm; The third step involves annealing the stacked silicon wafers and spacers in a hydrogen atmosphere to create uniform cavities. An ASM Epsilon 2000 silicon epitaxial furnace was used. Vacuum replacement was performed, with the vacuum level set to 5×10⁻⁶.-4 The torr process involves purging with 99.999% hydrogen three times, with each purging lasting 5 minutes. Heating: 8℃ / min to 1150℃; Annealing: 1150℃, 10 torr, 10 SLM hydrogen, hold for 10 min; Cooling: 4℃ / min to room temperature; See the cross-sectional view of the silicon substrate cavity after annealing. Figure 2 As shown; see the surface morphology diagram of the cavity formed after annealing. Figure 3 As shown, the cavity has a high degree of flatness.

[0049] Example 2

[0050] This embodiment provides a method for surface treatment of cavities on a silicon substrate. Compared with Embodiment 1, the difference in this embodiment is that the etching depth is 20 μm, forming dense circular holes (diameter 1-5 μm) with an aspect ratio of 5. The remaining raw materials and preparation process are the same as in Embodiment 1, resulting in a silicon substrate with high cavity flatness.

[0051] Example 3

[0052] This embodiment provides a method for surface treatment of cavities on a silicon substrate. Compared with Embodiment 1, the difference in this embodiment is that the etching depth is 9 μm, forming dense square holes (side length 1-5 μm) with a depth-to-width ratio of 4. The remaining raw materials and preparation process are the same as in Embodiment 1, resulting in a silicon substrate with high cavity flatness.

[0053] Example 4

[0054] This embodiment provides a method for surface treatment of cavities on a silicon substrate. The difference between this embodiment and Embodiment 1 is that the hard mask is silicon oxide with a thickness of 1 μm, while the other raw materials and preparation process remain the same as in Embodiment 1, resulting in a silicon substrate cavity with high flatness.

[0055] Example 5

[0056] This embodiment provides a method for surface treatment of cavities on a silicon substrate. Compared with Embodiment 1, the difference in this embodiment is that the annealing conditions are: temperature 1150℃, pressure 10 torr, hydrogen flow rate 20 slm, and holding time 10 min. The remaining raw materials and preparation process are the same as in Embodiment 1, resulting in a silicon substrate with high cavity flatness.

[0057] Example 6

[0058] This embodiment provides a method for surface treatment of cavities on a silicon substrate. Compared with Embodiment 1, the difference in this embodiment is that the annealing conditions are: temperature 1150℃, pressure 10 torr, hydrogen flow rate 30 slm, and holding time 10 min. The other raw materials and preparation process are the same as in Embodiment 1, resulting in a silicon substrate with high cavity flatness.

[0059] Comparative Example 1

[0060] This comparative example provides a method for surface treatment of cavities on a silicon substrate. The difference between this comparative example and Example 1 is that the second step is not performed: single-piece annealing is performed without using graphite spacers.

[0061] A flow field distribution of "high-speed region at the edge and low-speed region at the center" is formed on the wafer surface. The low hydrogen density at the edge weakens the ability to "scour" and dilute residual oxygen atoms, allowing free oxygen to penetrate the boundary layer and combine with silicon surface atoms to form silicon oxide or silicon-oxygen crystals. This results in irreparable defects such as pitting and haze within a 3-5mm radius at the edge. See the flow field distribution diagram for the "high-speed region at the edge and low-speed region at the center" on a single wafer surface. Figure 4 As shown. See the surface morphology diagram of the cavity formed after annealing. Figure 5 As shown.

[0062] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0063] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for treating the surface of a cavity on a silicon substrate, characterized in that, Includes the following steps: Hard masks and etching processes are used to form a central hole distribution area and an edge-free hole area on the surface of a silicon wafer. A spacer is placed between the non-porous areas at the edges of two silicon wafers, and the central hole distribution areas of the two silicon wafers are aligned to form a silicon wafer-spacer-silicon wafer stacked structure; the thickness of the spacer is 1-4mm, and the spacer does not block the flow channel of the central hole; The stacked silicon wafers and spacers are annealed in a hydrogen atmosphere to form uniform cavities.

2. The method for cavity surface treatment on a silicon substrate according to claim 1, characterized in that, The positional deviation of the holes in the hole distribution area of ​​the two silicon wafers is ≤1μm.

3. The method for cavity surface treatment on a silicon substrate according to claim 1, characterized in that, The septum has a temperature tolerance of ≥1200℃.

4. The method for surface treatment of a cavity on a silicon substrate according to claim 1, characterized in that, The septum is a ring-shaped graphite septum.

5. The method for cavity surface treatment on a silicon substrate according to claim 1, characterized in that, The depth-to-width ratio of the holes in the central hole distribution area is 3-9.5, and the spacing is 0.5-2μm.

6. The method for cavity surface treatment on a silicon substrate according to claim 1, characterized in that, The silicon wafer is a 6-8 inch P-type monocrystalline silicon wafer; the thickness of the silicon wafer is 500-750μm.

7. The method for cavity surface treatment on a silicon substrate according to claim 1, characterized in that, The etching process employs ICP etching, with the etching gas being a mixture of SF6 and C4F8, and the etching depth being 5-20 μm.

8. The method for cavity surface treatment on a silicon substrate according to claim 1, characterized in that, The hard mask is made of silicon oxide or silicon nitride and has a thickness of 1-2 μm.

9. The method for cavity surface treatment on a silicon substrate according to claim 1, characterized in that, Annealing conditions: temperature 1150℃, pressure 10 torr, hydrogen flow rate 5 slm-30 slm, holding time 10 min.

10. The method for cavity surface treatment on a silicon substrate according to claim 1, characterized in that, The annealing heating rate is 5-10℃ / min, and the cooling rate is 3-5℃ / min. The annealing furnace is first evacuated to a vacuum of 1×10⁻⁶. -3 For temperatures below torr, hydrogen purity ≥ 99.999% and replacement time ≥ 5 min.

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