Resistance switching circuit and method for current sampling

Abstract

The invention belongs to the technical field of power equipment measurement, relates to a resistor switching circuit and method for current sampling, and aims to solve the problems that a traditional fixed sampling resistor cannot adapt to a wide current range (pA level to 2A or above), low-current measurement is distorted, high-current sampling voltage exceeds the upper limit of a single chip microcomputer, manual switching is needed, the efficiency is low, and sudden current change is easily caused. The circuit comprises a control signal module, a delay switching module and a resistance switching module. An external single-chip microcomputer outputs a K1 signal, the control module carries out reverse processing on the K1 signal and then transmits the K1 signal to the delay module, and after RC delay processing and feedback, the control module generates a driving signal again to drive the relay to switch a 10KOmega sampling resistor (for small current) and a 0.1 KOmega sampling resistor (for large current). According to the invention, automatic resistance switching is realized, the sampling precision in a total current range is guaranteed, the test efficiency is improved, current abrupt change is avoided, and the device is suitable for generator rotor external voltage withstanding tests.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of power equipment measurement, and particularly relates to a resistance switching circuit and method for current sampling. BACKGROUND

[0002] In the generator rotor related test, the external AC withstand voltage test is one of the core detection projects, and the current collection range of the test is usually 0-2A. The traditional scheme adopts a 1KΩ fixed sampling resistance. However, in actual testing, there are two accuracy pain points: one is in the small current scene (pA level), the sampling voltage value is seriously distorted due to the influence of system measurement error; the second is in the large current scene (more than 2A), the sampling voltage is easy to exceed the upper limit of the single-chip measurement, resulting in invalid data. The traditional scheme needs manual intervention to switch the resistance, which is not only low in efficiency, but also may cause current mutation due to improper switching time, affecting the safety of the test and the reliability of the data, so an intelligent and automatic resistance switching circuit is needed to solve the above problems. SUMMARY

[0003] The purpose of the present application is to provide a resistance switching circuit and method for current sampling, which is used to solve the problem that the traditional fixed sampling resistance cannot adapt to the pA level small current measurement distortion and the 2A or more large current sampling voltage exceeds the upper limit of the single-chip in the current sampling of the generator rotor external AC withstand voltage test and other high voltage tests, and the resistance needs to be manually switched, which has the hidden danger of low efficiency and easy to cause current mutation, and it is difficult to realize accurate, efficient and safe sampling in a wide current range.

[0004] In order to solve the above problems, the technical scheme of the present application is as follows: A resistance switching circuit for current sampling, comprising a control signal module circuit, a delay switching module circuit and a resistance switching module circuit; an external single-chip outputs a K1 signal to the control signal module circuit, the control signal module circuit outputs a K1_CK signal and a K1_CB signal to the delay switching module circuit after reversing the K1 signal once and twice respectively; the delay switching module circuit outputs an OUT_CK signal and an OUT_CB signal after delaying the K1_CK signal and the K1_CB signal, and feeds back to the control signal module circuit; the control signal module circuit outputs an OUT_CK* signal and an OUT_CB* signal after reversing the OUT_CK signal twice and the OUT_CB signal once; the OUT_CK signal is electrically connected with a relay S2 in the resistance switching module circuit, and the OUT_CB signal is electrically connected with a relay S1 in the resistance switching module circuit.

[0005] The element of the control signal module circuit is a 74hc14 chip, the K1 signal generated by the external single-chip microcomputer is connected to the 74hc14 chip, and the K1_CK signal is output once reversely, and the K1_CB signal is output twice reversely; the OUT_CK signal is connected to the 74hc14 chip, and the OUT_CK* signal is output twice reversely, and the OUT_CB signal is connected to the 74hc14 chip, and the OUT_CB* signal is output once reversely.

[0006] The delay switching module circuit comprises a capacitor C1, a capacitor C2, a resistor R1, a resistor R2 and a resistor R3; the capacitor C1 and the capacitor C2 are connected in parallel to form a parallel capacitor group, one end of the parallel capacitor group is connected to the resistor R1, the other end is connected to the resistor R3, and the other end of the resistor R3 is grounded; one end of the resistor R2 is connected to the connection node of the resistor R1 and the parallel capacitor group, and the other end is grounded; the other end of the resistor R1 is used as a signal input end to receive the K1_CK signal or the K1_CB signal, and the connection node of the parallel capacitor group and the resistor R3 is used as a signal output end to output the OUT_CK signal or the OUT_CB signal.

[0007] The resistor switching module circuit comprises a relay S1, a relay S2, a sampling resistor R9 and a sampling resistor R10; the initial state of the relay S1 is normally open, and the initial state of the relay S2 is normally open; the moving contact of the relay S1 is connected to one end of the sampling resistor R9, and the normally open contact is grounded; the moving contact of the relay S2 is connected to one end of the sampling resistor R10, and the normally open contact is grounded; the other ends of the sampling resistor R9 and the sampling resistor R10 are connected to a current sampling loop; the coil of the relay S1 is electrically connected to the OUT_CB* signal output end, and the coil of the relay S2 is electrically connected to the OUT_CK* signal output end.

[0008] The control signal module circuit and the delay switching module circuit share the same direct current power supply and the common ground end; the signal input end of the delay switching module circuit is connected in series with a current limiting resistor.

[0009] The external single-chip microcomputer is connected to the control signal module circuit through a TTL level interface; a driving resistor is connected in series between the OUT_CK* signal output end and the coil of the relay S2, and a driving resistor is connected in series between the OUT_CB* signal output end and the coil of the relay S1.

[0010] The application discloses a current sampling initial state setting method, which comprises the following steps: setting a K1 signal output by an external single-chip microcomputer as a low level; after a control signal module circuit receives the low level K1 signal, outputting a high level K1_CK signal and a low level K1_CB signal; after a delay switching module circuit receives the high level K1_CK signal, outputting a high level OUT_CK signal, and after receiving the low level K1_CB signal, outputting a low level OUT_CB signal; after the control signal module circuit reverses the high level OUT_CK signal twice, outputting a high level OUT_CK* signal, and after reversing the low level OUT_CB signal once, outputting a high level OUT_CB* signal; the high level OUT_CK signal and the OUT_CB signal drive relays S2 and S1 to be attracted, the 1 and 2 pins of the relay S1 are turned on, the 1 and 2 pins of the relay S2 are turned on, the sampling resistor R9 is grounded through the relay S1, and the sampling resistors R9 and R10 are in a parallel state.

[0011] The application discloses a small current sampling resistor switching method, which comprises the following steps: when the current in a sampling loop is smaller than a preset value, an external single-chip microcomputer switches a K1 signal from a low level to a high level; after a control signal module circuit receives the high level K1 signal, outputting a low level K1_CK signal and a high level K1_CB signal; in a delay switching module circuit, the K1_CK signal input end becomes a low level, the OUT_CK signal is delayed from a high level to a low level, the K1_CB signal input end becomes a high level, and the OUT_CB signal is changed from a low level to a high level; after the control signal module circuit reverses the delayed low level OUT_CK signal twice, outputting a delayed low level OUT_CK* signal, and after reversing the high level OUT_CB signal once, outputting a low level OUT_CB* signal; the low level OUT_CB signal drives the relay S1 to be released, the moving contact of the relay S1 is reset to a normally open state, the sampling resistor R9 is disconnected with a grounding end, and the R9 is suspended; the delayed low level OUT_CK signal drives the relay S2 to be delayed to be disconnected, and the sampling resistor R10 is suspended.

[0012] A kind of high current sampling resistance switching method, comprising the following steps: when the current in sampling loop is greater than preset value, external single-chip microcomputer switches K1 signal from high level to low level;Control signal module circuit receives low level K1 signal, and outputs high level K1_CK signal and low level K1_CB signal;K1_CB signal input end in delay switching module circuit becomes low level, OUT_CB signal delay changes from high level to low level, K1_CK signal input end becomes high level, and OUT_CK signal changes from low level to high level;Control signal module circuit outputs high level OUT_CK * signal after reversing high level OUT_CK signal twice, and outputs delay low level OUT_CB * signal after reversing delay low level OUT_CB signal once;High level OUT_CK signal drives relay S2 to attract, sampling resistance R10 is grounded by relay S2, and delay low level OUT_CB signal drives relay S1 to delay release, and sampling resistance R9 is suspended.

[0013] A kind of sampling voltage stabilization control method, comprising the following steps: the switching time difference of relay S1 and S2 is controlled by delay switching module circuit;According to the size of sampling current, the sampling resistance accessed to sampling loop is switched to R9 or R10;OUT_CK * signal, OUT_CB * signal are output by the 74hc14 chip of control signal module circuit to drive relay S2, S1 to act.

[0014] The beneficial effects of the present application are: 1. Ensure wide range current sampling accuracy: by adapting the large resistance sampling resistance of small current and the small resistance sampling resistance of large current to automatically switch, the sampling voltage corresponding to small current in small current scene can be released, and voltage distortion caused by system measurement error is avoided;In large current scene, the sampling voltage corresponding to large current can be limited to prevent exceeding the upper limit of single-chip microcomputer measurement, and finally realize accurate sampling of wide current range (including small current and large current), ensure reliable sampling data.

[0015] 2. Improve test automation efficiency: without manual intervention sampling resistance switching, external single-chip microcomputer can automatically trigger control signal according to the size of sampling current, drive relay to complete time sequence switching of resistance through the cooperative work of control signal module and delay switching module, save the operation of manual replacement of resistance by manual judgment of current range, simplify test process, shorten test cycle, especially suitable for batch test scene.

[0016] 3. Enhance switching stability and circuit safety: The delay switching module forms a reasonable switching time difference between the two relays through RC charge and discharge design, and there is a transient state of double resistance parallel during the resistance switching process, which avoids the current mutation caused by the sudden connection or disconnection of single resistance; at the same time, the signal shaping function of the control signal module can filter interference clutter, and the protection design of the relay drive end can prevent the damage of components caused by overcurrent, reduce the risk of circuit impact, and ensure the stability of the test process and the service life of the components.

[0017] 4. Strong scene adaptability: The core design meets the current sampling needs of the generator rotor external AC withstand voltage test, and without significantly adjusting the circuit structure, it can be extended to other high-voltage equipment (such as transformers, high-voltage switches, etc.) current sampling scenes, and has strong universality and promotion value. BRIEF DESCRIPTION OF DRAWINGS

[0018] The application will be further described below in combination with the drawings: Fig. 1 The control signal module circuit of the application is shown in the figure, Fig. 2 The delay switching module circuit of the application is shown in the figure Fig. 3 The resistance switching module circuit of the application is shown in the figure. DETAILED DESCRIPTION

[0019] The technical solutions in the embodiments of the application will be described clearly and completely below in combination with the drawings in the embodiments of the application. Obviously, the described embodiments are only part of the embodiments of the application, not all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the application.

[0020] As Figs. 1 to 3As shown, a resistance switching circuit for current sampling includes a control signal module circuit, a delay switching module circuit and a resistance switching module circuit; an external single-chip microcomputer outputs a K1 signal to the control signal module circuit through a TTL level interface, the control signal module circuit respectively performs once reverse, twice reverse on the K1 signal, and outputs a K1_CK signal and a K1_CB signal to the delay switching module circuit; the delay switching module circuit performs delay processing on the K1_CK signal and the K1_CB signal, and outputs an OUT_CK signal and an OUT_CB signal, and feeds back to the control signal module circuit; the control signal module circuit performs twice reverse on the OUT_CK signal, and performs once reverse on the OUT_CB signal, and outputs an OUT_CK* signal and an OUT_CB* signal, finally the OUT_CK signal is connected to a relay S2, and the OUT_CB signal is connected to a relay S1, the OUT_CK or the OUT_CB without "": belongs to "intermediate transition signal", is only used for feedback from the delay module to the control module, and does not directly participate in the control of the execution element (the relay); the OUT_CK or the OUT_CB with ": belongs to "final function signal", is an effective signal specially used for driving the relay after being shaped (reverse processing) by the control module, and directly determines the attraction / disconnection state of the relay S2 or the relay S1.

[0021] Through the closed-loop logic of "control signal generation-delay feedback-driving signal output-relay action", automatic switching of the sampling resistance is realized, different current scenes can be adapted without manual intervention, the problem that the traditional fixed resistance cannot cover a wide current range is solved, and the continuity of signal transmission and execution action is guaranteed by the cooperation of each module, and the sampling flexibility and reliability are improved.

[0022] The element of the control signal module circuit is a 74hc14 six inverter chip, a VCC pin of the chip is connected to a (5V) direct current power supply, and a GND pin is grounded; the K1 signal generated by the external single-chip microcomputer is connected to an input end (such as an A4 pin) of the 74hc14 chip, the K1_CK signal is output after once reverse, and the K1_CB signal is output after twice reverse, the feedback OUT_CK signal is output after twice reverse as the OUT_CK* signal, and the feedback OUT_CB signal is output after once reverse as the OUT_CB* signal. The 74hc14 chip has reverse and signal shaping functions, can filter interference and clutter in the K1 signal and the feedback signal, makes the output signal form a logic complement through differential reverse processing, provides a stable signal source for relay timing control, avoids relay misoperation caused by interference signals, ensures the accuracy of the driving signal, and lays a foundation for accurate control of the entire circuit.

[0023] The delay switching module circuit includes capacitors C1 and C2 (both are (10uF)), resistors R1 ((300Ω)), R2 ((1KΩ)) and R3 ((100KΩ)); C1 and C2 are connected in parallel, one end of which is connected to R1 and the other end is connected to R3 (the other end of R3 is connected to the ground), R2 is connected in parallel between the connection node of R1 and the parallel capacitor group and the ground, and the other end of R1 receives K1_CK / K1_CB signals, and the connection node of the parallel capacitor group and R3 outputs OUT_CK / OUT_CB signals. When the signal is high, the current charges C1 and C2 through R1, and the output end maintains a high level; when the signal becomes low, C1 and C2 are discharged through R2 and R3, and the output end voltage slowly decreases to realize delay and low, and the RC charging and discharging characteristics provide a relay switching time difference to avoid the sudden change of the sampling resistance caused by the simultaneous action of the two relays, ensure the continuity of the circuit switching process, and prevent current from suddenly changing.

[0024] The resistance switching module circuit includes relays S1 (initially open) and S2 (initially open), sampling resistors R9 ((10KΩ)) and R10 ((0.1KΩ)); the moving contact of relay S1 is connected to one end of R9, and the normally open contact is connected to the ground; the moving contact of relay S2 is connected to one end of R10, and the normally open contact is connected to the ground; the other ends of R9 and R10 are both connected to the sampling loop; the coil of relay S1 is connected to OUT_CB* signal, and the coil of relay S2 is connected to OUT_CK* signal (both coils are connected in series with a (200Ω) driving resistor). The level change of OUT_CK* and OUT_CB* signals controls the attraction and disconnection of the relays, high level drives attraction and low level drives disconnection, to realize the alternate connection of R9 and R10; R9 of 10KΩ is suitable for pA level small current to avoid measurement distortion caused by too small sampling voltage, R10 of 0.1KΩ is suitable for 2A or more large current to prevent the sampling voltage from exceeding the upper limit of the single-chip microcomputer measurement, and the driving resistor ensures the reliable action of the relay and prolongs the service life of the element.

[0025] The control signal module circuit and the delay switching module circuit share the same (5V) DC power supply and the common ground, and the signal input end of the delay switching module circuit is connected in series with a (300Ω) current limiting resistor. The common power supply and the common ground design ensure that the potentials of the two modules are consistent, avoid signal transmission abnormalities caused by potential difference, and prevent signal distortion; the current limiting resistor can limit the instantaneous current of the input signal, avoid damage to capacitors C1 and C2 caused by large current impact, and improve the overall stability of the circuit.

[0026] The external single-chip microcomputer and the control signal module circuit are connected through a TTL level interface, the OUT_CK* signal and the coil of the relay S2 are connected in series with a driving resistor (200 Ω), and the OUT_CB* signal and the coil of the relay S1 are connected in series with a driving resistor (200 Ω). The TTL level interface has the characteristics of strong anti-interference and stable transmission, which ensures the accurate transmission of the K1 signal and avoids interference and attenuation; the driving resistor can match the rated current demand of the relay coil, ensures that the relay obtains stable driving current, prevents the coil from being damaged due to excessive current, and ensures the reliability of the relay action.

[0027] In the embodiment, the element of the control signal module circuit is a 74hc14 hex inverter chip (the VCC pin is connected to a 5V direct-current power supply, and the GND pin is grounded), the capacitances C1 and C2 of the delay switching module circuit are both 10uF, the resistances R1, R2 and R3 are 300Ω, 1KΩ and 100KΩ respectively, the sampling resistances R9 and R10 of the resistance switching module circuit are 10KΩ and 0.1KΩ respectively, and the coils of the relays S1 and S2 are connected in series with a driving resistor (200 Ω).

[0028] The method specifically includes the following steps: S11. The K1 signal output by the external single-chip microcomputer is set to a low level, the single-chip microcomputer and the control signal module circuit are connected through a TTL level interface, and the low-level K1 signal is transmitted to the input end (such as the A4 pin) of the 74hc14 chip through the interface; S12. After the 74hc14 chip of the control signal module circuit receives the low-level K1 signal, the high-level K1_CK signal is output from the Y4 pin through the first internal inverter (corresponding to the A4-Y4 pin) after once reverse; at the same time, the high-level K1_CK signal is further connected to another input end (such as the A5 pin) of the 74hc14 chip, the low-level K1_CB signal is output from the Y5 pin through the second internal inverter (corresponding to the A5-Y5 pin) after twice reverse; S13. After the signal input end (the free end of the resistance R1) of the delay switching module circuit receives the high-level K1_CK signal, the current flows to the parallel capacitors C1 and C2 through R1, the parallel capacitor group is charged, the voltage between the parallel capacitor group gradually rises to a high level, and then the high-level OUT_CK signal is output from the connection node of the parallel capacitor group and R3; at the same time, the delay switching module circuit receives the low-level K1_CB signal, there is no charging process, and the low-level OUT_CB signal is directly output from the corresponding output node; S14. The 74hc14 chip of the control signal module circuit receives the high-level OUT_CK signal and inputs it into the input end (such as the A2 pin), and then the signal is reversed twice in turn by the internal two inverters (corresponding to the A2-Y1-Y2 pins) and output from the Y2 pin as the high-level OUT_CK* signal; at the same time, the 74hc14 chip receives the low-level OUT_CB signal and inputs it into the input end (such as the A3 pin), and then the signal is reversed once by the internal one inverter (corresponding to the A3-Y3 pin) and output from the Y3 pin as the high-level OUT_CB* signal; S15. The high-level OUT_CK signal is transmitted to the relay S2 coil through the 200Ω driving resistor in series, the relay S2 is attracted, and the 1 and 2 pins of the relay S2 are turned on; the high-level OUT_CB signal is transmitted to the relay S1 coil through the 200Ω driving resistor in series, the relay S1 is attracted, and the 1 and 2 pins of the relay S1 are turned on; at this time, one end of the sampling resistor R10 is grounded through the 1 and 2 pins of the relay S2, and the other end is connected to the current sampling loop, one end of the sampling resistor R9 is grounded through the 1 and 2 pins of the relay S1, and R9 and R10 are in parallel.

[0029] Through the above steps, the initial state of the circuit is set to the large-current sampling ready state, and the double-relay attraction logic triggered by the low-level K1 signal can make the small resistance R10 preferentially access the sampling loop, which is suitable for the large current scene commonly seen in the initial stage of the generator rotor withstand voltage test. Without manual configuration of the resistance and relay state, the test preparation time is shortened, and the pre-access of R10 can avoid the direct impact of the initial large current on the circuit components, reduce the risk of component damage, and ensure the safety and stability of the test start-up stage.

[0030] Embodiment 2: Small-current sampling resistor switching method, in this embodiment, the preset value of the sampling loop current is set to 100mA (adapted to the small-current and large-current demarcation requirement in the generator rotor withstand voltage test), the element parameters of the control signal module circuit, the delay switching module circuit and the resistance switching module circuit are consistent with those in the corresponding embodiment of claim 7 (the 74hc14 chip is powered by 5V, C1 / C2=10uF, R1=300Ω, R2=1KΩ, R3=100KΩ, R9=10KΩ, R10=0.1KΩ, and the relay coil is connected with a 200Ω driving resistor in series).

[0031] The method specifically includes the following steps: S21. The external single-chip microcomputer monitors the current in the sampling loop in real time through the current detection element (such as a current sensor) in the sampling loop, and when it is detected that the current in the sampling loop is ≤100mA, the single-chip microcomputer switches the K1 signal from low level to high level, and the high-level K1 signal is transmitted to the input end (A4 pin) of the 74hc14 chip of the control signal module circuit through the TTL level interface. S22. The 74hc14 chip of the control signal module circuit receives the high-level K1 signal, and outputs a low-level K1_CK signal from the Y4 pin after being reversed once by the first internal inverter (A4-Y4 pin); at the same time, the low-level K1_CK signal is input to the A5 pin of the 74hc14 chip, and a high-level K1_CB signal is output from the Y5 pin after being reversed twice by the second internal inverter (A5-Y5 pin); S23. In the delay switching module circuit, the potential of the input end (R1 free end) receiving the low-level K1_CK signal drops suddenly, and the previously charged capacitors C1 and C2 start to discharge through resistors R2 and R3, and the voltage across the parallel capacitor group slowly decreases during the discharging process, so that the OUT_CK signal is delayed from high level to low level; at the same time, the potential of the input end receiving the high-level K1_CB signal rises suddenly, and the current directly drives the corresponding output node, so that the OUT_CB signal immediately changes from low level to high level; S24. After the 74hc14 chip of the control signal module circuit receives the delayed low-level OUT_CK signal, it is input to the A2 pin, and the delayed low-level OUT_CK* signal is output after being reversed twice by the internal two inverters (A2-Y1-Y2 pins); at the same time, the 74hc14 chip receives the high-level OUT_CB signal, and inputs it to the A3 pin, and outputs a low-level OUT_CB* signal after being reversed once by the internal inverter (A3-Y3 pin); S25. The low-level OUT_CB signal is transmitted to the relay S1 coil through the 200Ω driving resistor, the coil loses power, and the relay S1 is released, and the movable contact is reset to the normally open state, and the sampling resistor R9 is disconnected with the ground end, and R9 is suspended; the delayed low-level OUT_CK signal is transmitted to the relay S2 coil through the 200Ω driving resistor, and the coil loses power, and the relay S2 is disconnected, and the movable contact of the relay S2 is separated from the normally open contact, and the connection between the sampling resistor R10 and the ground end is interrupted, and is in a suspended state.

[0032] In the above steps, the low-level OUT_CB signal first drives the relay S1 to disconnect, which can preferentially connect the 10KΩ large resistance R9 to the sampling circuit, so that even if the sampling current is a small current of pA level, a large enough sampling voltage can be generated through U=RI, avoiding voltage distortion caused by system measurement error; the delay characteristic of the OUT_CK signal makes the relay S2 delay to disconnect, forming a temporary parallel transition state of R9 and R10, avoiding the disconnection of the sampling circuit due to the sudden switching of the resistor, and ensuring the continuity and accuracy of the signal in the small current sampling process, and improving the sampling accuracy in the small current scene.

[0033] Embodiment 3: Large current sampling resistance switching method, in this embodiment, the preset value of the sampling loop current is still 100 mA, the element parameters of the control signal module circuit, the delay switching module circuit and the resistance switching module circuit are consistent with the corresponding embodiment of claim 7 (74hc14 chip is supplied with 5V, C1 / C2=10uF, R1=300Ω, R2=1KΩ, R3=100KΩ, R9=10KΩ, R10=0.1KΩ, the relay coil is connected with a 200Ω driving resistor in series).

[0034] The method specifically comprises the following steps: S31. The external single-chip microcomputer monitors the sampling loop current in real time through the current detection element, and when it is detected that the current >100mA, the single-chip microcomputer switches the K1 signal from high level to low level, and the low-level K1 signal is transmitted to the input end (A4 pin) of the 74hc14 chip of the control signal module circuit through the TTL level interface; S32. After the 74hc14 chip of the control signal module circuit receives the low-level K1 signal, the high-level K1_CK signal is output from the Y4 pin through the first internal inverter (A4-Y4 pin) once reversed; at the same time, the high-level K1_CK signal is connected to the A5 pin of the 74hc14 chip, and the low-level K1_CB signal is output from the Y5 pin through the second internal inverter (A5-Y5 pin) twice reversed; S33. In the delay switching module circuit, the potential of the input end (R1 free end) receiving the low-level K1_CB signal drops suddenly, the capacitors C1 and C2 that have been charged before are discharged through the resistors R2 and R3, so that the OUT_CB signal is delayed from high level to low level; at the same time, the potential of the input end receiving the high-level K1_CK signal rises suddenly, and the current directly drives the corresponding output node, so that the OUT_CK signal immediately changes from low level to high level; S34. After the 74hc14 chip of the control signal module circuit receives the high-level OUT_CK signal, it is connected to the A2 pin, and the high-level OUT_CK* signal is output through the two internal inverters (A2-Y1-Y2 pins) twice reversed; at the same time, the 74hc14 chip receives the delayed low-level OUT_CB signal and connects it to the A3 pin, and the delayed low-level OUT_CB* signal is output through the internal inverter (A3-Y3 pin) once reversed; S35. The high-level OUT_CK* signal is transmitted to the relay S2 coil through a 200Ω driving resistor, and the coil is powered to attract the relay S2, and the 1, 2 pins of the relay S2 are turned on, and the sampling resistor R10 is grounded through the 1, 2 pins of the relay S2, and is connected to the sampling loop; the delay low-level OUT_CB* signal is transmitted to the relay S1 coil through a 200Ω driving resistor, and the coil is delayed to release the relay S1, and the movable contact of the relay S1 is reset to the normally open state, and the sampling resistor R9 is disconnected with the ground terminal, and R9 is suspended.

[0035] In the above steps, the high-level OUT_CK signal first drives the relay S2 to attract, which can preferentially connect the small resistance R10 of 0.1KΩ to the sampling loop. Even if the sampling current exceeds 2A, the sampling voltage can be limited within the upper limit of the single-chip microcomputer measurement (such as 0-5V) through U=RI, avoiding data invalidation caused by voltage out of range; the delay characteristic of the OUT_CB signal makes the relay S1 delay to attract, avoiding the sudden connection of R9 to cause the sudden change of circuit load, preventing the impact of current mutation on relays, resistors and other elements, ensuring the stability and safety of the large current sampling process, and improving the sampling reliability in large current scenarios.

[0036] In this embodiment, the elements of the control signal module circuit are 74hc14 hex inverter chips (VCC pin connected to 5V DC power supply, GND pin grounded), the capacitances of the delay switching module circuit capacitors C1 and C2 are both 10uF, the resistances of the resistors R1, R2 and R3 are 300Ω, 1KΩ and 100KΩ respectively, the resistances of the sampling resistors R9 and R10 of the resistor switching module circuit are 10KΩ and 0.1KΩ respectively, and the coils of the relays S1 and S2 are both connected in series with a 200Ω driving resistor.

[0037] The method specifically includes the following steps: S41. By matching the parameters (C1 / C2=10uF, R2=1KΩ, R3=100KΩ) of the RC delay discharge circuit in the delay switching module circuit, the charging and discharging time of the capacitors C1 and C2 is controlled, so that the switching time difference of the relays S1 and S2 is stabilized at about 5ms, forming a transient state of temporary parallel connection of the double resistors (R9 and R10), avoiding the current mutation caused by the sudden connection or disconnection of a single resistor; S42. The external single-chip microcomputer collects the current size of the sampling loop in real time through the current detection element, and when the current is ≤100mA, the sampling resistor connected to the sampling loop is R9 (10KΩ) through the circuit switching, and the sampling voltage corresponding to the large current is discharged through the large resistance resistor; when the current is >100mA, the sampling resistor connected to the sampling loop is R10 (0.1KΩ) through the circuit switching, and the sampling voltage corresponding to the large current is limited through the small resistance resistor; S43. The K1 signal, OUT_CK signal and OUT_CB signal are inversely shaped by the 74hc14 chip of the control signal module circuit: the K1 signal generates the logic complementary K1_CK and K1_CB signals after being reversed by the chip, the OUT_CK and OUT_CB signals generate the stable OUT_CK* signal and OUT_CB* signal after being reversed by the chip, and high-frequency interference clutter in the signal transmission process is filtered; finally, the OUT_CK signal and the OUT_CB signal are transmitted to the relay S2 and S1 coil through the 200Ω driving resistor, the relay is driven to accurately act, and the stable switching of the sampling resistor is realized.

[0038] In the above steps, the timing difference controlled by the RC parameter can smooth the change of the circuit load, the adaptive switching of the resistor ensures that the sampling voltage is always within the effective measurement range of the single-chip microcomputer, and the shaping function of the 74hc14 chip guarantees the stability of the driving signal, so that the three work together to realize the accurate sampling of the full range from the pA level small current to the 2A or above large current; without manual intervention in the resistance switching, the human operation error is reduced, the test efficiency of the generator rotor applied voltage withstand test is improved, the current mutation and component impact are avoided, the service life of the circuit is prolonged, and the safety and data reliability of the test process are guaranteed.

[0039] The embodiments of the present specification are only enumerations of implementation forms of the inventive concept, and the protection scope of the present application should not be regarded as being limited to the specific forms stated in the embodiments, and the protection scope of the present application also extends to equivalent technical means that can be thought of by those skilled in the art according to the inventive concept.

Claims

1. A resistance switching circuit for current sampling, characterized by, The control signal module circuit, the delay switching module circuit and the resistance switching module circuit are included; the external single-chip microcomputer outputs K1 signal to the control signal module circuit, the control signal module circuit reverses the K1 signal once and twice respectively, and then outputs K1_CK signal and K1_CB signal to the delay switching module circuit; the delay switching module circuit delays the K1_CK signal and the K1_CB signal, and then outputs OUT_CK signal and OUT_CB signal, and feeds back to the control signal module circuit; the control signal module circuit reverses the OUT_CK signal twice and the OUT_CB signal once, and then outputs OUT_CK* signal and OUT_CB* signal; the OUT_CK* signal is electrically connected with the relay S2 in the resistance switching module circuit, and the OUT_CB* signal is electrically connected with the relay S1 in the resistance switching module circuit.

2. A resistance switching circuit for current sampling according to claim 1, characterized in that, The element of the control signal module circuit is 74hc14 chip, the K1 signal generated by the external single-chip microcomputer is connected to the 74hc14 chip, and then the K1_CK signal is outputted once, and the K1_CB signal is outputted twice; the feedback OUT_CK signal is connected to the 74hc14 chip, and then the OUT_CK* signal is outputted twice, and the feedback OUT_CB signal is connected to the 74hc14 chip, and then the OUT_CB* signal is outputted once.

3. A resistance switching circuit for current sampling according to claim 1, characterized in that, The delay switching module circuit includes capacitor C1, capacitor C2, resistance R1, resistance R2 and resistance R3; the capacitor C1 and the capacitor C2 are connected in parallel to form a parallel capacitor group, one end of the parallel capacitor group is connected with the resistance R1, the other end is connected with the resistance R3, and the other end of the resistance R3 is grounded; one end of the resistance R2 is connected to the connection node of the resistance R1 and the parallel capacitor group, and the other end is grounded; the other end of the resistance R1 is used as a signal input end to receive the K1_CK signal or the K1_CB signal, and the connection node of the parallel capacitor group and the resistance R3 is used as a signal output end to output the OUT_CK signal or the OUT_CB signal.

4. A resistance switching circuit for current sampling according to claim 1, characterized in that, The resistance switching module circuit includes relay S1, relay S2, sampling resistance R9 and sampling resistance R10; the initial state of the relay S1 is normally open, and the initial state of the relay S2 is normally open; the moving contact of the relay S1 is connected with one end of the sampling resistance R9, and the normally open contact is grounded; the moving contact of the relay S2 is connected with one end of the sampling resistance R10, and the normally open contact is grounded; the other ends of the sampling resistance R9 and the sampling resistance R10 are connected to the current sampling loop; the coil of the relay S1 is electrically connected with the OUT_CB* signal output end, and the coil of the relay S2 is electrically connected with the OUT_CK* signal output end.

5. A resistance switching circuit for current sampling according to claim 1, characterized in that, The control signal module circuit and the delay switching module circuit share the same direct current power supply and the common ground end; the signal input end of the delay switching module circuit is connected with the current limiting resistance in series.

6. A resistance switching circuit for current sampling according to claim 1, characterized in that, The external single-chip microcomputer and the control signal module circuit are connected through TTL level interface; the driving resistance is connected in series between the OUT_CK* signal output end and the coil of the relay S2, and between the OUT_CB* signal output end and the coil of the relay S1.

7. A method for setting the initial state of a current sample based on the circuit according to any one of claims 1 to 6, characterized in that, The following steps are included: S11. The K1 signal outputted by the external single-chip microcomputer is set to low level; S12. The control signal module circuit outputs a high level K1_CK signal and a low level K1_CB signal after receiving a low level K1 signal; S13. The delay switching module circuit outputs a high level OUT_CK signal after receiving a high level K1_CK signal, and outputs a low level OUT_CB signal after receiving a low level K1_CB signal; S14. The control signal module circuit outputs a high level OUT_CK* signal after reversing the high level OUT_CK signal twice, and outputs a high level OUT_CB* signal after reversing the low level OUT_CB signal once; S15. The high level OUT_CK* signal and OUT_CB* signal drive the relays S2 and S1 to be attracted, the 1 and 2 pins of the relay S1 are turned on, the 1 and 2 pins of the relay S2 are turned on, the sampling resistor R9 is grounded through the relay S1, and the sampling resistors R9 and R10 are in parallel.

8. A low current sampling resistor switching method based on the circuit of any of claims 1-6, characterized in that, The method comprises the following steps: S21. When the current in the sampling circuit is less than a preset value, the external single-chip microcomputer switches the K1 signal from a low level to a high level; S22. The control signal module circuit outputs a low level K1_CK signal and a high level K1_CB signal after receiving a high level K1 signal; S23. In the delay switching module circuit, the K1_CK signal input end becomes a low level, the OUT_CK signal is delayed from a high level to a low level, the K1_CB signal input end becomes a high level, and the OUT_CB signal is changed from a low level to a high level; S24. The control signal module circuit outputs a delay low level OUT_CK* signal after reversing the delay low level OUT_CK signal twice, and outputs a low level OUT_CB* signal after reversing the high level OUT_CB signal once; S25. The low level OUT_CB* signal drives the relay S1 to release, the movable contact of the relay S1 is reset to a normally open state, the sampling resistor R9 is disconnected with the ground end, and the R9 is suspended; the delay low level OUT_CK* signal drives the relay S2 to delay to disconnect, and the sampling resistor R10 is suspended.

9. A method of high current sampling resistor switching based on the circuit of any of claims 1-6, characterized by, The method comprises the following steps: S31. When the current in the sampling circuit is greater than a preset value, the external single-chip microcomputer switches the K1 signal from a high level to a low level; S32. The control signal module circuit outputs a high level K1_CK signal and a low level K1_CB signal after receiving a low level K1 signal; S33. In the delay switching module circuit, the K1_CB signal input end becomes a low level, the OUT_CB signal is delayed from a high level to a low level, the K1_CK signal input end becomes a high level, and the OUT_CK signal is changed from a low level to a high level; S34. The control signal module circuit outputs a high level OUT_CK* signal after reversing the high level OUT_CK signal twice, and outputs a delay low level OUT_CB* signal after reversing the delay low level OUT_CB signal once; S35. The high level OUT_CK* signal drives the relay S2 to be attracted, the sampling resistor R10 is grounded through the relay S2, the delay low level OUT_CB* signal drives the relay S1 to delay to release, and the sampling resistor R9 is suspended.

10. A method for sampling voltage stabilization control based on the circuit according to any one of claims 1-6, characterized in that, The method comprises the following steps: S41. The switching timing difference of relays S1 and S2 is controlled by the delay switching module circuit; S42. According to the size of the sampling current, the sampling resistance R9 or R10 is switched to access the sampling loop; S43. The 74hc14 chip of the control signal module circuit is used to perform reverse shaping processing on the signal, and the OUT_CK* signal and the OUT_CB* signal are output to drive the relays S2 and S1 to act.

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