Multimode analysis method based on electrical parameters of semiconductor

Abstract

The invention discloses a multimode analysis method based on semiconductor electrical parameters, and relates to the technical field of semiconductor testing, and the method comprises the steps: obtaining test input data containing an original test file name and a chip position identifier, analyzing a SetupTitle field and a DataName field in an original test file, and generating a target data column position record; based on the target data column position record, extracting test voltage and current data from the original test file, including VGS, current ABSID, current ABSIG, VDS and ID; performing electrical parameter extraction processing on the test voltage and current data to generate electrical parameters including a threshold voltage value, an on-resistance value, a gate current value, a breakdown voltage value and an off-state leakage current value; according to the method, under the multi-test mode, multiple electrical performance expressions can form stable parameter expressions under a unified structure, and the parameter expressions extend to wafer space distribution and packaging grading, so that a complete analysis link penetrating through data analysis, parameter judgment and finished product grading is realized in large-scale wafer processing.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor testing, in particular to a multi-mode analysis method based on semiconductor electrical parameters. BACKGROUND

[0002] With the development of semiconductor manufacturing towards higher density wafers and complex test flow, test data processing is gradually shifting from single electrical index static analysis to multi-test mode, multi-parameter parallel data analysis mode. In this process, a large number of test files contain different field structures, different voltage and current formats, and spatial information related to chip position identification. Various test tasks appear alternately in the same production batch, which makes the original data highly discrete in terms of organization method, field arrangement order, test mode difference and test target difference, resulting in the need to establish an overall analysis system that can understand multiple test modes, identify test data structure characteristics and simultaneously associate spatial information in large-scale wafer test scenarios.

[0003] Currently, in the process of processing structured test data containing original test file names, chip position identification and voltage and current values, due to the inconsistent field arrangement between different test modes, frequent data column position changes and large file structure differences, it is often difficult to stably lock the target field position, maintain consistent parameter extraction logic under mode changes, and maintain the continuity of the analysis of the same type of data between test files. The behavior characteristics between voltage and current are difficult to form a unified expression and maintain consistent parameter generation mode in batch wafers.

[0004] Secondly, in the process of corresponding multiple electrical parameters to chip specifications and configuring a multi-parameter comprehensive judgment structure based on the judgment results, the lack of uniform comparison relationship between parameters often leads to the difficulty of aggregating multiple electrical parameters under a unified benchmark, and further leads to a series of processing obstacles such as the inability to effectively form a comprehensive judgment across test modes, the inability to determine the regional differences within the wafer through parameter correlation, and the inability to realize the mapping of electrical performance to wafer spatial distribution.

[0005] In addition, in the wafer-level production process, the matching of multi-parameter comprehensive judgment data and wafer layout coordinates and further conversion to grading codes to construct a packaging picking data file often leads to a disconnection between grading output and electrical analysis due to the lack of continuous structure in the electrical judgment system, the difficulty of stable mapping between spatial coordinate information and judgment results, and the lack of uniform data link between different wafers. The wafer distribution characteristics cannot be continuously transmitted to the packaging link, and the yield management process is broken in the data flow. SUMMARY

[0006] To solve the above technical problems, the present application provides a multi-mode analysis method based on semiconductor electrical parameters, which comprises: S11, obtaining test input data containing original test file name and chip position identification, parsing SetupTitle field and DataName field in the original test file, and generating target data column position record; S12, extracting test voltage and current data, including VGS, current ABS_ID, current ABS_IG, VDS and ID, from the original test file based on the target data column position record; S13, generating electrical parameters, including threshold voltage value, on-resistance value, gate current value, breakdown voltage value and off-state leakage current value, by performing electrical parameter extraction processing on the test voltage and current data; S14, parsing the unique laser mark code of the wafer and retrieving the chip configuration database to generate chip specification configuration, and performing item-by-item judgment on the electrical parameters according to the chip specification configuration to obtain multi-parameter comprehensive judgment data; S15, analyzing chip position coordinates according to chip position identification, mapping multi-parameter comprehensive judgment data to wafer layout coordinates, and generating wafer electrical distribution output data; S16, performing grading coding according to multi-parameter comprehensive judgment data and grading rules specified in the chip specification configuration, and constructing packaging picking data file based on chip position coordinates and grading coding to generate packaging output data.

[0007] Further, the step of generating target data column position record comprises: S111, performing traversal operation based on original test file name in test input data, locating SetupTitle field in original test file, and extracting field content adjacent to SetupTitle field as test mode identification; S112, performing traversal operation based on original test file name in test input data, locating DataName field in original test file, and extracting field content in the row where DataName field is located as data column header array; S113, performing field correspondence judgment according to field content of test mode identification and data column header array, and taking column position of corresponding data column header in original test file as target data column position record.

[0008] Further, the step of extracting test voltage and current data from the original test file comprises: S121, in the case that the test mode identifier contains "IdVg", extracting the corresponding column values of field VGS and field current ABS_ID from the original test file as test voltage current data; S122, in the case that the test mode identifier contains "IgVg", extracting the corresponding column values of field VGS and field current ABS_IG from the original test file as test voltage current data; S123, in the case that the test mode identifier contains "IdVd", extracting the corresponding column values of field VDS and field ID from the original test file as test voltage current data; S124, in the case that the test mode identifier contains "Id_off", extracting the corresponding column values of field VDS and field ID from the original test file as test voltage current data.

[0009] Further, the step of generating the threshold voltage value in the electrical parameter includes: a131, extracting the VGS values corresponding to the current ABS_ID at two target current levels of 1uA and 1mA based on the test voltage current data of the test mode "IdVg"; a132, recording the VGS value corresponding to 1uA as a first threshold voltage, and recording the VGS value corresponding to 1mA as a second threshold voltage; a133, combining the first threshold voltage and the second threshold voltage as a threshold voltage value.

[0010] Further, the step of generating the on-resistance value in the electrical parameter includes: b131, grouping VDS and ID by VGS based on the test voltage current data of the test mode "IdVd", each group corresponding to a fixed VGS value; b132, performing a linear fitting operation on ID and VDS in each VGS group to calculate a slope value; b133, taking the reciprocal of each linear fitting slope, and constructing an on-resistance value based on the reciprocal of the slope.

[0011] Further, the step of generating the gate current value in the electrical parameter includes: c131, extracting the current ABS_IG value corresponding to the VGS voltage value of 5V based on the test voltage current data of the test mode "IgVg"; c132, taking the current ABS_IG value when VGS=5V as the gate current value.

[0012] Further, the step of generating the breakdown voltage value and the off-state leakage current value in the electrical parameter includes: d131, identifying the first VDS value at which the current ID exceeds the preset current threshold based on the test voltage-current data of the test mode "Id_off", and recording the VDS value as the breakdown voltage value; d132, counting the absolute value of the largest ID value in all VDS corresponding intervals before the breakdown voltage value, and recording the ID value as the off-state leakage current value.

[0013] Further, the step of performing item-by-item determination on the electrical parameters according to the chip specification configuration to obtain multi-parameter comprehensive determination data comprises: S141, parsing the wafer number field and wafer batch field in the wafer laser mark code, and constructing a wafer identification primary key; S142, retrieving the matching record in the chip configuration database based on the wafer identification primary key, and extracting the chip specification configuration containing the upper and lower limits of the determination of various electrical parameters; S143, if no matching record is retrieved, a preset general chip specification configuration is called as a fallback solution; S144, comparing each electrical parameter with the corresponding parameter threshold in the chip specification configuration respectively, and outputting the determination result of each electrical parameter; S145, merging the determination results of all electrical parameters to generate multi-parameter comprehensive determination data.

[0014] Further, the step of generating wafer electrical property distribution output data comprises: S151, based on the chip position identifier, parsing the wafer number field, row and column coordinate field and Die index field, and constructing wafer layout coordinates; S152, matching the multi-parameter comprehensive determination data of each chip with its corresponding wafer layout coordinates to form a structured coordinate-determination data pair; S153, performing color coding based on the combination state of the determination result in each coordinate-determination data pair: S154, binding the above color coding with the wafer layout coordinates to generate wafer electrical property distribution output data.

[0015] Further, the step of generating packaging output data comprises: S161, matching the multi-parameter comprehensive determination data with the grading rules in the chip specification configuration to determine the target grading level of each chip; S162, converting the target grading level into the corresponding grading code, and combining the chip position coordinates with the grading code into chip grading data; S163, performing a summary operation on all chip grading data according to the wafer number field to construct a packaging picking data file, and outputting the packaging picking data file as the packaging output data.

[0016] Compared with the prior art, the application has the beneficial effects that: The application makes the voltage and current changes generated under different test modes form quantifiable parameter expressions on the basis of unified determination, so that the multiple electrical performances within a wafer can be analyzed and classified in a consistent manner, and the stability and continuity of the determination process are maintained in the scenario where process differences and data structure differences coexist. In addition, the application also constructs item-by-item determination logic based on the corresponding relationship between multiple electrical parameters and chip specification configurations to realize effective aggregation of multi-parameter comprehensive determination data in large-scale wafer samples, so that the determination results can further correspond to wafer layout coordinates, thereby improving the presentation ability of electrical differences between different regions within a wafer, and extending the parameter system formed by the target data column position record and the test voltage and current data in the spatial dimension. Further, the application extends the aforementioned spatial distribution characteristics to the packaging picking process based on the mapping relationship between multi-parameter comprehensive determination data, wafer layout coordinates, and grading codes, so that the electrical determination, wafer distribution, and packaging grading form a continuous data link, thereby strengthening the consistency and traceability from electrical analysis to finished product classification, and laying a complete data support for improving the yield management level of large-scale wafer production.

[0017] In summary, the application realizes that multiple electrical performances under multiple test modes can form stable parameter expressions under a unified structure, and are extended to wafer spatial distribution and packaging grading, thereby realizing a complete analysis link of data analysis, parameter determination, and finished product grading in large-scale wafer processing. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments described in the present application, and other drawings can also be obtained by those skilled in the art based on these drawings.

[0019] Figure 1 A flowchart of a multi-mode analysis method based on semiconductor electrical parameters is provided for the embodiments of the present application. Figure 2 A visual wafer electrical mapping diagram of wafer 1836 is provided for the embodiments of the present application. Figure 3 A visual wafer electrical mapping diagram of wafer 1840 is provided for the embodiments of the present application. DETAILED DESCRIPTION

[0020] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0021] Referring to Figure 1 The embodiment shown discloses a multi-mode analysis method based on semiconductor electrical parameters, which comprises the following steps: S11, obtaining test input data containing original test file name and chip position identification, parsing the SetupTitle field and the DataName field in the original test file, and generating target data column position record; In the embodiment, the target data column position record is used to guide the subsequent electrical data extraction and parameter analysis operation, and its generation process depends on the parsing of the structured field content and the chip position identification content in the original test file. The original test file can be in CSV format, TXT format or Excel table format, and the file structure is usually composed of multiple rows and columns, with the first row being the field title row, and the field names being separated by a specific delimiter (such as comma or tab).

[0022] The original test file name is named by the test task number, and the test input data contains the chip position identification paired with the file name, which is used to map the chip coordinates and electrical determination results subsequently.

[0023] In a specific embodiment, the step of generating the target data column position record comprises: S111, performing traversal operation based on the original test file name in the test input data, locating the SetupTitle field in the original test file, and extracting the field content adjacent to the SetupTitle field as the test mode identification; In the implementation process, according to the original test file name provided in the test input data, the corresponding original test file is called in. The line traversal from top to bottom is performed on the file, and the line containing the "SetupTitle" field is searched row by row; The field is located in the front information area of the test file structure, and coexists with a group of test configuration parameters; After identifying the line containing the "SetupTitle" field, the field content of the line is continuously scanned to the right, and the field content adjacent to the "SetupTitle" field in the same line is extracted as the test mode identification corresponding to the current test data.

[0024] It should be noted that different test mode identifiers (such as "IdVg", "IgVg", "IdVd", "Id_off") are used to indicate the type of voltage / current data collected by the current test task and its test method, and the data columns extracted in the subsequent steps are closely related to the mode; To avoid the mis-matching caused by multiple fields containing the "SetupTitle" word in the test file, the embodiment increases the field accurate matching mechanism when extracting the test mode identifier, including: Preferentially matching the column whose field name is exactly equal to "SetupTitle"; If there are multiple suspected fields, secondary screening is performed; if there are still multiple candidates, the field with the smallest column index in the file front information area is selected as the final SetupTitle field; Specifically, if the content is "Idvg", it is preliminarily determined as threshold voltage test; If the content is "IdVd", it is preliminarily determined as on-resistance test; If the content is "IgVg", it is preliminarily determined as gate current test; If the content is "Id_off", it is preliminarily determined as voltage resistance and leakage test.

[0025] S112, based on the original test file name in the test input data, performing traversal operation, locating the DataName field in the original test file, and extracting the field content of the row where the DataName field is located as a data column header array; Performing traversal operation on the original test file to find the target row containing the "DataName" field, which marks the beginning of the test data part; Among them, the DataName field is usually located in the row before the "data area" of the test file, and the row is the boundary, and the numerical value row of the test data is after the row. After successfully locating the DataName field, extract the entire field header content of the row where it is located, divide it into multiple field units according to the separator (such as comma), and construct the data column header array according to the original arrangement order; It should be noted that each element in the array corresponds to a column in the subsequent data row, which is used to map the column position and field meaning; A typical data column header array includes "VGS", "ID", "VDS", "IG", "TEMP", "SITE" and the like. These fields correspond to the measurement data such as voltage, current, temperature or measurement point identifier in the subsequent rows; If there are repeated field names in the data column header array, for example, multiple "ID" fields caused by multi-channel sampling, the embodiment records the correspondence between the field name and its column index when constructing the data column header array, forming a unique mapping table {field name -> column index list}.

[0026] To ensure the accuracy of the test mode identification, based on the test mode identification extracted in S111, a secondary verification based on the array content is performed: Specifically, if the array contains [VGS, VDS, IG, ID, ABS_ID], it is confirmed that the test mode is Idvg; If the array contains [VGS, VDS, IG, ID, ABS_IG], it is confirmed that the test mode is IgVg; If the array contains [VGS, IG, ID, VDS], it is confirmed that the test mode is IdVd; If the array contains [VDS, VGS, IG, ID, ABS_ID, ABS_IG], it is confirmed that the test mode is Id_off; It should be noted that: only when the identification of S111 is consistent with the array characteristics of S112, the mode recognition is successful, otherwise an abnormal alarm is triggered.

[0027] S113, according to the test mode identification and the field content of the data column header array, the column position of the corresponding data column header in the original test file is recorded as the target data column position.

[0028] After the extraction of the test mode identification and the data column header array, the data field combination required by the current task is determined according to the test mode identification; If the test mode identification is "IdVg", lock and extract the "VGS" and "ABS_ID" column data; If the test mode identification is "IgVg", lock and extract the "VGS" and "ABS_IG" column data; If the test mode identification is "IdVd", lock and extract the "VGS", "VDS" and ID three column data; If the test mode identification is "Id_off", the target field is "VDS", "ABS_ID" and "ABS_IG" three column data; It should be noted that: through column name index instead of fixed column number extraction, it can adapt to the column sequence change when different engineers set the export format; The column position number of each matching field is combined into a target data column position record, which is used for quick positioning of the corresponding voltage or current value in the subsequent data extraction step.

[0029] It should be noted that before performing field matching, the data column header array needs to be subjected to field name standardization processing, including: removing white space characters before and after the field name; converting the field name to a uniform capital format; removing common prefixes (such as "ABS_" and "RAW_") to enhance matching compatibility; and matching the standardized field name with the corresponding field of the test pattern one by one to ensure consistency of pointing. When performing field name standardization processing, the original name of the field is retained and stored in the field mapping table together with the standardized name.

[0030] S12, based on the target data column position record, extracting test voltage and current data from the original test file, including VGS, current ABS_ID, current ABS_IG, VDS, and ID; In this embodiment, the test voltage and current data are used for subsequent electrical parameter extraction operations, and the acquisition process depends on the target data column position record generated in step S11. The record describes the column position of the voltage or current data in the original test file, enabling the subsequent data extraction process to complete fast and accurate data reading according to the column number.

[0031] The structure of the original test file is a data area arranged by rows, and each row corresponds to a set of test point sampling results. Each column corresponds to a field title. In order to ensure the stability of data parsing, the embodiment performs separator parsing (such as comma or tab) on each data row in the file when performing data extraction, and reads the values of the target fields according to the column index.

[0032] It should be noted that in order to ensure the accuracy of data reading, the embodiment performs validity judgment before parsing the value rows of the original test file, skips rows containing empty strings, NaN, illegal characters, or insufficient columns, and records the abnormal row number as needed for log auditing.

[0033] If there are sporadic missing values in a column of the test file, linear interpolation can be used to compensate for single-point missing values to ensure data continuity to meet the subsequent fitting or search requirements.

[0034] In one specific embodiment, the step of extracting test voltage and current data from the original test file includes: S121, in the case where the test pattern identifier contains "IdVg", extracting the corresponding column values of field VGS and field current ABS_ID from the original test file as test voltage and current data; When the test mode identifier is "IdVg", it means that the current test task collects the drain current variation curve under the condition of gate voltage scanning. Such a test file usually contains a large amount of current ABS_ID measurement data corresponding to different VGS voltage application conditions; Specifically, the column numbers corresponding to the field VGS and the field current ABS_ID are determined through the target data column position record, the values in the two column positions are read from all the numerical rows of the original test file row by row, and the values are combined as a pair of "voltage-current" data as test voltage-current data. Exemplarily: Suppose the field VGS is located in the 3rd column and the field current ABS_ID is located in the 7th column, then the following reading is performed on the nth row of the original test file: The value in the 3rd column is read as VGS; The value in the 7th column is read as the current ABS_ID; The values read in each row are sequentially stored as a record, and finally the test voltage-current data for threshold voltage value extraction is constructed.

[0035] S122, in the case where the test mode identifier contains "IgVg", the column values corresponding to the field VGS and the field current ABS_IG are extracted from the original test file as test voltage-current data; When the test mode identifier is "IgVg", the test task focuses on the gate leakage current characteristics under the condition of gate voltage scanning. Such a test is used to evaluate the quality of gate dielectric, gate oxide reliability or gate leakage under high voltage working condition; Specifically, the column numbers corresponding to the field VGS and the field current ABS_IG are determined according to the target data column position record, and all data rows of the original test file are read.

[0036] Each row extracts a VGS voltage value and a corresponding ABS_IG gate current value.

[0037] Exemplarily: If the field VGS is located in the 3rd column and the field ABS_IG is located in the 8th column, then the data in the two columns are read row by row and combined as test voltage-current data, which provides basic data for subsequent gate current value extraction operation.

[0038] S123, in the case where the test mode identifier contains "IdVd", the column values corresponding to the field VDS and the field ID are extracted from the original test file as test voltage-current data; When the test mode identifier is "IdVd", it indicates that the test task is an electrical property scan of drain current (ID) varying with drain voltage (VDS) under a fixed gate voltage (VGS), which is used to extract the on-resistance value or output curve characteristics.

[0039] Specifically, the column position indexes of the fields VDS and ID are determined based on the target data column position record, and the VDS and ID values in each record are extracted as voltage-current data pairs by parsing the numerical area of the original test file row by row.

[0040] The data will be used in subsequent S13 to group and linearly fit under a fixed VGS to generate the on-resistance value.

[0041] S124, in the case where the test mode identifier contains "Id_off", the corresponding column values of the fields VDS and ID are extracted from the original test file as test voltage-current data; When the test mode is "Id_off", the test content is usually used to evaluate the leakage current size and breakdown behavior of the device under the off-state condition, and the test file contains ID current data under multiple different VDS conditions; Specifically, the column numbers of the fields VDS and ID are determined based on the target data column position record, and the VDS and ID values in the file numerical area are read row by row, and the VDS value of each row and the corresponding ID value are saved as paired data to form a data set for extracting the breakdown voltage value and the off-state leakage current value.

[0042] S13, by performing electrical parameter extraction processing on the test voltage-current data, generating electrical parameters including threshold voltage value, on-resistance value, gate current value, breakdown voltage value and off-state leakage current value; In this embodiment, in order to construct an electrical parameter extraction processing flow for multiple test modes, the test voltage-current data for test modes "IdVg", "IdVd", "IgVg" and "Id_off" are processed according to the preset extraction logic to generate parameters. The parameter calculation methods are as follows: In one specific embodiment, the step of generating the threshold voltage value in the electrical parameters includes: a131, based on the test voltage-current data for the test mode "IdVg", extracting the VGS value corresponding to the current ABS_ID at two target current levels of 1uA and 1mA; For test data with test mode "IdVg", a corresponding array of current ABS_ID and VGS is constructed, and by bidirectional traversal of the array, the data point closest to 1uA and 1mA is searched, and its corresponding VGS voltage value is returned; To ensure the extraction accuracy, the following processing flow is performed in this step: Specifically, all data points are sorted in ascending order of current ABS ID value. In the sorted data, the point closest to 1uA is found, and its corresponding VGS is recorded as VGS_Low. Similarly, the point closest to 1mA is found, and its corresponding VGS is recorded as VGS_High. It should be noted that if the target current value does not exactly appear in the test data, a linear interpolation calculation is performed between the two points before and after it to obtain the corresponding VGS value, so as to avoid the influence of discrete point fluctuations on threshold judgment.

[0043] a132, record the VGS value corresponding to 1uA as the first threshold voltage, and record the VGS value corresponding to 1mA as the second threshold voltage; After the execution of step a131, VGS_Low is directly used as the first threshold voltage, and VGS_High is used as the second threshold voltage; a133, combine the first threshold voltage and the second threshold voltage into a threshold voltage value Combine the two voltage values extracted in a132 into a structured record, and generate a "threshold voltage value" representing the opening boundary interval of the device in the "IdVg" mode, which is used to judge the opening ability and migration threshold of the device.

[0044] In one specific embodiment, the step of generating the on-resistance value in the electrical parameter includes: b131, group VDS and ID by VGS based on test voltage and current data in the test mode "IdVd", and each group corresponds to a fixed VGS value; Divide the original test data in the test mode "IdVd" by group: Specifically, traverse all data records, and for each record, extract its VGS, VDS and ID, and construct a key-value mapping according to the VGS value, and divide the VDS-ID pair with the same VGS into a group. b132, perform linear fitting operation on ID and VDS in each VGS group to calculate the slope value; Perform linear fitting operation on the corresponding relationship between current ID and voltage VDS in each VGS group to obtain the response slope value of current to voltage.

[0045] Specifically, perform linear regression on all data points in the group to construct a linear function model; represented as: ; In the formula, is the first ID value in a VGS group, VDS value in the VGS group, slope value fitted in the group, intercept term in the linear fitting; The slope value is calculated based on the least square method formula, which is expressed as: ; In the formula, is the number of data points in the current group, is the average value of all VDS values in the current group, is the average value of all ID values in the current group; The intercept term is calculated according to the formula: ;

[0046] It should be noted that the above fitting process is performed on the data of each fixed VGS value group respectively.

[0047] b133, take the reciprocal of the linear fitting slope of each group, and construct the on-resistance value based on the reciprocal of the slope.

[0048] In one specific embodiment, the step of generating the gate current value in the electrical parameter includes: c131, based on the test voltage-current data of the test mode "IgVg", extract the current ABS_IG value corresponding to the VGS voltage value of 5V; Specifically, from the "IgVg" mode test data, select all records with VGS=5V, and extract the current value ABS_IG corresponding to this point.

[0049] The specific process is as follows: traverse the data row by row, and judge whether the VGS value is 5.00V; If matched, add the ABS_IG value of the point to the candidate list; If there are multiple values, calculate the mean or median value as the final value.

[0050] When selecting the ABS_IG value corresponding to VGS=5V, if there is no point in the test data that is exactly equal to 5.00V, an interval search strategy is executed; Search for the two data points closest to VGS in the interval [5V-0.02V, 5V+0.02V] Obtain the ABS_IG value corresponding to VGS=5.00V through linear interpolation.

[0051] c132, take the current ABS_IG value at VGS=5V as the gate current value; Set the ABS_IG value screened out in c131 as the "gate current value" of the current chip, which is used to judge the risk of gate leakage.

[0052] In one specific embodiment, the step of generating the breakdown voltage value and the off-state leakage current value in the electrical parameter includes: d131, based on the test voltage-current data of the test mode "Id_off", identify the first VDS value at which the current ID exceeds the preset current threshold, and record the VDS value as the breakdown voltage value; Specifically, from the test data under the "Id_off" mode: Set the preset current threshold value (1uA), traverse the test data according to VDS from small to large, find the first data point at which ID exceeds the threshold value, and record the corresponding VDS value as the "breakdown voltage value".

[0053] d132, within all VDS corresponding intervals before the breakdown voltage value, count the absolute value of the largest ID value, and record the ID value as the off-state leakage current value.

[0054] Among them, before identifying the breakdown point, all ID data are calculated for absolute value, all records before the breakdown voltage are extracted, and the data point with the largest ID absolute value is counted as the "off-state leakage current value", which is used to evaluate the off-state performance.

[0055] S14, parse the unique laser mark code of the wafer and retrieve the chip configuration database to generate the chip specification configuration, perform item-by-item judgment on the electrical parameter according to the chip specification configuration, and obtain multi-parameter comprehensive judgment data; In one specific embodiment, the step of performing item-by-item judgment on the electrical parameter according to the chip specification configuration to obtain multi-parameter comprehensive judgment data includes: S141, parse the wafer number field and wafer batch field in the wafer laser mark code, and construct a wafer identification primary key; Specifically, the laser mark code string information on the wafer is obtained through image recognition or scanning reading, the string is parsed for format, and the wafer number field and wafer batch field are extracted; The wafer number field is the number of single wafer in the batch, for example "WAF12"; the wafer batch field is the processing time or production batch identifier, for example "20231124_TSMC_12inch"; The extracted wafer number field and wafer batch field are spliced with an underscore to construct a wafer identification primary key, for example: "20231124_TSMC_12inch_WAF12", which is used to retrieve the chip specification configuration in the chip configuration database.

[0056] S142, based on the wafer identification primary key, retrieve the matching record in the chip configuration database, and extract the chip specification configuration containing various electrical parameter determination upper and lower limits; Specifically, the wafer identification primary key constructed in S141 is used as a search keyword to access the chip configuration database to locate the data record that completely matches the identification primary key. The chip configuration database is a structured table, and the fields include but are not limited to: wafer identification primary key, threshold voltage value upper and lower limits, on-resistance value upper and lower limits, gate current value upper limit, breakdown voltage value lower limit, and off-state leakage current value upper limit. If the match is successful, the upper and lower limit values of each electrical parameter in the record are extracted to form the chip specification configuration, which is used as the standard basis for subsequent electrical parameter determination.

[0057] S143, if no matching record is retrieved, a preset general chip specification configuration is called as a fallback solution; Specifically, if no database record completely matching the wafer identification primary key is retrieved in S142, the fallback process is automatically entered, and the general chip specification configuration data is called. The general chip specification configuration is composed of pre-set standard electrical parameter determination upper and lower limits, and is suitable for unified standard determination when there is no customized configuration for new wafer data. The general chip specification configuration also includes the upper and lower limit settings of the above-mentioned five electrical parameters, and has been confirmed to be applicable to the determination of new wafer data without customized configuration in the process verification stage.

[0058] S144, compare each electrical parameter with the corresponding parameter threshold in the chip specification configuration respectively, and output the determination result of each electrical parameter; Specifically, the threshold voltage value, on-resistance value, gate current value, breakdown voltage value, and off-state leakage current value in the generated electrical parameters are read in sequence, and compared with the upper and lower limits of the corresponding fields in the chip specification configuration: If the electrical parameter is between the upper and lower limits, the determination result of the parameter is "pass"; If the electrical parameter exceeds one of the upper and lower limits, the determination result of the parameter is "not pass".

[0059] The determination result is expressed in a single field Boolean or character type, and is assigned to five independent electrical parameter determination fields, such as "VT determination result", "Ron determination result", "IG determination result", "BV determination result", and "Ioff determination result.

[0060] S145, merging the determination results of all electrical parameters to generate multi-parameter comprehensive determination data; Specifically, the single determination results of the five electrical parameters, including the threshold voltage value determination result, the on-resistance value determination result, the gate current value determination result, the breakdown voltage value determination result, and the off-state leakage current value determination result, are summarized into the data structure corresponding to the same wafer coordinate chip, and the following multi-parameter compliance determination logic is executed: If any determination result is "not passed", the multi-parameter comprehensive determination data of the current chip is marked as "unqualified"; Only when all five parameters are determined as "passed", the multi-parameter comprehensive determination data of the current chip is marked as "qualified"; The multi-parameter comprehensive determination data structure includes: wafer number field, chip position identification field, each parameter determination field, and multi-parameter synthesis determination field, wherein the multi-parameter synthesis determination field is "PASS" or "FAIL".

[0061] S15, according to the chip position identification, the chip position coordinates are analyzed, the multi-parameter comprehensive determination data is mapped to the wafer layout coordinates, and wafer electrical property distribution output data is generated; In one specific embodiment, the step of generating wafer electrical property distribution output data includes: S151, based on the chip position identification, the wafer number field, the row and column coordinate field, and the Die index field are analyzed to construct the wafer layout coordinates; Specifically, for the chip position identification contained in each piece of test input data, the wafer number field, the row and column coordinate field, and the Die index field in the position identification are analyzed according to the preset format: The wafer number field is used to distinguish different wafer numbers, the row and column coordinate field is used to identify the two-dimensional arrangement position of the chip in the wafer, and the Die index field is used to distinguish when there are multiple Dies in the same coordinate.

[0062] The above three fields are combined to form the wafer layout coordinates, which are used as the reference coordinates for subsequent electrical property data space mapping.

[0063] S152, match the multi-parameter comprehensive determination data of each chip with its corresponding wafer layout coordinates to form a structured coordinate-determination data pair; Specifically, each data record that has completed determination is traversed, and the wafer layout coordinates contained therein are paired with the multi-parameter comprehensive determination data corresponding to the record to form a structured coordinate-determination data pair.

[0064] The data form of this structured data pair is: [wafer number, row number, column number, Die index] → multi-parameter comprehensive judgment data.

[0065] The pairing data of all chips is grouped by wafer number and buffered in the wafer electrical mapping cache structure as input for subsequent color coding and visualization processing.

[0066] S153, based on the combination state of the judgment result in each coordinate-judgment data pair, color coding is performed: Specifically, each structured coordinate-judgment data pair is traversed, and based on the single judgment result of each electrical parameter in the multi-parameter comprehensive judgment data, the following color coding logic is performed: If all five electrical parameter judgment results are "pass", mark it as blue; If at least one item is "failed" but none of them appears "both exceeds the upper limit and is lower than the lower limit", mark it as black; If there is any item "both exceeds the upper limit and is lower than the lower limit", mark it as red; Among them, the visual wafer electrical mapping diagram is as shown in Figure 2 、 3 ; It should be noted that the "upper limit" and "lower limit" come from the chip specification configuration record extracted in step S142, and the chip specification configuration includes the qualified upper and lower limit interval of each electrical parameter under the specified process, and serves as the upper and lower limit reference benchmark for performing the grading judgment in this step.

[0067] S154, bind the above color coding information with wafer layout coordinates to generate wafer electrical distribution output data; Specifically, the color coding result is combined with the wafer layout coordinates to generate structured output data containing the two-dimensional coordinates of each chip and the corresponding color identification, which is used as wafer electrical distribution output data.

[0068] The output data is organized in the form of [wafer number, row number, column number, Die index, color coding], which can be directly used for wafer distribution diagram visualization rendering or output as a spatial judgment heat map in the analysis report.

[0069] Exemplarily, referring to Figure 2 and Figure 3 , the electrical distribution of different wafers (1836 and 1840) is respectively displayed through the visualization output of the present application; The electrical distribution diagram of wafer 1836 can be observed to have obvious leakage high point groups in the center area, which can be judged to be caused by abnormal center thickness or film formation in the epitaxial process; The electrical distribution map of the wafer 1840 shows an abnormal increase in the on-off resistance of the edge region, which can be caused by uneven edge current density in the electroplating process.

[0070] Through the visual output mechanism of the present application, the electrical failure performance can be intuitively observed at the wafer level, significantly improving the process abnormality positioning capability.

[0071] S16, according to the multi-parameter comprehensive judgment data, and the established grading rule in the chip specification configuration, performing grading coding, and based on the chip position coordinates and the grading coding, constructing a packaging picking data file to generate packaging output data.

[0072] In one specific embodiment, the step of generating packaging output data includes: S161, based on the multi-parameter comprehensive judgment data matching the grading rule in the chip specification configuration, determining the target grading level of each chip; Specifically, according to the grading rule contained in the chip specification configuration record obtained by the wafer identification primary key, the multi-parameter comprehensive judgment data of each chip is matched and calculated.

[0073] The grading rule defines the electrical parameter allowable range of each grading level in the form of multiple threshold combinations as: A grade: all electrical parameter judgment results are passed; F grade: any one of the electrical parameters simultaneously exceeds the upper limit and is lower than the lower limit; B grade: in the absence of F grade, only one electrical parameter has a judgment result of "not passed"; C grade: in the absence of F grade, two or more electrical parameters have a judgment result of "not passed".

[0074] It should be noted that the "upper limit" and "lower limit" come from the chip specification configuration record extracted in step S142.

[0075] Through the above grading rule, the comprehensive judgment result of each chip is mapped to a unique target grading level, which serves as the basis for classifying the chip.

[0076] S162, converting the target grading level into a corresponding grading code, and combining the chip position coordinates with the grading code into chip grading data; Specifically, the target grading level of each chip is converted into a preset grading code, and the mapping relationship between the grading level and the grading code is provided by the grading dictionary preset in the chip specification configuration, which is represented as: A grade -> code "00"; B grade -> code "01"; C-file → Code "10"; F mode → Code "11".

[0077] The chip classification code is combined with the corresponding chip location coordinates to form the chip classification data for that chip. The data structure is as follows: [Wafer ID, Row ID, Column ID, Die Index, File Code]; It should be noted that the above encoding is not the only encoding method.

[0078] S163, perform a summary operation on all chip classification data according to the wafer number field, construct a packaging and picking data file, and output the packaging and picking data file as packaging output data; Specifically, all chip classification data are grouped by the wafer number field, with each group corresponding to one wafer; The [position coordinates + grade code] data of all chips in each group are stored in a structured manner to build a packaged picking data file; The organization structure of the packaged picking data file is as follows: Each line contains data for one chip; Each row contains the following fields: wafer number, row number, column number, die index, and file code; The file format is standard CSV or a custom data format that can be parsed by the encapsulation device, including but not limited to TXT or XML.

[0079] The packaging and sorting data file is used as packaging output data, which can be directly called by subsequent physical packaging or chip sorting systems to achieve automated sorting and precise packaging control. Through the yield analysis of this invention, the data processing time for 8 wafers is only 15 minutes, averaging 2 minutes per wafer, which is faster than the traditional manual processing time of 2 to 3 days. To further demonstrate the beneficial effects, samples were randomly selected for verification. The false positive rate was less than 0.2%, and the overall yield of each wafer was quickly given as 61%-78%. It can also quickly determine the cause of the fault in the center area of ​​the wafer, which facilitates subsequent epitaxial improvement.

[0080] The above embodiments are only used to illustrate the technical methods of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical methods of the present invention without departing from the spirit and scope of the technical methods of the present invention.

Claims

1. A multimode analysis method based on semiconductor electrical parameters, characterized in that, The method includes: S11, obtain test input data containing the original test file name and chip location identifier, parse the SetupTitle and DataName fields in the original test file, and generate the target data column location record; S12, based on the target data column position record, extract test voltage and current data from the original test file, including VGS, current ABS_ID, current ABS_IG, VDS and ID; S13, by performing electrical parameter extraction processing on the test voltage and current data, electrical parameters are generated, including threshold voltage value, on-resistance value, gate current value, breakdown voltage value and off-state leakage current value. S14, parse the unique laser marking code of the wafer and search the chip configuration database to generate the chip specification configuration. Perform item-by-item judgment on the electrical parameters according to the chip specification configuration to obtain multi-parameter comprehensive judgment data; S15, parse the chip position coordinates according to the chip position identifier, map the multi-parameter comprehensive judgment data to the wafer layout coordinates, and generate wafer electrical distribution output data; S16: Based on the comprehensive judgment data of multiple parameters and the predetermined grading rules in the chip specification configuration, perform grading encoding, and construct a packaging picking data file based on the chip position coordinates and grading encoding to generate packaging output data.

2. The multimode analysis method based on semiconductor electrical parameters according to claim 1, characterized in that, The steps to generate the target data column position record include: S111, perform a traversal operation based on the original test file name in the test input data, locate the SetupTitle field in the original test file, and extract the content of the field adjacent to the SetupTitle field as the test mode identifier; S112, perform a traversal operation based on the original test file name in the test input data, locate the DataName field in the original test file, and extract the field content of the row where the DataName field is located as the data column header array; S113, perform field correspondence judgment based on the test mode identifier and the field content of the data column header array, and record the column position of the corresponding data column header in the original test file as the target data column position.

3. The multimode analysis method based on semiconductor electrical parameters according to claim 2, characterized in that, The steps for extracting test voltage and current data from the original test file include: S121, when the test mode identifier contains "IdVg", extract the corresponding column values ​​of the VGS field and the current ABS_ID field from the original test file to serve as test voltage and current data; S122, when the test mode identifier contains "IgVg", extract the corresponding column values ​​of the VGS field and the current ABS_IG field from the original test file to serve as test voltage and current data; S123, if the test mode identifier contains "IdVd", extract the corresponding column values ​​of field VDS and field ID from the original test file to serve as test voltage and current data; S124, if the test mode identifier contains "Id_off", extract the corresponding column values ​​of field VDS and field ID from the original test file to serve as test voltage and current data.

4. The multimode analysis method based on semiconductor electrical parameters according to claim 3, characterized in that, The steps for generating the threshold voltage value in the electrical parameters include: a131, based on the test voltage and current data in test mode "IdVg", extract the VGS value corresponding to the current ABS_ID at two target current levels of 1uA and 1mA; a132, record the VGS value corresponding to 1uA as the first-level threshold voltage, and record the VGS value corresponding to 1mA as the second-level threshold voltage; a133 combines the first-level threshold voltage and the second-level threshold voltage into a threshold voltage value.

5. The multimode analysis method based on semiconductor electrical parameters according to claim 4, characterized in that, The steps for generating the on-resistance value in the electrical parameters include: b131, based on the test voltage and current data in test mode "IdVd", group VDS and ID according to VGS, with each group corresponding to a fixed VGS value; b132, perform a linear fit operation on ID and VDS in each VGS group and calculate the slope value; b133 takes the reciprocal of the slope of each linear fit and constructs the on-resistance value based on the reciprocal of the slope.

6. The multimode analysis method based on semiconductor electrical parameters according to claim 5, characterized in that, The steps for generating the gate current value in the electrical parameters include: c131, based on the test voltage and current data in test mode "IgVg", extract the current ABS_IG value corresponding to a VGS voltage value of 5V; c132 uses the current ABS_IG value when VGS=5V as the gate current value.

7. The multimode analysis method based on semiconductor electrical parameters according to claim 6, characterized in that, The steps for generating the breakdown voltage and off-state leakage current values ​​in the electrical parameters include: d131, based on the test voltage and current data in test mode "Id_off", identify the first VDS value where the current ID exceeds the preset current threshold, and record this VDS value as the breakdown voltage value; d132, within all VDS intervals before the breakdown voltage value, count the ID value with the largest absolute value and record this ID value as the off-state leakage current value.

8. The multimode analysis method based on semiconductor electrical parameters according to claim 7, characterized in that, The steps involved in performing item-by-item evaluation of electrical parameters based on chip specifications to obtain comprehensive multi-parameter evaluation data include: S141, parse the wafer number field and wafer batch field in the wafer laser marking code, and construct the wafer identification primary key; S142, based on the wafer identification primary key, retrieve matching records in the chip configuration database and extract chip specification configurations containing upper and lower limits of various electrical parameters; S143, If no matching record is found, the preset general chip specification configuration is used as a fallback scheme; S144: Compare each electrical parameter with the corresponding parameter threshold in the chip specification configuration, and output the judgment result for each electrical parameter; S145, merge the judgment results of all electrical parameters to generate multi-parameter comprehensive judgment data.

9. The multimode analysis method based on semiconductor electrical parameters according to claim 8, characterized in that, The steps for generating wafer electrical distribution output data include: S151, based on the chip location identifier, the wafer number field, row and column coordinate field, and die index field are parsed to construct the wafer layout coordinates; S152, matches the multi-parameter integrated judgment data of each chip with its corresponding wafer layout coordinates to form a structured coordinate-judgment data pair; S153, perform color coding based on the combined state of the judgment results for each coordinate-judgment data pair: S154, bind the above color code with the wafer layout coordinates to generate wafer electrical distribution output data.

10. The multimode analysis method based on semiconductor electrical parameters according to claim 9, characterized in that, The steps for generating encapsulated output data include: S161, based on the multi-parameter comprehensive judgment data matching chip specification configuration grading rules, determine the target grading level of each chip; S162, convert the target classification level into the corresponding classification code, and combine the chip position coordinates with the classification code to form chip classification data; S163, perform a summary operation on all chip classification data based on the wafer number field, construct a packaging and picking data file, and output the packaging and picking data file as packaging output data.

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