Method and device for measuring rise time and fall time, medium and equipment

Abstract

The invention provides a rise time and fall time measuring method and device, a medium and equipment, and relates to the technical field of chip testing. According to the technical scheme provided by the invention, a high-precision time measurement problem is converted into a digital scanning problem with controllable delay amount, so that the dependence of related technologies on expensive equipment such as a high-speed sampling rate analog-to-digital converter and a high-bandwidth oscilloscope is avoided; accurate measurement can be achieved only through low-cost digital devices such as a comparator, a programmable delay circuit and a trigger, and therefore the test cost is remarkably reduced on the premise that the chip test precision is met.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip testing, and in particular to a method and device for measuring rising time and falling time, a medium and equipment. BACKGROUND

[0002] The rising time (tr, Rising Time) and the falling time (tf, Falling Time) are respectively defined as the time required for a signal to rise from 10% to 90% of the amplitude or to fall from 90% to 10% of the amplitude. The two parameters reflect the steepness of the signal edge, and the shorter the rising time, the faster the signal changes. The rising time and the falling time are important parameters in signal analysis, and are used to measure the change speed of the signal from low level to high level or from high level to low level.

[0003] In the related art, the rising and falling time test method for the chip MCU usually uses a high-precision oscilloscope for measurement. However, as the signal frequency increases, the rising and falling time is usually in nanoseconds or even shorter, which requires the oscilloscope to have a high enough bandwidth to avoid measurement distortion. In the production test of the chip, this method has obvious limitations: on the one hand, the high-bandwidth oscilloscope itself is expensive, and if multiple channels need to be tested simultaneously, the cost will increase exponentially; on the other hand, the oscilloscope needs to be configured with trigger conditions, time bases and other parameters for different chips before testing, which also increases the time cost. In summary, the test method for the rising and falling time of the chip in the related art has the problem of high test cost. SUMMARY

[0004] The present application provides a method and device for measuring rising time and falling time, which can reduce the test cost while meeting the chip test accuracy.

[0005] In a first aspect, the present application provides a method for measuring rising time and falling time, which comprises: configuring different threshold levels for two comparators respectively; inputting a to-be-tested signal into the two comparators respectively, and comparing the edge waveform of the to-be-tested signal with the threshold level through the two comparators to obtain two same-direction digital pulse signals; controlling the first pulse signal that arrives first in the two digital pulse signals through a delay circuit to obtain a delay pulse signal; connecting the delay pulse signal to the data input end of an edge trigger, and connecting the second pulse signal that arrives later in the two digital pulse signals to the clock input end of the edge trigger; The delay circuit is controlled to gradually increase the delay duration of the delay pulse signal by a preset step value, and the output state of the edge trigger is read after each adjustment of the delay duration until the output state is flipped. The rise time or fall time of the signal under test is determined based on the target delay duration corresponding to the state flip of the output terminal.

[0006] By employing the above technical solution, a delay circuit gradually increases the delay duration of the first arriving pulse signal by a preset step value, and time comparison is performed using the setup time characteristics of an edge-triggered flip-flop. As the delay of the delayed pulse signal continuously increases and approaches the actual time difference between the two digital pulse signals, the edge-triggered flip-flop will capture the established data signal when the clock edge arrives, causing the output state to flip. At this point, the corresponding target delay duration is equal to the rise time or fall time of the signal under test. This solution transforms the high-precision time measurement problem into a digital scanning problem with controllable delay, avoiding the dependence of related technologies on expensive equipment such as high-speed sampling rate analog-to-digital converters and high-bandwidth oscilloscopes. Accurate measurement can be achieved using only low-cost digital devices such as comparators, programmable delay circuits, and flip-flops, thereby significantly reducing testing costs while meeting chip testing accuracy requirements.

[0007] Optionally, configuring different threshold levels for the two comparators includes: When testing the rise time of the signal under test, the first threshold level corresponding to the first pulse signal is configured to 10%-20% of the amplitude of the signal under test, and the second threshold level corresponding to the second pulse signal is configured to 80%-90% of the amplitude of the signal under test. The sum of the first threshold level and the second threshold level is 1. When testing the fall time of the signal under test, the first threshold level corresponding to the first pulse signal is configured to 80%-90% of the amplitude of the signal under test, and the second threshold level corresponding to the second pulse signal is configured to 10%-20% of the amplitude of the signal under test. The sum of the first threshold level and the second threshold level is 1.

[0008] Optionally, determining the rise time or fall time of the signal under test based on the target delay duration corresponding to the state flip of the output terminal includes: Before testing the signal under test, the inherent delay of the hardware loop consisting of the comparator, the edge trigger and the delay circuit is determined. The rise time or fall time of the signal under test is obtained by subtracting the inherent delay from the target delay time corresponding to the state flip of the output terminal.

[0009] Optionally, the determining the inherent delay of the hardware loop composed of the comparator, the edge trigger and the delay circuit comprises: adjusting the delay time length of the delay circuit to zero and reading the output end state of the edge trigger; controlling the delay circuit to gradually increase the delay time length by the preset step value and reading the output end state of the edge trigger after each adjustment of the delay time length until the output end state flips; recording the delay time length corresponding to the flipping of the output end state as the inherent delay of the entire hardware loop.

[0010] Optionally, the delay circuit comprises a first delay circuit and a second delay circuit, and the two comparators are connected with the first delay circuit and the second delay circuit respectively, and the delay control of the first pulse signal of the two digital pulse signals arriving first through the delay circuit comprises: delaying the first pulse signal of the two digital pulse signals arriving first through the first delay circuit to obtain a delay pulse signal; not delaying or keeping zero delay control on the second pulse signal of the two digital pulse signals arriving later through the second delay circuit.

[0011] Optionally, before the target delay time length corresponding to the flipping of the output end state, the method further comprises: when the output end state flips, recording the step number of the preset step value; calculating the product of the step number and the preset step value to obtain the target delay time length corresponding to the flipping of the output end state.

[0012] Optionally, the method further comprises: recording the starting time corresponding to 50% of the amplitude of the two digital pulse signals; determining the starting time as the rising edge time or the falling edge time of the digital pulse signal.

[0013] In a second aspect, the application provides a device for measuring the rise time and the fall time, which comprises: a configuration module configured to configure different threshold levels for two comparators respectively; a comparison module configured to input a to-be-measured signal into the two comparators respectively and compare the edge waveform of the to-be-measured signal with the threshold levels through the two comparators to obtain two digital pulse signals in the same direction; a delay module configured to delay the first pulse signal of the two digital pulse signals arriving first through a delay circuit to obtain a delay pulse signal; an edge trigger configuration module, configured to input the delay pulse signal into a data input end of an edge trigger, and input a second pulse signal of the two digital pulse signals which arrives later into a clock input end of the edge trigger; a step control module, configured to control the delay circuit to gradually increase the delay time length of the delay pulse signal by a preset step value, and read a state of an output end of the edge trigger after each adjustment of the delay time length, until the state of the output end is flipped; an output module, configured to determine the rise time or the fall time of the to-be-tested signal according to a target delay time length corresponding to the flipping of the state of the output end.

[0014] In a third aspect, a computer storage medium is provided, which stores a plurality of instructions. The instructions are adapted to be loaded by a processor and to execute any of the above methods.

[0015] In a fourth aspect, an electronic device is provided, which includes a processor, a memory and a transceiver. The memory is configured to store instructions, and the transceiver is configured to communicate with other devices. The processor is configured to execute the instructions stored in the memory, so that the electronic device performs any of the above methods.

[0016] In summary, the technical scheme of the present application has the following beneficial effects: 1. By converting the high-precision time measurement problem into a digital scanning problem of controllable delay amount, the dependence on expensive devices such as high-speed sampling rate analog-to-digital converters and high-bandwidth oscilloscopes is avoided, and only low-cost digital devices such as comparators, programmable delay circuits and flip-flops are needed to achieve accurate measurement, thereby significantly reducing the test cost while meeting the chip test accuracy.

[0017] 2. By determining the inherent delay of the hardware loop composed of the comparator, the edge trigger and the delay circuit once before testing, and recording and compensating it as a system parameter, since the inherent delay is a physical characteristic of the hardware loop itself and remains constant when the hardware configuration does not change, it only needs to be measured once at system initialization. When measuring the rise time or fall time of the to-be-tested signal of different chips, the measured target delay time length only needs to be reduced by the inherent delay to obtain the accurate result, without the need for recalibration or configuration for each measured chip. Compared with the traditional oscilloscope test method, which needs to set multiple parameters such as trigger level, trigger mode, time base position, vertical sensitivity, etc. for different signal characteristics of different chips, and needs to adjust these parameters again to ensure accurate capture and measurement of the waveform each time the measured chip is replaced, the inherent delay compensation mechanism greatly simplifies the test process, reduces the manual configuration and debugging time, and reduces the requirement for the skill level of the operator, thereby effectively reducing the test cost and improving the test efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 is a flowchart of a rise time and fall time measurement method of an embodiment of the present application; Figure 2 is a flowchart of a rise time and fall time measurement method provided by an embodiment of the present application; Figure 3 is a schematic diagram of a principle of a rise time and fall time measurement method provided by an embodiment of the present application; Figure 4 is a hardware architecture diagram of a rise time and fall time measurement method provided by an embodiment of the present application; Figure 5 is a structural schematic diagram of a rise time and fall time measurement device of an embodiment of the present application; Figure 6 is a structural schematic diagram of an electronic device provided by an embodiment of the present application.

[0019] Reference signs are described as follows: 600, electronic device; 601, processor; 602, communication bus; 603, user interface; 604, network interface; 605, memory. DETAILED DESCRIPTION

[0020] In order to enable persons skilled in the art to better understand the technical solutions in the specification, the technical solutions in the specification will be clearly and completely described below in conjunction with the drawings in the embodiments of the specification. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments.

[0021] In the description of the embodiments of the present application, the words such as “exemplary”, “for example”, or “for instance” are used to represent an example, illustration, or description. Any embodiment or design scheme described as “exemplary”, “for example”, or “for instance” in the embodiments of the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the words such as “exemplary”, “for example”, or “for instance” are intended to present the relevant concept in a specific manner.

[0022] In the description of the embodiments of the present application, the term "a plurality of" means two or more. For example, a plurality of devices means two or more devices, and a plurality of screen terminals means two or more screen terminals. In addition, the terms "first" and "second" are used only for the purpose of description and cannot be understood as indicating or implying relative importance or implicitly indicating the indicated technical features. Therefore, the features defined with "first" and "second" can explicitly or implicitly include one or more features. The terms "include", "contain", "have" and their variants mean "include but are not limited to", unless otherwise specifically emphasized.

[0023] Please refer to Figure 1 A flowchart of a measurement method of rise time and fall time provided by the embodiments of the present application. The method can be implemented by relying on a computer program, relying on a single-chip microcomputer, or running on a rise time and fall time measurement device based on the Von Neumann system. The computer program can be integrated in an application or run as a standalone tool application. The specific steps of the measurement method of rise time and fall time are described in detail below.

[0024] S101: Configure different threshold levels for two comparators respectively; Among them, the two comparators refer to two independent voltage comparison circuits, each comparator has independent input and output terminals, and can compare the input analog signal with the set reference voltage. The threshold level represents the reference voltage value used by the comparator to determine the high and low of the input signal. When the voltage of the signal to be measured exceeds or is lower than the threshold, the output state of the comparator will change. Different threshold levels are used to represent the reference voltage values set by the two comparators respectively, which are usually set at the lower position (such as 10%-20%) of the signal amplitude, and the other is set at the higher position (such as 80%-90%) of the signal amplitude.

[0025] Specifically, when performing this step, the peak-to-peak value or amplitude information of the signal to be measured needs to be obtained first, which can be obtained by pre-measurement or according to the known parameters of the signal source. Then, according to the measurement target, the threshold value is calculated. If the rise time is measured, the threshold value of the first comparator is set to the low percentage position of the signal amplitude as the starting detection point, and the threshold value of the second comparator is set to the high percentage position of the signal amplitude as the termination detection point. If the fall time is measured, the threshold value is set in reverse. During the configuration process, the stability and accuracy of the two threshold levels need to be ensured, and the actual output reference voltage will be verified by the calibration program whether it is consistent with the set value.

[0026] In some embodiments, the configuration of the threshold level can be achieved in various ways. Optionally, a digitally controlled DAC scheme can be adopted: first, the product of the signal amplitude to be measured and the target percentage is calculated by software to obtain the required threshold voltage value; then the voltage value is converted into the corresponding DAC digital code, taking into account the number of bits and the reference voltage for conversion calculation; then the digital code is written into the control register of the DAC chip through the control bus; finally, the corresponding analog voltage output by the DAC is connected to the reference input of the comparator.

[0027] S102: input the signal to be measured into two comparators respectively, and compare the edge waveform of the signal to be measured with the threshold level through the two comparators to obtain two digital pulse signals in the same direction; The signal to be measured refers to an analog electrical signal whose rising time or falling time characteristics need to be measured. The signal has a certain amplitude and edge change characteristics, and can be a square wave, a pulse wave or other periodic or non-periodic signals with obvious rising and falling edges.

[0028] The edge waveform is used to represent the transient waveform characteristics of the signal to be measured during the level transition process, including the rising edge and the falling edge. The edge waveform is usually not an ideal vertical transition, but has a certain slope and time span. The digital pulse signals in the same direction represent the digital signals output by the two comparators, which have the same polarity change direction. When measuring the rising time, both comparators are turned from low to high during the rising process of the signal to be measured, forming the same rising edge. When measuring the falling time, both comparators output the same falling edge.

[0029] Specifically, when performing this step, it is first necessary to ensure that the signal to be measured has been correctly connected to the input end of the measuring device, and the amplitude and frequency of the signal are within the measuring range of the device. Then the signal to be measured is sent to the positive input end of the two comparators through the signal distribution circuit, while the negative input end or the reference input end of the comparators has been set to the corresponding threshold level in the previous step. When the edge of the signal to be measured arrives, the two comparators will work independently according to the size relationship between the signal voltage and the respective threshold value: the first comparator will immediately flip its output state when the voltage of the signal to be measured crosses its threshold value, and the second comparator will also flip its output state when the voltage of the signal to be measured crosses its threshold value. Since the two threshold points are located at different positions of the edge of the signal to be measured, there is a time difference between the output flip times of the two comparators, and this time difference is the target parameter to be measured.

[0030] S103: delay control the first pulse signal that arrives first among the two digital pulse signals through a delay circuit to obtain a delayed pulse signal; The delay circuit refers to an electronic circuit capable of generating controllable time delay for input digital signals. The circuit can be an analog delay line, a digital delay timer, a programmable delay chip, or a digital delay logic based on a counter, and the delay amount can be precisely adjusted through an external control signal. The first pulse signal that arrives first represents the signal that arrives earlier at the edge flip moment among the two comparator output digital pulses. In the measurement of the rising time, this is the pulse generated by the low threshold comparator, because the measured signal will first pass through the low threshold during the rising process; in the measurement of the falling time, it is the pulse generated by the high threshold comparator, because the measured signal will first pass through the high threshold during the falling process. The delay pulse signal refers to an output signal that is shifted backward in time axis relative to the original first pulse signal after being processed by the delay circuit. The waveform characteristics of the signal remain unchanged, and only the time position is moved.

[0031] Specifically, when performing this step, it is first necessary to identify which pulse signal arrives first. This can be determined by pre-understanding the measurement type and threshold configuration, or by dynamically determining the order of the two signals through a timing comparison circuit. After determining the first pulse signal that arrives first, it is introduced into the input end of the delay circuit, and the second pulse signal that arrives later is directly bypassed or processed through zero delay. The delay circuit generates a corresponding delay amount according to the current control setting. The initial value of the delay amount is usually set to zero or a small reference value. The first pulse signal after delay is introduced from the output end of the delay circuit. At this time, the edge moment of the signal has been later than the original first pulse signal by the set delay time. This delay pulse signal will be compared with the second pulse signal without delay in the subsequent steps. By gradually increasing the delay amount, the first pulse that originally arrives first can gradually catch up with the second pulse that arrives later, until the timing relationship of the two pulses is reversed. The delay amount corresponding to this reversal point reflects the original time difference between the two pulses.

[0032] S104: introducing the delay pulse signal into the data input end of the edge flip-flop, and introducing the second pulse signal that arrives later among the two digital pulse signals into the clock input end of the edge flip-flop; The delay pulse signal is a first pulse signal obtained after processing by a delay circuit, whose time position has been artificially delayed. The edge trigger represents a kind of timing logic device, usually a D flip-flop, which has the working characteristic of locking the logic state of the data input end to the output end at the specific edge of the clock signal. The second pulse signal that arrives later is the signal that arrives later in the digital pulse output by the two comparators, which is the pulse generated by the high threshold comparator when measuring the rise time, and is the pulse generated by the low threshold comparator when measuring the fall time.

[0033] Specifically, when performing this step, a suitable edge trigger device is first selected, and the setup time and hold time of the device should be much smaller than the time parameter to be measured, so as to avoid the occurrence of metastable state in the critical state. Then, the physical connection is performed: the delay pulse signal output by the delay circuit is connected to the D input pin of the edge trigger, and the signal integrity is ensured, and a matching resistor can be connected in series or differential transmission can be used if necessary; at the same time, the second pulse signal that arrives later without delay processing is connected to the CLK input pin of the edge trigger. Such a connection configuration constitutes a timing detection mechanism: when the active edge of the second pulse signal that arrives later arrives, the edge trigger will immediately sample the level state of the data input end at this moment. If the delay pulse signal has not arrived due to insufficient delay at this time, the trigger output will be latched to low level; if the delay pulse signal has arrived in advance due to the delay applied, the trigger output will be latched to high level.

[0034] S105: controlling the delay circuit to gradually increase the delay time length of the delay pulse signal by a preset step value, and reading the output end state of the edge trigger after each adjustment of the delay time length until the output end state flips; The preset step value represents a fixed amount of increase of the delay time length each time, and the step value is preset, and the size of the step value determines the resolution of the measurement. The smaller the step value, the higher the measurement accuracy, but the longer the measurement time. The delay time length refers to the actual time delay amount of the input signal generated by the delay circuit, which starts from an initial value and increases by a step value each time. The flipping of the output end state refers to the change of the output of the edge trigger from one logic level to another logic level, which is usually from low level to high level or from high level to low level. The flipping point indicates that the timing relationship between the delay pulse signal and the second pulse signal has been reversed.

[0035] Specifically, when performing this step, first set the delay time of the delay circuit to an initial value, usually zero or a small reference value, at this time the first pulse signal still arrives earlier than the second pulse signal after delay. Then read the output state of the edge trigger, since the delayed pulse signal arrives before the active edge of the clock signal, the trigger will capture the high level state of the delayed pulse when sampling at the clock edge, the output is high level; Or if the delay is still not enough to make the delayed pulse arrive in advance, the output may be low, depending on the initial timing relationship. Then the controller sends a command to the delay circuit to increase the delay time by a preset step value, and the delay circuit adjusts its delay according to the new control parameter.

[0036] After adjustment, the device waits for signal stabilization, and then triggers the edge event of the signal to be measured again, or waits for the next period in the continuous signal mode, and the edge trigger re-executes the sampling and latching operation under the new delay condition. The controller reads the output state of the trigger again and compares it with the state read last time. If the output state does not change, it means that the current delay adjustment has not reached the critical point, and the device continues to increase the delay time by the step value, and repeats the above adjustment and reading process. This iterative loop continues until the output state of the trigger is found to have flipped compared with the previous one, which means that the arrival time of the delayed pulse signal has crossed the clock edge time of the second pulse signal, and the timing relationship of the two signals has reversed, and the delay time at this time is the approximate value of the original time difference of the two pulse signals, and the iteration process terminates.

[0037] In some embodiments, the delay scanning and state reading process can be implemented in various ways. Optionally, a sequential scanning scheme controlled by a microcontroller can be used: first initialize the delay control variable in the microcontroller, set the initial delay value and step value parameters; then write the current delay control value to the delay circuit through the digital interface, and the delay circuit adjusts the delay according to the value; then the microcontroller triggers the generation of the signal to be measured or waits for external signal events to ensure that the edge trigger completes the sampling operation; then the microcontroller reads the output state of the edge trigger through the digital input pin and stores the read value in a variable; next, the microcontroller compares the current read state with the previous read state, detects whether a flip occurs through XOR operation or conditional judgment; if no flip occurs, the microcontroller increases the delay control variable by a step value and jumps back to the second step to continue the loop; if a flip is detected, the microcontroller records the current delay value as the measurement result and exits the loop to enter the result processing stage.

[0038] S106: Determine the rise time or fall time of the signal to be measured according to the target delay time corresponding to the output state flip.

[0039] Wherein, the target delay time length represents the delay amount value set by the delay circuit when the output state turns over, which is a key parameter determined at the end of the delay scanning process, and it is approximately equal to the time difference between the two comparator output pulses. The rise time or fall time is used to represent the time required for the signal to be measured to convert from one stable level to another, and the rise time is usually defined as the time required for the signal to rise from a certain percentage of the low level to another percentage of the high level, and the fall time is the time required for the opposite process, and these two parameters are important indicators of signal quality and circuit speed.

[0040] Specifically, determining the final rise or fall time is a calculation process based on the original measured value and combined with the inherent error of the device. The host unit first multiplies the total delay step number recorded with the known unit step delay value, thereby calculating the original "target delay time length". This target delay time length represents the external compensation amount applied to align the digital signals output by the two comparators in time. However, this length is not the true rise or fall time of the signal to be measured, because it also contains the device error introduced by the inherent and asymmetric transmission delay of the two signal paths in the test device. Therefore, in order to obtain accurate measurement results, the host unit must retrieve a pre-measured and stored hardware loop calibration value from its internal storage. The calibration value accurately quantifies the above-mentioned device error. Finally, by subtracting the hardware loop calibration value from the calculated target delay time length, the influence of the device error can be eliminated, and the true and accurate rise time or fall time of the signal to be measured can be obtained.

[0041] Please refer to Figure 2 , Figure 2 A flowchart of a rise time and fall time measurement method provided by an embodiment of the present application is shown in FIG. 1. The specific implementation process of the embodiment of the present application will be described below with reference to FIG. 2. Figure 2

[0042] At this stage, the host unit first reads a pre-calibrated board-level initial delay calibration value from the memory, which is a key parameter that quantifies the inherent delay difference of different signal paths in the test hardware, and lays the foundation for subsequent accurate correction. Then, the device sets accurate reference voltages for the two high-speed comparators by configuring the digital-to-analog converter (DAC), and these voltages correspond to specific percentages (such as 10% and 90%) of the signal amplitude, which are used to generate the leading waveform and the trailing waveform when the edge of the signal to be measured passes. At the same time, the device sets the minimum delay step and the maximum scanning range TMAX of the programmable delay circuit, the former determines the time resolution of the measurement, and the latter serves as an over-time protection.

[0043] ​After initialization, the flow proceeds to either the rise time (tr) or fall time (tf) test branch, depending on external instructions or internal settings. Both branches share the same core measurement principle, which is an iterative delay sweep and synchronization detection loop. In this loop, the device applies a programmable delay to the leading waveform, and then simultaneously feeds the delayed leading waveform and the undelayed trailing waveform into an edge flip-flop acting as a synchronization detector. The goal of this loop is to incrementally increase the delay until the delayed leading waveform is exactly aligned in time with the trailing waveform, and both reach the flip-flop simultaneously. This synchronization point is precisely captured by monitoring the logic level transition at the flip-flop output. Before each incremental delay step, the device checks whether the current total delay exceeds TMAX to ensure that the test completes within the valid time.

[0044] The rise time and fall time test flows are logically mirror-symmetric. For the rise time (tr) test, the 10% level point generates the leading waveform, and the 90% level point generates the trailing waveform, and the device looks for the moment when the flip-flop output transitions from the initial logic low to high. Conversely, for the fall time (tf) test, the 90% level point generates the leading waveform, and the 10% level point generates the trailing waveform, and the device looks for the moment when the flip-flop output transitions from the initial logic high to low. Once the expected state transition is detected, the delay sweep loop terminates immediately, signifying that the target time interval has been successfully locked.

[0045] After the loop terminates, the flow proceeds to the final calculation and decision stage. The master unit multiplies the total number of delay steps accumulated during the loop by the preset delay step value to obtain an original target delay duration. Subsequently, to obtain the final accurate result, the device subtracts the board-level initial delay calibration value read during initialization from this original duration, effectively eliminating the device error caused by the hardware itself. This calibrated final value is the sought rise time (tr) or fall time (tf). Finally, the device can also compare this accurate measurement value with the preset specification range to determine whether the device under test is qualified.

[0046] On the basis of the above embodiment, as an optional implementation, the manner of configuring different threshold levels for the two comparators in step S101 can be implemented through the following steps.

[0047] When testing the rise time of the signal to be measured, the first threshold level corresponding to the first pulse signal is configured as 10%-20% of the amplitude of the signal to be measured, and the second threshold level corresponding to the second pulse signal is configured as 80%-90% of the amplitude of the signal to be measured, and the sum of the first threshold level and the second threshold level is 1.

[0048] In practice, the control unit first needs to determine the amplitude of the signal under test. This is usually done through an automated measurement process: the device samples the low voltage (V_low) when the signal is stable at the low level, and samples the high voltage (V_high) when the signal is stable at the high level, and then calculates the precise amplitude by V_high - V_low. Next, the control unit calculates two specific threshold voltages based on this amplitude. The first threshold level is set between 10% and 20% of the signal amplitude (usually 10%), and its specific voltage value is V_low + amplitude x 10%. The second threshold level is set between 80% and 90% of the signal amplitude (usually 90%), and its voltage value is V_low + amplitude x 90%. This selection is a common industry standard, and the purpose is to avoid the non-linear corner regions at the beginning and end of the signal, so as to ensure that the measurement is the most steep and linear part of the signal. The sum of the first threshold level and the second threshold level is 1, which should be understood as a description in the normalized coordinate system. That is, if the signal amplitude is considered as a whole of 1 unit (from 0% to 100%), the sum of the normalized values of 10% (0.1) and 90% (0.9) is exactly 1, which reflects the symmetry of the measurement points in the signal swing. In hardware implementation, the two calculated target voltage values are converted into digital codes and written into two high-precision digital-to-analog converters (DAC) channels. The DAC converts the digital code into a stable analog DC voltage as the reference input (for example, the inverting input) of the two high-speed comparators. The signal under test is simultaneously sent to the non-inverting input of the two comparators. After such configuration, when the rising edge of the signal under test passes through the first lower threshold voltage, the first comparator output flips, generating the first pulse signal (i.e., the leading waveform); when the signal voltage continues to rise and passes through the second higher threshold voltage, the second comparator output flips, generating the second pulse signal (i.e., the trailing waveform). The time difference between the two pulse signals, i.e., the target of the subsequent delay scan measurement, is the rise time.

[0049] When testing the fall time of the signal under test, the first threshold level corresponding to the first pulse signal is configured as 80%-90% of the amplitude of the signal under test, and the second threshold level corresponding to the second pulse signal is configured as 10%-20% of the amplitude of the signal under test, and the sum of the first threshold level and the second threshold level is 1.

[0050] The operation flow is similar to the rising time test. The first step is to determine the signal amplitude (V_high-V_low). Then, the control unit calculates the threshold voltages, but the assignment is opposite to the rising time test. The first threshold level is set to 80% to 90% of the signal amplitude (usually 90%), and its voltage value is V_low+amplitude×90%. The second threshold level is set to 10% to 20% of the signal amplitude (usually 10%), and its voltage value is V_low+amplitude×10%. This reverse configuration ensures that the measurement starts when the signal changes significantly from the stable high level and ends when it approaches the stable low level. The constraint that the sum of the first threshold level and the second threshold level is 1 is also applicable, i.e., the sum of 90% (0.9) and 10% (0.1) is 1, which guarantees the symmetry and standardization of the measurement interval relative to the total swing of the signal. At the hardware implementation level, the control unit writes the digital codes corresponding to the two calculated voltage values to the DAC, and the two stable DC voltages output by the DAC are sent to the reference input terminals of the two high-speed comparators. The key difference is that now the comparator corresponding to the higher threshold voltage (e.g., 90% amplitude point) generates the first pulse signal (leading waveform), while the comparator corresponding to the lower threshold voltage (e.g., 10% amplitude point) generates the second pulse signal (trailing waveform). When the falling edge of the signal under test passes the first higher threshold, the first pulse is triggered; and when it continues to fall and passes the second lower threshold, the second pulse is triggered. The generation time of these two pulse signals precisely frames the falling time interval that needs to be measured, providing accurate input signals for the subsequent delay scanning and synchronization detection steps.

[0051] Based on the above embodiment, as an optional implementation, the way to determine the rising time or falling time of the signal under test according to the target delay duration corresponding to the output state flip in step S106 can be implemented through the following steps S201-S202.

[0052] S201: Before testing the signal under test, determine the inherent delay of the hardware circuit composed of the comparator, the edge trigger, and the delay circuit; Wherein, the hardware circuit refers to a complete physical path that the signal must pass through inside the measuring instrument, which specifically refers to the entire signal link starting from the output terminals of the two comparators, passing through the respective wiring, one of which passes through the programmable delay circuit, and finally converging at the input terminal of the edge trigger and ultimately affecting its output.

[0053] The inherent delay is a fixed, non-ideal time delay that the hardware circuit itself has. This delay is caused by the response time of each electronic component (such as comparators, logic gates, flip-flops) itself, the propagation time of signals on the copper foil traces of the circuit board, and the small time difference between different signal paths due to physical length, load, etc. Even if the programmable delay circuit is set to zero delay, this inherent delay still exists objectively, and it is a device error source that needs to be accurately measured. For example, if an ideal, completely vertical edge pulse signal is simultaneously input to the input terminals of two comparators, in theory, the two comparators should output pulses at the same time, but due to the small differences in the transistor characteristics of the two comparators and the unequal lengths of the traces between them and the edge flip-flop, there will actually be a small time difference between the two signals reaching the input terminals of the edge flip-flop, and this time difference is part of the inherent delay.

[0054] The specific implementation is that the device does not use an external signal to be measured, but uses an internal signal source to generate a pulse signal with an extremely fast edge. This calibration pulse signal is split into two identical, theoretically completely synchronized signals by a precise power divider or symmetric fanout structure. These two signals are then fed into the input terminals of the two comparators used to generate the first pulse signal and the second pulse signal, respectively. Since the signals input to the two comparators are completely consistent in time, in an ideal case, their output pulses should also be synchronized, and the subsequent delay scan measurement result should be zero. However, due to the existence of inherent delay, the edge flip-flop does not detect synchronization in the initial state. At this time, the device starts the same delay scan process as normal measurement: a programmable digital delay is applied to one of the signals (for example, the one that should be the leading waveform), and the delay is gradually increased until the output state of the edge flip-flop flips, indicating that the two signals have achieved time alignment at their input terminals. At this moment, the total delay amount applied by the programmable delay circuit is exactly equal to the inherent delay of the hardware circuit. This value represents the amount of time needed to compensate for internal asymmetry of the hardware.

[0055] S202: Subtract the inherent delay from the target delay length corresponding to the output state flip to obtain the rise time or fall time of the signal to be measured.

[0056] In implementation, first, the master control unit acquires the total delay step number at the end of the cycle. Then, the master control unit performs a multiplication operation: multiplying the total step number by the precise duration of a single delay step set at the initialization of the device. Next, in order to obtain the final precise result, the master control unit reads the intrinsic delay value pre-determined and stored in the non-volatile memory in the calibration process in step S201. Then, a subtraction operation is performed: subtracting the read intrinsic delay value from the target delay duration just calculated. The physical meaning of this subtraction operation is to accurately strip off the hardware error part from the total measurement value containing the real signal time and the hardware error, and the remaining net value is the real time parameter of the signal to be measured.

[0057] On this basis, for the determination of the intrinsic delay, the following method can be used before testing: adjusting the delay duration of the delay circuit to zero and reading the output state of the edge trigger; controlling the delay circuit to gradually increase the delay duration by a preset step value, and reading the output state of the edge trigger after each adjustment of the delay duration, until the output state flips; recording the corresponding delay duration when the output state flips as the intrinsic delay of the entire hardware loop.

[0058] In implementation, a specific digital control word is sent to the programmable delay circuit, which adjusts its delay setting to zero, thereby minimizing the variable delay part in the signal path to isolate the inherent and unchangeable delay difference of the device. Then, the pulse signal with extremely fast edges generated by the internal calibration signal source is accurately divided into two, forming two theoretically completely synchronized calibration signals in time. The two signals are fed into two comparators in the subsequent measurement link, respectively, and then generate two pulse signals, one as the data input of the edge trigger and the other as the clock input. Due to the inherent difference between the two physical paths, one of the signals must arrive at the edge trigger before the other. According to its working principle, the edge trigger presents a certain logic state (high or low) at its output according to the principle of triggering according to the first signal and sampling the second signal. This initial output state is then read and recorded.

[0059] After the initial state is recorded, a loop control sequence is initiated. In each loop, first a command is sent to the delay circuit to increase the delay time by a preset step value based on the current value. This means that the signal which originally travels faster in the two paths is artificially delayed by a small amount. After the delay circuit stabilizes at the new delay setting, the synchronized calibration pulse signal is sent again through the entire hardware loop to the input of the edge trigger. At this moment, the output state of the edge trigger is read again and compared with the previously recorded initial state. If the two states are the same, it means that the added delay is not enough to change the order of arrival of the two signals. Therefore, the loop continues and the delay time will be increased by another step value. This process of increasing delay - reading state - comparing state will be repeated until the output state of the edge trigger changes (e.g. from low to high) after an increase in delay, i.e. a flip occurs. This flip event is a key indicator that the total delay amount has just compensated and slightly exceeded the inherent delay of the hardware loop, causing the order of arrival of the signals at the edge trigger to be reversed.

[0060] When the output state of the edge trigger flips, causing the scan loop to terminate, the current setting of the delay circuit is locked. At this time, an internal counter holds a value representing how many step increase operations have been performed in total since the zero delay. Then, a multiplication calculation is performed: multiply the total number of steps by the precise time represented by the preset step value. For example, if the step value is 1 picosecond and the loop terminates after 25 steps, the calculated delay time corresponding to the flip of the output state is 25 picoseconds. This calculated 25 picoseconds is confirmed as the inherent delay of the entire hardware loop. Finally, in order to ensure the long-term validity and reliability of this calibration value, the value representing the inherent delay (whether it is the number of steps or the calculated time value) is written into the non-volatile memory (such as EEPROM or flash memory) of the device.

[0061] In this way, the inherent delay value is permanently saved and will not be lost after the device is powered off, and is used to correct the original measurement results in subsequent actual signal measurements to eliminate the device error caused by the hardware itself.

[0062] The following will be combined Figure 3 to explain in detail how the preset step length delay measurement is used to measure the rise time and fall time. Please refer to Figure 3 , Figure 3 a schematic diagram of the principle of a rise time and fall time measurement method provided by an embodiment of the present application.

[0063] As Figure 3As shown, this method cleverly utilizes three key steps: dual threshold comparison, programmable digital delay, and edge-triggered comparison. It transforms the problem of measuring a continuous time interval into a step-delay scan of a reference signal until it flips in time with another reference signal, and determines the final time value by recording the total number of delay steps.

[0064] against Figure 3 (a) illustrates the rise time (tr) measurement process. The rising edge signal to be measured is first fed into a parallel dual-channel analog comparator (two-channel ACMP) circuit. One comparator has its threshold set at 10% of the signal amplitude, while the other has it set at 90%. As the input signal voltage rises and successively crosses these two thresholds, the comparator outputs two time-separated digital transition signals, labeled T1 (triggered at 10%) and T2 (triggered at 90%). The precise time interval between these two signal edges is the rise time tr to be measured. To quantify this time interval, the earlier T1 signal is fed into a high-precision programmable delay circuit, while the later T2 signal serves as a fixed time reference. This delay circuit can delay the T1 signal in precise and fixed minimum delay unit steps S. At the start of the measurement, the device compares the arrival order of the delayed T1 (denoted as T1+nS) with the reference T2 using an edge-triggered flip-flop (e.g., a D flip-flop). Initially, the delay is zero or very small, and T1+nS arrives before T2, causing the flip-flop to output a stable state (H as shown in the figure). The device then enters an iterative scanning process, increasing the delay applied to T1 by a step S in each cycle and comparing again. This process continues until the accumulated delay is large enough that the arrival time of T1+nS is exactly later than the arrival time of T2. At this critical moment, the output state of the edge-triggered flip-flop flips over (from H to L). The device records the total number of steps N required to cause this flip. Finally, the rise time tr to be measured can be accurately calculated by subtracting the inherent delay of the hardware loop from the product of the number of steps and the step value.

[0065] Similarly, Figure 3(b) The falling time (tf) measurement is based on the same principle as the rising time measurement, but with a different threshold definition in the initial comparison stage. For the falling edge, the thresholds of the two-channel comparator are set at 90% and 10% of the signal amplitude, respectively. When the signal voltage is falling from high, the T1 signal is first triggered at 90%, and then the T2 signal is triggered at 10%. The time interval between these two signal edges is the falling time tf to be measured. The subsequent processing procedure is exactly the same as the rising time measurement: the T1 signal, which occurs earlier, is sent into the programmable delay circuit for step-by-step delay, and compared with the T2 signal as the reference in the edge flip-flop for the arrival order. The device increases the delay step S by iteration until the flip-flop output state flips, and records the total step number N at this moment. The falling time tf is calculated by the formula tf = N x S. In this way, whether it is the rising time or the falling time, the measurement accuracy depends directly on the accuracy and stability of the minimum step S of the delay circuit, thus achieving high-precision, digital measurement of the tiny time interval.

[0066] Based on this, the step of the target delay time length specifically includes: when the output end state flips, recording the step number of the preset step value; Calculating the product of the step number and the preset step value to obtain the target delay time length corresponding to the output end state flipping.

[0067] The step number is a dimensionless pure digital count, which represents how many preset step value units need to be accumulated to reach a certain total delay amount. For example, if the preset step value is 10 picoseconds, then 5 step numbers correspond to a total delay of 50 picoseconds.

[0068] In a complete measurement cycle, the control logic drives the programmable delay circuit to apply an increasing delay to the earlier arriving Tl signal. The increase in the amount of delay is not continuous, but rather discrete and step-wise, with each step being exactly the pre-set step size. At the same time, a digital counter that is synchronized with the delay control logic is also incrementing in synchronism, with its count value reflecting in real time the number of steps that have been accumulated so far. After each delay increment and comparison of the order of arrival of the Tl and T2 signals, the device detects the state of the output of the edge-triggered flip-flop. In the initial phase of insufficient delay, the output will remain steadily in a certain logic state. As the amount of delay is continuously accumulated, when the total amount of delay crosses a critical point such that the originally leading Tl signal arrives exactly later than the T2 signal, the output state of the edge-triggered flip-flop will undergo a clear flip. A dedicated state change detection circuit will immediately capture this flip event and immediately generate a latch command. The command will act on the digital counter that is incrementing in synchronism, causing it to stop counting and to latch and save its current count value, i.e. the critical step number that caused the flip, into a dedicated data register.

[0069] The next calculation process is a multiplication operation performed by an arithmetic logic unit (ALU) or digital signal processor (DSP). The operation unit reads the step number (150) from the register as the multiplicand and reads the value representing the pre-set step size (10) as the multiplier, and performs the multiplication operation. The result of the operation, i.e. the product (150 multiplied by 10 to get 1500), is a new value. Finally, the device combines this value with the unit of the pre-set step size (picoseconds) to obtain the final target delay time, i.e. 1500 picoseconds. This calculation process converts the discrete, digital count value back to a continuous, analog time value, which is numerically equal to the total delay that needs to be applied to the Tl signal to align it in time with the T2 signal, and thus equivalent to the rise or fall time of the signal under test.

[0070] On the basis of the above embodiment, as an optional implementation, the starting time corresponding to the amplitude of 50% of the two digital pulse signals is recorded; The starting time is determined as the rising edge time or the falling edge time of the digital pulse signal.

[0071] Specifically, for each signal under test, the device is configured with a dedicated high-speed analog comparator. The comparator is configured to compare the amplitude of the signal under test with a pre-set reference value, and to output a logic state that is stable when the amplitude of the signal under test is less than the reference value and that is unstable when the amplitude of the signal under test is greater than the reference value. Figure 3The two threshold values are different, and the reference voltage of each comparator is set to 50% of the amplitude of the input signal. When the first digital pulse signal is input and starts to transition, the voltage will sweep through the 50% reference voltage point. At the moment when the voltage crosses the point, the output of the comparator will produce a sharp logic level jump. This jump edge is sent to the latch port of a time-to-digital converter (TDC) or a high-frequency counter as a high-precision trigger event. The time measurement unit immediately records the exact time of the trigger event, and this recorded time value is the starting time of the first signal. Similarly, the second digital pulse signal also triggers another time measurement unit through a completely independent comparator channel configured with its own 50% amplitude reference voltage, thereby recording the starting time of the second signal. Finally, the output of this step is two time data accurately quantified and stored in hardware registers, which represent the absolute times of the two signals passing through the midpoint level.

[0072] Next, the transition direction information of the signal needs to be obtained. This direction information can be pre-set (for example, the test program explicitly indicates that the rising edge is currently being measured) or dynamically determined by an auxiliary circuit (for example, by comparing the voltage before and after the edge occurs to determine whether it is rising or falling). Once the transition direction is known, the processing unit performs a conditional assignment operation. If the transition direction of the signal is from low to high, the value of the starting time recorded in the previous step is officially stored in a variable or register marked as the rising edge time. Conversely, if the signal is transitioning from high to low, the time value is stored in a variable or register marked as the falling edge time. This determination process is the basis for all subsequent advanced timing analysis. For example, to calculate the pulse width of a signal, the falling edge time of the signal is subtracted from the rising edge time; to calculate the propagation delay of a signal, the edge time of the device output port signal is subtracted from the edge time of the input port signal.

[0073] Based on the above embodiment, as an optional implementation, the delay circuit includes a first delay circuit and a second delay circuit, and the two comparators are connected with the first delay circuit and the second delay circuit respectively. The first pulse signal of the two digital pulse signals which arrives first is controlled by the delay circuit in step S103 to obtain the delay pulse signal. The method can be implemented by the following steps S301-S302.

[0074] S301: The first pulse signal of the two digital pulse signals which arrives first is controlled by the first delay circuit to obtain the delay pulse signal; Specifically, the core operation of this step is to first judge the arrival time of the two digital pulse signals, and identify which one is the "first pulse signal" that arrives first in time. After identifying the first pulse signal, the system guides it to the input end of the first delay circuit. Subsequently, through an external control mechanism, the "delay control" operation is performed on the first delay circuit, that is, a specific delay amount is set. The first delay circuit processes the "first pulse signal" input according to the setting, so that the propagation time of the signal in the circuit is accurately prolonged. Finally, a signal that is shifted backward in time axis relative to the original input signal, that is, a "delay pulse signal", is generated at the output end of the circuit.

[0075] S302: The second pulse signal that arrives later in the two digital pulse signals is not delayed or kept zero delay control by the second delay circuit.

[0076] Specifically, after the system identifies the "second pulse signal" that arrives later in the two digital pulse signals, the signal is sent to the second delay circuit. Unlike the first delay circuit, the second delay circuit is set to a non-delay or minimum delay working mode. This means that when the "second pulse signal" passes through it, the time delay it experiences is only the physical propagation delay inherent to the components and wiring that make up the circuit, and no variable delay set by external control is added to it. Therefore, the time position of the signal output from the second delay circuit is highly consistent with the time position of the input "second pulse signal".

[0077] The above steps are described in combination with the hardware architecture of the present application. Please refer to Figure 4 , Figure 4 A hardware architecture diagram of a rise time and fall time measurement method provided by an embodiment of the present application.

[0078] As shown in the figure, the figure depicts a hardware architecture for accurate measurement of digital signal rise time (tr) and fall time (tf). The whole measurement is scheduled and controlled by a core microcontroller unit (MCU). The basic measurement principle is to capture the time when the signal edge passes through the key point by comparing the signal to be measured with two preset voltage thresholds. Specifically, the architecture generates two accurate reference voltages corresponding to 10% and 90% of the full amplitude voltage (VI) of the signal to be measured through two digital-to-analog converters (DAC_1 and DAC_2) integrated in the MCU. These two reference voltages are sent to the reference input terminals of two high-speed analog comparators (ACMP_1 and ACMP_2). The signal to be measured is input to the signal input terminals of the two comparators at the same time, so that the instantaneous voltage of the signal is compared with the two thresholds of 10% VI and 90% VI in real time. When the signal passes through these two voltage points during the rising or falling process, the output state of the corresponding comparator will flip, thereby generating an accurate logic edge signal.

[0079] In the specific implementation of the rise time (tr) measurement task, the device will first set the two thresholds of 10% and 90% full amplitude voltage through the DAC inside the MCU and send them to the two high-speed comparators. When the voltage of the signal to be measured rises from low and first passes through the 10% threshold, the output state of the comparator (ACMP_1) connected thereto will flip, and this flip event is captured by the edge flip-flop as the start signal (START) of the entire measurement process. The start signal will immediately trigger one of the two delay circuits, which we call delay circuit_1. At the same time, the device will wait for the signal voltage to continue to rise and pass through the 90% threshold, and the flip of the output of the other comparator (ACMP_2) at this moment constitutes the stop signal (STOP). The key to the entire measurement is that the MCU continuously adjusts the delay amount applied to the delay circuit_1 through an iterative search process, and the goal is to make the start signal after accurate delay and the stop signal without delay completely coincide at a certain logic judgment point. The MCU judges whether the coincidence is reached by reading the feedback port (GPIO_3), and adjusts the delay configuration for the next time accordingly. When the delay value that makes the two signals "arrive" at the same time is finally found, this delay value itself is the rise time tr sought.

[0080] When the falling time (tf) needs to be measured, the whole logic process is similar, but the order of events and the circuit enabled are completely opposite. At this time, the signal falls from high level, and the first trigger is the comparator (ACMP_2) corresponding to the 90% threshold. This event now becomes the start signal of the falling time measurement. The start signal triggers another independent delay circuit, delay circuit_2. Then, when the signal voltage continues to fall and crosses the 10% threshold, the flip of the comparator ACMP_1 constitutes the end signal. Similarly, the MCU fine-tunes the delay of the delay circuit_2 through the control port (GPIO_2), and iteratively finds the accurate delay value that makes the delayed start signal and the end signal time coincident. The final locked delay value is subtracted by the inherent delay of the hardware, and the result is the falling time tf of the signal. Therefore, the real purpose of setting two independent delay circuits is to provide each with a dedicated, independently calibrated measurement channel for timing events in opposite directions of the rising edge and the falling edge, ensuring the flexibility and accuracy of the measurement and reducing the measurement cost.

[0081] The following is an apparatus embodiment of the present application, which can be used to perform the method embodiments of the present application. For details not disclosed in the apparatus embodiments of the present application, please refer to the method embodiments.

[0082] Please refer to Figure 5 , which shows a structure diagram of a rising time and falling time measurement device provided by an exemplary embodiment of the present application. The device can be realized by software, hardware or a combination of both to become all or part of the device. A rising time and falling time measurement device includes: A configuration module is configured to configure different threshold levels for the two comparators respectively; A comparison module is configured to input the to-be-measured signal into the two comparators respectively, and compare the edge waveform of the to-be-measured signal with the threshold level through the two comparators to obtain two same-direction digital pulse signals; A delay module is configured to control the delay of the first pulse signal arriving first in the two digital pulse signals through a delay circuit to obtain a delay pulse signal; An edge flip-flop configuration module is configured to connect the delay pulse signal to the data input end of an edge flip-flop, and connect the second pulse signal arriving later in the two digital pulse signals to the clock input end of the edge flip-flop; A step control module is configured to control the delay circuit to gradually increase the delay time length of the delay pulse signal by a preset step value, and read the state of the output end of the edge flip-flop after adjusting the delay time length each time until the state of the output end flips; An output module is configured to determine the rising time or falling time of the to-be-measured signal according to the target delay time length corresponding to the state flip of the output end.

[0083] The embodiment of the present application further provides a computer storage medium, which can store a plurality of instructions, and the instructions are suitable for being loaded and executed by a processor to implement the measurement method of the rise time and the fall time of the embodiment, and the specific implementation process can be referred to the specific description of the embodiment, which will not be repeated here.

[0084] Please refer to Figure 6 The embodiment of the present application provides a structural schematic diagram of an electronic device. As shown in the figure, Figure 6 The electronic device 600 can include at least one processor 601, at least one network interface 604, a user interface 603, a memory 605 and at least one communication bus 602.

[0085] The communication bus 602 is used to realize the connection and communication between the components.

[0086] The user interface 603 can include a display screen (Display) and a camera (Camera).

[0087] The network interface 604 can optionally include a standard wired interface and a wireless interface (such as a WI-FI interface).

[0088] The processor 601 can include one or more processing cores. The processor 601 connects various parts of the server through various interfaces and lines, executes various functions of the server and processes data by running or executing instructions, programs, code sets or instruction sets stored in the memory 605, and calling data stored in the memory 605. Optionally, the processor 601 can be realized in at least one of the hardware forms of digital signal processing, field programmable gate array and programmable logic array. The processor 601 can integrate a combination of one or several of central processing units, image processors and modems. Among them, the CPU mainly processes operating systems, user interfaces and application programs; the GPU is responsible for rendering and drawing the content to be displayed on the display screen; and the modem is used for processing wireless communication. It can be understood that the above-mentioned modem can also not be integrated into the processor 601, but be realized by a separate chip.

[0089] The memory 605 can include a random access memory and can also include a read-only memory. Optionally, the memory 605 includes a non-transitory computer-readable medium. The memory 605 can be used to store instructions, programs, codes, code sets, or instruction sets. The memory 605 can include a program storage area and a data storage area, where the program storage area can store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing the various method embodiments described above, etc.; the data storage area can store data involved in the various method embodiments described above, etc. The memory 605 can also optionally be at least one storage device located away from the aforementioned processor 601. As shown in Figure 6 The memory 605, as a computer storage medium, can include an operating system, a network communication module, a user interface module, and an application program of a rise time and a fall time measurement method.

[0090] In the electronic device 600 shown in Figure 6 In the electronic device 600 shown in

[0091] An electronic device readable storage medium stores instructions. When executed by one or more processors, the electronic device performs the method of one or more of the above embodiments.

[0092] It should be noted that, for the above-mentioned method embodiments, in order to simply describe, they are all expressed as a series of action combinations, but those skilled in the art should know that the application is not limited by the action order described, because according to the application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification all belong to preferred embodiments, and the actions and modules involved are not necessarily required by the application.

[0093] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0094] In several embodiments provided in the present application, it should be understood that the disclosed apparatus can be implemented in other manners. For example, the division of the apparatus embodiments is merely illustrative, and the units can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections can be indirect couplings or communication connections through some interfaces, devices or units, and can be in electrical, mechanical or other forms.

[0095] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one place, or distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0096] In addition, the functional units in each embodiment of the present application can be integrated into a processing unit, or each unit can be physically present separately, or two or more units can be integrated into one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0097] If the integrated unit is realized in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server or a network device, etc.) to execute all or part of the steps of the methods in the embodiments. The aforementioned storage medium includes: U disk, mobile hard disk, magnetic disk or optical disk, and various program codes that can be stored.

[0098] The above is only an exemplary embodiment of the present disclosure, and cannot limit the scope of the present disclosure. That is, any equivalent changes and modifications made in accordance with the teachings of the present disclosure are still within the scope of the present disclosure. Other embodiments of the present disclosure will be readily apparent to those skilled in the art upon considering the specification and practicing the disclosure. The present application is intended to cover any variations, uses or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or conventional techniques in the art not described in the present disclosure.

Claims

1. A method for measuring rise time and fall time, characterized in that, include: Configure different threshold levels for the two comparators; The signal to be tested is input into two comparators, and the edge waveform of the signal to be tested is compared with the threshold level by the two comparators to obtain two digital pulse signals in the same direction. The first pulse signal that arrives first among the two digital pulse signals is delayed by a delay circuit to obtain a delayed pulse signal. The delayed pulse signal is connected to the data input terminal of the edge trigger, and the second pulse signal that arrives later among the two digital pulse signals is connected to the clock input terminal of the edge trigger. The delay circuit is controlled to gradually increase the delay duration of the delay pulse signal by a preset step value, and the output state of the edge trigger is read after each adjustment of the delay duration until the output state is flipped. The rise time or fall time of the signal under test is determined based on the target delay duration corresponding to the state flip of the output terminal.

2. The method according to claim 1, characterized in that, The method of configuring different threshold levels for the two comparators includes: When testing the rise time of the signal under test, the first threshold level corresponding to the first pulse signal is configured to 10%-20% of the amplitude of the signal under test, and the second threshold level corresponding to the second pulse signal is configured to 80%-90% of the amplitude of the signal under test. The sum of the first threshold level and the second threshold level is 1. When testing the fall time of the signal under test, the first threshold level corresponding to the first pulse signal is configured to 80%-90% of the amplitude of the signal under test, and the second threshold level corresponding to the second pulse signal is configured to 10%-20% of the amplitude of the signal under test. The sum of the first threshold level and the second threshold level is 1.

3. The method according to claim 1, characterized in that, Determining the rise time or fall time of the signal under test based on the target delay duration corresponding to the output state flip includes: Before testing the signal under test, the inherent delay of the hardware loop consisting of the comparator, the edge trigger and the delay circuit is determined. The rise time or fall time of the signal under test is obtained by subtracting the inherent delay from the target delay time corresponding to the state flip of the output terminal.

4. The method according to claim 3, characterized in that, Determining the inherent delay of the hardware loop consisting of the comparator, the edge-triggered flip-flop, and the delay circuit includes: Adjust the delay duration of the delay circuit to zero, and read the output state of the edge trigger. The delay circuit is controlled to gradually increase the delay duration according to the preset step value, and the output state of the edge trigger is read after each adjustment of the delay duration until the output state flips. The delay time corresponding to the state transition of the output terminal is recorded as the inherent delay of the entire hardware circuit.

5. The method according to claim 1, characterized in that, The delay circuit includes a first delay circuit and a second delay circuit. The two comparators are respectively connected to the first delay circuit and the second delay circuit. The delay control of the first arriving pulse signal from the two digital pulse signals through the delay circuit to obtain a delayed pulse signal includes: The first delay circuit controls the delay of the first pulse signal that arrives first among the two digital pulse signals to obtain a delayed pulse signal. The second delay circuit either does not perform delay control on the second pulse signal that arrives later in the two digital pulse signals or maintains zero delay control.

6. The method according to claim 1, characterized in that, Before the target delay duration corresponding to the output state flip, the method further includes: When the output state flips, record the number of steps of the preset step value; Calculate the product of the number of steps and the preset step value to obtain the target delay duration corresponding to the state flip of the output terminal.

7. The method according to claim 1, characterized in that, The method further includes: Record the start time corresponding to 50% of the amplitude of the two digital pulse signals; The start time is determined as the rising edge or falling edge of the digital pulse signal.

8. A measuring device for rise time and fall time, characterized in that, The device includes: The configuration module is used to configure different threshold levels for the two comparators respectively; The comparison module is used to input the signal to be tested into two comparators respectively, and compare the edge waveform of the signal to be tested with the threshold level through the two comparators to obtain two digital pulse signals in the same direction; The delay module is used to control the delay of the first pulse signal that arrives first among the two digital pulse signals through a delay circuit, so as to obtain a delayed pulse signal. An edge trigger configuration module is used to connect the delayed pulse signal to the data input terminal of the edge trigger and to connect the second pulse signal, which arrives later among the two digital pulse signals, to the clock input terminal of the edge trigger. The step control module is used to control the delay circuit to gradually increase the delay duration of the delay pulse signal according to a preset step value, and to read the output state of the edge trigger after each adjustment of the delay duration until the output state is flipped. The output module is used to determine the rise time or fall time of the signal under test based on the target delay duration corresponding to the state flip of the output terminal.

9. A computer storage medium, characterized in that, The computer storage medium stores a plurality of instructions, which are adapted to be loaded by a processor and executed as described in any one of claims 1 to 7.

10. An electronic device, characterized in that, The device includes a processor, a memory, and a transceiver, wherein the memory is used to store instructions, the transceiver is used to communicate with other devices, and the processor is used to execute the instructions stored in the memory to cause the electronic device to perform the method as described in any one of claims 1 to 7.

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