Boost circuit self-checking method, boost circuit self-checking method and boost circuit self-checking device

Abstract

The invention provides a boost circuit self-checking method, a boost circuit self-checking method and a boost circuit self-checking device. The boost circuit self-checking method comprises the following steps: acquiring the voltage and the input voltage of a flying capacitor Cfly; when the change amplitude of the voltage of the flying capacitor Cfly is smaller than or equal to a first preset threshold value, a first driving signal is output to the lower switch tube T2, if the change amplitude of the voltage of the flying capacitor Cfly is smaller than or equal to a second preset threshold value, the lower switch tube T2 breaks down, and otherwise, the lower switch tube T2 passes the test; wherein the first preset threshold is greater than or equal to 0, and the second preset threshold is greater than or equal to 0. According to the self-checking method, self-checking can be carried out on the three-level boost circuit of the flying capacitor.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power supply, in particular to a self-checking method of boost circuit, a self-checking method of circuit and a device thereof. BACKGROUND

[0002] The flying capacitor three-level boost circuit has the advantages of improving equivalent switching frequency, reducing the volume and cost of inductance, and reducing the complexity of the inverter insulation impedance detection circuit, and is increasingly widely used in inverters. It can be understood that if a component in the flying capacitor three-level boost circuit fails, the boost circuit cannot work normally. Therefore, it is an urgent problem to design a self-checking method for the flying capacitor three-level boost circuit. SUMMARY

[0003] The present application relates to the technical field of power supply, in particular to a self-checking method of boost circuit, a self-checking method of circuit and a device thereof.

[0004] In order to achieve one of the above-mentioned purposes, an embodiment of the present application provides a self-checking method for a flying capacitor three-level boost circuit, the boost circuit comprising: an upper switch tube T1, a lower switch tube T2, a flying capacitor Cfly, a boost inductor L1, a diode D1, a diode D2, a diode D3, a relay RLY, a first capacitor Cin, a second capacitor BUSP and a third capacitor BUSN, the first end of the boost inductor L1 is electrically connected to the first end of the first capacitor Cin, the first end of the boost inductor L1 is respectively electrically connected to the first end of the upper switch tube T1 and the input end of the diode D1, the output end of the diode D1 is respectively electrically connected to the first end of the flying capacitor Cfly and the input end of the diode D2, the output end of the diode D2 is electrically connected to the first end of the second capacitor BUSP, the second end of the upper switch tube T1 is respectively electrically connected to the first end of the lower switch tube T2 and the second end of the flying capacitor Cfly, and the input end of the diode D3, the output end of the diode D3 is electrically connected to the first end of the relay RLY, the second end of the second capacitor BUSP is respectively electrically connected to the second end of the relay RLY and the first end of the third capacitor BUSP, the second end of the first capacitor Cin is respectively electrically connected to the second end of the lower switch tube T2 and the second end of the third capacitor BUSP; in the upper switch tube T1, the lower switch tube T2, the flying capacitor Cfly, the boost inductor L1, the diode D1, the diode D2, the diode D3, the relay RLY, the first capacitor Cin, the second capacitor BUSP and the third capacitor BUSN, the first end and the second end are different ends; comprising the following steps: obtaining the voltage of the flying capacitor Cfly , and the input voltage ; when When the voltage change of the flying capacitor Cfly is less than or equal to the first preset threshold, the lower switch T2 outputs the first drive signal. If the voltage change of the flying capacitor Cfly is less than or equal to the second preset threshold, the lower switch T2 fails. Otherwise, the lower switch T2 passes the test. The first preset threshold is greater than or equal to 0, and the second preset threshold is greater than or equal to 0.

[0005] As a further improvement to one embodiment of the present invention, the method further includes the following step: obtaining the voltage of the negative half-bus. ,when When the voltage change of the upper switch T1 is less than or equal to the third preset threshold, the upper switch T1 outputs the first drive signal. If the voltage change of the negative half bus is less than or equal to the fourth preset threshold or the voltage change of the flying capacitor Cfly is less than or equal to the fifth preset threshold, the upper switch T1 fails. Otherwise, the upper switch T1 passes the test. The third preset threshold is greater than or equal to 0, the fourth preset threshold is greater than or equal to 0, and the fifth preset threshold is greater than or equal to 0.

[0006] As a further improvement to one embodiment of the present invention, the method further includes the following step: obtaining the voltage of the positive half-bus. and the output voltage of the boost circuit Both the upper switch T1 and the lower switch T2 passed the test, and threshold and threshold At this time, the downward switching transistor T2 outputs the third drive signal, and then the voltage of the flying capacitor Cfly is obtained. ,if, When the condition is met, the lower switching transistor T2 is normal; otherwise, the lower switching transistor T2 is abnormal. Both threshold values ​​V1 and V2 are greater than zero. For the threshold, thr ≥ 0, The target charging voltage value for the flying capacitor Cfly.

[0007] As a further improvement of one embodiment of the present invention, the following step is also included: after the downward switching transistor T2 outputs the third driving signal, if the voltage of the flying capacitor Cfly is short-circuited, then the diode D2 is short-circuited.

[0008] As a further improvement to one embodiment of the present invention, the following step is also included: when both the upper switch T1 and the lower switch T2 pass the test, and the condition " ≥threshold "and conditions" threshold "At least one of them is not true, and Threshold First, obtain the voltage of the flying capacitor Cfly. The fourth drive signal is output from the upward-switching transistor T1. Then, the voltage of the flying capacitor Cfly is acquired. ,if, When the switch T1 is active, it is normal; otherwise, it is abnormal. The threshold V3 is greater than zero. For the threshold, thr2≥0, , The target value for the voltage change of the flying capacitor Cfly.

[0009] As a further improvement of one embodiment of the present invention, the following step is also included: after the fourth drive signal is output by the upward switching transistor T1, if the voltage of the flying capacitor Cfly is short-circuited, then the diode D1 is short-circuited.

[0010] This invention also provides a self-testing device for a three-level boost circuit with a flying capacitor. The boost circuit includes: an upper switch T1, a lower switch T2, a flying capacitor Cfly, a boost inductor L1, diodes D1, D2, and D3, a relay RLY, a first capacitor Cin, a second capacitor BUSP, and a third capacitor BUSN. The first terminal of the boost inductor L1 is electrically connected to the first terminal of the first capacitor Cin. The first terminal of the boost inductor L1 is also electrically connected to the first terminal of the upper switch T1 and the input terminal of diode D1. The output terminal of diode D1 is electrically connected to the first terminal of the flying capacitor Cfly and the input terminal of diode D2. The output terminal of diode D2 is electrically connected to the first terminal of the second capacitor BUSP. The second terminal of the upper switch T1 is electrically connected to the lower switch T2 and the third capacitor BUSP. The first terminal of switch T2, the second terminal of flying capacitor Cfly, and the input terminal of diode D3 are electrically connected to the first terminal of relay RLY. The second terminal of second capacitor BUSP is electrically connected to the second terminal of relay RLY and the first terminal of third capacitor BUSP. The second terminal of first capacitor Cin is electrically connected to the second terminal of lower switch T2 and the second terminal of third capacitor BUSP. Among upper switch T1, lower switch T2, flying capacitor Cfly, boost inductor L1, diodes D1, D2, D3, relay RLY, first capacitor Cin, second capacitor BUSP, and third capacitor BUSN, the first and second terminals are different terminals. The system includes the following module: an information acquisition module for acquiring the voltage of flying capacitor Cfly. and input voltage The first self-test module is used when... When the voltage change of the flying capacitor Cfly is less than or equal to the first preset threshold, the lower switch T2 outputs the first drive signal. If the voltage change of the flying capacitor Cfly is less than or equal to the second preset threshold, the lower switch T2 fails. Otherwise, the lower switch T2 passes the test. The first preset threshold is greater than or equal to 0, and the second preset threshold is greater than or equal to 0.

[0011] As a further improvement of one embodiment of the present invention, it further includes: a second self-test module, used to acquire the voltage of the negative half bus. ,when When the voltage change of the upper switch T1 is less than or equal to the third preset threshold, the upper switch T1 outputs the first drive signal. If the voltage change of the negative half bus is less than or equal to the fourth preset threshold or the voltage change of the flying capacitor Cfly is less than or equal to the fifth preset threshold, the upper switch T1 fails. Otherwise, the upper switch T1 passes the test. The third preset threshold is greater than or equal to 0, the fourth preset threshold is greater than or equal to 0, and the fifth preset threshold is greater than or equal to 0.

[0012] This invention also provides a circuit self-testing method, including multiple flying capacitor three-level boost circuits as described above, wherein the first terminal of the second capacitor BUSP and the second terminal of the third capacitor BUSN of the multiple flying capacitor three-level boost circuits are respectively used as output terminals, and the output terminals are electrically connected to the main bus; the self-testing method includes the following steps: applying the above self-testing method to the first boost circuit, when both the upper switch T1 and the lower switch T2 are normal, and both diodes D1 and D2 are not short-circuited, increasing the output voltage of the output terminal of the first boost circuit; performing the following operation on any second boost circuit: if the input voltage of the second boost circuit does not increase, then at least one of the diodes D1 and D2 in the second boost circuit is in a normal state, and then applying the above self-testing method to the second boost circuit; otherwise, both diodes D1 and D2 in the second boost circuit are short-circuited; the first and second boost circuits are different.

[0013] This invention also provides a circuit self-testing device, including multiple flying capacitor three-level boost circuits as described above, wherein the first terminal of the second capacitor BUSP and the second terminal of the third capacitor BUSN of the multiple flying capacitor three-level boost circuits are respectively used as output terminals, and the output terminals are electrically connected to the main bus; the self-testing method includes the following modules: a third self-testing module, used to apply the above self-testing method to the first boost circuit, when both the upper switch T1 and the lower switch T2 are normal, and both diodes D1 and D2 are not short-circuited, increasing the output voltage of the output terminal of the first boost circuit; a fourth self-testing module, used to perform the following operation on any second boost circuit: if the input voltage of the second boost circuit does not increase, then at least one of the diodes D1 and D2 in the second boost circuit is in a normal state, and then the above self-testing method is applied to the second boost circuit; otherwise, both diodes D1 and D2 in the second boost circuit are short-circuited; the first and second boost circuits are different.

[0014] Compared to existing technologies, the technical advantages of this invention are as follows: This invention provides a self-testing method for a boost circuit, a circuit self-testing method and apparatus thereof, the self-testing method comprising the following steps: obtaining the voltage of the flying capacitor Cfly. and input voltage ;when When the voltage change of the flying capacitor Cfly is less than or equal to the first preset threshold, the lower switch T2 outputs the first drive signal. If the voltage change of the flying capacitor Cfly is less than or equal to the second preset threshold, then the lower switch T2 has failed; otherwise, the lower switch T2 passes the test. The first preset threshold is greater than or equal to 0, and the second preset threshold is greater than or equal to 0. This self-test method can perform a self-test on a three-level boost circuit with a flying capacitor. Attached Figure Description

[0015] Figure 1 This is a structural diagram of the three-level boost circuit with a flying capacitor in an embodiment of the present invention; Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 7 A schematic diagram of the three-level boost circuit with a flying capacitor in an embodiment of the present invention; Figure 8 This is a flowchart illustrating the self-test method of the three-level boost circuit with a flying capacitor in an embodiment of the present invention. Detailed Implementation

[0016] The following description and accompanying drawings fully illustrate specific embodiments described herein to enable those skilled in the art to practice them. Some embodiments may include or substitute parts and features of other embodiments. The scope of the embodiments herein encompasses the entire scope of the claims and all available equivalents thereof. Throughout this document, the terms “first,” “second,” etc., are used only to distinguish one element from another without requiring or implying any actual relationship or order between the elements. Indeed, a first element can also be referred to as a second element, and vice versa. Furthermore, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that a structure, apparatus, or device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a structure, apparatus, or device. Without further limitation, an element defined by the phrase “comprising one…” does not exclude the presence of other identical elements in the structure, apparatus, or device that includes said element. The various embodiments described herein are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments; similar or identical parts between embodiments can be referred to interchangeably.

[0017] The terms "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer" used in this document to indicate orientation or positional relationships are based on the orientation or positional relationships shown in the accompanying drawings and are used only for the convenience of describing this document and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention. In the description herein, unless otherwise specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can refer to mechanical or electrical connections, or internal connections between two elements, or direct connections or indirect connections through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms according to the specific circumstances.

[0018] Embodiment 1 of the present invention provides a self-test method for a boost circuit with a flying capacitor and three-level circuitry, such as... Figure 1As shown, the boost circuit includes: an upper switch T1, a lower switch T2, a flying capacitor Cfly, a boost inductor L1, diodes D1, D2, and D3, a relay RLY, a first capacitor Cin, a second capacitor BUSP, and a third capacitor BUSN. The first terminal of the boost inductor L1 is electrically connected to the first terminal of the first capacitor Cin. The first terminal of the boost inductor L1 is also electrically connected to the first terminal of the upper switch T1 and the input terminal of diode D1. The output terminal of diode D1 is electrically connected to the first terminal of the flying capacitor Cfly and the input terminal of diode D2. The output terminal of diode D2 is electrically connected to the first terminal of the second capacitor BUSP. The second terminal of the upper switch T1 is electrically connected to the lower switch T2. The first terminal of transistor T2, the second terminal of flying capacitor Cfly, and the input terminal of diode D3 are electrically connected to the first terminal of relay RLY. The second terminal of second capacitor BUSP is electrically connected to the second terminal of relay RLY and the first terminal of third capacitor BUSP. The second terminal of first capacitor Cin is electrically connected to the second terminal of lower switch transistor T2 and the second terminal of third capacitor BUSP. Among upper switch transistor T1, lower switch transistor T2, flying capacitor Cfly, boost inductor L1, diodes D1, D2, D3, relay RLY, first capacitor Cin, second capacitor BUSP, and third capacitor BUSN, the first and second terminals are different terminals. Figure 8 As shown, it includes the following steps: Step 801: Obtain the voltage across the flying capacitor Cfly. and input voltage ; Step 802: When When the voltage change of the flying capacitor Cfly is less than or equal to the first preset threshold, the lower switch T2 outputs the first drive signal. If the voltage change of the flying capacitor Cfly is less than or equal to the second preset threshold, the lower switch T2 fails. Otherwise, the lower switch T2 passes the test. The first preset threshold is greater than or equal to 0, and the second preset threshold is greater than or equal to 0.

[0019] Optionally, the driving signal is a PWM (Pulse Width Modulation) signal with a duty cycle of D.

[0020] Here, as Figure 1 As shown, the input voltage of this boost circuit is This refers to the voltage input from the external power supply. The flying capacitor Cfly in this boost circuit plays a role in balancing the voltage and stabilizing the circuit; its voltage is typically the same as the input voltage. There is a specific pairing relationship. For example, it is... Part of, or through topological logic and Related. The lower switch T2 is a power switching device, such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), used to control the on / off state of the circuit. The duty cycle D is the ratio of the on-time of the drive signal to its period. The duty cycle D determines the proportion of time the lower switch T2 is on, thus affecting the circuit's voltage, current, and other parameters.

[0021] In a three-level boost circuit with a flying capacitor, the voltage across the flying capacitor... The switching logic of the circuit (multiple sets of switches working together) will limit it to a much smaller size. Within the range (e.g., (1 / 2 or 1 / 3, etc.).

[0022] If the lower switching transistor T2 experiences a short circuit fault, the on / off logic originally controlled by T2 will be disrupted, and the charging / discharging circuit of the flying capacitor Cfly may be directly connected to the input voltage. A shoot-through occurs, causing the voltage across the flying capacitor to rise uncontrollably, eventually approaching or even equaling the input voltage. .therefore, A threshold of ≤1 preset threshold is a preliminary characteristic of T2 short circuit.

[0023] To confirm whether T2 is truly short-circuited, a voltage disturbance test is required. A drive signal with a duty cycle of D is output to the lower switch T2. The switching of T2 will change the charging and discharging state of the flying capacitor Cfly, thus causing a change in the voltage of Cfly (e.g., increasing, decreasing, or fluctuating). If the voltage of the flying capacitor Cfly does not change or changes very little, it indicates that the lower switch T2 has lost its on / off control capability. That is, after a short circuit, the lower switch T2 is essentially always on, and the drive signal cannot change its state. Therefore, it can be determined that T2 is short-circuited.

[0024] In this embodiment, the following step is also included: obtaining the voltage of the negative half bus. ,when When the voltage change of the upper switch T1 is less than or equal to the third preset threshold, the upper switch T1 outputs the first drive signal. If the voltage change of the negative half bus is less than or equal to the fourth preset threshold or the voltage change of the flying capacitor Cfly is less than or equal to the fifth preset threshold, the upper switch T1 fails. Otherwise, the upper switch T1 passes the test. The third preset threshold is greater than or equal to 0, the fourth preset threshold is greater than or equal to 0, and the fifth preset threshold is greater than or equal to 0.

[0025] The upper switching transistor T1 is a power switching device (e.g., IGBT or MOSFET), which normally controls the voltage distribution in the circuit through "on / off". If the upper switching transistor T1 experiences a short circuit fault, it is equivalent to T1 being in a constantly conducting state, which will disrupt the original voltage distribution logic and affect the input voltage. The energy will be transferred uncontrollably to the negative half of the busbar, eventually leading to... The voltage amplitude is close to The voltage amplitude, therefore The value ≤ the third preset threshold becomes the initial abnormal signal of short circuit in the upper switch T1.

[0026] To further confirm the fault, it is necessary to actively apply the drive signal to the upper switch transistor T1 and attempt to turn it on and off as instructed. If the upper switch transistor T1 is functioning normally, the drive signal will change its on / off state, thereby affecting the negative half-bus voltage or the voltage of the flying capacitor.

[0027] If the upper switching transistor T1 is short-circuited (equivalent to being "soldered in the on state"), the drive signal cannot change the state of T1. The negative half-bus voltage will not change or will change very little, or the voltage of the flying capacitor Cfly will not change or will change very little. Therefore, after outputting a drive signal to the upper switching transistor T1, if the negative half-bus voltage does not change or changes very little, or the voltage of the flying capacitor Cfly does not change or changes very little, then the upper switching transistor T1 has failed.

[0028] In this embodiment, the following step is also included: obtaining the voltage of the positive half bus. and the output voltage of the boost circuit Both the upper switch T1 and the lower switch T2 passed the test, and threshold and threshold At this time, the downward switching transistor T2 outputs the third drive signal, and then the voltage of the flying capacitor Cfly is obtained. ,if, When the condition is met, the lower switching transistor T2 is normal; otherwise, the lower switching transistor T2 is abnormal. Both threshold values ​​V1 and V2 are greater than zero. For the threshold, thr ≥ 0, The target charging voltage value for the flying capacitor Cfly.

[0029] When satisfied threshold and threshold At this time, the lower switching transistor T2 is triggered to perform a self-test. These two conditions are based on the voltage across the flying capacitor Cfly when the circuit is operating normally. Positive half-bus voltage and total bus voltage The inherent voltage logic relationship is set to filter out applicable scenarios for the self-test driven by the lower switching transistor T2. The voltage after sampling and waveform generation... Set the target charging voltage value The lower switching transistor T2 generates a waveform with a duty cycle D2 (the duty cycle determines the on-time ratio of T2, thus controlling the charging and discharging of the flying capacitor). If ( This can be understood as the tolerance range), indicating that the flying capacitor voltage can be charged to the target value as expected, and the lower switching transistor T2 is driving normally. In addition, a short circuit occurred in the main bus during waveform generation, indicating that diode D2 is short-circuited (a short circuit in diode D2 will cause abnormal conduction in the main bus circuit).

[0030] here, Figure 6 The self-test current path (in red) of the boost circuit is shown when the lower switch T2 is turned on.

[0031] Figure 7 The diagram shows the self-test current path (red) of the boost circuit when the lower switch T2 is turned off. If... Then the current flows through path 1, if Then the current flows through path 2.

[0032] In this embodiment, the following steps are also included: after the downward switching transistor T2 outputs the third drive signal, if the voltage of the flying capacitor Cfly is short-circuited, then the diode D2 is short-circuited.

[0033] Here, capacitor voltage short circuit refers to the phenomenon where a capacitor exhibits short-circuit characteristics due to its extremely low capacitive reactance during charging, resulting in a sudden increase in current.

[0034] In this embodiment, the following step is also included: when both the upper switch T1 and the lower switch T2 pass the test, and the condition " ≥threshold "and conditions" threshold "At least one of them is not true, and Threshold First, obtain the voltage of the flying capacitor Cfly. The fourth drive signal is output from the upward-switching transistor T1. Then, the voltage of the flying capacitor Cfly is acquired. ,if, When the switch T1 is active, it is normal; otherwise, it is abnormal. The threshold V3 is greater than zero. For the threshold, thr2≥0, , The target value for the voltage change of the flying capacitor Cfly.

[0035] When the condition is met ≥threshold "and conditions" threshold "At least one of them is not true, and Threshold When this occurs, the upper switching transistor T1 is triggered to perform a self-test. This condition is based on the input voltage. and negative half bus voltage The normal logic relationship setting is used to filter the applicable scenarios for the self-test of the upper switch transistor T1.

[0036] Sampling and wave-flying capacitor voltage and voltage after wave generation Set the target value for voltage change. The upper switch T1 generates a waveform with a duty cycle D1, and the voltage change across the flying capacitor is altered by controlling the on / off state of the upper switch T1. If... This indicates that the change in the flying capacitor voltage is in line with expectations, and the upper switch T1 is driving normally. If the flying capacitor voltage is short-circuited during waveform generation, it indicates that diode D1 is short-circuited (a short circuit in diode D1 will cause abnormal conduction in the flying capacitor circuit).

[0037] here, Figure 2 This shows that the voltage across the flying capacitor Cfly is greater than When the upper switch T1 is turned on, the self-test current path of the boost circuit is shown in red.

[0038] Figure 3 This shows that the voltage across the flying capacitor Cfly is greater than When the upper switch T1 is turned off, the self-test current path of the boost circuit is shown in red.

[0039] Figure 4 This shows that the voltage across the flying capacitor Cfly is less than When the upper switch T1 is turned on, the self-test current path of the boost circuit is shown in red.

[0040] Figure 5 This shows that the voltage across the flying capacitor Cfly is less than When the upper switch T1 is turned off, the self-test current path of the boost circuit is shown in red.

[0041] In this embodiment, the following steps are also included: after the fourth drive signal is output by the upward switching transistor T1, if the voltage of the flying capacitor Cfly is short-circuited, then the diode D1 is short-circuited.

[0042] This embodiment provides a self-testing device for a three-level boost circuit with a flying capacitor. The boost circuit includes: an upper switch T1, a lower switch T2, a flying capacitor Cfly, a boost inductor L1, diodes D1, D2, and D3, a relay RLY, a first capacitor Cin, a second capacitor BUSP, and a third capacitor BUSN. The first terminal of the boost inductor L1 is electrically connected to the first terminal of the first capacitor Cin. The first terminal of the boost inductor L1 is also electrically connected to the first terminal of the upper switch T1 and the input terminal of diode D1. The output terminal of diode D1 is electrically connected to the first terminal of the flying capacitor Cfly and the input terminal of diode D2. The output terminal of diode D2 is electrically connected to the first terminal of the second capacitor BUSP. The second terminal of the upper switch T1 is electrically connected to the first terminal of the lower switch T2. The first terminal of transistor T2, the second terminal of flying capacitor Cfly, and the input terminal of diode D3 are electrically connected to the first terminal of relay RLY. The second terminal of second capacitor BUSP is electrically connected to the second terminal of relay RLY and the first terminal of third capacitor BUSP. The second terminal of first capacitor Cin is electrically connected to the second terminal of lower switch transistor T2 and the second terminal of third capacitor BUSP. Among upper switch transistor T1, lower switch transistor T2, flying capacitor Cfly, boost inductor L1, diodes D1, D2, D3, relay RLY, first capacitor Cin, second capacitor BUSP, and third capacitor BUSN, the first and second terminals are different terminals. The system includes the following module: an information acquisition module for acquiring the voltage of flying capacitor Cfly. and input voltage The first self-test module is used when... When the voltage change of the flying capacitor Cfly is less than or equal to the first preset threshold, the lower switch T2 outputs the first drive signal. If the voltage change of the flying capacitor Cfly is less than or equal to the second preset threshold, the lower switch T2 fails. Otherwise, the lower switch T2 passes the test. The first preset threshold is greater than or equal to 0, and the second preset threshold is greater than or equal to 0.

[0043] This embodiment also includes: a second self-test module, used to acquire the voltage of the negative half bus. ,when When the voltage change of the upper switch T1 is less than or equal to the third preset threshold, the upper switch T1 outputs the first drive signal. If the voltage change of the negative half bus is less than or equal to the fourth preset threshold or the voltage change of the flying capacitor Cfly is less than or equal to the fifth preset threshold, the upper switch T1 fails. Otherwise, the upper switch T1 passes the test. The third preset threshold is greater than or equal to 0, the fourth preset threshold is greater than or equal to 0, and the fifth preset threshold is greater than or equal to 0.

[0044] This embodiment three provides a circuit self-testing method, including multiple three-level boost circuits with flying capacitors as described in embodiment one, wherein the first terminal of the second capacitor BUSP and the second terminal of the third capacitor BUSN of the multiple three-level boost circuits with flying capacitors are respectively used as output terminals, and the output terminals are electrically connected to the main bus; the self-testing method includes the following steps: The self-test method in Example 1 is used for the first boost circuit. When both the upper switch T1 and the lower switch T2 are normal and both diodes D1 and D2 are not short-circuited, the output voltage of the first boost circuit is increased. For any second boost circuit, perform the following operation: if the input voltage of the second boost circuit does not increase, then at least one of diodes D1 and D2 in the second boost circuit is in a normal state, and then the self-test method in Example 1 is used on the second boost circuit; otherwise, both diodes D1 and D2 in the second boost circuit are short-circuited; the first and second boost circuits are different.

[0045] In practical applications, multiple multi-channel boost circuits are typically selected, and the outputs of these multiple boost circuits are connected in parallel and connected to the same bus to improve input and output power.

[0046] This embodiment four provides a circuit self-testing device, including multiple three-level boost circuits with flying capacitors as described in embodiment one. The first terminal of the second capacitor BUSP and the second terminal of the third capacitor BUSN in the multiple three-level boost circuits with flying capacitors are respectively used as output terminals, and the output terminals are electrically connected to the main bus. The self-testing method includes the following modules: The third self-test module is used to test the first boost circuit using the self-test method in Embodiment 1. When both the upper switch T1 and the lower switch T2 are normal and both diodes D1 and D2 are not short-circuited, the output voltage of the output terminal of the first boost circuit is increased. The fourth self-test module is used to perform the following operations on any second boost circuit: if the input voltage of the second boost circuit does not increase, then at least one of the diodes D1 and D2 in the second boost circuit is in a normal state, and then the self-test method in Example 1 is used on the second boost circuit; otherwise, both diodes D1 and D2 in the second boost circuit are short-circuited; the first and second boost circuits are different.

[0047] It should be noted that although the steps are described in a specific order above, it does not mean that the steps must be executed in the above specific order. In fact, some of these steps can be executed concurrently, or even in a different order, as long as the required function can be achieved.

[0048] This invention can be a system, method, and / or computer program product. A computer program product may include a readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement various aspects of the invention.

[0049] A readable storage medium can be a tangible device that holds and stores instructions for use by an instruction execution device. Readable storage media can include, for example, but not limited to, electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. More specific examples (a non-exhaustive list) of readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination thereof.

[0050] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A self-test method for a boost circuit with a flying capacitor and three-level operation, the boost circuit comprising: The circuit consists of an upper switching transistor T1, a lower switching transistor T2, a flying capacitor Cfly, a boost inductor L1, diodes D1, D2, and D3, a relay RLY, a first capacitor Cin, a second capacitor BUSP, and a third capacitor BUSN. The first terminal of the boost inductor L1 is electrically connected to the first terminal of the first capacitor Cin. The first terminal of the boost inductor L1 is also electrically connected to the first terminal of the upper switching transistor T1 and the input terminal of diode D1. The output terminal of diode D1 is electrically connected to the first terminal of the flying capacitor Cfly and the input terminal of diode D2. The output terminal of diode D2 is electrically connected to the first terminal of the second capacitor BUSP. The second terminal of the upper switching transistor T1 is electrically connected to the first terminal of the lower switching transistor T2 and the flying capacitor. The second terminal of Cfly and the input terminal of diode D3 are electrically connected to the first terminal of relay RLY. The second terminal of the second capacitor BUSP is electrically connected to the second terminal of relay RLY and the first terminal of third capacitor BUSP. The second terminal of the first capacitor Cin is electrically connected to the second terminal of lower switch T2 and the second terminal of third capacitor BUSP. Among the upper switch T1, lower switch T2, flying capacitor Cfly, boost inductor L1, diodes D1, D2, D3, relay RLY, first capacitor Cin, second capacitor BUSP, and third capacitor BUSN, the first terminal and the second terminal are different terminals. The system is characterized by including the following steps: Obtain the voltage across the flying capacitor Cfly. and input voltage ; when When the voltage change of the flying capacitor Cfly is less than or equal to the first preset threshold, the lower switch T2 outputs the first drive signal. If the voltage change of the flying capacitor Cfly is less than or equal to the second preset threshold, the lower switch T2 fails. Otherwise, the lower switch T2 passes the test. The first preset threshold is greater than or equal to 0, and the second preset threshold is greater than or equal to 0.

2. The self-testing method according to claim 1, characterized in that, It also includes the following steps: Obtain the voltage of the negative half bus ,when When the voltage change of the upper switch T1 is less than or equal to the third preset threshold, the upper switch T1 outputs the first drive signal. If the voltage change of the negative half bus is less than or equal to the fourth preset threshold or the voltage change of the flying capacitor Cfly is less than or equal to the fifth preset threshold, the upper switch T1 fails. Otherwise, the upper switch T1 passes the test. The third preset threshold is greater than or equal to 0, the fourth preset threshold is greater than or equal to 0, and the fifth preset threshold is greater than or equal to 0.

3. The self-testing method according to claim 2, characterized in that, It also includes the following steps: Obtain the voltage of the positive half bus and the output voltage of the boost circuit ; Both the upper switching transistor T1 and the lower switching transistor T2 passed the test, and threshold and threshold At this time, the downward switching transistor T2 outputs the third drive signal, and then the voltage of the flying capacitor Cfly is obtained. ,if, When the condition is met, the lower switching transistor T2 is normal; otherwise, the lower switching transistor T2 is abnormal. Both threshold values ​​V1 and V2 are greater than zero. For the threshold, thr ≥ 0, The target charging voltage value for the flying capacitor Cfly.

4. The self-testing method according to claim 3, characterized in that, It also includes the following steps: After the third drive signal is output from the downward switching transistor T2, if the voltage of the flying capacitor Cfly is short-circuited, then the diode D2 will be short-circuited.

5. The self-testing method according to claim 4, characterized in that, It also includes the following steps: When both the upper switch T1 and the lower switch T2 pass the test, and the condition is " ≥threshold "and conditions" threshold "At least one of them is not true, and Threshold First, obtain the voltage of the flying capacitor Cfly. The fourth drive signal is output from the upward-switching transistor T1. Then, the voltage of the flying capacitor Cfly is acquired. ,if, When the switch T1 is active, it is normal; otherwise, it is abnormal. The threshold V3 is greater than zero. For the threshold, thr2≥0, , The target value for the voltage change of the flying capacitor Cfly.

6. The self-testing method according to claim 5, characterized in that, It also includes the following steps: After the fourth drive signal is output from the upward switching transistor T1, if the voltage of the flying capacitor Cfly is short-circuited, then the diode D1 will be short-circuited.

7. A self-testing device for a boost circuit with a flying capacitor three-level circuit, the boost circuit comprising: The circuit consists of an upper switching transistor T1, a lower switching transistor T2, a flying capacitor Cfly, a boost inductor L1, diodes D1, D2, and D3, a relay RLY, a first capacitor Cin, a second capacitor BUSP, and a third capacitor BUSN. The first terminal of the boost inductor L1 is electrically connected to the first terminal of the first capacitor Cin. The first terminal of the boost inductor L1 is also electrically connected to the first terminal of the upper switching transistor T1 and the input terminal of diode D1. The output terminal of diode D1 is electrically connected to the first terminal of the flying capacitor Cfly and the input terminal of diode D2. The output terminal of diode D2 is electrically connected to the first terminal of the second capacitor BUSP. The second terminal of the upper switching transistor T1 is electrically connected to the first terminal of the lower switching transistor T2 and the flying capacitor. The second terminal of Cfly and the input terminal of diode D3 are electrically connected to the first terminal of relay RLY. The second terminal of the second capacitor BUSP is electrically connected to the second terminal of relay RLY and the first terminal of third capacitor BUSP. The second terminal of the first capacitor Cin is electrically connected to the second terminal of lower switch T2 and the second terminal of third capacitor BUSP. Among the upper switch T1, lower switch T2, flying capacitor Cfly, boost inductor L1, diodes D1, D2, D3, relay RLY, first capacitor Cin, second capacitor BUSP, and third capacitor BUSN, the first terminal and the second terminal are different terminals. The system is characterized by including the following modules: The information acquisition module is used to acquire the voltage of the flying capacitor Cfly. and input voltage ; The first self-test module is used when... When the voltage change of the flying capacitor Cfly is less than or equal to the first preset threshold, the lower switch T2 outputs the first drive signal. If the voltage change of the flying capacitor Cfly is less than or equal to the second preset threshold, the lower switch T2 fails. Otherwise, the lower switch T2 passes the test. The first preset threshold is greater than or equal to 0, and the second preset threshold is greater than or equal to 0.

8. The self-testing device according to claim 7, characterized in that, Also includes: The second self-test module is used to obtain the voltage of the negative half bus. ,when When the voltage change of the upper switch T1 is less than or equal to the third preset threshold, the upper switch T1 outputs the first drive signal. If the voltage change of the negative half bus is less than or equal to the fourth preset threshold or the voltage change of the flying capacitor Cfly is less than or equal to the fifth preset threshold, the upper switch T1 fails. Otherwise, the upper switch T1 passes the test. The third preset threshold is greater than or equal to 0, the fourth preset threshold is greater than or equal to 0, and the fifth preset threshold is greater than or equal to 0.

9. A self-testing method for a circuit, characterized in that, The system includes multiple three-level boost circuits with flying capacitors as described in claim 6, wherein the first terminal of the second capacitor BUSP and the second terminal of the third capacitor BUSN in the multiple three-level boost circuits with flying capacitors are respectively used as output terminals, and the output terminals are electrically connected to the main bus; the self-test method includes the following steps: The self-test method described in claim 6 is used on the first boost circuit. When both the upper switch T1 and the lower switch T2 are normal and both diodes D1 and D2 are not short-circuited, the output voltage of the output terminal of the first boost circuit is increased. For any second boost circuit, the following operation is performed: if the input voltage of the second boost circuit does not increase, then at least one of diodes D1 and D2 in the second boost circuit is in a normal state, and then the self-test method described in claim 6 is used on the second boost circuit; otherwise, both diodes D1 and D2 in the second boost circuit are short-circuited; the first and second boost circuits are not the same.

10. A circuit self-testing device, characterized in that, The system includes multiple three-level boost circuits with flying capacitors as described in claim 6, wherein the first terminal of the second capacitor BUSP and the second terminal of the third capacitor BUSN in the multiple three-level boost circuits with flying capacitors are respectively used as output terminals, and the output terminals are electrically connected to the main bus; the self-test method includes the following modules: The third self-test module is used to test the first boost circuit using the self-test method described in claim 6. When both the upper switch T1 and the lower switch T2 are normal and both diodes D1 and D2 are not short-circuited, the output voltage of the output terminal of the first boost circuit is increased. The fourth self-test module is used to perform the following operation on any second boost circuit: if the input voltage of the second boost circuit does not increase, then at least one of the diodes D1 and D2 in the second boost circuit is in a normal state, and then the self-test method described in claim 6 is used on the second boost circuit; otherwise, both diodes D1 and D2 in the second boost circuit are short-circuited; the first and second boost circuits are different.

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