Multi-axis synchronous control system based on VPX bus

Abstract

The invention discloses a multi-axis synchronous control system based on a VPX bus, and the system comprises a control platform initialization module which is used for generating a system initialization parameter set; the timing pulse synchronization module is used for forming a timing interrupt signal set; the state acquisition and error write-in module is used for acquiring an axial state, calculating an error signal and writing the error signal into the private area and the broadcast area; the distributed deviation coupling module is used for constructing a state synchronization data set; the sliding mode surface construction and state judgment module is used for constructing a non-singular fast terminal sliding mode surface; the sliding mode control output generation module is used for executing a distributed sliding mode control strategy; the optical signal conversion and data stream generation module is used for generating an optical signal control data stream; and the actuating mechanism driving module is used for converting the optical signal control data stream into an analog driving signal. According to the invention, a distributed sliding mode control and VPX high-speed synchronization mechanism is adopted, and multi-axis high-precision cooperative servo control is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of multi-axis motion control, and particularly relates to a multi-axis synchronous control system based on a VPX bus. BACKGROUND

[0002] The existing multi-axis motion control system usually relies on a traditional industrial bus or an Ethernet structure to realize data exchange and timing synchronization. In the high-speed multi-axis servo scene, the synchronization precision of such a system is limited by the software timing mechanism and network jitter, and it is difficult to ensure that each control axis responds consistently within the same control cycle. In the existing architecture, error signals are usually transmitted between different control cores through shared variables or periodic communication methods. However, the partition of the shared memory structure is not clear, and the timing of writing and reading error signals is not uniform, which leads to insufficient consistency of cross-axis data and affects the effect of synchronous control.

[0003] In terms of control algorithms, the traditional multi-axis control strategy mainly uses independent axis control. Even if the sliding mode control method is used, it is mostly limited to the internal structure of a single axis, and lacks a distributed state interaction mechanism. Although the non-singular fast terminal sliding mode control can improve the convergence speed and control accuracy of a single axis, it lacks a coupling structure of error signals and a collaborative sliding mode surface construction method suitable for a multi-core distributed environment, making it difficult to apply to multi-axis synchronous control occasions. The existing technology generally lacks a mechanism for realizing collaborative sliding mode control between multiple control cores using shared states, making it difficult to achieve strict multi-axis synchronization in complex equipment.

[0004] In terms of control links, the traditional control output mostly relies on serial communication or local signal distribution methods, lacks a unified high-speed optical signal coding and mapping rule, and the control output signal is likely to have inconsistent formats or timing deviations during transmission to the actuator, thereby affecting the synchronization precision of multi-axis servo motion.

[0005] Therefore, how to provide a multi-axis synchronous control system based on a VPX bus is a problem that those skilled in the art need to solve. SUMMARY

[0006] One object of the present application is to provide a multi-axis synchronous control system based on a VPX bus. The present application makes full use of the high-speed backplane communication capability of the VPX bus, the RapidIO low-latency interconnection mechanism, and the distributed sliding mode control algorithm. By establishing timing pulse synchronization, error signal sharing broadcast, distributed deviation coupling calculation, and sliding mode surface collaborative construction steps, high-speed state consistency and collaborative control between multiple DSP control cores are realized. The present application describes in detail the whole process of control output signals from distributed sliding mode control calculation, optical signal format coding to driving the actuator, and can complete high-precision multi-axis synchronous servo motion in equipment with strict real-time requirements. This method has the advantages of high synchronization precision, fast control response, strong anti-interference ability, and suitability for multi-core parallel architecture.

[0007] A multi-axis synchronous control system based on a VPX bus according to an embodiment of the present invention includes:

[0008] The control platform initialization module is used to configure the VPX control platform, establish RapidIO communication paths and GPIO synchronization lines, and generate a set of system initialization parameters.

[0009] The timing pulse synchronization module is used to generate timing pulses from the FPGA and broadcast them through the VPX backplane to form a set of timing interrupt signals.

[0010] The status acquisition and error writing module is used to acquire the axial status, calculate the error signal, and write it to the private area and broadcast area of ​​the shared memory after the DSP receives a timer interrupt.

[0011] The distributed deviation coupling module is used to calculate the distributed deviation coupling amount based on the shared broadcast area error signal and construct the state synchronization dataset;

[0012] The sliding surface construction and state determination module is used to construct a non-singular fast terminal sliding surface based on error signals and coupling quantities and generate intermediate variables for sliding mode control.

[0013] The sliding mode control output generation module is used to execute the distributed sliding mode control strategy and generate control output signals;

[0014] The optical signal conversion and data stream generation module is used to transmit the control output signal to the FPGA via RapidIO and then encode it according to the optical signal output rules to generate an optical signal control data stream.

[0015] The actuator drive module is used to convert optical signal control data streams into analog drive signals and drive the motors of each axis to complete multi-axis synchronous servo control.

[0016] Optionally, modules can be integrated using the following methods:

[0017] Initialize the VPX control platform, establish the RapidIO bus communication path and GPIO synchronization line, and generate a set of system initialization parameters;

[0018] Based on the system initialization parameter set, the FPGA fiber optic interface card periodically generates timing pulse signals and broadcasts the timing pulse signals through the synchronization channel of the P6 area of ​​the VPX backplane to obtain a set of timing interrupt signals.

[0019] Based on the set of timed interrupt signals, the real-time status information of the connected shaft is collected, the axial error signal is calculated, and written into the private area and shared broadcast area of ​​the local shaft in the shared memory.

[0020] Each DSP control core reads the error signals of other axes from the shared broadcast area, calculates the distributed deviation coupling amount based on the preset coupling weight parameters, and constructs a state synchronization dataset;

[0021] Based on the coupling amount of axial error signal and distributed deviation, a non-singular fast terminal sliding surface is constructed inside each DSP control core to execute sliding state determination logic and generate intermediate variables for sliding control.

[0022] The distributed non-singular fast terminal sliding mode control strategy is executed based on the intermediate variables of sliding mode control, a control output signal is generated, and the control output signal is written into the control quantity mapping area in shared memory.

[0023] The control output signal is transmitted to the FPGA fiber optic interface card via the RapidIO bus and converted into a standard optical signal format to generate an optical signal control data stream.

[0024] The optical signal controls the data stream output to the D / A digital-to-analog converter card, which then acts on each axis motor via the driver module to complete multi-axis synchronous servo control actions.

[0025] Optionally, the initialization of the VPX control platform, the establishment of the RapidIO bus communication path and the GPIO synchronization line, and the generation of the system initialization parameter set specifically include:

[0026] Load the VPX backplane configuration file, perform slot mapping on the P0 to P6 areas of the VPX backplane, determine the number of slots on the VPX backplane, and generate a set of VPX backplane parameters containing the configuration content of the power supply interface, communication interface and synchronization interface of each slot.

[0027] Configure the FPGA fiber optic interface card, including setting the synchronous clock frequency of the FPGA chip, generating clock source parameters for driving timing pulse signals, setting the number of channels of the SFP fiber optic communication interface configured on the FPGA board, and assigning channel numbers. Based on the synchronous clock frequency and the number of fiber optic channels, form a set of FPGA interface parameters.

[0028] Configure the DSP motion control card, including setting the number of DSP control cores enabled on the DSP motion control card, allocating a corresponding private memory space for each DSP control core to store the control status data of this axis, setting the axial error signal variable to represent the control deviation of this axis, and establishing the storage location and access index of the error signal for each DSP control core. Based on the number of DSP control cores, the size of the private memory space, and the axial error signal variable, a set of DSP control parameters is formed.

[0029] Configure the CPU main control card, set the instruction scheduling path between the CPU main control card and each DSP motion control card, determine the scheduling order and distribution rules of various control instructions within the CPU main control card, and establish a scheduling parameter mapping table for sending control instructions, parameter update instructions and status query instructions from the CPU main control card to each DSP motion control card.

[0030] Establish a RapidIO bus communication path, set the topology to a fully interconnected structure, define the RapidIO data path set, and set the transmission bandwidth;

[0031] Establish GPIO synchronous lines, set trigger signal tolerances, and form a set of GPIO interrupt response channels;

[0032] The VPX backplane parameter set, FPGA interface parameter set, DSP control parameter set, scheduling parameter mapping table, RapidIO data path set, and GPIO interrupt response channel set are summarized and integrated to form the system initialization parameter set.

[0033] Optionally, the step of periodically generating timing pulse signals based on the system initialization parameter set, and broadcasting the timing pulse signals through the synchronization channel of the P6 area of ​​the VPX backplane to obtain the timing interrupt signal set specifically includes:

[0034] Extract the FPGA interface parameter set from the system initialization parameter set, and set the synchronization pulse signal frequency and pulse period;

[0035] The FPGA fiber optic interface card uses an internal timer to generate a synchronous pulse signal according to a set pulse period, and outputs the corresponding synchronous trigger rising edge signal at the continuous period.

[0036] The synchronous rising edge trigger signal is broadcast to the GPIO interrupt channel set through the corresponding GPIO synchronous line in the P6 area of ​​the VPX backplane, and enters the interrupt interface of each DSP control core.

[0037] All DSP control cores generate a set of timer interrupt signals based on the synchronous rising edge trigger signal received from the GPIO synchronous line, forming a timer interrupt signal set.

[0038] Optionally, the step of collecting real-time status information of the connected shaft based on a set of timed interrupt signals, calculating the axial error signal, and writing it into the private area and shared broadcast area of ​​the local shaft in shared memory specifically includes:

[0039] After receiving the synchronous interrupt signal corresponding to its index in the set of timer interrupt signals, each DSP control core immediately starts the data acquisition process of the current control cycle, acquires the real-time position status value of the corresponding axis through the sensor channel connected to the core, and reads the target position reference value of the axis from the preset desired trajectory register.

[0040] The difference between the current position value collected and the expected position value read is calculated to obtain the axial error signal, and the timestamp of the error calculation is recorded to identify the corresponding sampling period number.

[0041] The axial error signal calculated in the current control cycle will be written to two different areas in the shared memory structure. One copy will be written to the private area of ​​the control core corresponding to this axis for local calling during the sliding surface construction process of this control core. The other copy will be written to the shared broadcast area for all DSP control cores to perform cross-core state reading and collaborative processing when performing distributed deviation coupling calculation.

[0042] All axial error signals stored in the shared broadcast area are transmitted at high speed through the RapidIO communication bus according to a unified shared memory address mapping rule on the system backplane, and are synchronously updated to all DSP control cores in a broadcast manner, thereby forming a complete set of broadcast-level error signals in each control core.

[0043] Optionally, each DSP control core reads error signals from other axes from the shared broadcast area, calculates the distributed deviation coupling amount based on preset coupling weight parameters, and constructs a state synchronization dataset, specifically including:

[0044] In the current control cycle, each DSP control core sequentially reads all axial error signals from the broadcast-level error signal set and excludes the axial error signal corresponding to its own axis during the reading process, retaining only the axial error signals from other control cores to form an external error set;

[0045] Each external axial error signal in the extracted external error set is subtracted from the axial error signal inside the control core to obtain the error difference between the control core and other control cores. All error differences are combined to form the error difference set corresponding to the current control cycle.

[0046] After obtaining the set of error differences in the current control cycle, each DSP control core performs a step-by-step multiplication operation between each error difference and the corresponding coupling weight parameter according to the coupling weight parameter matrix preset by the system. All multiplication results are accumulated and superimposed according to the control core index order to form the distributed deviation coupling amount of the control core in the current cycle. The distributed deviation coupling amount is used to describe the weighted deviation relationship between the error of this axis and the errors of other axes.

[0047] Each DSP control core will write the distributed deviation coupling amount calculated in the current control cycle into the control input buffer area corresponding to this axis in the shared memory. Each DSP control core will locally construct a state synchronization dataset consisting of the axial error signal of this axis and the corresponding distributed deviation coupling amount.

[0048] Optionally, the step of constructing a non-singular fast terminal sliding surface within each DSP control core based on the axial error signal and distributed deviation coupling, executing sliding state determination logic, and generating intermediate variables for sliding control specifically includes:

[0049] After entering the current control cycle, each DSP control core reads the axial error signal of its axis and the corresponding distributed deviation coupling amount from the state synchronization data set of its own control core.

[0050] Then, the error change rate of this axis is calculated based on the collected real-time status changes, and the error signal and the error change rate are combined to form the error signal pair for this period.

[0051] Each DSP control core, based on the sliding surface definition of non-singular fast terminal sliding mode control, substitutes the error signal and error rate of change into the sliding surface to construct an expression, thereby generating the local axis sliding surface variable;

[0052] The sliding mode state determination process is executed based on the sliding surface variables and the distributed deviation coupling quantity. The sliding mode state identification information is generated by determining and calculating each state quantity in the sliding mode state set. The sliding mode state identification information is stored inside the control core as one of the input bases for generating intermediate variables of the next stage of sliding mode control.

[0053] The sliding surface variables and the distributed deviation coupling amount are combined to form the intermediate variables of sliding mode control, thus forming a set of intermediate variables for sliding mode control.

[0054] Optionally, the step of executing a distributed non-singular fast terminal sliding mode control strategy based on the sliding mode control intermediate variables, generating a control output signal, and writing the control output signal into the control quantity mapping area in shared memory specifically includes:

[0055] When each DSP control core begins calculating the control output of the current control cycle, it reads the set of intermediate control quantities generated and stored in the previous stage from the local cache of the control core. The set of intermediate control quantities is composed of sliding surface variables and distributed deviation coupling quantities.

[0056] Among them, the sliding surface variable of this axis is used to characterize the current error state position of this axis on the sliding surface, and the distributed deviation coupling amount of this axis is used to characterize the cooperative deviation compensation relationship between this axis and other axes;

[0057] After reading the data, each DSP control core uses the two quantities mentioned above as the direct input quantities for forming the control output signal in the current control cycle, and prepares to proceed to the next step of the control law calculation process.

[0058] The sliding surface variables and the distributed deviation coupling amount are substituted as input parameters to execute the distributed non-singular fast terminal sliding mode control strategy, and the distributed non-singular fast terminal sliding mode control function is constructed.

[0059] Each DSP control core generates a control output signal for the current control cycle of the current axis based on the output result of the distributed non-singular fast terminal sliding mode control function, and forms a set of control output signals;

[0060] Each DSP control core writes the control output signal into the control quantity mapping area in the shared memory according to the preset address mapping rules, and submits the control output signal set to the FPGA fiber optic interface card through the RapidIO bus.

[0061] Optionally, the step of transmitting the control output signal to the FPGA fiber optic interface card via the RapidIO bus and converting it into a standard optical signal format to generate an optical signal control data stream specifically includes:

[0062] After generating the native axis control output signal, each DSP control core reads the path information for multi-board communication from the RapidIO data path set pre-configured during the system startup phase;

[0063] The RapidIO data path set consists of the available transmission links between boards, the port number of each link, the link bandwidth parameters, the link direction attributes, and the link priority parameters.

[0064] Each DSP control core searches for a link entry matching the board address in the RapidIO data path set based on the axis index of the control output signal and the corresponding FPGA fiber optic interface card board address. It then selects the RapidIO transmission path for transmitting the control output signal in the current cycle based on the link priority parameter, thereby determining the actual transmission link of the control output signal of this axis in the RapidIO network.

[0065] The control output signals generated by each DSP control core are sent to the FPGA fiber optic interface card via the RapidIO bus. Protocol mapping and format conversion operations are performed inside the FPGA to convert the control signals into data frame structures that conform to the standard optical communication protocol. The control signals are then segmented into frames according to the preset channel number, frame length parameters and data format encapsulation method to finally generate a set of control transmission frames for fiber optic channel transmission.

[0066] The control transmission frame set is sent to the FPGA fiber optic interface card via the RapidIO bus. Based on the synchronization frequency parameters and control frame format configuration parameters in the FPGA interface parameter set, the scheduling order of the control transmission frames, data category marking, and target channel allocation operations are completed respectively. On this basis, each control transmission frame is formatted according to the allocated optical signal conversion channel, converted into the corresponding optical signal control unit, and constitutes an optical signal format control set. Each optical signal control unit is used to instruct the real-time driving behavior of the actuator controlled by the corresponding DSP control core.

[0067] After the control output signal is transmitted to the FPGA fiber optic interface card via the RapidIO bus, it is converted into a format according to the preset optical signal output rules. The optical signal output rules include: assigning independent fiber optic channel numbers to different control axis numbers, adding start frame identifier, timestamp identifier and check field to the control output signal in each control cycle, and queuing the output signals of different control cores synchronously and packaging and encoding them according to a fixed frame structure.

[0068] Subsequently, the FPGA control logic module maps the encoded data into an optical signal modulation format that conforms to industrial standards, and the optical fiber transceiver module sends it to the corresponding actuator control interface, ultimately generating a set of optical signal control data streams to drive the synchronous action of the multi-axis actuator.

[0069] Optionally, the step of outputting the optical signal control data stream to the D / A digital-to-analog converter card, and then acting on each axis motor via the driver module to complete the multi-axis synchronous servo control action specifically includes:

[0070] The optical signal format control units output by the FPGA fiber optic interface card are obtained from the optical signal control data stream set, and the control axis corresponding to each optical signal is determined according to the mapping relationship between the optical signal channel number and the control axis index.

[0071] Each optical signal format control unit in the optical signal control data stream is input to the digital-to-analog converter (DAC). The DAC uses its internal photoelectric conversion circuit to convert the optical signal into an electrical signal. According to the preset DAC rules, the electrical signal is further converted into an analog control signal for driving the motor. The DAC rules include parsing the amplitude information of the optical signal, mapping the amplitude of the control quantity of the corresponding control axis, and adjusting the voltage and current output range. Finally, an analog control signal consistent with the actual actuator drive requirements is formed and provided to the next step.

[0072] The set of analog control signals is input to the driver module. The driver module performs current amplification, pulse modulation or torque command generation on each analog control signal according to the set of driver parameters to form a set of drive control commands.

[0073] The set of drive control commands is applied sequentially to the corresponding axial motors, so that each axial motor performs synchronous servo control actions according to the control cycle, forming a multi-axis servo execution set, thereby completing the multi-axis synchronous servo control under the current control cycle.

[0074] The beneficial effects of this invention are:

[0075] This invention improves upon the problems of asynchronous cross-axis error signals and insufficient data consistency in traditional multi-axis control systems by constructing a timing pulse synchronization mechanism and a shared memory dual-path error signal writing structure under the VPX bus architecture. This enables multiple DSP control cores to complete real-time status acquisition and error calculation under unified timing. Furthermore, this invention introduces a distributed deviation coupling calculation method based on the shared broadcast area, allowing each control core to construct cross-axis related control inputs locally using error signals from other axes, thereby enhancing the overall stability of multi-axis collaborative control.

[0076] At the control algorithm level, this invention combines the construction process of the non-singular fast terminal sliding surface with a distributed state synchronization mechanism, enabling the sliding mode control strategy to maintain a consistent dynamic convergence process in a multi-core architecture. Furthermore, by determining the sliding mode state and generating intermediate control quantities, it achieves uniformity of control laws across multiple axes, thereby maintaining the synchronous response characteristics of each control axis under high-speed conditions. In addition, this invention constructs a control output link based on RapidIO and an optical signal coding structure, realizing a standardized mapping process from the control output signal to the optical signal control data stream, reducing format deviations and timing errors that may occur during the transmission and conversion of the control output.

[0077] In summary, the present invention can achieve high timing synchronization accuracy and cross-axis state consistency in multi-axis servo systems, enabling multi-axis control actions to maintain good stability and response consistency in high-speed dynamic environments, thereby effectively improving the overall performance of multi-axis synchronous servo control. Attached Figure Description

[0078] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0079] Figure 1 This is a flowchart of a method for a multi-axis synchronous control system based on the VPX bus proposed in this invention;

[0080] Figure 2 This is a schematic diagram of a dual-path writing mechanism for error signals in a private area and a broadcast area in a multi-axis synchronous control system based on the VPX bus proposed in this invention.

[0081] Figure 3This is a schematic diagram of a distributed non-singular fast terminal sliding mode control structure in a multi-axis synchronous control system based on the VPX bus proposed in this invention. Detailed Implementation

[0082] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the invention, and therefore only show the components relevant to the invention.

[0083] refer to Figures 1-3 A multi-axis synchronous control system based on VPX bus, comprising:

[0084] The control platform initialization module is used to configure the VPX control platform, establish RapidIO communication paths and GPIO synchronization lines, and generate a set of system initialization parameters.

[0085] The timing pulse synchronization module is used to generate timing pulses from the FPGA and broadcast them through the VPX backplane to form a set of timing interrupt signals.

[0086] The status acquisition and error writing module is used to acquire the axial status, calculate the error signal, and write it to the private area and broadcast area of ​​the shared memory after the DSP receives a timer interrupt.

[0087] The distributed deviation coupling module is used to calculate the distributed deviation coupling amount based on the shared broadcast area error signal and construct the state synchronization dataset;

[0088] The sliding surface construction and state determination module is used to construct a non-singular fast terminal sliding surface based on error signals and coupling quantities and generate intermediate variables for sliding mode control.

[0089] The sliding mode control output generation module is used to execute the distributed sliding mode control strategy and generate control output signals;

[0090] The optical signal conversion and data stream generation module is used to transmit the control output signal to the FPGA via RapidIO and then encode it according to the optical signal output rules to generate an optical signal control data stream.

[0091] The actuator drive module is used to convert optical signal control data streams into analog drive signals and drive the motors of each axis to complete multi-axis synchronous servo control.

[0092] In this embodiment, the modules are interconnected using the following method:

[0093] Initialize the VPX control platform, establish the RapidIO bus communication path and GPIO synchronization line, and generate a set of system initialization parameters;

[0094] Based on the system initialization parameter set, the FPGA fiber optic interface card periodically generates timing pulse signals and broadcasts the timing pulse signals through the synchronization channel of the P6 area of ​​the VPX backplane to obtain a set of timing interrupt signals.

[0095] Based on the set of timed interrupt signals, the real-time status information of the connected shaft is collected, the axial error signal is calculated, and written into the private area and shared broadcast area of ​​the local shaft in the shared memory.

[0096] Each DSP control core reads the error signals of other axes from the shared broadcast area, calculates the distributed deviation coupling amount based on the preset coupling weight parameters, and constructs a state synchronization dataset;

[0097] Based on the coupling amount of axial error signal and distributed deviation, a non-singular fast terminal sliding surface is constructed inside each DSP control core to execute sliding state determination logic and generate intermediate variables for sliding control.

[0098] The distributed non-singular fast terminal sliding mode control strategy is executed based on the intermediate variables of sliding mode control, a control output signal is generated, and the control output signal is written into the control quantity mapping area in shared memory.

[0099] The control output signal is transmitted to the FPGA fiber optic interface card via the RapidIO bus and converted into a standard optical signal format to generate an optical signal control data stream.

[0100] The optical signal controls the data stream output to the D / A digital-to-analog converter card, which then acts on each axis motor via the driver module to complete multi-axis synchronous servo control actions.

[0101] In this embodiment, the initialization of the VPX control platform, the establishment of the RapidIO bus communication path and the GPIO synchronization line, and the generation of the system initialization parameter set specifically include:

[0102] Load the VPX backplane configuration file, perform slot mapping on the P0 to P6 areas of the VPX backplane, determine the number of slots on the VPX backplane, and generate a set of VPX backplane parameters containing the configuration content of the power supply interface, communication interface and synchronization interface of each slot.

[0103] Configure the FPGA fiber optic interface card, including setting the synchronous clock frequency of the FPGA chip, generating clock source parameters for driving timing pulse signals, setting the number of channels of the SFP fiber optic communication interface configured on the FPGA board, and assigning channel numbers. Based on the synchronous clock frequency and the number of fiber optic channels, form a set of FPGA interface parameters.

[0104] Configure the DSP motion control card, including setting the number of DSP control cores enabled on the DSP motion control card, allocating a corresponding private memory space for each DSP control core to store the control status data of this axis, setting the axial error signal variable to represent the control deviation of this axis, and establishing the storage location and access index of the error signal for each DSP control core. Based on the number of DSP control cores, the size of the private memory space, and the axial error signal variable, a set of DSP control parameters is formed.

[0105] Configure the CPU main control card, set the instruction scheduling path between the CPU main control card and each DSP motion control card, determine the scheduling order and distribution rules of various control instructions within the CPU main control card, and establish a scheduling parameter mapping table for sending control instructions, parameter update instructions and status query instructions from the CPU main control card to each DSP motion control card.

[0106] Establish a RapidIO bus communication path, set the topology to a fully interconnected structure, define the RapidIO data path set, and set the transmission bandwidth;

[0107] Establish GPIO synchronous lines, set trigger signal tolerances, and form a set of GPIO interrupt response channels;

[0108] The VPX backplane parameter set, FPGA interface parameter set, DSP control parameter set, scheduling parameter mapping table, RapidIO data path set, and GPIO interrupt response channel set are summarized and integrated to form the system initialization parameter set.

[0109] In this embodiment, the step of periodically generating timing pulse signals based on the system initialization parameter set by the FPGA fiber optic interface card and broadcasting the timing pulse signals through the synchronization channel of the P6 area of ​​the VPX backplane to obtain the timing interrupt signal set specifically includes:

[0110] Extract the FPGA interface parameter set from the system initialization parameter set, and set the synchronization pulse signal frequency and pulse period;

[0111] The FPGA fiber optic interface card uses an internal timer to generate a synchronous pulse signal according to a set pulse period, and outputs the corresponding synchronous trigger rising edge signal at the continuous period.

[0112] The synchronous rising edge trigger signal is broadcast to the GPIO interrupt channel set through the corresponding GPIO synchronous line in the P6 area of ​​the VPX backplane, and enters the interrupt interface of each DSP control core.

[0113] All DSP control cores generate a set of timer interrupt signals based on the synchronous rising edge trigger signal received from the GPIO synchronous line, forming a timer interrupt signal set.

[0114] In this embodiment, the step of collecting real-time status information of the connected shaft based on a set of timed interrupt signals, calculating the axial error signal, and writing it into the private area and shared broadcast area of ​​the local shaft in shared memory specifically includes:

[0115] After receiving the synchronous interrupt signal corresponding to its index in the set of timer interrupt signals, each DSP control core immediately starts the data acquisition process of the current control cycle, acquires the real-time position status value of the corresponding axis through the sensor channel connected to the core, and reads the target position reference value of the axis from the preset desired trajectory register.

[0116] The difference between the current position value collected and the expected position value read is calculated to obtain the axial error signal, and the timestamp of the error calculation is recorded to identify the corresponding sampling period number.

[0117] The axial error signal calculated in the current control cycle will be written to two different areas in the shared memory structure. One copy will be written to the private area of ​​the control core corresponding to this axis for local calling during the sliding surface construction process of this control core. The other copy will be written to the shared broadcast area for all DSP control cores to perform cross-core state reading and collaborative processing when performing distributed deviation coupling calculation.

[0118] All axial error signals stored in the shared broadcast area are transmitted at high speed through the RapidIO communication bus according to a unified shared memory address mapping rule on the system backplane, and are synchronously updated to all DSP control cores in a broadcast manner, thereby forming a complete set of broadcast-level error signals in each control core.

[0119] In this embodiment, each DSP control core reads error signals from other axes from the shared broadcast area, calculates the distributed deviation coupling amount based on preset coupling weight parameters, and constructs a state synchronization dataset, specifically including:

[0120] In the current control cycle, each DSP control core sequentially reads all axial error signals from the broadcast-level error signal set and excludes the axial error signal corresponding to its own axis during the reading process, retaining only the axial error signals from other control cores to form an external error set;

[0121] Each external axial error signal in the extracted external error set is subtracted from the axial error signal inside the control core to obtain the error difference between the control core and other control cores. All error differences are combined to form the error difference set corresponding to the current control cycle.

[0122] After obtaining the set of error differences in the current control cycle, each DSP control core performs a step-by-step multiplication operation between each error difference and the corresponding coupling weight parameter according to the coupling weight parameter matrix preset by the system. All multiplication results are accumulated and superimposed according to the control core index order to form the distributed deviation coupling amount of the control core in the current cycle. The distributed deviation coupling amount is used to describe the weighted deviation relationship between the error of this axis and the errors of other axes.

[0123] Each DSP control core will write the distributed deviation coupling amount calculated in the current control cycle into the control input buffer area corresponding to this axis in the shared memory. Each DSP control core will locally construct a state synchronization dataset consisting of the axial error signal of this axis and the corresponding distributed deviation coupling amount.

[0124] In this embodiment, the step of constructing a non-singular fast terminal sliding surface within each DSP control core based on the coupling amount of the axial error signal and the distributed deviation, executing the sliding state determination logic, and generating intermediate variables for sliding control specifically includes:

[0125] After entering the current control cycle, each DSP control core reads the axial error signal of its axis and the corresponding distributed deviation coupling amount from the state synchronization data set of its own control core.

[0126] Then, the error change rate of this axis is calculated based on the collected real-time status changes, and the error signal and the error change rate are combined to form the error signal pair for this period.

[0127] Each DSP control core, based on the sliding surface definition of non-singular fast terminal sliding mode control, substitutes the error signal and error rate of change into the sliding surface to construct an expression, thereby generating the sliding surface variable for this axis:

[0128] ;

[0129] in, This refers to the sliding surface variable corresponding to this axis, which consists of the error signal and the rate of change of the error of this axis. It is a state variable of the non-singular fast terminal sliding surface constructed within the DSP control core. This is the error signal for this axis during the current control cycle. The rate of change of the error signal for this axis is denoted as , and the amount of error change calculated by the DSP control core based on the sampled error signal changes is denoted as . Together with the error signal, they form an error signal pair. The sliding surface gain parameters used to construct the sliding surface of this axis. This refers to the numerator parameter in the sliding mode index of this axis. The denominator parameter of the sliding mode index at the end of the shaft, together with the numerator parameter, determines the terminal sliding mode index, satisfying the aforementioned constraint relationship. , For sign function processing of the local axis error signal, This indicates the axial index corresponding to the DSP control core, used to distinguish control variables, control parameters and control states of different axes, and its value range covers all axial control objects in the entire system.

[0130] This invention enables multi-axis control to achieve faster error convergence under dynamic conditions by constructing a non-singular fast terminal sliding surface based on the error signal and the error rate of change within a multi-DSP control core. The expression used to construct the sliding surface combines the amplitude term of the error signal with the error rate of change to form a sliding variable describing the current control state of the axis. An exponential term is used to adjust the nonlinear convergence characteristics of the sliding surface, allowing the control system to maintain good convergence speed within a small error range. This construction method accurately reflects the changing trend of the axial error in each control cycle and provides a valid basis for subsequent sliding state determination and control law generation. By combining this sliding surface construction strategy with a distributed error signal processing mechanism, this invention enables the control system to maintain high consistency and synchronization during multi-axis cooperative operation, thereby improving the stability and control accuracy of the multi-axis servo system during acceleration / deceleration and high-dynamic operation.

[0131] The sliding mode state determination process is executed based on the sliding surface variables and the distributed deviation coupling quantity. The sliding mode state identification information is generated by determining and calculating each state quantity in the sliding mode state set. The sliding mode state identification information is stored inside the control core as one of the input bases for generating intermediate variables of the next stage of sliding mode control.

[0132] The sliding surface variables and the distributed deviation coupling amount are combined to form the intermediate variables of sliding mode control, thus forming a set of intermediate variables for sliding mode control.

[0133] In this embodiment, the step of executing a distributed non-singular fast terminal sliding mode control strategy based on intermediate variables of sliding mode control, generating a control output signal, and writing the control output signal into the control quantity mapping area in shared memory specifically includes:

[0134] When each DSP control core begins calculating the control output of the current control cycle, it reads the set of intermediate control quantities generated and stored in the previous stage from the local cache of the control core. The set of intermediate control quantities is composed of sliding surface variables and distributed deviation coupling quantities.

[0135] Among them, the sliding surface variable of this axis is used to characterize the current error state position of this axis on the sliding surface, and the distributed deviation coupling amount of this axis is used to characterize the cooperative deviation compensation relationship between this axis and other axes;

[0136] After reading the data, each DSP control core uses the two quantities mentioned above as the direct input quantities for forming the control output signal in the current control cycle, and prepares to proceed to the next step of the control law calculation process.

[0137] By substituting the sliding mode surface variables and the distributed deviation coupling amount as input parameters into the distributed non-singular fast terminal sliding mode control strategy, a distributed non-singular fast terminal sliding mode control function is constructed:

[0138] ;

[0139] in, For the first Distributed non-singular fast terminal sliding mode control function for axes. This indicates the axial index corresponding to the DSP control core. This refers to the variable of the sliding surface corresponding to this axis. For the first Distributed deviation coupling of the shaft. For the first The first sliding surface gain parameter in axis sliding mode control is the preset proportional gain of the control law. For the first The second sliding surface gain parameter in axis sliding mode control is used to control the amplitude of the switching component. For the first The first power exponent parameter in axis sliding mode control is used to adjust the nonlinearity of the power function term in the sliding mode control law. For the first The second power-law parameter in axis sliding mode control is used as an enhancement term to construct a fast terminal sliding mode structure. For the first The sign term obtained by performing sign function operation on the shaft sliding surface variable is used to determine the switching direction of the control law;

[0140] This invention achieves higher dynamic consistency and convergence performance in multi-axis cooperative servo control by substituting sliding mode surface variables and distributed deviation coupling quantities as input parameters into a distributed non-singular fast terminal sliding mode control function. The control function consists of a sliding mode gain term, a power term, and a sign term. The first sliding mode gain parameter is used to adjust the response speed of the sliding mode surface to errors, the second sliding mode gain parameter is used to adjust the output amplitude of the control quantity, the power term is used to form nonlinear accelerated convergence characteristics, and the sign term is used to determine the control switching direction. Through this expression, the control output can be quickly pulled back to the system state when the error is large and maintain stable convergence when the error is small, thereby effectively improving the oscillation and lag problems that are prone to occur in traditional control methods under high dynamic and multi-axis coupling conditions. Combined with the distributed deviation coupling structure, each DSP control core can achieve cross-axis cooperative adjustment based on a unified sliding mode control strategy, enabling the multi-axis system to maintain high synchronization accuracy and trajectory consistency during high-speed operation, load disturbances, and frequent acceleration and deceleration, thus improving the overall control stability.

[0141] Each DSP control core generates a control output signal for the current control cycle of the current axis based on the output result of the distributed non-singular fast terminal sliding mode control function, and forms a set of control output signals;

[0142] Each DSP control core writes the control output signal into the control quantity mapping area in the shared memory according to the preset address mapping rules, and submits the control output signal set to the FPGA fiber optic interface card through the RapidIO bus.

[0143] In this embodiment, the step of transmitting the control output signal to the FPGA fiber optic interface card via the RapidIO bus and converting it into a standard optical signal format to generate an optical signal control data stream specifically includes:

[0144] After generating the native axis control output signal, each DSP control core reads the path information for multi-board communication from the RapidIO data path set pre-configured during the system startup phase;

[0145] The RapidIO data path set consists of the available transmission links between boards, the port number of each link, the link bandwidth parameters, the link direction attributes, and the link priority parameters.

[0146] Each DSP control core searches for a link entry matching the board address in the RapidIO data path set based on the axis index of the control output signal and the corresponding FPGA fiber optic interface card board address. It then selects the RapidIO transmission path for transmitting the control output signal in the current cycle based on the link priority parameter, thereby determining the actual transmission link of the control output signal of this axis in the RapidIO network.

[0147] The control output signals generated by each DSP control core are sent to the FPGA fiber optic interface card via the RapidIO bus. Protocol mapping and format conversion operations are performed inside the FPGA to convert the control signals into data frame structures that conform to the standard optical communication protocol. The control signals are then segmented into frames according to the preset channel number, frame length parameters and data format encapsulation method to finally generate a set of control transmission frames for fiber optic channel transmission.

[0148] The control transmission frame set is sent to the FPGA fiber optic interface card via the RapidIO bus. Based on the synchronization frequency parameters and control frame format configuration parameters in the FPGA interface parameter set, the scheduling order of the control transmission frames, data category marking, and target channel allocation operations are completed respectively. On this basis, each control transmission frame is formatted according to the allocated optical signal conversion channel, converted into the corresponding optical signal control unit, and constitutes an optical signal format control set. Each optical signal control unit is used to instruct the real-time driving behavior of the actuator controlled by the corresponding DSP control core.

[0149] After the control output signal is transmitted to the FPGA fiber optic interface card via the RapidIO bus, it is converted into a format according to the preset optical signal output rules. The optical signal output rules include: assigning independent fiber optic channel numbers to different control axis numbers, adding start frame identifier, timestamp identifier and check field to the control output signal in each control cycle, and queuing the output signals of different control cores synchronously and packaging and encoding them according to a fixed frame structure.

[0150] Subsequently, the FPGA control logic module maps the encoded data into an optical signal modulation format that conforms to industrial standards, and the optical fiber transceiver module sends it to the corresponding actuator control interface, ultimately generating a set of optical signal control data streams to drive the synchronous action of the multi-axis actuator.

[0151] In this embodiment, the step of outputting the optical signal control data stream to the D / A digital-to-analog converter card, and then acting on each axis motor via the driver module to complete the multi-axis synchronous servo control action specifically includes:

[0152] The optical signal format control units output by the FPGA fiber optic interface card are obtained from the optical signal control data stream set, and the control axis corresponding to each optical signal is determined according to the mapping relationship between the optical signal channel number and the control axis index.

[0153] Each optical signal format control unit in the optical signal control data stream is input to the digital-to-analog converter (DAC). The DAC uses its internal photoelectric conversion circuit to convert the optical signal into an electrical signal. According to the preset DAC rules, the electrical signal is further converted into an analog control signal for driving the motor. The DAC rules include parsing the amplitude information of the optical signal, mapping the amplitude of the control quantity of the corresponding control axis, and adjusting the voltage and current output range. Finally, an analog control signal consistent with the actual actuator drive requirements is formed and provided to the next step.

[0154] The set of analog control signals is input to the driver module. The driver module performs current amplification, pulse modulation or torque command generation on each analog control signal according to the set of driver parameters to form a set of drive control commands.

[0155] The set of drive control commands is applied sequentially to the corresponding axial motors, so that each axial motor performs synchronous servo control actions according to the control cycle, forming a multi-axis servo execution set, thereby completing the multi-axis synchronous servo control under the current control cycle.

[0156] Example 1:

[0157] To verify the feasibility of this invention in practice, it was applied to a multi-axis high-speed servo workstation. This workstation contains multiple parallel execution axes, driven by independent DSP control cores. Each control axis undertakes an independent but strictly synchronized high-speed adjustment action. Traditional multi-axis control systems, relying on general Ethernet or software synchronization mechanisms, are prone to periodic asynchrony, large error sharing delays, and cross-axis response drift during high-speed operation. This results in slight time deviations in the position switching and speed adjustment processes of the multi-axis execution actions, reducing the overall stability of the machine.

[0158] In this scenario, the present invention employs a VPX bus to construct a multi-board control platform. The FPGA fiber optic interface card periodically broadcasts timing pulses to all DSP control cores. Upon receiving a synchronization interrupt, each DSP control core immediately acquires its own axis position status and calculates the error. This invention simultaneously writes the error signal into both the private and broadcast areas of shared memory, enabling each DSP control core to independently control its own axis while simultaneously acquiring error signals from other axes in real time. In this way, each control core can calculate the distributed deviation coupling amount based on shared cross-axis error information, forming a consistent cross-axis state synchronization dataset. Subsequently, each DSP control core constructs a non-singular fast termination sliding surface for its own axis based on the error signal, error rate of change, and coupling amount. Based on this, it generates intermediate variables for sliding mode control, ensuring consistent dynamic convergence characteristics in the multi-axis control law. Finally, the generated control output signal is transmitted to the FPGA via the RapidIO bus and encoded into an optical signal control data stream according to optical signal output rules. This data stream is then applied to the actuators of each axis via a D / A converter and driver module, ensuring strict synchronization of the servo actions of each axis at high speeds.

[0159] During continuous operation testing, the multi-axis synchronization accuracy of the traditional multi-axis control system and the system of this invention was first compared under the same operating conditions. Six axes were tested, with each axis operating at a mixture of high-speed and variable acceleration speeds. The time error, position error, and cross-axis synchronization offset were collected for each axis at the periodic switching points. To ensure objectivity, the same model of motor, mechanical structure, and load conditions were used for testing. Test results show that with the traditional control method, the synchronization offset of multiple axes during high-speed operation switching is stable at the millisecond level, while with the present invention, the offset is stable at the microsecond level. The tests also show that, under the effect of error signal coupling and sliding mode collaborative control mechanisms, the maximum position deviation of each axis during rapid acceleration and deceleration is significantly reduced, and the overall synchronization error remains within a narrow range. Furthermore, the present invention uses an optical signal to control the data stream output structure, further reducing timing fluctuations in the control output on the transmission link and resulting in more consistent driver response.

[0160] As can be seen from the table below, under the same operating conditions, the synchronization accuracy, error convergence speed, and cross-axis consistency of the embodiments of the present invention are all superior to the traditional control schemes, which can effectively make up for the problems of insufficient synchronization performance, lag in cross-axis error transmission, and control response drift in the prior art.

[0161] Table 1. Comparison Test Results of Multi-Axis Synchronous Control Performance Test metrics Conventional control system average Inventive system average Cycle synchronization offset (μs) 950 42 Cross-axis motion switching time difference (μs) 1120 55 High speed segment maximum position deviation (mm) 0.86 0.12 Acceleration segment error convergence time (ms) 13.5 4.1 Cross-axis error transfer delay (μs) 780 31 Control link output timing jitter (μs) 120 14 Multi-axis synchronization stability score (0-100) 63 94

[0162] As can be seen from the table above, the present invention significantly improves the key performance indicators of multi-axis synchronous servo control compared to traditional control systems. Firstly, regarding periodic synchronization offset, the average offset of traditional control systems reaches 950 microseconds, while the system based on the VPX bus synchronization mechanism of the present invention reduces this indicator to 42 microseconds, a reduction of over 95%, indicating that the present invention can achieve higher-precision periodic synchronization among multiple control cores. Regarding cross-axis motion switching time difference, the traditional system averages 1120 microseconds, while the system of the present invention averages 55 microseconds, an improvement of 1065 microseconds. This demonstrates that the present invention significantly improves the real-time performance of cross-axis linkage through the collaborative method of shared broadcast area and distributed deviation coupling.

[0163] Regarding position deviation in the high-speed segment, the maximum position deviation of the traditional system is 0.86 mm, while the deviation of the system of this invention is 0.12 mm, representing an improvement in position synchronization accuracy of approximately 7 times. This invention, through the shared error signal structure and the construction of a non-singular fast terminal sliding surface, enables the error to converge faster during the dynamic process. In terms of error convergence time in the acceleration segment, the traditional system averages 13.5 milliseconds, while this invention reduces it to 4.1 milliseconds, a convergence speed improvement of more than three times. This demonstrates that the sliding mode control intermediate variable generation mechanism of this invention improves the control response in the dynamic process.

[0164] Regarding cross-axis error propagation delay, the conventional system has a delay of 780 microseconds, while the system of this invention has a delay of 31 microseconds, a reduction of 749 microseconds. This further verifies the effectiveness of the shared broadcast area structure in the multi-control core collaborative process. In terms of control link output timing jitter, the conventional system has a jitter of 120 microseconds, while the system of this invention has a jitter of 14 microseconds, a reduction of approximately 88%. This demonstrates that the optical signal control data stream output rules effectively improve timing consistency during the link transmission phase. Overall, this invention achieves comprehensive improvements in synchronization accuracy, cross-axis response consistency, and dynamic tracking performance, enabling multi-axis servo systems to maintain high stability and high consistency in high-speed scenarios.

[0165] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A multi-axis synchronous control system based on VPX bus, characterized in that, include: The control platform initialization module is used to configure the VPX control platform, establish RapidIO communication paths and GPIO synchronization lines, and generate a set of system initialization parameters. The timing pulse synchronization module is used to generate timing pulses from the FPGA and broadcast them through the VPX backplane to form a set of timing interrupt signals. The status acquisition and error writing module is used to acquire the axial status, calculate the error signal, and write it to the private area and broadcast area of ​​the shared memory after the DSP receives a timer interrupt. The distributed deviation coupling module is used to calculate the distributed deviation coupling amount based on the shared broadcast area error signal and construct the state synchronization dataset; The sliding surface construction and state determination module is used to construct a non-singular fast terminal sliding surface based on error signals and coupling quantities and generate intermediate variables for sliding mode control. The sliding mode control output generation module is used to execute the distributed sliding mode control strategy and generate control output signals; The optical signal conversion and data stream generation module is used to transmit the control output signal to the FPGA via RapidIO and then encode it according to the optical signal output rules to generate an optical signal control data stream. The actuator drive module is used to convert optical signal control data streams into analog drive signals and drive the motors of each axis to complete multi-axis synchronous servo control.

2. A multi-axis synchronous control system based on VPX bus, characterized in that, The modules are connected in the following way: Initialize the VPX control platform, establish the RapidIO bus communication path and GPIO synchronization line, and generate a set of system initialization parameters; Based on the system initialization parameter set, the FPGA fiber optic interface card periodically generates timing pulse signals and broadcasts the timing pulse signals through the synchronization channel of the P6 area of ​​the VPX backplane to obtain a set of timing interrupt signals. Based on the set of timed interrupt signals, the real-time status information of the connected shaft is collected, the axial error signal is calculated, and written into the private area and shared broadcast area of ​​the local shaft in the shared memory. Each DSP control core reads the error signals of other axes from the shared broadcast area, calculates the distributed deviation coupling amount based on the preset coupling weight parameters, and constructs a state synchronization dataset; Based on the coupling amount of axial error signal and distributed deviation, a non-singular fast terminal sliding surface is constructed inside each DSP control core to execute sliding state determination logic and generate intermediate variables for sliding control. The distributed non-singular fast terminal sliding mode control strategy is executed based on the intermediate variables of sliding mode control, a control output signal is generated, and the control output signal is written into the control quantity mapping area in shared memory. The control output signal is transmitted to the FPGA fiber optic interface card via the RapidIO bus and converted into a standard optical signal format to generate an optical signal control data stream. The optical signal controls the data stream output to the D / A digital-to-analog converter card, which then acts on each axis motor via the driver module to complete multi-axis synchronous servo control actions.

3. A multi-axis synchronous control system based on VPX bus according to claim 2, characterized in that, The initialization of the VPX control platform, the establishment of the RapidIO bus communication path and the GPIO synchronization line, and the generation of the system initialization parameter set specifically include: Load the VPX backplane configuration file, perform slot mapping for the P0 to P6 areas of the VPX backplane, determine the number of slots for the VPX backplane, and generate the VPX backplane parameter set. Configure the FPGA fiber optic interface card, set the synchronous clock frequency and the number of SFP fiber optic channels to form the FPGA interface parameter set; Configure the DSP motion control card, set the number of DSP cores, the size of the private memory space, and the axial error signal variables to form a set of DSP control parameters; Configure the CPU main control card, set the main control scheduling path between the CPU main control card and the DSP motion control card, and build a scheduling parameter mapping table; Establish a RapidIO bus communication path, set the topology to a fully interconnected structure, define the RapidIO data path set, and set the transmission bandwidth; Establish GPIO synchronous lines, set trigger signal tolerances, and form a set of GPIO interrupt response channels; The VPX backplane parameter set, FPGA interface parameter set, DSP control parameter set, scheduling parameter mapping table, RapidIO data path set, and GPIO interrupt response channel set are summarized and integrated to form the system initialization parameter set.

4. A multi-axis synchronous control system based on VPX bus according to claim 2, characterized in that, Based on the system initialization parameter set, the FPGA fiber optic interface card periodically generates timing pulse signals and broadcasts these signals through the synchronization channel in the P6 area of ​​the VPX backplane, resulting in a timing interrupt signal set that specifically includes: Extract the FPGA interface parameter set from the system initialization parameter set, and set the synchronization pulse signal frequency and pulse period; The FPGA fiber optic interface card uses an internal timer to generate a synchronous pulse signal according to a set pulse period, and outputs the corresponding synchronous trigger rising edge signal at the continuous period. The synchronous rising edge trigger signal is broadcast to the GPIO interrupt channel set through the corresponding GPIO synchronous line in the P6 area of ​​the VPX backplane, and enters the interrupt interface of each DSP control core. All DSP control cores generate a set of timer interrupt signals based on the synchronous rising edge trigger signal received from the GPIO synchronous line, forming a timer interrupt signal set.

5. A multi-axis synchronous control system based on VPX bus according to claim 2, characterized in that, The process of collecting real-time status information of the connected shaft based on a set of timed interrupt signals, calculating the axial error signal, and writing it into the private area and shared broadcast area of ​​the local shaft in shared memory specifically includes: Each DSP control core receives a set of timer interrupt signals, starts the data acquisition process for this cycle, acquires the real-time position status value of this axis, and reads the target position value from the desired trajectory register; Each DSP control core calculates the control error value based on the real-time position status value and the target position value to obtain the axial error signal, and records the timestamp of the error calculation completion; Each DSP control core synchronously writes the axial error signal into its own axis private area and shared broadcast in the shared memory structure; The shared broadcast area synchronously broadcasts the current error signal to all DSP control cores via the RapidIO communication bus and shared address index rules, forming a broadcast-level error signal set.

6. A multi-axis synchronous control system based on VPX bus according to claim 2, characterized in that, Each DSP control core reads error signals from other axes from the shared broadcast area, calculates the distributed deviation coupling amount based on preset coupling weight parameters, and constructs a state synchronization dataset, specifically including: Each DSP control core reads all axial error signals except for its own axis from the broadcast-level error signal set of the shared broadcast area under the current control cycle, forming an external error set; Each DSP control core calculates the error difference set based on the external error set and the axial error signal of its own axis; The distributed deviation coupling amount is calculated by weighting and superimposing the error difference set according to the preset coupling weight parameter matrix. Each DSP control core will write the distributed deviation coupling amount calculated in the current control cycle into the control input buffer area corresponding to the local axis in the shared memory, and construct a state synchronization dataset composed of the axial error signal of the local axis and the corresponding distributed deviation coupling amount.

7. A multi-axis synchronous control system based on VPX bus according to claim 2, characterized in that, The specific steps for constructing a non-singular fast terminal sliding surface within each DSP control core based on the coupling amount of axial error signal and distributed deviation, executing sliding state determination logic, and generating intermediate variables for sliding control include: After entering the current control cycle, each DSP control core reads the axial error signal of its own axis and the corresponding distributed deviation coupling amount from the state synchronization data of its own control core, calculates the error change rate of its own axis, and combines the axial error signal and the error change rate to form the error signal pair of the current cycle. Based on the definition of the sliding surface in non-singular fast terminal sliding mode control, the error signal and the rate of change of error are substituted into the sliding surface to construct the expression, generating the sliding surface variable of the current axis; The sliding mode state determination process is executed based on the coupling amount of sliding surface variables and distributed deviation, and a sliding mode state identifier is generated. The sliding surface variables and the distributed deviation coupling amount are combined to form the intermediate variables of sliding mode control, thus forming a set of intermediate variables for sliding mode control.

8. A multi-axis synchronous control system based on VPX bus according to claim 2, characterized in that, The step of executing a distributed non-singular fast terminal sliding mode control strategy based on intermediate variables of sliding mode control, generating a control output signal, and writing the control output signal into the control quantity mapping area in shared memory specifically includes: Each DSP control core reads the set of intermediate sliding mode control variables generated and stored in the previous stage, and uses the sliding mode surface variables and the distributed deviation coupling amount as the direct input of the control output signal in the current control cycle. The sliding surface variables and the distributed deviation coupling amount are substituted as input parameters to execute the distributed non-singular fast terminal sliding mode control strategy, and the distributed non-singular fast terminal sliding mode control function is constructed. The control output signal for the current control cycle of this axis is generated based on the output result of the distributed non-singular fast terminal sliding mode control function, and a set of control output signals is formed. The control output signals are written into the control quantity mapping area in the shared memory according to the preset address mapping rules, and the set of control output signals is submitted to the FPGA fiber optic interface card through the RapidIO bus.

9. A multi-axis synchronous control system based on VPX bus according to claim 2, characterized in that, The process of transmitting the control output signal to the FPGA fiber optic interface card via the RapidIO bus and converting it into a standard optical signal format to generate an optical signal control data stream specifically includes: Read the control output signals calculated by each DSP control core from the control output signal set, and determine the corresponding RapidIO transmission path according to the preset RapidIO data path set; Each control output signal is encapsulated into a set of control transmission frames according to the RapidIO data frame organization format; The control transmission frame set is sent to the FPGA fiber optic interface card via the RapidIO bus, and the scheduling, classification and optical signal conversion channel allocation of the transmission frames are completed according to the FPGA interface parameter set to obtain the optical signal format control set. The optical signal format control set is integrated in the FPGA fiber optic interface card and arranged according to the optical signal output rules to form an optical signal control data stream.

10. A multi-axis synchronous control system based on VPX bus according to claim 2, characterized in that, The process of outputting the optical signal control data stream to the D / A digital-to-analog converter card, and then acting on each axis motor via the driver module to complete the multi-axis synchronous servo control action specifically includes: The optical signal format control units output by the FPGA fiber optic interface card are obtained from the optical signal control data stream set, and the control axis corresponding to each optical signal is determined according to the mapping relationship between the optical signal channel number and the control axis index. The optical signal format control unit is input to the D / A digital-to-analog converter card through the optical fiber physical link. Based on the input parameter set of the digital-to-analog converter card, each optical signal format control unit is subjected to photoelectric conversion and voltage and current amplitude mapping processing to generate a set of analog control signals. The set of analog control signals is input to the driver module. Based on the set of driver parameters, current amplification, pulse modulation or torque command generation is performed on each analog control signal to form a set of drive control commands. The set of drive control commands is applied sequentially to the corresponding axial motors, so that each axial motor performs synchronous servo control actions according to the control cycle, forming a multi-axis servo execution set.

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