A data transmission method and device based on a solid state disk, a medium and a product

Abstract

A data transfer method, apparatus, medium, and product based on a solid-state drive (SSD) are disclosed, relating to the field of SSDs. In this method, a data layout description header is obtained from host memory via direct memory access based on the target memory start address. The data layout description header is parsed through the SSD's flash translation layer to identify each data segment entry, and the length information and lifecycle attribute tag of the corresponding data segment are extracted from each entry. Based on the lifecycle attribute tag, a corresponding physical flash page is planned for each data segment as the target write address. Based on the target write address, the SSD is controlled to perform DMA operations segment by segment according to the order of the data segment entries in the data layout description header until the total data length is written. Implementing the technical solution provided in this application improves the data storage efficiency of the SSD.

Description

Technical Field

[0001] This application relates to the field of solid-state drives (SSDs), specifically to a data transmission method, apparatus, medium, and product based on SSDs. Background Technology

[0002] With the widespread adoption of data-intensive applications, solid-state drives (SSDs) have become the mainstream storage device due to their high read and write speeds. In traditional data transfer models, the host's central processing unit (CPU) is deeply involved in the entire I / O (input / output) process. That is, the CPU needs to read data from system memory and then write the read data to the SSD's controller. When faced with the high bandwidth of SSDs, this method will consume a large amount of CPU resources, limit the computing efficiency of upper-layer applications, and form a performance bottleneck.

[0003] To address the issue of excessive CPU overhead during data transfer, existing technologies commonly employ Direct Memory Access (DMA). DMA allows the SSD controller to directly exchange data with system memory without continuous CPU intervention. The CPU only needs to set parameters such as the data source address, destination address, and transfer size before the transfer. The DMA controller then handles all data transfer and notifies the CPU of completion via an interrupt. This way, the CPU only needs to perform setup at the start of the transfer and can then focus on computational tasks, significantly improving system efficiency.

[0004] However, while DMA reduces CPU load, it also has its limitations. DMA lacks semantic understanding of data and cannot distinguish between content with different lifecycles within a data block (e.g., long-lived metadata and short-lived temporary data). Although the host system understands these differences, it cannot inform the SSD through DMA. This results in data with different lifecycles being mixed and written to the same physical block. When short-lived data is deleted, it leaves a hole in the physical block, triggering the SSD's internal garbage collection (GC) mechanism. The GC process involves additional data migration, leading to write amplification and reducing the SSD's data storage efficiency. Summary of the Invention

[0005] This application provides a data transmission method, apparatus, medium, and product based on a solid-state drive (SSD), which improves the data storage efficiency of the SSD.

[0006] A first aspect of this application provides a data transfer method based on a solid-state drive (SSD). The method includes: receiving a write instruction sent by a host, containing a target memory start address and a total data length; obtaining a data layout description header from host memory via direct memory access based on the target memory start address, wherein the data layout description header is a preset data structure, located at the target memory start address, and contains at least one data segment entry; parsing the data layout description header through the flash translation layer of the SSD, identifying each data segment entry, and extracting the length information and lifecycle attribute tag of the corresponding data segment from each data segment entry; planning a corresponding physical flash page as the target write address for each data segment based on the lifecycle attribute tag; and controlling the SSD to perform DMA operations segment by segment according to the order of the data segment entries in the data layout description header, until the total data length is written.

[0007] By adopting the above technical solution, a write instruction containing the target memory start address and total data length is received. A data layout description header with a preset data structure is obtained from the host memory using direct memory access, avoiding the occupation of host CPU resources during data transmission and improving data transmission efficiency. Simultaneously, the flash translation layer parses the data layout description header, identifies each data segment entry, and extracts the length information and lifecycle attribute tags of the corresponding data segment, achieving fine-grained management and optimization of different data segments. Combined with the lifecycle attribute tags, a corresponding physical flash page is planned as the target write address for each data segment, fully considering the access characteristics and lifecycle features of different data segments, improving flash memory utilization efficiency and data access performance. Finally, data is written segment by segment according to the order of data segment entries in the data layout description header through DMA operations, ensuring the sequentiality and integrity of data writing, effectively avoiding data out-of-order or loss problems, thereby significantly improving the reliability of data transmission. The above technical solution, by introducing a data layout description header during data transmission on the host side, enables the solid-state drive to perceive the structured information and lifecycle attribute tags of the data, and combines this with the flash translation layer to classify and store data with different lifecycles and plan physical flash page addresses, optimizing the data writing method. This solution effectively addresses the lack of data semantic understanding in traditional DMA transfers, reduces the write amplification effect caused by the co-storage of short-lifetime and long-lifetime data, thereby improving the write performance, storage efficiency, and lifespan of solid-state drives. It also reduces resource consumption caused by garbage collection, further optimizing the overall system performance.

[0008] Optionally, the step of parsing the data layout description header through the flash translation layer of the solid-state drive to identify each data segment entry specifically includes: defining a parser corresponding to the data layout description header in the flash translation layer of the solid-state drive; the parser containing the data structure definition information of the data layout description header and the data structure definition information of the data segment entries; using the parser to decode the binary data content of the data layout description header byte by byte to obtain the start flag and end flag of the data layout description header; obtaining the effective data length of the data layout description header based on the start flag and end flag; and parsing each data segment entry from the effective data of the data layout description header based on the effective data length and the data structure definition information of the data segment entries.

[0009] By adopting the above technical solution, a parser corresponding to the data layout description header is defined in the flash conversion layer. This parser includes the data structure definition information of the data layout description header and data segment entries, enabling the flash conversion layer to accurately understand the format and content of the data layout description header, thus improving the accuracy and efficiency of data parsing. The parser decodes the binary data content of the data layout description header byte by byte to obtain start and end flags, accurately locating the boundaries of the data layout description header and ensuring that the parsing process does not involve offsets or misjudgments. The effective data length of the data layout description header is obtained based on the start and end flags, avoiding the parsing of invalid data and reducing parsing overhead. Finally, combining the effective data length and the structure definition of the data segment entries, each data segment entry is accurately parsed from the effective data of the data layout description header, achieving efficient identification and extraction of data segments and providing a reliable foundation for subsequent data segment storage optimization.

[0010] Optionally, the step of planning corresponding physical flash pages as the target write address for each data segment based on the lifecycle attribute tag specifically includes: dividing the solid-state drive (SSD) into multiple physical storage partitions according to the SSD model and capacity, and assigning a corresponding lifecycle attribute tag to each physical storage partition; creating a mapping table between the lifecycle attribute tag and the physical storage partition in the flash translation layer of the SSD, and adjusting the mapping relationship between the lifecycle attribute tag and the physical storage partition when the SSD is idle to update the mapping table; when the target lifecycle attribute tag of the target data segment entry is parsed, searching for the target physical storage partition corresponding to the target lifecycle attribute tag in the mapping table, and obtaining the starting address and number of free pages of the target physical storage partition, wherein the target data segment entry is any one of the multiple data segment entries; calculating the number of target pages required to write the target data segment entry according to the data segment length corresponding to the target data segment entry; if the number of free pages is greater than or equal to the number of target pages, then allocating physical flash pages equal to the number of target pages starting from the starting address of the target physical storage partition as the target write address.

[0011] By adopting the above technical solution, multiple physical storage partitions are created based on the model and capacity of the solid-state drives (SSDs), and each partition is assigned a lifecycle attribute tag. This enables the rational planning and classification of the physical storage space of the SSDs, providing a foundation for differentiated storage management of data segments. By creating a mapping table between lifecycle attribute tags and physical storage partitions at the flash conversion layer, a correspondence between the lifecycle characteristics of data segments and physical storage areas is established, facilitating the rapid retrieval of the corresponding storage area based on the lifecycle attributes of the data segments. By obtaining the starting address and number of free pages of the target physical storage partition, the space usage of each physical storage partition can be monitored in real time. When allocating physical pages to data segments, partitions with sufficient free space can be selected, improving the utilization rate of storage space. Simultaneously, by comparing the number of free pages with the target number of pages, it is ensured that the allocated physical pages can fully accommodate the data segments, avoiding data storage overflow issues.

[0012] Optionally, adjusting the mapping relationship between the lifecycle attribute tag and the physical storage partition when the solid-state drive is idle specifically includes: monitoring the write / erase balance of each physical storage partition when the solid-state drive is idle; when the difference in write / erase balance between the first physical storage partition and the second physical storage partition exceeds a preset threshold, obtaining the first lifecycle attribute tag corresponding to the first physical storage partition and the second lifecycle attribute tag corresponding to the second physical storage partition, wherein the first physical storage partition and the second physical storage partition are any two physical storage partitions of the solid-state drive, and the write / erase balance of the first physical storage partition is higher than that of the second physical storage partition; updating the first physical storage partition to a new first physical storage partition and updating the second physical storage partition to a new second physical storage partition; establishing a mapping relationship between the first lifecycle attribute tag and the new second physical storage partition, and establishing a mapping relationship between the second lifecycle attribute tag and the new first physical storage partition.

[0013] By adopting the above technical solution, when the solid-state drive (SSD) is idle, the write balance of each physical storage partition is monitored in real time to grasp the write balance status of each partition, providing a basis for dynamically adjusting the data layout. When the write balance difference between two partitions exceeds a preset threshold, the lifecycle attribute tags corresponding to these two partitions are obtained to prepare for the remapping of lifecycle tags. During partition updates, the first and second partitions are redefined as new partitions according to their physical boundaries, avoiding physical movement of data within the partitions and reducing data migration overhead. By establishing a mapping relationship between the first lifecycle tag and the new second partition, and between the second lifecycle tag and the new first partition, data exchange between high-write and low-write partitions is realized. Low-write data segments are stored in high-write partitions, and high-write data segments are stored in low-write partitions, balancing the write cycles of each partition and extending the overall lifespan of the SSD.

[0014] Optionally, updating the first physical storage partition to a new first physical storage partition and updating the second physical storage partition to a new second physical storage partition specifically includes: migrating all valid data in the first physical storage partition to the available free pages of the second physical storage partition to obtain the new second physical storage partition; and erasing the first physical storage partition after the data migration is completed to obtain a new first physical storage partition containing consecutive free pages.

[0015] By adopting the above technical solution, during the physical storage partition update process, data exchange between the two partitions is achieved by migrating all valid data from the first partition to the available free pages of the second partition. Low-write-rate data from the first partition is transferred to the second partition, and high-write-rate data from the second partition is indirectly transferred to the first partition, completing the remapping of lifecycle attribute tags. After the data migration is complete, the first partition is completely erased, transforming it into a new partition containing contiguous free pages. This releases invalid space in the first partition and provides a large number of contiguous physical pages for newly written high-write-rate data, optimizing the write performance of high-write-rate data. Simultaneously, since the physical boundaries of the partitions remain unchanged, the data migration operation is transparent to upper-layer applications. Applications do not need to be concerned with the underlying partition adjustments, ensuring the continuity and stability of data access.

[0016] Optionally, after obtaining the starting address and the number of free pages of the target physical storage partition, the method further includes: if the number of free pages is less than the target number of pages, triggering a garbage collection operation for the target physical storage partition, reclaiming invalid pages in the target physical storage partition, and converting the invalid pages into available free pages; after the garbage collection operation is completed, obtaining the number of free pages in the target physical storage partition after reclamation, and determining whether the number of free pages after reclamation is greater than or equal to the target number of pages; if yes, allocating physical flash pages equal to the target number of pages starting from the starting address of the target physical storage partition as the target write address; if no, upgrading and adjusting the lifecycle attribute label of the target data segment entry to obtain a new lifecycle attribute label, and re-searching for the corresponding new physical storage partition in the mapping table according to the new lifecycle attribute label.

[0017] By adopting the above technical solution, when the number of free pages in the target physical storage partition is insufficient to accommodate the data segment to be written, a garbage collection operation is triggered on the target partition to promptly reclaim invalid pages within the partition and convert them into usable free pages, dynamically expanding the available space of the partition and improving storage space utilization. After garbage collection is completed, the number of free pages in the target partition is retrieved again and compared with the data segment length to ensure that the reclaimed free space can meet the storage requirements of the data segment, avoiding data write failures. If the free space is still insufficient, the lifecycle attribute label of the target data segment is upgraded and adjusted to a higher-level lifecycle label, and the corresponding physical storage partition is searched again based on the new label, realizing dynamic adjustment of the data segment storage area and ensuring reliable data storage. This mechanism of dynamically triggering garbage collection and adjusting the data lifecycle according to actual conditions effectively adapts to changes in data segment size and storage space, improving the flexibility and availability of the system.

[0018] Optionally, the step of controlling the solid-state drive (SSD) to perform DMA operations segment by segment according to the order of data segment entries in the data layout description header, based on the target write address, until the total data length is written, specifically includes: creating a DMA task queue in the flash translation layer of the SSD; generating a corresponding DMA write task for each data segment entry according to the order of data segment entries in the data layout description header, and inserting the DMA write task into the tail of the DMA task queue; and sequentially reading and executing each DMA write task from the head of the DMA task queue through the DMA controller of the SSD; for each The DMA write task, according to task parameters, reads target data of a specified length from a specified starting address in the host memory through the DMA channel and writes the target data to a target write address on the solid-state drive. After the DMA write task is completed, it is deleted from the DMA task queue, and it is determined whether the DMA task queue is empty. If the DMA task queue is empty, it indicates that the total length of data has been written, and the DMA controller is controlled to stop working. If the DMA task queue is not empty, the next DMA write task is read and executed through the DMA controller until the DMA task queue is empty.

[0019] By adopting the above technical solution, a DMA task queue is created in the flash memory conversion layer. Data segment write operations are transformed into corresponding DMA write tasks, and DMA write tasks are inserted into the tail of the task queue according to the order of data segment entries in the data layout description header. This achieves serialization and asynchronous processing of data write operations, improving the concurrency and throughput of data writes. The DMA controller reads and executes each DMA write task sequentially according to the first-in-first-out (FIFO) order of the task queue, ensuring the orderliness and consistency of data writes. For each DMA write task, the target data is read from the host memory through the DMA channel according to the task parameters and written to the target physical page of the solid-state drive (SSD), achieving high-speed data transfer from the host to the SSD and reducing data migration latency. After the task is completed, it is promptly removed from the task queue, and the DMA controller is stopped if the queue is empty, avoiding unnecessary resource waste. This data write mechanism based on the DMA task queue fully utilizes the data transfer capabilities of the DMA hardware, reduces the burden on the host CPU, and automates and pipelines the data write process, thereby significantly improving the efficiency and performance of data writes.

[0020] In a second aspect, embodiments of this application provide a data transmission device based on a solid-state drive (SSD). The SSD-based data transmission device includes one or more processors and a memory. The memory is coupled to the one or more processors and is used to store computer program code, which includes computer instructions. The one or more processors invoke the computer instructions to cause the SSD-based data transmission device to perform the method described in the first aspect and any possible implementation thereof.

[0021] Thirdly, embodiments of this application provide a computer-readable storage medium including instructions that, when executed on a solid-state drive-based data transmission device, cause the solid-state drive-based data transmission device to perform the method described in the first aspect and any possible implementation thereof.

[0022] Fourthly, embodiments of this application provide a computer program product containing instructions that, when the computer program product is run on a solid-state drive-based data transmission device, cause the solid-state drive-based data transmission device to perform the method described in the first aspect and any possible implementation thereof.

[0023] In summary, one or more technical solutions provided in this application have at least the following technical effects or advantages:

[0024] 1. This technical solution introduces a data layout description header, combined with the flash translation layer and DMA technology of the SSD, to enable structured and semantically aware data transfer. By parsing data segment entries and lifecycle attribute tags, the SSD can achieve classified data storage and optimized resource allocation, reducing the inefficiency of indiscriminate data movement in traditional DMA technology and significantly improving data transfer efficiency and overall system performance.

[0025] 2. By planning physical storage partitions and dynamically adjusting mapping relationships based on lifecycle attribute tags, this solution effectively avoids frequent garbage collection (GC) operations caused by the co-storage of short-lifecycle and long-lifecycle data, significantly reducing write amplification. Simultaneously, through erase / write balance monitoring and dynamic migration optimization of physical storage partitions, the erase / write load of flash memory cells is further balanced, extending the lifespan of the SSD.

[0026] 3. This solution ensures efficient utilization of physical storage space through dynamic physical page allocator, garbage collection mechanism, and lifecycle attribute tag upgrades and adjustments. When storage resources are insufficient, new storage resources can be dynamically allocated through emergency garbage collection or lifecycle tag adjustments. Furthermore, the sequential operation design based on DMA task queues ensures the orderliness and reliability of the data writing process, improving system stability and concurrent processing capabilities. Attached Figure Description

[0027] Figure 1 This is a flowchart illustrating a data transmission method based on a solid-state drive disclosed in an embodiment of this application;

[0028] Figure 2 This is another schematic diagram of a data transmission method based on a solid-state drive disclosed in an embodiment of this application;

[0029] Figure 3 This is a schematic diagram of a data transmission device based on a solid-state drive provided in an embodiment of this application.

[0030] Explanation of reference numerals in the attached drawings: 301, Central Processing Unit; 302, Read-Only Memory; 303, Random Access Memory; 304, Bus; 305, Input / Output Interface; 306, Input Section; 307, Output Section; 308, Storage Section; 309, Communication Section; 310, Driver; 311, Removable Media. Detailed Implementation

[0031] To enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0032] In the description of the embodiments of this application, the words "for example" or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design that is described as "for example" or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design options. Rather, the use of the words "for example" or "for instance" is intended to present the relevant concepts in a specific manner.

[0033] In the description of the embodiments of this application, the term "multiple" means two or more. For example, multiple system devices refer to two or more system devices, and multiple screen terminals refer to two or more screen terminals. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0034] This application provides a data transfer method based on a solid-state drive, referring to... Figure 1 , Figure 1This is a flowchart illustrating a data transfer method based on a solid-state drive (SSD) according to an embodiment of this application. The method is applied to a device, which is a solid-state drive (SSD), and the device can execute a data transfer program based on the SSD. The method includes steps S101 to S105, as follows:

[0035] Step S101: Receive a write command sent by the host, which includes the starting address of the target memory and the total length of the data.

[0036] In step S101, the host refers to the computer system that initiates the data write request, such as a personal computer or server running an operating system and applications. The target memory start address indicates the starting physical address of the data required for this write operation in the host memory. The total data length refers to the total number of bytes of data to be written to the solid-state drive starting from this start address. The write command is a command sent by the host to the solid-state drive controller via a bus protocol, such as NVMe or SATA, which encapsulates the parameters necessary to perform the data write task.

[0037] Specifically, when a host application or operating system needs to persistently store data in a memory region, the host device driver constructs a specific write instruction. This write instruction, in addition to traditional logical block address (LBA) information, specifically includes the exact starting location of the data to be written in the host's physical memory (the target memory starting address) and the total size of the data to be written (the total data length). The SSD controller, continuously monitoring the command queue, receives and identifies this write instruction, and parses the target memory starting address and total data length from it, preparing for subsequent data acquisition and processing.

[0038] Step S102: Based on the target memory start address, obtain the data layout description header from the host memory via direct memory access. The data layout description header is a preset data structure, located at the target memory start address, and contains at least one data segment entry.

[0039] In step S102, direct memory access refers to the technology by which the solid-state drive controller directly reads data from the host memory without the intervention of the host central processing unit (CPU). The data layout description header is a predefined data structure placed at the beginning of the data block to be written, used to describe the internal logical composition of the subsequent actual data. Data segment entries are the basic building blocks within the data layout description header; each data segment entry describes the attributes of a specific piece of data.

[0040] Specifically, after obtaining the target memory start address in step S101, the SSD controller firmware initializes the onboard Direct Memory Access (DMA) controller. The firmware instructs the DMA controller to perform a small-scale data read operation, with the target address being the target memory start address, and the read length being the preset size of the data layout description header. The DMA controller then independently accesses the host memory via the system bus, completely fetching the data layout description header located at the target memory start address into the SSD's internal cache or static random access memory (SRAM). This process is highly efficient because it bypasses the host CPU, avoiding the overhead of context switching and interrupt handling.

[0041] In one possible implementation, the data layout description header is parsed through the flash translation layer of the solid-state drive to identify each data segment entry, specifically including steps S1021-S1024, as follows:

[0042] Step S1021: In the flash translation layer of the solid-state drive, define a parser corresponding to the data layout description header. The parser contains the data structure definition information of the data layout description header and the data structure definition information of the data segment entries.

[0043] In step S1021, the parser refers to a specific program code embedded in the flash memory conversion layer firmware. This program code is specifically designed to identify and interpret the binary stream of the data layout description header. The data structure definition information refers to a precise description of the fields within the data layout description header and data segment entries, including the name, data type, number of bytes occupied, and order of each field in the overall structure.

[0044] Specifically, during the solid-state drive (SSD) design and firmware development phases, engineers pre-implement a parser within the flash translation layer's code. This parser embeds complete knowledge of the data layout descriptor header. For example, it knows that the data layout descriptor header always begins with a specific 4-byte magic number and ends with another 4-byte magic number; and it knows that the data between the start and end magic numbers consists of several data segment entries arranged sequentially. Simultaneously, the parser precisely defines the structure of each data segment entry; for instance, each entry consists of a 4-byte unsigned integer representing the data segment length and a 1-byte character representing the lifecycle attribute label. This definition information is fundamental to the parser's correct operation.

[0045] Step S1022: Use the parser to decode the binary data content of the data layout description header byte by byte to obtain the start flag and end flag of the data layout description header.

[0046] In step S1022, the binary data content refers to the unprocessed raw data layout description header data stream obtained from the host memory. Byte-by-byte decoding refers to the process by which the parser sequentially reads and analyzes the binary data content byte by byte. The start and end flags are predefined special byte sequences used to mark the boundaries of the valid content of the data layout description header.

[0047] Specifically, after the binary data content of the data layout description header is loaded into the internal cache of the solid-state drive, the flash translation layer calls the parser defined in step S1021 to process the data. The parser scans from the first byte of the binary data content, comparing the read byte sequence with a preset start flag. Once a match is found, the parser records the position of the start flag. Subsequently, the parser continues scanning to find the preset end flag. In this way, the parser can accurately define the start and end boundaries of the data layout description header from a data stream that may contain other irrelevant data.

[0048] Step S1023: Obtain the effective data length of the data layout description header based on the start flag and end flag.

[0049] In step S1023, the effective data length refers to the total number of bytes of data located between the start flag and the end flag, which includes all data segment entries.

[0050] Specifically, after the parser successfully locates the start and end flags, it determines the effective data length by calculating the address difference between these two flags in memory. For example, if the start flag occupies 4 bytes, the effective data begins after the start flag. The parser subtracts the start address of the effective data from the start address of the end flag to obtain a precise byte count, which is the effective data length. This length represents the total size of all data segment entries, providing crucial information for accurately separating each entry in the next step.

[0051] Step S1024: Based on the valid data length and the data structure definition information of the data segment entries, parse out each data segment entry from the valid data in the data layout description header.

[0052] In step S1024, this step is the core of the parsing process, which aims to decompose consecutive valid data blocks into independent, meaningful data segment entries.

[0053] Specifically, the parser utilizes the valid data length obtained in step S1023 and the data structure definition information of a single data segment entry defined in step S1021, such as knowing that each entry occupies a fixed 5 bytes. The parser calculates the total number of data segment entries by dividing the valid data length by the length of a single data segment entry. Subsequently, the parser starts a loop, the number of loops being the number of data segment entries. In each loop, the parser starts from the current processing position of the valid data and reads a block of bytes the length of one data segment entry. Then, according to the data structure definition of the data segment entry, it extracts the corresponding information from this block of bytes; for example, interpreting the first 4 bytes as an integer as length information and the 5th byte as a character as a lifecycle attribute label. After completing one extraction, the parser moves the processing position forward by the length of one data segment entry, preparing to parse the next entry. This loop continues until all valid data is processed, ultimately parsing all data segment entries completely and independently.

[0054] To facilitate understanding, a specific example is given below to explain steps S2021-S1024:

[0055] Suppose a parser is defined in the flash translation layer of a solid-state drive (SSD). This parser knows that the start flag of the data layout description header is 0xABCDABCD, the end flag is 0xDCBADBCA, and each data segment entry consists of a 4-byte length field and a 1-byte lifetime tag field, totaling 5 bytes. Now, the SSD retrieves a piece of binary data from host memory via DMA. The parser begins its work, scanning the data byte by byte. It finds 0xABCDABCD at the beginning of the data, confirming the start position. Continuing to scan, it finds 0xDCBADBCA at the 19th byte, confirming the end position. Based on these two positions, the parser calculates the effective data length between them to be 10 bytes, which is located 4 bytes after the start flag and 4 bytes before the end flag. Subsequently, based on the definition that each data segment entry is 5 bytes, the parser divides the effective data length of 10 bytes by 5 bytes, resulting in 2 data segment entries. The parser then begins a loop to parse the data. The first time, it reads the first 5 bytes of valid data, parsing the first 4 bytes as length information (e.g., 0x00001000, which is 4096) and the 5th byte as a lifecycle attribute label (e.g., 0x01 representing hot data). The second time, it reads the last 5 bytes of valid data, parsing the first 4 bytes as length information (e.g., 0x00004000, which is 16384) and the 5th byte as a lifecycle attribute label (e.g., 0x03 representing cold data). At this point, the parser has successfully extracted two complete data segment entries and their contained length information and lifecycle attribute labels from the original binary data.

[0056] Step S103: Parse the data layout description header through the flash conversion layer of the solid-state drive, identify each data segment entry, and extract the length information and lifecycle attribute label of the corresponding data segment from each data segment entry.

[0057] In step S103, the Flash Translation Layer (FTL) refers to the core firmware layer inside the solid-state drive (SSD), responsible for mapping upper-layer logical addresses to physical addresses in the flash memory and managing low-level operations such as garbage collection and wear leveling. Length information refers to the number of bytes occupied by a specific data segment. Lifetime attribute tags are classification markers used to identify data update frequency or expected retention time; for example, they can be categorized as extremely hot data, hot data, warm data, and cold data.

[0058] Specifically, once the data layout description header is successfully acquired by the SSD's internal memory, the flash translation layer firmware running on the SSD's embedded processor begins executing a parsing procedure. This procedure reads the content field-by-field according to the preset data structure definition of the data layout description header. For example, the firmware first reads a field to determine how many data segment entries are contained in the data layout description header, and then enters a loop. In each loop, the firmware sequentially reads all fields of a data segment entry, precisely separating the length information indicating the size of the data segment, and the lifecycle attribute label characterizing the data segment's features. The flash translation layer pairs each set of parsed length information and lifecycle attribute label and stores them in a temporary internal data structure for use in subsequent write planning steps.

[0059] Step S104: Based on the lifecycle attribute label, plan the corresponding physical flash page for each data segment as the target write address of the data segment.

[0060] In step S104, a physical flash page is the smallest physical unit in a NAND flash memory chip that can be programmed and written once. The target write address refers to the specific physical page address (PPA) on the flash memory chip allocated for a certain data segment.

[0061] Specifically, the flash translation layer internally pre-divides the physical storage space of the solid-state drive into multiple logical partitions or block pools based on different lifecycle attribute tags. For example, some high-performance SLC or low-density TLC blocks are designated as hot data areas, while other standard TLC or QLC blocks are designated as cold data areas. For each data segment entry parsed in step S103, the flash translation layer checks its lifecycle attribute tag. Based on this tag, the flash translation layer locates the corresponding physical partition and requests one or more contiguous, available physical flash pages from the free block manager of that partition. The flash translation layer uses the address of the requested physical flash page as the target write address for the data segment and associates it with the length information of the data segment to form a complete write task description. This process is repeated for all data segments, ultimately generating a detailed write mapping table from data segments to physical locations.

[0062] Please refer to Figure 2 In one possible implementation, based on the lifecycle attribute tag, a corresponding physical flash page is planned as the target write address for each data segment, specifically including steps S201-S209, as follows:

[0063] Step S201: Divide the solid-state drive into multiple physical storage partitions according to its model and capacity, and assign a corresponding lifecycle attribute tag to each physical storage partition.

[0064] In step S201, a physical storage partition refers to a contiguous storage area logically divided on the physical flash memory medium of a solid-state drive (SSD) using firmware. Each partition consists of several physical erase blocks. Lifecycle attribute tags are classification labels used to identify the frequency characteristics of data updates. For example, they are divided into hot data tags, warm data tags, and cold data tags, corresponding to high-frequency, medium-frequency, and low-frequency updated data, respectively.

[0065] Specifically, the flash conversion layer firmware performs this step during the initial initialization or formatting of the solid-state drive (SSD). The firmware divides the entire physical NAND flash memory space into a preset number of physical storage partitions based on the SSD's total capacity and design specifications. For example, a 1TB SSD might be divided into three partitions: a 200GB partition, a 300GB partition, and a 500GB partition. After partitioning, the firmware assigns an initial role to each partition, that is, it assigns an initial lifecycle attribute label to each physical storage partition. For example, the 200GB partition is labeled as a hot data area, the 300GB partition as a warm data area, and the 500GB partition as a cold data area.

[0066] Step S202: In the flash translation layer of the solid-state drive, create a mapping table between lifecycle attribute tags and physical storage partitions.

[0067] In step S202, the mapping table refers to a data structure stored in the high-speed dynamic random access memory inside the solid-state drive. This data structure records the physical start address and range information of the specific physical storage partition corresponding to each lifecycle attribute tag.

[0068] Specifically, after completing the physical storage partitioning and initial tag assignment, the flash translation layer establishes and maintains this mapping table in its working memory. This mapping table serves as a dynamic routing guide for data writes. For example, the mapping table might contain entries such as: hot data tags pointing to the address information of physical storage partition A, warm data tags pointing to the address information of physical storage partition B, and cold data tags pointing to the address information of physical storage partition C. When a certain type of data needs to be written, the flash translation layer queries this table to determine the correct target physical location.

[0069] Step S203: When the solid-state drive is idle, monitor the write / erase balance of each physical storage partition.

[0070] In step S203, "solid disk idle time" refers to a time window during which the solid-state drive (SSD) is not currently executing read / write commands from the host or performing internal emergency garbage collection tasks. Write-erase balance is an indicator used to measure the wear and tear of a physical storage partition, typically quantified by calculating the average number of erases across all physical blocks within that partition.

[0071] Specifically, the flash translation layer includes a background monitoring task designed to activate during the SSD's idle periods. Once activated, this task iterates through each physical storage partition on the SSD, reads and increments the erase count for each physical block within the partition, and then calculates the average number of erases for each partition. This average value is the erase-write balance of that partition. The flash translation layer updates and records the erase-write balance value for each partition in real time or periodically, providing data support for subsequent wear-leveling decisions.

[0072] Step S204: When the difference in erase / write balance between the first physical storage partition and the second physical storage partition exceeds a preset threshold, obtain the first lifecycle attribute tag corresponding to the first physical storage partition and the second lifecycle attribute tag corresponding to the second physical storage partition. The first physical storage partition and the second physical storage partition are any two physical storage partitions of the solid-state drive, and the erase / write balance of the first physical storage partition is higher than that of the second physical storage partition.

[0073] In step S204, the difference value refers to the absolute value of the difference between the write / erase balance values ​​of the two physical storage partitions. The preset threshold is an integer value pre-set in the firmware; when the wear difference reaches this value, the leveling mechanism is triggered. The first physical storage partition and the second physical storage partition refer to the two partitions with higher and lower wear levels during the comparison. The first lifecycle attribute label and the second lifecycle attribute label refer to the labels corresponding to these two partitions in the mapping table when the leveling mechanism is triggered.

[0074] Specifically, after obtaining the write balance scores of all physical storage partitions, the background monitoring task compares them pairwise. For example, comparing physical storage partition A and physical storage partition C, it finds that partition A has a write balance score of 1000, while partition C has a score of 50, and the preset threshold is 800. Since the difference of 950 exceeds the threshold of 800, the balancing condition is triggered. At this point, the system designates partition A as the first physical storage partition and partition C as the second physical storage partition. Subsequently, the system queries the mapping table to obtain the current label for partition A as a "hot data" label (the first lifecycle attribute label); and the current label for partition C as a "cold data" label (the second lifecycle attribute label).

[0075] Step S205: Migrate all valid data in the first physical storage partition to the available free pages of the second physical storage partition to obtain a new second physical storage partition.

[0076] In step S205, valid data refers to data in the physical storage partition that is still logically referenced by address mapping and has not been marked as invalid or deleted. Available free pages refer to physical pages in the target physical storage partition that have undergone erasure but have not yet been written with new data. The new second physical storage partition refers to the second physical storage partition after the data migration operation has been completed.

[0077] Specifically, after the load balancing operation is triggered, the flash translation layer initiates the data migration process. The flash translation layer first scans the first physical storage partition, identifying all physical pages containing valid data. Then, the flash translation layer reads this valid data and sequentially writes it to the available free pages of the second physical storage partition. After this process is complete, the second physical storage partition will contain the original data as well as all valid data migrated from the first physical storage partition; this second physical storage partition in this state is referred to as the new second physical storage partition.

[0078] Step S206: Erase the first physical storage partition after the data migration is completed to obtain a new first physical storage partition containing consecutive free pages.

[0079] In step S206, total erasure refers to executing an erase command on all physical blocks within a physical storage partition, restoring them to a writable state. The new first physical storage partition refers to the first physical storage partition after the total erasure operation has been completed.

[0080] Specifically, after confirming that all valid data in the first physical storage partition has been safely migrated to the second physical storage partition, the flash translation layer sends block erase commands to all physical blocks constituting the first physical storage partition. This process resets the state of all physical pages within the partition. Once completed, the first physical storage partition becomes a clean area consisting entirely of contiguous free pages, ready to receive new data. This state of the first physical storage partition is referred to as the new first physical storage partition.

[0081] Step S207: Establish the mapping relationship between the first lifecycle attribute label and the new second physical storage partition, and establish the mapping relationship between the second lifecycle attribute label and the new first physical storage partition.

[0082] In step S207, the mapping relationship refers to the correspondence between lifecycle attribute labels and physical storage partition addresses in the mapping table created in step S202.

[0083] Specifically, after data migration and partition erasure are completed, the flash translation layer updates the mapping table to achieve a logical role swap. The flash translation layer finds entries with the first lifecycle attribute tags (hot data tags) and modifies their pointed-to physical partition addresses to the addresses of the new second physical storage partitions. Simultaneously, the flash translation layer finds entries with the second lifecycle attribute tags (cold data tags) and modifies their pointed-to physical partition addresses to the addresses of the new first physical storage partitions. Through this update, previously heavily worn physical areas are now allocated to less frequently written cold data, while less worn physical areas begin to handle frequently written hot data, thus achieving wear leveling.

[0084] Step S208: When the target lifecycle attribute tag of the target data segment entry is parsed, the target physical storage partition corresponding to the target lifecycle attribute tag is searched in the mapping table, and the starting address and number of free pages of the target physical storage partition are obtained. The target data segment entry is any one of multiple data segment entries.

[0085] In step S208, the target data segment entry refers to the specific data segment that needs to be written to the solid-state drive. The target lifecycle attribute label is a label contained within this data segment entry. The target physical storage partition is the physical partition found in the current mapping table based on this label. The starting address and the number of free pages are the status information of the target physical storage partition.

[0086] Specifically, when a write command arrives and its data segment entry is parsed, the flash translation layer extracts the target lifecycle attribute tag, such as the hot data tag, from the entry. The flash translation layer immediately uses this tag as a lookup key in the mapping table. The mapping table returns the physical address information of the target physical storage partition currently associated with the hot data tag. Simultaneously, the flash translation layer reads the starting physical address of the target physical storage partition and the total number of remaining free pages from the partition management metadata.

[0087] Step S209: Calculate the number of target pages required to write the target data segment entry based on the data segment length corresponding to the target data segment entry.

[0088] In step S209, the data segment length is used to represent the logical size of the data segment described by the target data segment entry, which is usually measured in bytes; the target page number represents the minimum integer number of physical flash memory pages required to completely store the data corresponding to the data segment length into the physical flash memory.

[0089] Specifically, when the solid-state drive (SSD) performs this calculation step, it first needs to obtain two key parameters: the first is the length of the data segment read from the target data segment entry, and the second is the size of a single physical flash page pre-configured in the flash management system, which is a fixed value. After obtaining these two parameters, the SSD uses the data segment length as the dividend and the size of the physical flash page as the divisor to perform a division operation. If the result of the division operation is an integer, it indicates that the data corresponding to the target data segment entry can exactly fill several complete physical flash pages, and the SSD determines the integer result as the target page number. If the result of the division operation is a non-integer with a decimal, it indicates that after the data corresponding to the target data segment entry fills several complete physical flash pages, there is still some data remaining that needs to occupy part of the space of the next physical flash page. In this case, the SSD adds one to the integer part of the division result and determines the sum as the target page number. This operation ensures that the calculated target page number is always sufficient to accommodate all the data, avoiding the problem of insufficient data storage space allocation caused by the data length not being divisible by the page size.

[0090] Step S210: If the number of free pages is greater than or equal to the number of target pages, then starting from the starting address of the target physical storage partition, allocate physical flash pages equal to the number of target pages as the target write address.

[0091] In step S210, the target write address refers to the starting address of a contiguous physical page that the flash translation layer ultimately allocates for the data segment on the physical flash memory.

[0092] Specifically, the flash translation layer compares the number of free pages obtained in step S208 with the target number of pages. If there are enough free pages to accommodate the entire data segment, the flash translation layer will allocate a continuous number of physical flash pages equal to the target number of pages within the target physical storage partition, starting from the currently available write position. The physical address of the first page in this series of allocated physical pages is determined as the target write address for this write operation. Subsequently, data will be written to this address. If there are insufficient free pages, a garbage collection operation will be triggered in the partition to free up space before allocation is performed.

[0093] To facilitate understanding, a specific example is given below to explain steps S201-S210:

[0094] Suppose a solid-state drive (SSD) is initialized with physical partitions A and B. The flash translation layer creates a mapping table, mapping "hot data" to partition A and "cold data" to partition B. After running for a period, due to numerous high-frequency write operations targeting "hot data," partition A's average erase count reaches 600, while partition B, primarily storing static files, averages only 50 erases. At this point, the SSD enters an idle state, and a background monitoring task detects that the write-erase balance difference between the two partitions (550) exceeds the preset threshold of 500, triggering the wear leveling mechanism. The system identifies partition A as the first physical storage partition with higher wear and partition B as the second physical storage partition with lower wear. Next, the system copies all remaining valid data from partition A (e.g., 50GB) and writes it to the available free pages of partition B. After the migration is complete, the system performs a full erase on partition A, making it a completely clean and free partition. Finally, the system updates the mapping table: pointing the "hot data" label to the address of partition B, and pointing the "cold data" label to the address of the newly erased partition A. A few days later, a host requests to write a 2GB data segment tagged with "hot data". The flash memory translation layer parses the "hot data" label, queries the updated mapping table, and finds that "hot data" now corresponds to physical partition B. The system checks and finds that partition B still has a large number of free pages, far exceeding 2GB. Therefore, the system allocates 2GB of contiguous physical flash pages starting from the current write point on partition B, and returns this address as the target write address. The data is then written to this previously cold data area, a less worn physical location, effectively extending the overall lifespan of the solid-state drive.

[0095] In one possible implementation, after obtaining the starting address and number of free pages of the target physical storage partition, the method further includes steps S211-S214, as follows:

[0096] Step S211: If the number of free pages is less than the number of target pages, a garbage collection operation is triggered for the target physical storage partition to reclaim invalid pages in the target physical storage partition and convert the invalid pages into available free pages.

[0097] In step S211, garbage collection refers to a space defragmentation mechanism automatically executed within the solid-state drive (SSD). This mechanism reclaims the physical space occupied by data pages marked as invalid by moving valid data from physical blocks and erasing old physical blocks. Invalid pages are physical pages that store outdated data, which, due to updates or deletions, no longer have logical addresses pointing to them.

[0098] Specifically, when the flash memory conversion layer determines in step S209 that the number of free pages in the target physical storage partition is insufficient to accommodate the target number of pages, it immediately initiates a garbage collection operation for that target physical storage partition. The flash memory conversion layer scans all physical blocks within the partition and selects one or more physical blocks containing a large number of invalid pages as targets for collection. Subsequently, the flash memory conversion layer reads the remaining small amount of valid data from these target physical blocks and writes it to the free pages of other physical blocks within the partition. After confirming that all valid data has been successfully migrated, the flash memory conversion layer executes a total erase command on these original target physical blocks. After the erase is complete, all pages in these physical blocks become available free pages for new data to be written, thereby increasing the available space of the target physical storage partition.

[0099] Step S212: After the garbage collection operation is completed, obtain the number of free pages after garbage collection of the target physical storage partition, and determine whether the number of free pages after garbage collection is greater than or equal to the number of target pages.

[0100] In step S212, the number of free pages after reclamation refers to the sum of the latest available free pages in the target physical storage partition after the garbage collection operation in step S211 is completed.

[0101] Specifically, after the garbage collection operation is completed, the flash translation layer immediately queries the status information of the target physical storage partition again to obtain the updated total number of free pages, which is the number of free pages after reclamation. Next, the flash translation layer performs another space check, comparing this number of free pages after reclamation with the number of target pages required by the target data segment entry to be written. The result of this comparison determines the subsequent execution path: if there is enough space, proceed to step S213; if there is still insufficient space, proceed to step S214.

[0102] Step S213: If yes, then starting from the starting address of the target physical storage partition, allocate a number of physical flash pages equal to the number of target pages as the target write address.

[0103] In step S213, if the judgment result of step S212 is yes, meaning that after the garbage collection operation, the target physical storage partition has enough free pages to store the target data segment, then the flash translation layer will execute the same allocation logic as in step S210. The flash translation layer will allocate a block of physical flash pages, starting from the currently available write position of the target physical storage partition, in a sequence equal to the number of target pages. The starting physical address of this allocated physical flash page is then determined as the target write address for this write operation, and the data write operation can then proceed.

[0104] Step S214: If not, upgrade and adjust the lifecycle attribute label of the target data segment entry to obtain a new lifecycle attribute label, and search for the corresponding new physical storage partition in the mapping table according to the new lifecycle attribute label.

[0105] In step S214, upgrading and adjusting the lifecycle attribute label refers to adjusting the data's lifecycle attribute label from a level representing a higher update frequency to a level representing a lower update frequency, according to a preset strategy. For example, adjusting from hot data to warm data, or from warm data to cold data. The new lifecycle attribute label refers to the new label obtained after the upgrade and adjustment. The new physical storage partition refers to the physical storage partition associated with the new lifecycle attribute label in the mapping table.

[0106] Specifically, if the result of step S212 is negative, it means that even after garbage collection, the target physical storage partition (e.g., the hot data area) still lacks sufficient space, which usually indicates that the partition is filled with a large amount of recently used valid data. In this case, the flash translation layer initiates a backup strategy. The flash translation layer downgrades the lifecycle attribute label of the target data segment entry to be written, for example, changing the original "hot data" label to a "warm data" label. This "warm data" label is the new lifecycle attribute label. Subsequently, the flash translation layer uses this new lifecycle attribute label to perform a completely new lookup in the mapping table between lifecycle attribute labels and physical storage partitions. This lookup will locate a new physical storage partition corresponding to the "warm data" label. Afterward, the entire process returns to step S209, where the system re-examines the space for this new physical storage partition and attempts to allocate a write address.

[0107] To facilitate understanding, the following concrete example will be used to explain steps S211-S214:

[0108] Suppose a write request arrives at the SSD containing a target data segment entry of 5GB length with a lifecycle attribute label of "hot data". The flash translation layer uses the mapping table to find the target physical storage partition currently used to store the hot data as partition A. The system checks and finds that partition A has only 2GB of free pages remaining, less than 5GB. Therefore, the system immediately triggers a garbage collection operation for partition A. However, since most of the data stored in partition A is recently accessed valid hot data, there are very few invalid pages, and the garbage collection operation can only reclaim 1GB of space. After the operation, the system obtains that the number of free pages in partition A after reclamation is 3GB. The system checks again and finds that 3GB is still less than the required 5GB. At this point, the system determines that partition A cannot accommodate the data segment, so it upgrades and adjusts the lifecycle attribute label of the data segment entry, changing the label from "hot data" to "warm data". Subsequently, the system uses the new lifecycle attribute label "warm data" to re-query the mapping table and finds the corresponding physical storage partition as partition C. Next, the system will restart the allocation process for partition C, checking the number of free pages in partition C. If partition C has sufficient space, allocate physical flash pages within partition C as the target write address for this 5GB data segment.

[0109] Step S105: Based on the target write address, control the solid-state drive to perform DMA operations segment by segment according to the order of data segment entries in the data layout description header until the total length of data is written.

[0110] In step S105, DMA operation refers to the process by which the solid-state drive controller uses direct memory access technology again to transfer user data from the host memory to the flash memory medium.

[0111] Specifically, after the target write addresses for all data segments have been planned, the SSD controller begins executing the actual data write process. The controller strictly follows the original order of the data segment entries in the data layout description header. For the first data segment entry, the controller configures the DMA engine, setting the source address to the target memory start address plus the length of the data layout description header, setting the target address to the target write address planned for this data segment in step S104, and the transfer length to the length information of this data segment. After the DMA transfer starts, the first data segment is written directly from the host memory to the specified physical flash page. After the transfer is complete, the DMA controller reports a completion status. The firmware then processes the second data segment entry. At this time, the DMA source address is updated to the end address of the previous data segment in the host memory, and the target address is updated to the address of the new physical flash page planned for the second data segment. This "configure DMA - execute - complete - process the next segment" cycle is executed continuously, segment by segment, until all data segments are accurately written to their respective planned physical locations, and the total amount of data written reaches the total data length. After all tasks are completed, the SSD sends a confirmation signal to the host indicating that the write is complete.

[0112] In one possible implementation, based on the target write address, the solid-state drive is controlled to perform DMA operations segment by segment according to the order of data segment entries in the data layout description header until the total length of data is written. Specifically, this includes steps S1051-S1057, as follows:

[0113] Step S1051: Create a DMA task queue in the flash translation layer of the solid-state drive.

[0114] In step S1051, the flash translation layer refers to the firmware layer inside the solid-state drive (SSD) responsible for managing flash memory chips, performing address mapping, garbage collection, and wear leveling. The DMA task queue is a data structure created within the flash translation layer to store and manage direct memory access tasks awaiting execution. This data structure follows a first-in, first-out (FIFO) principle, ensuring that tasks are processed in the order they are submitted.

[0115] Specifically, upon receiving the write command from the upper layer, the solid-state drive's flash memory translation layer allocates a contiguous block of memory in its internal working memory and initializes this space as a queue data structure. This queue is specifically designated as the DMA task queue, used to sequentially receive and store the various DMA write tasks generated for this data write operation. The queue is initially empty.

[0116] Step S1052: Based on the order of the data segment entries in the data layout description header, generate a corresponding DMA write task for each data segment entry and insert the DMA write task into the tail of the DMA task queue.

[0117] In step S1052, a DMA write task refers to a data structure containing all the parameters required to perform a single direct memory access operation. These parameters typically include the source address, the destination address, and the data transfer length.

[0118] Specifically, the flash translation layer begins parsing the data layout description header obtained in the previous steps. The flash translation layer processes the data segment entries one by one in the order they are listed in the data layout description header. For the first data segment entry, the flash translation layer generates a DMA write task. The task parameters include the starting address of the data segment in host memory, the data segment length, and the target write address determined in the previous steps. For each subsequent data segment entry, the flash translation layer similarly generates a DMA write task. The task parameters include the starting address of the data segment in host memory and the data segment length, while the target write address is calculated by adding the length of the previous data segment to the target write address of the previous task. Each time a DMA write task is generated, the flash translation layer inserts it at the end of the DMA task queue. This process continues until all data segment entries have been processed.

[0119] Step S1053: Starting from the head of the DMA task queue, read and execute each DMA write task sequentially using the DMA controller of the solid-state drive.

[0120] In step S1053, the DMA controller refers to a dedicated hardware unit inside the solid-state drive. This unit is responsible for performing direct memory access operations and can autonomously complete the data transfer between the host memory and flash memory without occupying central processing unit resources.

[0121] Specifically, after all DMA write tasks have been filled into the DMA task queue, the flash translation layer sends a start signal to the SSD's DMA controller. Upon receiving the signal, the DMA controller accesses the head of the DMA task queue and reads the first DMA write task at the head of the queue. The DMA controller parses the parameters contained in this task, preparing for the actual data transfer. This operation marks the beginning of the physical execution phase of the data write process.

[0122] Step S1054: For each DMA write task, according to the task parameters, read the target data of a specified length from the specified starting address of the host memory through the DMA channel, and write the target data to the target write address on the solid-state drive.

[0123] In step S1054, a DMA channel refers to a logical path established by the DMA controller for an independent data transfer operation. Host memory refers to the main random access memory of a computer system connected to a solid-state drive.

[0124] Specifically, based on the parameters parsed from the DMA write task, the DMA controller configures a DMA channel. Using the host memory start address and data length specified in the task, the DMA controller initiates a data read request to the host memory system. Simultaneously, using the target write address specified in the task, the DMA controller prepares the SSD's internal data path to receive data. The data stream is transferred directly from host memory to the physical flash page pointed to by the target write address on the SSD via the DMA channel, without the intervention of the central processing unit. The DMA controller monitors the transfer process to ensure that the specified length of data is written accurately.

[0125] Step S1055: After the DMA write task is completed, delete the DMA write task from the DMA task queue and determine whether the DMA task queue is empty.

[0126] In step S1055, when the DMA controller confirms that the data transfer specified by the current DMA write task has been successfully completed, the flash translation layer performs a dequeue operation, removing the just-completed DMA write task from the head of the DMA task queue. After the task is removed, the head pointer of the queue will automatically point to the next task. Immediately afterwards, the flash translation layer checks the current state of the DMA task queue to determine whether there are any remaining tasks in the queue.

[0127] Step S1056: If the DMA task queue is empty, it means that the total length of data has been written and the DMA controller is stopped.

[0128] In step S1056, if the judgment result of step S1055 is yes, that is, the DMA task queue is empty, this indicates that all data segments defined in the data layout description header have been successfully written to the flash memory medium of the solid-state drive in sequence. At this time, the flash translation layer sends a stop command to the DMA controller to terminate its work and release the occupied DMA channel. Simultaneously, the flash translation layer can report to the upper-layer application or operating system that the entire write operation has been successfully completed.

[0129] Step S1057: If the DMA task queue is not empty, the next DMA write task is read and executed through the DMA controller until the DMA task queue is empty.

[0130] In step S1057, if the judgment result of step S1055 is negative, meaning there are still pending DMA write tasks in the DMA task queue, the DMA controller will immediately access the updated head of the queue and read the next DMA write task. Subsequently, the system will repeat the data transfer operation of step S1054 and the task completion processing operation of step S1055. This cycle of reading, executing, deleting, and judging will continue until the DMA task queue eventually becomes empty, thereby triggering the completion logic of step S1056.

[0131] To facilitate understanding, a specific example is given below to explain steps S1051-S1057:

[0132] Suppose a write request's data layout description header contains two data segment entries, and previous steps have assigned a starting target write address of physical address PBA_1000 for this write request. The first data segment entry describes the need to read 4MB of data from host memory address HMA_A; the second data segment entry describes the need to read 8MB of data from host memory address HMA_B. First, the SSD's flash translation layer creates an empty DMA task queue in its internal memory. Next, the flash translation layer parses the first data segment entry, generates a DMA write task with parameters including source address HMA_A, length 4MB, and target address PBA_1000, and inserts this task into the queue. Then, the flash translation layer parses the second data segment entry, generates a second DMA write task with parameters including source address HMA_B, length 8MB, and target address PBA_1000 plus a 4MB offset, and also inserts this task into the queue. At this point, there are two tasks in the queue. The flash memory translation layer activates the DMA controller. The DMA controller reads the first task from the head of the queue and transfers 4MB of data from host memory HMA_A to the PBA_1000 address of the solid-state drive via the DMA channel. After the transfer is complete, the task is removed from the queue. The flash memory translation layer determines that the queue is not empty, so the DMA controller reads the new head task, the second task. The DMA controller then transfers 8MB of data from host memory HMA_B to the address PBA_1000 plus a 4MB offset on the solid-state drive. After the transfer is complete, the second task is also removed. At this point, the flash memory translation layer determines that the queue is empty and controls the DMA controller to stop working. The entire 12MB data write operation, including two data segments, is now complete.

[0133] The following describes a data transmission device based on a solid-state drive (SSD) from a hardware processing perspective. Please refer to [link to relevant documentation]. Figure 3 This is a schematic diagram of a data transmission device based on a solid-state drive in an embodiment of this application.

[0134] It should be noted that, Figure 3 The structure of the solid-state drive-based data transfer device shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the present invention.

[0135] like Figure 3 As shown, a solid-state drive-based data transfer device includes a central processing unit (CPU) 301, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 302 or a program loaded from storage portion 308 into random access memory (RAM) 303, such as performing the methods described in the above embodiments. The RAM 303 also stores various programs and data required for device operation. The CPU 301, ROM 302, and RAM 303 are interconnected via a bus 304. An input / output (I / O) interface 305 is also connected to the bus 304.

[0136] The following components are connected to I / O interface 305: input section 306 including audio input devices, push-button switches, etc.; output section 307 including a liquid crystal display (LCD) and audio output devices, indicator lights, etc.; storage section 308 including a hard disk, etc.; and communication section 309 including a network interface card such as a LAN (Local Area Network) card, modem, etc. Communication section 309 performs communication processing via a network such as the Internet. Drive 310 is also connected to I / O interface 305 as needed. Removable media 311, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., are installed on drive 310 as needed so that computer programs read from them can be installed into storage section 308 as needed.

[0137] In particular, according to embodiments of the present invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of the present invention include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing computer programs for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication section 309, and / or installed from removable medium 311. When the computer program is executed by central processing unit (CPU) 301, it performs the various functions defined in the present invention.

[0138] It should be noted that specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical fiber, portable compact disc read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this invention, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0139] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of the present invention. Each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those shown in the drawings.

[0140] Specifically, a solid-state drive-based data transmission device according to this embodiment includes a processor and a memory. The memory stores a computer program, and when the computer program is executed by the processor, it implements a solid-state drive-based data transmission method provided in the above embodiment.

[0141] In another aspect, the present invention also provides a computer-readable storage medium, which may be included in a solid-state drive-based data transmission device described in the above embodiments; or it may exist independently and not assembled into the solid-state drive-based data transmission device. The storage medium carries one or more computer programs, which, when executed by a processor of the solid-state drive-based data transmission device, cause the solid-state drive-based data transmission device to implement the solid-state drive-based data transmission method for IoT-based encrypted data transmission provided in the above embodiments.

Claims

1. A data transfer method based on a solid-state drive, characterized in that, The method includes: Receive a write command sent by the host, which includes the starting address of the target memory and the total length of the data; Based on the target memory start address, a data layout description header is obtained from the host memory via direct memory access. The data layout description header is a preset data structure, located at the target memory start address, and contains at least one data segment entry. The data layout description header is parsed through the flash conversion layer of the solid-state drive to identify each data segment entry, and the length information and lifecycle attribute label of the corresponding data segment are extracted from each data segment entry; Based on the lifecycle attribute tags, a corresponding physical flash page is planned for each data segment as the target write address of the data segment; Based on the target write address, the solid-state drive is controlled to perform DMA operations segment by segment according to the order of the data segment entries in the data layout description header until the total length of data is written. The step of parsing the data layout description header through the flash translation layer of the solid-state drive to identify each data segment entry specifically includes: In the flash conversion layer of the solid-state drive, a parser corresponding to the data layout description header is defined. The parser contains the data structure definition information of the data layout description header and the data structure definition information of the data segment entries. The parser is used to decode the binary data content of the data layout description header byte by byte to obtain the start flag and end flag of the data layout description header; The effective data length of the data layout description header is obtained based on the start flag and the end flag. Based on the effective data length and the data structure definition information of the data segment entries, each data segment entry is parsed from the effective data of the data layout description header; The step of planning a corresponding physical flash page as the target write address for each data segment based on the lifecycle attribute tag specifically includes: Based on the model and capacity of the solid-state drive, multiple physical storage partitions are divided, and a corresponding lifecycle attribute tag is assigned to each physical storage partition; In the flash conversion layer of the solid-state drive, a mapping table is created between the lifecycle attribute tags and the physical storage partitions. When the solid-state drive is idle, the mapping relationship between the lifecycle attribute tags and the physical storage partitions is adjusted to update the mapping table. When the target lifecycle attribute tag of the target data segment entry is parsed, the target physical storage partition corresponding to the target lifecycle attribute tag is searched in the mapping table, and the starting address and number of free pages of the target physical storage partition are obtained. The target data segment entry is any one of the multiple data segment entries. Based on the data segment length corresponding to the target data segment entry, the number of target pages required to write the target data segment entry is calculated; If the number of free pages is greater than or equal to the number of target pages, then starting from the starting address of the target physical storage partition, allocate physical flash pages equal to the number of target pages as the target write address.

2. The method according to claim 1, characterized in that, The step of adjusting the mapping relationship between the lifecycle attribute tag and the physical storage partition when the solid-state drive is idle specifically includes: When the solid-state drive is idle, monitor the erase / write balance of each physical storage partition; When the difference in erase / write balance between the first physical storage partition and the second physical storage partition exceeds a preset threshold, the first lifecycle attribute tag corresponding to the first physical storage partition and the second lifecycle attribute tag corresponding to the second physical storage partition are obtained. The first physical storage partition and the second physical storage partition are any two physical storage partitions of the solid-state drive, and the erase / write balance of the first physical storage partition is higher than that of the second physical storage partition. Update the first physical storage partition to the new first physical storage partition, and update the second physical storage partition to the new second physical storage partition; Establish a mapping relationship between the first lifecycle attribute label and the new second physical storage partition, and establish a mapping relationship between the second lifecycle attribute label and the new first physical storage partition.

3. The method according to claim 2, characterized in that, The step of updating the first physical storage partition to a new first physical storage partition and updating the second physical storage partition to a new second physical storage partition specifically includes: All valid data in the first physical storage partition is migrated to the available free pages of the second physical storage partition to obtain the new second physical storage partition; The first physical storage partition after data migration is completed is completely erased to obtain a new first physical storage partition containing consecutive free pages.

4. The method according to claim 1, characterized in that, After obtaining the starting address and number of free pages of the target physical storage partition, the method further includes: If the number of free pages is less than the number of target pages, a garbage collection operation is triggered for the target physical storage partition to reclaim invalid pages in the target physical storage partition and convert the invalid pages into available free pages. After the garbage collection operation is completed, the number of free pages in the target physical storage partition after garbage collection is obtained, and it is determined whether the number of free pages after garbage collection is greater than or equal to the target number of pages. If so, then starting from the starting address of the target physical storage partition, allocate physical flash pages equal to the number of target pages as the target write address; If not, the lifecycle attribute label of the target data segment entry is upgraded and adjusted to obtain a new lifecycle attribute label, and the corresponding new physical storage partition is searched again in the mapping table according to the new lifecycle attribute label.

5. The method according to claim 1, characterized in that, Based on the target write address, controlling the solid-state drive to perform DMA operations segment by segment according to the order of data segment entries in the data layout description header until the total data length is written, specifically includes: In the flash memory translation layer of the solid-state drive, a DMA task queue is created; According to the order of the data segment entries in the data layout description header, a corresponding DMA write task is generated for each data segment entry, and the DMA write task is inserted into the tail of the DMA task queue. The DMA controller of the solid-state drive reads and executes each DMA write task sequentially, starting from the head of the DMA task queue. For each DMA write task, according to the task parameters, target data of a specified length is read from a specified starting address in the host memory through the DMA channel and written to the target write address on the solid-state drive; After the DMA write task is completed, the DMA write task is deleted from the DMA task queue, and it is determined whether the DMA task queue is empty. If the DMA task queue is empty, it indicates that the total length of data has been written and the DMA controller is stopped. If the DMA task queue is not empty, the DMA controller reads and executes the next DMA write task until the DMA task queue is empty.

6. A data transmission device based on a solid-state drive, characterized in that, The solid-state drive-based data transfer device includes: one or more processors and a memory; the memory is coupled to the one or more processors, the memory is used to store computer program code, the computer program code including computer instructions, and the one or more processors invoke the computer instructions to cause the solid-state drive-based data transfer device to perform the method as described in any one of claims 1-5.

7. A computer-readable storage medium comprising instructions, characterized in that, When the instruction is executed on a solid-state drive-based data transfer device, the solid-state drive-based data transfer device performs the method as described in any one of claims 1-5.

8. A computer program product, characterized in that, When the computer program product is run on a solid-state drive-based data transmission device, the solid-state drive-based data transmission device performs the method as described in any one of claims 1-5.

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