Method for determining an abnormal request

Abstract

The embodiment of the application provides a kind of determination method of abnormal request, this method includes: through the tracker deployed in node, corresponding entry is allocated for each request to node and the entry identification of generating entry identification;According to the generation order of entry identification, generate entry identification chain, wherein, entry identification chain includes entry identification and the validity state of entry identification;Through the polling detection of request in timer in tracker, determine timeout request, and the request corresponding to the first entry identification of chain is determined as abnormal request;Wherein, the first entry identification of chain is the earliest generation and the validity state is valid in entry identification chain.The technical problem that related art cannot accurately detect and locate abnormal request under the condition of low resource consumption is solved by the embodiment of the application.

Description

Methods for determining abnormal requests Technical Field

[0001] This application relates to the field of communications, and more specifically, to a method for determining abnormal requests. Background Technology

[0002] In a bus architecture, when the bus fails to return data from a slave device for more than a preset time due to physical damage, software failure, or design flaws, the timeout detection mechanism can promptly identify the anomaly and trigger an interrupt handling process. The core significance of monitoring bus timeouts lies in timely detection and response to system anomalies when the bus hangs or other modules and storage systems experience fatal problems. This prevents data transmission interruptions caused by hardware failures, software errors, or communication delays, thereby ensuring system reliability, availability, and serviceability.

[0003] In bus anomaly request detection in related technologies, a common approach is to detect all requests at each node of the bus, with each request having its own timer. When the lifecycle of a request exceeds a detection threshold, it is considered a timeout request and an anomaly is reported. This approach can accurately detect anomalies in each request. However, the resource consumption of this scheme is directly proportional to the outstanding capability of each node on the bus and the timeout detection threshold. Another approach is to share a single timer for all requests, tracking one request at a time. After the currently tracked request ends, the timer is reset to track the next request. This approach has the lowest resource consumption but a larger error rate and cannot accurately pinpoint which request caused the problem.

[0004] Therefore, the relevant technologies cannot solve the contradiction between resource consumption and detection accuracy in bus anomaly detection. Summary of the Invention

[0005] This application provides a method for determining abnormal requests, in order to solve the technical problem in related technologies that it is impossible to accurately detect and locate abnormal requests under low resource consumption conditions.

[0006] According to one embodiment of this application, a method for determining abnormal requests is provided, comprising: assigning a corresponding entry to each request for a node and generating an entry identifier for the entry through a tracker deployed on a node; generating an entry identifier chain according to the generation order of the entry identifiers, wherein the entry identifier chain includes entry identifiers and the validity status of the entry identifiers; polling the requests in the tracker using a timer to detect timeout requests, and determining the requests corresponding to the detected timeout requests and the entry identifiers at the head of the chain as abnormal requests; wherein the entry identifier at the head of the chain is the earliest generated entry identifier in the entry identifier chain and whose validity status is valid.

[0007] According to another embodiment of this application, a network device is also provided, the network device including a receiver, a transmitter and a processor, the network device being configured to perform the steps in the above method embodiments through at least one of the receiver, the transmitter and the processor.

[0008] According to yet another embodiment of this application, a computer-readable storage medium is also provided, wherein a computer program is stored in the computer program, and the computer program is configured to execute the steps in the above method embodiments when it is run.

[0009] According to yet another embodiment of this application, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in the above method embodiments.

[0010] According to yet another embodiment of this application, a computer program product is also provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0011] This embodiment deploys a tracker on each node, assigns an entry to each request, and generates a corresponding entry identifier. This ensures that each request has a unique identifier, facilitating subsequent tracking and detection. Compared to using a separate timer for each request, this method is more efficient in resource management because it eliminates the need to allocate complex timers or timestamp logic for each request. An entry identifier chain is generated based on the generation order of the entry identifiers. This chain not only contains the entry identifiers but also their validity status. This chain structure effectively manages the storage of entry information under limited resources, ensuring low resource consumption while preserving the temporal order of requests, thereby improving the accuracy of timeout detection. A general-purpose timer is used to poll the requests in the tracker. When a timeout request is detected, the entry identifier of the timeout request and the identifier of the first entry in the chain are returned. The first entry identifier is the earliest generated entry identifier in the entry identifier chain that is still valid. This embodiment significantly reduces the number of timers and resource consumption. Furthermore, because the entry identifier chain preserves the temporal order of requests, when a timeout occurs, the timeout request can be quickly located using the first entry identifier and the timeout entry identifier, improving detection accuracy. Therefore, this solves the technical problem in related technologies that cannot accurately detect and locate abnormal requests under low resource consumption conditions. Attached Figure Description

[0012] Figure 1 is a hardware structure block diagram of a mobile terminal for a method of determining abnormal requests according to an embodiment of this application.

[0013] Figure 2 is a flowchart of a method for determining abnormal requests according to an embodiment of this application;

[0014] Figure 3 is a schematic diagram of a tracker component according to an embodiment of this application;

[0015] Figure 4 is a schematic diagram of the entry identifier chain component according to an embodiment of this application;

[0016] Figure 5 is a schematic diagram of the search component according to an embodiment of this application;

[0017] Figure 6 is a schematic diagram of a timer component according to an embodiment of this application;

[0018] Figure 7 is an apparatus for determining abnormal requests according to an embodiment of this application;

[0019] Figure 8 is a structural block diagram of a network device according to an embodiment of this application;

[0020] Figure 9 is a schematic diagram of an abnormal request processing apparatus according to an embodiment of this application;

[0021] Figure 10 is a schematic diagram of an information capture component according to an embodiment of this application;

[0022] Figure 11 is a flowchart of an abnormal request processing method according to an embodiment of this application;

[0023] Figure 12 is a schematic diagram of displacement according to an embodiment of this application;

[0024] Figure 13 is a second schematic diagram of displacement according to an embodiment of this application;

[0025] Figure 14 is a schematic diagram of displacement according to an embodiment of this application. Detailed Implementation

[0026] The embodiments of this application will be described in detail below with reference to the accompanying drawings and examples.

[0027] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0028] The method embodiments provided in this application can be executed in a mobile terminal, computer terminal, or similar computing device. Taking a mobile terminal as an example, FIG1 is a hardware structure block diagram of a mobile terminal according to the abnormal request determination method of this application. As shown in FIG1, the mobile terminal may include one or more (only one is shown in FIG1) processors 102 (processor 102 may include, but is not limited to, processing devices such as microprocessors MCU or programmable logic devices FPGA) and a memory 104 for storing data. The mobile terminal may also include a transmission device 106 for communication functions and an input / output device 108. It will be understood by those skilled in the art that the structure shown in FIG1 is only illustrative and does not limit the structure of the mobile terminal. For example, the mobile terminal may also include more or fewer components than shown in FIG1, or have a different configuration than shown in FIG1.

[0029] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the abnormal request determination method in this embodiment. The processor 102 executes various functional applications and data processing by running the computer programs stored in the memory 104, thus implementing the above-described method. The memory 104 may include high-speed random access memory and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to the mobile terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0030] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by the mobile terminal's communication provider. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module, used for wireless communication with the Internet.

[0031] This embodiment provides a method for determining abnormal requests. Figure 2 is a flowchart of the method for determining abnormal requests according to an embodiment of this application. As shown in Figure 2, the process includes the following steps:

[0032] Step S202: Assign a corresponding entry to each request for the node and generate an entry identifier for the entry by using the tracker deployed on the node.

[0033] In one embodiment, a schematic diagram of the tracker component is shown in Figure 3. Each time the tracker receives a request, it assigns a specified entry and generates an entry identifier (Entry ID) for the entry. The tracker includes entry information (Entry Info) and the corresponding entry validity (Entry Valid). This embodiment does not limit the specific structure of the tracker, and the internal structure of the tracker can be designed according to different needs.

[0034] In related technologies, timeout detection methods may allocate a separate timer for each request, which consumes a significant amount of chip resources. However, the embodiments of this application significantly reduce the required hardware resources, particularly the number of timers, by allocating an entry for each request instead of a timer, thereby reducing the design complexity and manufacturing cost of the chip.

[0035] Step S204: Generate an entry identifier chain according to the generation order of the entry identifiers, wherein the entry identifier chain includes entry identifiers and the validity status of the entry identifiers.

[0036] In one embodiment, a schematic diagram of the item identifier chain component is shown in Figure 4. The item identifier chain includes item identifiers and corresponding item validity. Multiple item identifiers are written into the item identifier chain using a partial serial shift writing method.

[0037] The entry identifier chain stores entry identifiers arranged in the order of their generation, thus enabling accurate tracking of the time sequence and status of each request. In anomaly detection, by checking the validity status of the entry identifiers, it is possible to determine which specific request timed out, thereby achieving precise request tracing and anomaly localization.

[0038] In an exemplary embodiment of this application, generating an entry identifier chain according to the generation order of entry identifiers includes: obtaining the latest generated entry identifier, and writing the entry identifier and its validity status into the entry identifier chain according to the filling status of the entry identifier chain.

[0039] In an exemplary embodiment of this application, writing an entry identifier and its validity status into the entry identifier chain according to the filling status of the entry identifier chain includes: writing the entry identifier and its validity status into the tail of the chain when the tail of the entry identifier chain is not occupied; and searching from the tail of the chain towards the head of the chain for a position where the validity status is invalid.

[0040] In an exemplary embodiment of this application, after searching for a valid position with an invalid state from the tail of the chain to the head of the chain, the method further includes: if the search result is yes, updating the tail of the chain to an unoccupied state through a partial serial shift operation and writing the entry identifier to the tail of the chain; if the search result is no, determining that the entry identifier chain is in a full state.

[0041] By maintaining the validity status of each entry in the entry identifier chain, it is possible to accurately track and detect whether each request in the entry identifier chain has timed out. When a new request joins, if the entry identifier chain is not full, the entry identifier and validity status can be directly written to the tail of the chain; if the entry identifier chain is full, it waits for release. This ensures the continuity and integrity of the entry identifier chain, thereby improving the accuracy of timeout event detection. Updating the entry identifier chain using a partially serial shift method avoids performing a full chain shift when the tail of the chain is occupied, reducing unnecessary hardware resource consumption.

[0042] In an exemplary embodiment of this application, the depth of the tracker is equal to the length of the entry identifier chain.

[0043] Because the tracker depth and the entry identifier chain length are equal, this means that each tracker entry can be found in the entry identifier chain. Thus, when a request is assigned to an entry in the tracker, its entry identifier is accurately recorded in the entry identifier chain, ensuring a one-to-one correspondence between requests and tracking information.

[0044] Step S206: Poll the requests in the tracker using a timer to detect timeout requests, and identify the timeout requests and the requests corresponding to the first entry identifier as abnormal requests; wherein, the first entry identifier is the earliest generated entry identifier in the entry identifier chain and whose validity status is valid.

[0045] In an exemplary embodiment of this application, polling requests in the tracker using a timer to determine timeout requests includes: initializing the timer and setting a timing threshold for the timer, wherein the timing threshold is used to indicate a preset completion time for the request; starting the timer and simultaneously monitoring the selected request to be detected within the timing threshold to determine whether the request to be detected has been completed or released; if the request to be detected has been completed or released, stopping and resetting the timer, selecting the next request to be detected for monitoring within the timing threshold; and if the request to be detected has not been completed and has not been released, determining that the request to be detected is a timeout request.

[0046] In one embodiment, a schematic diagram of the lookup component for polling detection is shown in Figure 5. The lookup component receives multiple entry identifiers from the tracker, which represent request entries that are currently being processed or waiting to be processed. An entry release signal is input to the lookup component to indicate which entries have been released and no longer need to be monitored and tracked.

[0047] In one embodiment, a schematic diagram of the timer component is shown in Figure 6. `timer count++` indicates that, in the context of a timer, when a new entry identifier is enabled, the `count++` operation is performed every time the timer detects that one clock cycle has elapsed, causing the counter value to increase by 1. When the value of `timer count` exceeds a software-specified threshold, it indicates that the predetermined time has been exceeded, i.e., a timeout interrupt has occurred.

[0048] In an exemplary embodiment of this application, if the request corresponding to an entry identifier in the entry identifier chain is released, the validity status of the entry identifier is updated to invalid, and the entry identifier is deleted from the entry identifier chain.

[0049] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0050] This embodiment also provides an apparatus for determining abnormal requests, which is used to implement the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0051] Figure 7 is an apparatus for determining abnormal requests according to an embodiment of this application. The apparatus includes an allocation module 10, a generation module 20, and a determination module 30.

[0052] The allocation module 10 is used to allocate a corresponding entry for each request to the node and generate an entry identifier for the entry through the tracker deployed on the node;

[0053] The generation module 20 is used to generate an entry identifier chain according to the generation order of the entry identifiers, wherein the entry identifier chain includes entry identifiers and the validity status of the entry identifiers;

[0054] The determination module 30 is used to poll the requests in the tracker through a timer to detect timeout requests, and to determine the requests corresponding to the detected timeout requests and the chain head entry identifiers as abnormal requests; wherein, the chain head entry identifier is the earliest generated entry identifier in the entry identifier chain and whose validity status is valid.

[0055] In the embodiments of this application, the above-mentioned abnormal request determination device may also include different modules, and the naming and functional division of the modules may be selected in different ways according to the actual situation, without specific restrictions here.

[0056] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0057] This application also provides a network device. FIG8 is a structural block diagram of the network device according to an embodiment of this application. As shown in FIG8, the network device 400 includes a receiver 401, a transmitter 402 and a processor 403. The network device 400 is used to execute the steps of the above-mentioned abnormal request determination method embodiment through at least one of the receiver 401, transmitter 402 and processor 403.

[0058] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when run.

[0059] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0060] Embodiments of this application also provide an electronic device including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0061] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0062] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0063] In one exemplary embodiment, the computer program product described above includes a non-volatile computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the methods described in various embodiments of this application.

[0064] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0065] Obviously, those skilled in the art should understand that the modules or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.

[0066] To enable those skilled in the art to better understand the technical solutions of this application, the following description is provided in conjunction with different embodiments.

[0067] In large server chips, the bus interconnect is extremely large, with hundreds or even thousands of nodes connected. Each node, depending on its design, function, and resources, can simultaneously track dozens or hundreds of requests, forming an exceptionally large and complex data flow. If a request times out and hangs, it is necessary to quickly locate which node in the bus and which request has hanged, and to obtain detailed information about that request to assist chip testers in troubleshooting.

[0068] This application embodiment addresses the problems of high resource consumption or insufficient detection accuracy of some existing timeout detection mechanisms, and achieves accurate timeout detection and reporting of requests with less resource usage.

[0069] Figure 9 is a schematic diagram of an abnormal request processing device according to an embodiment of this application. As shown in Figure 9, the device includes a tracker, a lookup component, a timer, an information capture component, and an item identifier chain component. The tracker generates item identifiers based on requests and generates an item identifier chain according to the generation order of the item identifiers. The timer and the lookup component poll the requests in the tracker to determine timeout interruption requests. The information capture component obtains the head item identifier from the item identifier chain component, obtains item information from the tracker, and sends the head item identifier to the tracker.

[0070] Figure 10 is a schematic diagram of an information capture component according to an embodiment of this application. As shown in Figure 10, the information capture component can accept software configuration to read detailed information of a specified entry, such as entry, entry identifier, chain head entry identifier and timeout entry identifier, and then report this information after dividing it into 32-bit or 64-bit entry information (entry information 0 or 1).

[0071] Figure 11 is a flowchart of the abnormal request processing method according to an embodiment of the present application. As shown in Figure 11, the abnormal request processing method can be divided into two parallel processes: chain processing and timeout detection. The chain processing process is mainly completed by the entry identifier chain component, and the timeout detection is mainly completed by three components: the search component, the timer, and the information capture component.

[0072] The chain processing flow is as follows:

[0073] Assuming the tracker depth is n, the length of the entry identifier chain component is equal to the tracker depth. When the entry identifier chain component receives a notification that the tracker has a new request, it writes the received entry identifier to the end of the entry identifier chain, i.e., at index = n-1.

[0074] In the item identifier chain component, the first empty position index=i is found from index=n-1 towards index=0. The empty position refers to the position where the item validity (Entry Valid) = 0 in the schematic diagram of the item identifier chain component.

[0075] If an empty space is found, the index bits from n-1 to i+1 are shifted downwards to n-2 to i to obtain a new entry identifier chain. Therefore, if there is an empty space, after the shift is completed, the n-1 position is always empty, preparing for the next write.

[0076] In some embodiments of this application, taking a depth of 8 as an example, the writing of the entry identifier chain when it is empty is shown in Figure 12: the highest bit is written first, index=n-1, and then shifted to index=n-2. To simplify the above operation, the position of index=n-2=6 is written directly. Subsequent operations continue in a similar manner, with the new entry identifier written at index=n-2 and the entry identifier at the original index=i shifted down to index=i-1. The shift writing diagram after a release is shown in Figure 13: when position i in the entry identifier chain is released (dealloc), the validity of the corresponding entry is lowered, and no shift is needed at this time. When a new entry identifier is written, the entry identifiers at positions n-2 to i+1 are moved to positions n-3 to i, and the new entry identifier is written to n. -2; Figure 14 is used to explain when the bar indicator chain is full and the release after it is full. From left to right, Figure 14 includes left 1, left 2, left 3 and left 4. Specifically, left 1 shows that at this time, except for the entry with the highest bit index=7 which has a validity of 0, the validity of the other entries should be 1; left 2 shows that after the last write, the validity of all entries is 1; left 3 shows that except for the entry with the entry identifier 4 which has a validity of 0, the others are 1, which is to indicate that the entry identifier 4 has been released (dealloc), but the other entries remain unchanged. Left 3 shows that index=4 has been released, and the validity of the corresponding entry should be set to 0; left 4 shows that the entry identifier with index=7 is 0, and the others are all 1. Left 4 shows that a shift has been performed, and the entries with index=7~5 in left 3 have been moved to index=6~4.

[0077] If no empty slot is found, it means that both the tracker and the entry identifier chain component are full, and you need to wait for the request to be completed to release the tracker's specified entry.

[0078] When the tracker component releases an entry, it sends the corresponding entry identifier to the entry identifier chain component. If the tracker component supports releasing multiple entries at the same time, it sends multiple entry identifiers to the entry identifier chain component simultaneously.

[0079] After the item identifier chain component queries the position j in the item identifier chain based on the received item identifier, it sets the condition validity to 0 (sets the condition validity to invalid) to release this position, and then jumps to the step of finding an empty position. The index bits from n-1 to i+1 are shifted downward to n-2 to i to obtain a new item identifier chain. If the tracker component supports releasing multiple items at the same time, the item identifier chain component needs to support the simultaneous search and release of multiple item identifiers.

[0080] Search from the 0th to the (n-1)th position of the entry identifier chain. The first entry identifier with a validity of 1 is the chain head entry identifier. Send the chain head entry identifier to the information crawling component.

[0081] The timeout detection process is as follows:

[0082] The tracker component sends k (k < n) valid entry identifiers to the lookup component. The lookup component selects one entry identifier from the k valid entry identifiers in ascending order in a polling manner. After a new entry identifier is selected, the timer component is initialized and starts timing. When the time (Time) > threshold, the bus generates a timeout interrupt to notify the software that there is a request timeout on the bus. The software processes the timeout interrupt. The tester grabs the entry identifier of the timeout request and the head entry identifier of the chain as needed through the information capture component, and determines the request corresponding to the entry identifier as an abnormal request for debugging.

[0083] The embodiment of the present application can be integrated into any node of the bus, and the requests of the node are processed by shift string chaining according to the allocation order of the entries in the tracker. Whenever new entry identifier information is recorded in the entry identifier chain, a part of the entry identifier chain is shifted by judging the idle positions in the entry identifier chain to ensure that a new entry identifier can be written at the end of the chain. When the request is released, the corresponding entry identifier is removed from the entry identifier chain. The entry identifier chain ensures that the valid bit at the head of the chain is the oldest entry identifier and the valid bit at the end of the chain is the latest entry identifier. Then, by setting a timer, the transactions in the tracker are polled and detected. When the request does not timeout and is completed, the counter is reset and the tracking of the next request is started; when the request times out, a timeout interrupt is reported, and at the same time, the head entry identifier of the entry identifier chain and the entry identifier of the current timeout request are fed back. Finally, the entry information corresponding to the head entry identifier of the chain or the entry identifier of the timeout request is grabbed through software control to assist the tester in debugging.

[0084] The embodiment of the present application adopts a partial shift string chaining + timer polling detection scheme to record and track requests. The partial shift string chaining + timer polling detection effectively reduces the resource consumption and dynamic power consumption of the chip compared with the scheme of using a large number of timers or timestamps; at the same time, the time sequence relationship of requests can be fed back through the entry identifier chain to accurately track requests, greatly improving the detection accuracy. The embodiment of the present application can be applied to the technical fields of hardware architecture and system reliability, and can identify anomalies in time and trigger the interrupt processing flow to ensure the reliability, availability and serviceability of the system. Specifically, it can be applied to chips such as CPUs and DPUs that require a timeout monitoring mechanism, and can quickly and accurately locate the hung nodes and internal detailed information when the system hangs through the embodiment of the present application.

[0085] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A method for determining abnormal requests, characterized in that, include: The tracker deployed on the node assigns a corresponding entry to each request for the node and generates an entry identifier for the entry; An entry identifier chain is generated according to the generation order of the entry identifiers, wherein the entry identifier chain includes the entry identifiers and the validity status of the entry identifiers, the validity status including valid and invalid; a timer is initialized and a timing threshold is set for the timer, wherein the timing threshold is used to indicate the preset completion time of the request; the timer is started, and the selected request to be detected is monitored within the timing threshold to determine whether the request to be detected has been completed or released; if the request to be detected has been completed or released, the timer is stopped and reset, and the next request to be detected is selected for monitoring within the timing threshold; if the request to be detected has not been completed and has not been released, the request to be detected is determined to be a timeout request, and the detected timeout request and the chain are... The request corresponding to the first entry identifier is determined to be an abnormal request; wherein, the first entry identifier is the earliest generated entry identifier in the entry identifier chain with a valid status; generating the entry identifier chain according to the generation order of the entry identifiers includes: obtaining the latest generated entry identifier, and writing the entry identifier and the validity status of the entry identifier into the entry identifier chain according to the filling status of the entry identifier chain; writing the entry identifier and the validity status of the entry identifier into the entry identifier chain according to the filling status of the entry identifier chain includes: if the tail of the chain is occupied, searching from the tail of the chain towards the head of the chain for a position with an invalid status, and if the search result is yes, updating the tail of the chain to an unoccupied state through a partial serial shift operation, and writing the entry identifier into the tail of the chain.

2. The method according to claim 1, characterized in that, The step of writing the entry identifier and its validity status into the entry identifier chain according to the filling status of the entry identifier chain further includes: writing the entry identifier and its validity status into the tail of the chain when the tail of the entry identifier chain is not occupied.

3. The method according to claim 1, characterized in that, After searching from the end of the chain to the beginning of the chain for a valid position that is invalid, the method further includes: if the search result is negative, determining that the entry identifier chain is in a full state.

4. The method according to claim 1, characterized in that, in, The depth of the tracker is equal to the length of the entry identifier chain.

5. The method according to claim 1, characterized in that, If the request corresponding to the entry identifier in the entry identifier chain is released, the method further includes: updating the validity status of the entry identifier to invalid and deleting the entry identifier from the entry identifier chain.

6. A network device, characterized in that, The network device includes a receiver, a transmitter, and a processor, and the network device is configured to perform the steps of the method according to any one of claims 1 to 5 via at least one of the receiver, the transmitter, and the processor.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the method described in any one of claims 1 to 5.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method described in any one of claims 1 to 5.

9. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method described in any one of claims 1 to 5.

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