Instruction verification method, electronic equipment and storage medium
By automating the comparison between reference and actual instruction formats, the problem of low efficiency in CCC instruction parsing and verification in the I3C protocol is solved, achieving efficient and accurate instruction code verification.
Patent Information
- Application Number
- CN202511494965.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-17
- Publication Date
- 2026-02-27
AI Technical Summary
The CCC instruction parsing and verification in the I3C protocol is inefficient, requires a lot of manpower, and has a high probability of error.
By acquiring test files, generating reference instruction formats, and comparing them with actual instruction formats, the actual instruction codes are automatically verified.
It improves the efficiency and accuracy of instruction code verification, and reduces human intervention and errors.
Smart Images
Figure CN121579282A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of data processing technology, and in particular to instruction verification methods, electronic devices, and storage media. Background Technology
[0002] CCC (Common Command Codes) are instruction codes defined in the I3C (Improved Inter-Integrated Circuit) protocol, used to instruct devices to respond to specified commands during communication. In related technologies, data packets are typically captured from the bus and initially parsed. However, the parsing results often only display the raw values of the commands and data, failing to automatically and intuitively reconstruct the complete instruction format conforming to the protocol specification. Therefore, manual consultation of protocol documents is required to interpret their meaning and perform comparisons. Due to the numerous types of I3C instruction codes and their varying formats, significant manpower is typically required for analysis, resulting in low efficiency and a high probability of errors in the parsing and verification of CCC instructions. Summary of the Invention
[0003] This application provides an instruction verification method, electronic device, and storage medium to at least solve the problem of low efficiency in instruction code verification in related technologies.
[0004] This application provides an instruction verification method, including: Obtain a test file, which includes at least the instruction code to be verified; Based on the test file, the first instruction template corresponding to the instruction code to be verified is filled in to generate a reference instruction format; Obtain the actual instruction code, and fill the second instruction template corresponding to the actual instruction code to generate the actual instruction format. The actual instruction code is obtained from the data sent by the master device under test to the slave device. The reference instruction format is compared with the actual instruction format, and the verification result of the actual instruction code is determined based on the comparison result of the reference instruction format and the actual instruction format.
[0005] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the steps of any of the above-described instruction verification methods when executing the computer program.
[0006] This application also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of any of the above-described instruction verification methods.
[0007] This application addresses the issue that, due to the numerous types of I3C instruction codes and their varying formats, analysis typically requires significant manpower. This method first obtains a test file and then fills in the first instruction template corresponding to the instruction code to be verified within the test file, thereby generating a reference instruction format. Next, the actual instruction code is obtained, and the corresponding second instruction template is filled in based on the actual instruction code to generate the actual instruction format. By comparing the reference instruction format with the actual instruction format, the verification result of the actual instruction code is determined. Finally, a standard reference instruction format is generated from the test file and compared with the instruction format parsed by the device under test during actual data transmission. This automated verification of the actual instruction code improves the efficiency and accuracy of instruction code verification, solving the problem of low verification efficiency in related technologies. Attached Figure Description
[0008] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0009] Figure 1 A flowchart of an instruction verification method provided in an embodiment of this application; Figure 2 A schematic diagram of the instruction verification device provided in the embodiments of this application; Figure 3 A structural block diagram of an electronic device provided in an embodiment of this application. Detailed Implementation
[0010] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.
[0011] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.
[0012] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0013] I3C (Improved Inter-Integrated Circuit) is an upgraded version of the traditional I2C bus (Inter-Integrated Circuit) technology, significantly improving speed, reducing power consumption, and supporting features such as in-band interrupts, hot-plugging, and dynamic address allocation. Therefore, it is widely used in mobile devices, sensor hubs, and IoT devices, enabling more powerful communication with a simpler design. CCC (Common Command Codes) are instruction codes defined in the I3C protocol, used to determine the appropriate response from a device upon receiving a specified command during communication. CCC instructions can be broadcast to all I3C slave devices or sent to specific I3C slave devices. I3C has 255 CCC instructions. Besides some reserved instructions, the remaining instructions can be selected for support by the I3C device itself, and the I3C device must implement these instructions according to the I3C CCC-defined specifications.
[0014] CCC commands are divided into two categories: broadcast commands and direct commands. Broadcast commands range from 0x00 to 0x7F and apply to all slave devices; direct commands range from 0x80 to 0xFE and apply to specific slave devices. For an I3C master, issuing the correct command code means that the slave device can correctly respond to the master's requests, and the correct CCC code can avoid communication errors and data loss, thereby improving system stability and performance. By using the correct CCC commands, the master can effectively manage devices on the I3C bus, such as dynamic address allocation and device status queries. Therefore, ensuring that CCC commands are issued correctly is particularly important in verification work. However, due to the large number of I3C command codes and the different formats between them, a lot of manpower is usually required for analysis, resulting in low efficiency and a high probability of error in CCC command parsing and verification. Based on this, this application provides a command verification method. This method is applied to an I3C protocol command verification platform, which is located on the master device under test (DUT) that transmits data with slave devices in accordance with the I3C protocol.
[0015] According to an embodiment of the present invention, an instruction verification method embodiment is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.
[0016] This embodiment provides an instruction verification method. Figure 1 This is a flowchart of an instruction verification method according to an embodiment of the present invention, such as... Figure 1 As shown, the process includes the following steps: Step S101: Obtain the test file.
[0017] The test file must include at least the instruction code to be verified. The test file defines the specific instructions that need to be verified. The verification platform can read and parse the test file from external storage media or the user interface, loading its contents into memory or configuration registers for use in subsequent steps. The instruction code to be verified is the CCC instruction code issued by the master device according to the I3C protocol.
[0018] In some alternative implementations, the test file can be a plain text file written manually, following an easy-to-parse data serialization format such as YAML or JSON. Relevant technical personnel can directly specify key-value pairs such as instruction codes, instruction types, and target addresses in the file.
[0019] In some alternative implementations, the test file may also be an output file automatically generated by a preset test generation script or tool. For example, the test generation script may automatically generate a test file of the instruction code to be verified according to a set verification plan. The test file contains several attribute fields related to the command code, which may include the command content of the command code to be verified, the length of the data carried by the command code to be verified, the command type of the command code to be verified, and the target slave device address of the command code to be verified. As an example, the test file should at least include the following: CCC code: 0x80 (ENEC) Payload: 0x55 Payload length: 2 Type: wr or rd Addr: 0x36 Here, CCC code indicates that the instruction code to be verified is between 0x00-0x7F and 0x80-0xFE; Payload indicates that the command content of the instruction code to be verified is 0x55; Payload length indicates that the length of the data carried by the instruction code to be verified is 2, and the value of Payload length is strongly correlated with the value of Payload; Type indicates the read / write type of the instruction code to be verified, wr indicates a write command, and rd indicates a read command; Addr indicates the target slave device address of the instruction code to be verified, with a value of 0x36. Additionally, it includes the instruction type of the instruction code to be verified, which includes at least direct instructions and broadcast instructions.
[0020] This step is the initialization and configuration phase of the instruction verification method, providing configurable structured input data for the entire verification process.
[0021] Step S102: Based on the test file, fill in the first instruction template corresponding to the instruction code to be verified to generate a reference instruction format.
[0022] The first instruction template is a predefined structured data framework that describes the complete format specification of the instruction corresponding to the instruction code to be verified. It may include fields such as the instruction's start address, read / write bits, acknowledge bits, repeat start condition, target slave device address, data payload, and stop condition, along with their corresponding values. The contents of the test file are mapped and numerically converted to fill the corresponding reserved fields or variable positions in the first instruction template. The generated reference instruction format is a fully instantiated, complete instruction data structure containing all values. This reference instruction format conforms to the standard specifications of the communication protocol in both semantics and syntax.
[0023] The first instruction template can be stored in a preset instruction template library, which can be a collection of template files stored in the local file system. The instruction code to be verified is matched against the first instruction template corresponding to the instruction code in the library. Specifically, the first instruction template can be determined by matching the filename or the type of the instruction code. The test file is parsed, the parameters are extracted, and then each parameter is filled into the corresponding field of the first instruction template. During the filling process, the parameter format can be converted as needed to generate a reference instruction format.
[0024] Step S103: Obtain the actual instruction code, and fill the second instruction template corresponding to the actual instruction code based on the actual instruction code to generate the actual instruction format.
[0025] The actual instruction code is obtained from the data sent by the master device under test (DUT) to the slave device. The input source of the actual instruction code is the digital signal stream that the DUT actually sends to the communication bus through its physical interface during operation. The timing signals on the bus are sampled in real time by a bus monitor or protocol analyzer module, and the serial bit stream is decoded into parallel protocol data units according to the rules of the underlying communication protocol (I3C) to extract the actual instruction code.
[0026] The second instruction template is a predefined structured data framework that describes the complete format specification of the instruction corresponding to the actual instruction code. It may include fields such as the instruction's start address, read / write bits, acknowledge bits, repeat start condition, target slave device address, data payload, and stop condition, along with their corresponding values. The contents of the test file are mapped and numerically converted to fill the corresponding reserved fields or variable positions in the second instruction template. The generated reference instruction format is a fully instantiated, complete instruction data structure containing all values. This reference instruction format conforms to the standard specifications of the communication protocol in both semantics and syntax.
[0027] The second instruction template can be stored in a preset instruction template library, which can be a collection of template files stored in the local file system. The actual instruction code is matched against the library to find the corresponding second instruction template. Specifically, the second instruction template can be determined by matching the filename or the type of the instruction code. The actual instruction code is parsed, its parameters are extracted, and then these parameters are filled into the corresponding fields of the second instruction template. During the filling process, the parameters can be formatted as needed to generate the actual instruction format. The actual instruction format represents the data structure of the instruction actually issued by the device under test.
[0028] The first instruction template and the second instruction template are stored in the same preset template library. If the instruction code to be verified is the same as the actual instruction code, then the first instruction template and the second instruction template are the same.
[0029] Step S104: Compare the reference instruction format with the actual instruction format, and determine the verification result of the actual instruction code based on the comparison result between the reference instruction format and the actual instruction format.
[0030] The reference instruction format and the actual instruction format are compared. First, the templates used in the reference instruction format and the actual instruction format are compared to see if they are consistent, that is, whether the first instruction template and the second instruction template are the same. If they are the same, the values of each filled field are further compared, including the start signal type, slave device address value, data payload, and stop signal type. Based on the comparison results, a verification result is generated and output.
[0031] If the comparison result shows that the template used for the reference instruction format is consistent with the template used for the actual instruction format, and the values of each field are the same, then the actual instruction code verification is correct. If there are inconsistencies in the templates, or if the templates are consistent but the values are inconsistent, then the actual instruction code parsing is determined to be incorrect, and the output verification result will include the error information for relevant personnel to debug.
[0032] The instruction verification method provided in this invention includes: acquiring a test file, wherein the test file includes at least an instruction code to be verified; filling a first instruction template corresponding to the instruction code to be verified based on the test file to generate a reference instruction format; acquiring the actual instruction code and filling a second instruction template corresponding to the actual instruction code based on the actual instruction code to generate an actual instruction format; comparing the reference instruction format with the actual instruction format, and determining the verification result of the actual instruction code based on the comparison result. This method generates a standard reference instruction format from the test file and compares it with the instruction format parsed by the master device under test during actual data transmission, automating the verification of the actual instruction code and improving the verification efficiency and accuracy of the instruction code.
[0033] This embodiment provides an instruction verification method, which includes the following steps: Step S201: Obtain the test file.
[0034] Please see details Figure 1 Step S101 of the illustrated embodiment will not be described again here.
[0035] Step S202: Based on the test file, fill in the first instruction template corresponding to the instruction code to be verified to generate a reference instruction format.
[0036] Specifically, step S202 includes: Step S2021: Based on the instruction code to be verified in the test file, call the first instruction template corresponding to the instruction code to be verified.
[0037] The test file specifies the relevant parameters of the instruction code to be verified, and calls the corresponding first instruction template based on these parameters. Specifically, during the instruction template invocation process, the first instruction template is obtained according to the set invocation rules. The first instruction template is related to the instruction code to be verified; for example, the corresponding first instruction template can be obtained based on the instruction content or instruction type of the instruction code to be verified.
[0038] The first instruction template is stored in a preset instruction template library. The first instruction template is a structured data frame with empty variables. This data frame defines the communication format of the instruction code to be verified, including fields such as the instruction's start address, read / write bits, acknowledge bits, repeat start condition, target slave device address, data payload, and stop condition, as well as their corresponding values.
[0039] Based on the correspondence between instruction templates and instruction codes in the preset template library, the first instruction template corresponding to the instruction code to be verified is called from the preset template library.
[0040] Step S2022: Fill in the data of each field in the first instruction template based on the parameters in the test file to generate a reference instruction format.
[0041] The parameters in the test file include fields and corresponding values for various attributes of the instruction code to be verified, such as the target slave device address, data payload, payload length, and instruction type. The target slave device address specifies the target slave device to which the instruction code to be verified is sent. The data payload provides the specific data content carried by the instruction code. The payload length defines the length of the specific data content carried by the instruction code. Instruction types include direct instructions and broadcast instructions. By parsing the test file, the fields and corresponding values of various attributes of the instruction code to be verified are obtained. By traversing all fields to be filled in the first instruction template and combining the semantics of the fields, the corresponding values are selected from the fields and corresponding values of various attributes of the instruction code to be verified obtained by parsing the test file, and these values are filled into the corresponding positions in the first instruction template according to the format specified in the protocol.
[0042] After filling all the fields to be filled in the first instruction template with values, a fully instantiated, bit-precise communication data packet is obtained, which is the reference instruction format. This reference instruction format describes the sequence of levels that should appear on the serial data line (SDA) on the bus after the start signal, in each clock cycle, until the stop signal. The reference instruction format is used as a benchmark in the subsequent verification process.
[0043] In some optional implementations, step S2021 includes: analyzing the instruction type of the instruction code to be verified; and calling a first instruction template corresponding to the instruction type from a preset template library based on the instruction type of the instruction code to be verified.
[0044] The instruction type of the instruction code to be verified is determined by parsing the test file. Specifically, if the instruction code to be verified is in the range of 0x00 to 0x7F, it is determined to be a broadcast instruction. The target of a broadcast instruction is all slave devices on the bus, and its communication frame format usually does not contain an address field specific to a particular device. If the instruction code is in the range of 0x80 to 0xFE, it is determined to be a direct instruction. Direct instructions are used to communicate with a specific slave device, and their frame structure includes a target address field and a specific sequence of repeating start signals.
[0045] Based on the analysis results of the instruction type, templates are invoked. A pre-defined template library establishes a correspondence between instruction templates and instruction types in the instruction codes. Different instruction templates are predefined and stored in the pre-defined template library according to different instruction types. After determining the instruction type of the instruction code to be verified, the instruction template corresponding to that instruction type, i.e., the first instruction template, is retrieved from the pre-defined template library.
[0046] In some optional implementations, step S2022 above includes: parsing the test file to obtain padding parameters related to the instruction code to be verified; filling the padding parameters related to the instruction code to be verified into the corresponding fields based on the field structure of the first instruction template, and generating a reference instruction format.
[0047] The parameters in the test file include padding parameters related to the command code to be verified. These parameters can include various attribute fields and their corresponding values, such as the target slave device address, data payload, payload length, and command type. The target slave device address specifies the target slave device to which the command code to be verified is sent. The data payload provides the specific data content carried by the command code. The payload length defines the length of the specific data content carried by the command code. The command type includes direct commands, broadcast commands, etc. By parsing the test file, the padding parameters related to the command code to be verified are obtained; these padding parameters constitute the parameter set.
[0048] The padding parameters are associated with placeholder fields in the first instruction template. Each field in the first instruction template is iterated over; when a placeholder field is encountered, the corresponding parameter value is retrieved from the parameter set according to the mapping rules. The data is then converted and formatted according to the template's specifications for the field's bit width, data type (e.g., binary, hexadecimal), and byte order. The converted value is then written to or replaces the original placeholder. For the data payload, the Payload length parameter is used to ensure that the generated data field length meets the protocol requirements; padding is applied if insufficient, and truncation or an error is reported if excessive. Once all variable fields in the template have been instantiated with the correct parameter values, the reference instruction format is obtained.
[0049] Step S203: Obtain the actual instruction code, and fill the second instruction template corresponding to the actual instruction code based on the actual instruction code to generate the actual instruction format.
[0050] Specifically, obtaining the actual instruction code in step S203 includes: acquiring the physical signals emitted by the master device under test based on the I3C bus; parsing the physical signals to obtain the actual instruction code.
[0051] The verification platform continuously monitors the serial clock and serial data lines connected between the master and slave devices under test. While the serial clock line remains high, when a negative transition from high to low occurs on the serial data line, the platform's acquisition module synchronizes with the timing reference provided by the serial clock line. At the rising edge of each serial data line clock cycle, it samples and records the logic level on the serial data line, thus acquiring the physical signal. The acquired physical signal is then parsed according to the I3C protocol's frame structure standard to obtain the actual instruction code.
[0052] Specifically, in step S203, the second instruction template corresponding to the actual instruction code is filled in based on the actual instruction code to generate the actual instruction format, including: Step S2031: Based on the instruction type of the actual instruction code, call the second instruction template corresponding to the instruction type from the preset template library.
[0053] The actual instruction code is parsed to determine its instruction type. Specifically, if the actual instruction code is in the range of 0x00 to 0x7F, it is determined to be a broadcast instruction. The target of a broadcast instruction is all slave devices on the bus, and its communication frame format typically does not contain an address field specific to a particular device. If the instruction code is in the range of 0x80 to 0xFE, it is determined to be a direct instruction. Direct instructions are used to communicate with a specific slave device, and their frame structure includes a target address field and a specific sequence of repeating start signals.
[0054] Based on the analysis results of the instruction type, templates are invoked. A pre-defined template library establishes a correspondence between instruction templates and instruction types of instruction codes. Different instruction templates are predefined and stored in the pre-defined template library according to different instruction types. After determining the instruction type of the instruction code to be verified, the corresponding instruction template, i.e., the second instruction template, is retrieved from the pre-defined template library.
[0055] Step S2032: Parse the actual instruction code to obtain the padding parameters of the actual instruction code.
[0056] By parsing the actual command code, the associated padding parameters are obtained. These parameters can include various attribute fields and their corresponding values, such as the target slave device address, data payload, payload length, and command type. The target slave device address specifies the target slave device to which the command code to be verified is sent. The data payload provides the specific data content carried by the command code. The payload length defines the length of the specific data content carried by the command code. The command type includes direct commands, broadcast commands, etc. These padding parameters constitute a parameter set.
[0057] Step S2033: Based on the field structure of the second instruction template, fill the actual instruction code filling parameters into the corresponding fields to generate the actual instruction format.
[0058] The padding parameters are associated with placeholder fields in the second instruction template. Each field in the second instruction template is iterated over; when a placeholder field is encountered, the corresponding parameter value is retrieved from the parameter set according to the mapping rules. Then, the data is converted and formatted according to the template's specifications for the field's bit width, data type (e.g., binary, hexadecimal), and byte order. The converted value is written to or replaces the original placeholder. For the data payload, the Payload length parameter is used to ensure that the generated data field length meets the protocol requirements; if insufficient, padding is performed; if excessive, truncation or an error is reported. Once all variable fields in the template have been instantiated with the correct parameter values, the actual instruction format is obtained.
[0059] Step S204: Compare the reference instruction format with the actual instruction format, and determine the verification result of the actual instruction code based on the comparison result between the reference instruction format and the actual instruction format.
[0060] In some optional implementations, the step S204 of determining the verification result of the actual instruction code based on the comparison result between the reference instruction format and the actual instruction format includes: if the reference instruction format is consistent with the actual instruction format, then the actual instruction code is determined to have passed verification.
[0061] In some optional implementations, the step S204 of determining the verification result of the actual instruction code based on the comparison result between the reference instruction format and the actual instruction format further includes: if the reference instruction format is consistent with the actual instruction format, then the actual instruction code is determined to be in error and an error report is output.
[0062] The reference instruction format and the actual instruction format are compared. First, the templates used in the reference instruction format and the actual instruction format are compared to see if they are consistent, that is, whether the first instruction template and the second instruction template are the same. If they are the same, the values of each filled field are further compared, including the start signal type, slave device address value, data payload, and stop signal type. Based on the comparison results, a verification result is generated and output.
[0063] If the comparison result shows that the template used for the reference instruction format is consistent with the template used for the actual instruction format, and the values of each field are the same, then the actual instruction code verification is correct. If there is a template inconsistency, or a situation where the templates are consistent but the values are inconsistent, then the actual instruction code parsing is determined to be incorrect, and the output verification result will include the error information, i.e., an error report will be output for relevant personnel to debug.
[0064] From the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.
[0065] Embodiments of this application also provide an instruction verification device for implementing the above embodiments and preferred embodiments, which will not be repeated hereafter. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.
[0066] This embodiment provides an instruction verification device, such as... Figure 2 As shown, it includes: The file acquisition module is used to acquire test files, which include at least the instruction codes to be verified. The first generation module is used to fill the first instruction template corresponding to the instruction code to be verified based on the test file to generate a reference instruction format; The second generation module is used to obtain the actual instruction code and fill the second instruction template corresponding to the actual instruction code to generate the actual instruction format. The actual instruction code is obtained from the data sent by the master device under test to the slave device. The comparison and verification module is used to compare the reference instruction format with the actual instruction format, and determine the verification result of the actual instruction code based on the comparison result of the reference instruction format and the actual instruction format.
[0067] In some alternative implementations, the first generation module includes: The first template invocation unit is used to invoke the first instruction template corresponding to the instruction code to be verified in the test file. The first generation unit is used to fill data into each field of the first instruction template based on the parameters in the test file to generate a reference instruction format.
[0068] In some optional implementations, the first template invocation unit is further configured to analyze the instruction type of the instruction code to be verified; and to invoke the first instruction template corresponding to the instruction type from a preset template library based on the instruction type of the instruction code to be verified.
[0069] In some optional implementations, the first generation unit is further configured to parse the test file to obtain padding parameters related to the instruction code to be verified; and to fill the padding parameters related to the instruction code to be verified into the corresponding fields based on the field structure of the first instruction template to generate a reference instruction format.
[0070] In some alternative implementations, the second generation module includes: The signal acquisition unit is used to acquire the physical signals emitted by the device under test based on the I3C bus; The signal parsing unit is used to parse the physical signal to obtain the actual instruction code.
[0071] In some optional implementations, the second generation module further includes: The second calling unit is used to call a second instruction template corresponding to the instruction type from a preset template library based on the instruction type of the actual instruction code; The instruction code parsing unit is used to parse the actual instruction code to obtain the padding parameters of the actual instruction code; The second generation unit is used to fill the actual instruction code with the filling parameters into the corresponding fields based on the field structure of the second instruction template, thereby generating the actual instruction format.
[0072] In some optional implementations, the comparison verification module includes: The first determination unit is used to determine that the actual instruction code verification is successful if the reference instruction format is consistent with the actual instruction format.
[0073] In some optional implementations, the comparison verification module includes: The second determination unit is used to determine that the actual instruction code verification is incorrect if the reference instruction format is consistent with the actual instruction format, and to output an error report.
[0074] For a description of the features in the embodiment corresponding to the instruction verification device, please refer to the relevant description of the embodiment corresponding to the instruction verification method, which will not be repeated here.
[0075] Embodiments of this application also provide an electronic device, such as... Figure 3 As shown, it includes a memory 10 and a processor 20. The memory 10 stores a computer program, and the processor 20 is configured to run the computer program to perform the steps in any of the above-described instruction verification method embodiments.
[0076] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described instructions verification method embodiments when it is run.
[0077] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.
[0078] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described instruction verification method embodiments.
[0079] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described instruction verification method embodiments.
[0080] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0081] The foregoing has provided a detailed description of the instruction verification method, electronic device, and storage medium provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to aid in understanding the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.
Claims
1. An instruction verification method, characterized by, The method comprises the following steps: acquiring a test file, wherein the test file comprises at least instruction codes to be verified; filling a first instruction template corresponding to the instruction codes to be verified based on the test file to generate a reference instruction format; acquiring actual instruction codes, and filling a second instruction template corresponding to the actual instruction codes based on the actual instruction codes to generate an actual instruction format, wherein the actual instruction codes are obtained according to data sent by a master device to be tested to a slave device; comparing the reference instruction format with the actual instruction format, and determining a verification result of the actual instruction codes based on a comparison result of the reference instruction format and the actual instruction format.
2. The instruction verification method according to claim 1, characterized in that, The step of filling the first instruction template corresponding to the instruction codes to be verified based on the test file to generate the reference instruction format comprises the following steps: calling the first instruction template corresponding to the instruction codes to be verified based on the instruction codes to be verified in the test file; filling data in each field in the first instruction template based on parameters in the test file to generate the reference instruction format.
3. The instruction verification method according to claim 2, wherein The step of calling the first instruction template corresponding to the instruction codes to be verified based on the instruction codes to be verified in the test file comprises the following steps: analyzing an instruction type of the instruction codes to be verified; calling the first instruction template corresponding to the instruction type from a preset template library based on the instruction type of the instruction codes to be verified.
4. The instruction verification method according to claim 2, wherein The step of filling data in each field in the first instruction template based on parameters in the test file to generate the reference instruction format comprises the following steps: parsing the test file to obtain filling parameters related to the instruction codes to be verified; filling the filling parameters related to the instruction codes to be verified into corresponding fields based on a field structure of the first instruction template to generate the reference instruction format.
5. The instruction verification method according to claim 1, wherein The step of acquiring the actual instruction codes comprises the following steps: collecting physical signals sent by the master device to be tested based on an I3C bus; parsing the physical signals to obtain the actual instruction codes.
6. The instruction verification method according to claim 1, wherein The step of filling the second instruction template corresponding to the actual instruction codes based on the actual instruction codes to generate the actual instruction format comprises the following steps: calling the second instruction template corresponding to an instruction type of the actual instruction codes from a preset template library based on the instruction type of the actual instruction codes; parsing the actual instruction codes to obtain filling parameters of the actual instruction codes; filling the filling parameters of the actual instruction codes into corresponding fields based on a field structure of the second instruction template to generate the actual instruction format.
7. The instruction verification method according to claim 1, wherein The step of determining the verification result of the actual instruction codes based on the comparison result of the reference instruction format and the actual instruction format comprises the following steps: if the reference instruction format is consistent with the actual instruction format, it is determined that the actual instruction codes pass the verification.
8. The instruction verification method according to claim 1, wherein The step of determining the verification result of the actual instruction codes based on the comparison result of the reference instruction format and the actual instruction format further comprises the following steps: if the reference instruction format is inconsistent with the actual instruction format, it is determined that the actual instruction codes fail the verification, and an error report is output.
9. An electronic device, comprising: The computer program product comprises a memory for storing the computer program. A processor, configured to implement the steps of the instruction verification method as described in any one of claims 1 to 8 when executing the computer program.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the instruction verification method as described in any one of claims 1 to 8.