Test method and device for memory system

Abstract

The embodiment of the invention provides a test method and device for a memory system. Receiving a test command, wherein the test command at least comprises an initial address, a burst length, a base address and a test address size; determining a traversal interval of the size of the test address at least according to the initial address, the burst length and the base address; respectively traversing the initial address, the burst length, the base address and the size of the test address according to the traversal interval of the size of the test address, and acquiring a test request and test data corresponding to the test command; and comparing the test request with a standard request, and / or comparing the test data with standard data to obtain a test result. Therefore, all conditions possibly existing in the request range and the robust range in robustness detection are covered, the test results under the corresponding conditions are obtained, and the test efficiency is improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of chip testing, and in particular to a memory system testing method and device. BACKGROUND

[0002] In the design of modern GPU, NPU and other parallel acceleration chips, the performance and efficiency of the memory subsystem are very important for the performance improvement of the chip. SIMT (Single Instruction Multiple Threads) is a widely used parallel computing architecture in modern GPU, and the core idea is to control multiple threads to execute the same instruction in parallel. Multiple threads will form a thread bundle to execute the same instruction. If the instruction is a memory access instruction, the address accessed by each thread is usually different. If each request generates an access to the cache, it will cause pressure on the cache. In order to improve the utilization of the memory, a memory merging module is needed in front of the cache to merge different addresses in the same thread bundle by cache line size granularity, thereby reducing the access pressure on the cache. The granularity of data requested by each thread may be different, such as accessing any number of bytes (but usually there is an upper limit). The granularity of data requested by each thread is called burst (burst request).

[0003] In this way, the following situation may exist: only the data within a certain address range is valid (for example, there is a physical address in the memory), but the data requested by each thread may exceed the valid range. The data exceeding the valid range can be discarded in advance, thereby further reducing redundant requests and reducing the pressure on the memory subsystem.

[0004] Therefore, in order to improve the performance of the memory subsystem, robustness detection is generally performed when the request enters the memory subsystem, and only the request passing the detection is sent downstream. In this way, the pressure on the downstream memory module can be reduced, unnecessary memory lookup can be reduced, and errors caused by invalid address access can be avoided in advance, thereby improving the performance and efficiency of the memory subsystem.

[0005] However, the inventors found that there are some complex scenarios in robustness detection, for example, in robustness detection, a robust buffer (RB) range is defined using two parameters of buffer base and buffer size, and the RB range is [buffer base, buffer base + buffer size -1]. One request usually contains a start address of the request and a burst length of the bytes required by the request, and the address of the last byte of the request is end address = start address + burst length -1. At this time, the request has the following cases:

[0006] 1. Start address ≤ end address < buffer base

[0007] 2. Start address < buffer bases ≤end address < buffer base + buffersize

[0008] 3. Buffer base ≤ start address ≤ end address < buffer base + buffersize

[0009] 4. Buffer base ≤ start address < buffer base + buffer sizes ≤ endaddress

[0010] 5. Buffer base + buffer sizes ≤ start address ≤ end address

[0011] For the part of the request address within the RB range, normal processing is performed, that is, a request is initiated to the memory subsystem; for the part of the request address outside the RB range, the part of the request is not sent to the memory subsystem, and it is usually determined to return 0 directly.

[0012] Since the request address is byte-granular, the degree of freedom is very high, and the request address range and the RB range may appear the above various cases, which will increase the test scenarios when the chip is tested.

[0013] In addition, in the memory subsystem, each cacheline of each level of cache has a length limit, and therefore, a request sent to the memory subsystem must be in the granularity of the length of the cacheline. When a request crosses the boundary of a cacheline, the request is split into two requests and sent downstream separately due to the length limit of the cacheline. In addition, the data width of the return path also has a limit, and if the maximum burst length allowed by the request is greater than the limit, the return data corresponding to the request will be split into multiple pieces of data, which will make the test scenario more complex. For example, the data width of the return path is only 16 bytes, but the maximum burst length of a request on the request path is 32 bytes. Therefore, two responses are needed to return to the request source. In addition, it is assumed that the request crosses the boundary of a cacheline and 2 taps are needed to return all the data. The return value of the second tap falls into the previous cacheline and the next cacheline, and therefore, data needs to be cropped and merged when the data is returned to the request source.

[0014] On the request path, the split request can also be analyzed according to the robustness detection scenario to generate many scenarios. Therefore, robustness detection and cross-border detection, and some extreme boundary scenarios may also exist, which will generate a large number of complex scenarios, causing difficulties in testing.

[0015] Generally, a large number of system tests can be used to cover these functional scenarios. However, system tests need to be constructed manually and cannot cover all scenarios. In addition, due to potential interference of other modules in the system, it is difficult to quickly and accurately locate the problem source once an error occurs during the test process. In addition, the test results also need to be compared manually, which leads to low test efficiency.

[0016] It should be noted that the above introduction to the technical background is only to facilitate a clear and complete description of the technical solutions of the present application and facilitate the understanding of those skilled in the art. SUMMARY

[0017] To solve at least one of the above technical problems or other similar problems, embodiments of the present application provide a memory system test method and device.

[0018] According to a first aspect of embodiments of the present application, a memory system test method is provided, and the test method comprises:

[0019] receiving a test command, wherein the test command at least includes a start address, a burst length, a base address, and a test address size;

[0020] The traversal range of the test address size is determined at least based on the starting address, the burst length, and the base address;

[0021] The starting address, burst length, base address, and test address size are traversed according to the traversal interval of the test address size, and the test request and test data corresponding to the test command are obtained.

[0022] The test request is compared with the standard request, and / or the test data is compared with the standard data to obtain the test result.

[0023] In some embodiments, the testing method further includes:

[0024] The standard request and standard data are determined at least according to the test command.

[0025] In some embodiments, determining the standard request and standard data at least according to the test command includes:

[0026] In the case where the first address range and the second address range overlap, the addresses within the first address range that are located within the second address range are designated as the third address range, and the addresses within the first address range that are located outside the second address range are designated as the fourth address range. The first address range includes the address from the starting address to the first address, where the first address is the address obtained by subtracting one from the sum of the starting address and the burst length. The second address range includes the address from the base address to the second address, where the second address is the address obtained by subtracting one from the sum of the base address and the test address size.

[0027] When the test command is a read command, the address range of the standard request is determined, which includes the first address range. The standard data is also determined, which includes data pre-stored in the memory system corresponding to the third address range and data 0 corresponding to the fourth address range.

[0028] When the test command is a write command, the address range of the standard request is determined, the address range of the standard request includes the first address range, and the standard data is determined, the standard data includes the data in the third address range carried by the test command corresponding to the third address range, and the data to be discarded corresponding to the fourth address range.

[0029] In some embodiments, determining the standard request and standard data at least according to the test command further includes:

[0030] If the first address range and the second address range do not overlap, the standard request is discarded.

[0031] When the test command is a read command, the standard data is determined, and the standard data includes data 0 corresponding to the first address range.

[0032] When the test command is a write command, the standard data is determined, which includes data that will be discarded corresponding to the first address range.

[0033] In some embodiments, determining the traversal interval for the test address size based at least on the starting address, the burst length, and the base address includes:

[0034] The traversal range of the test address size is determined based on the starting address, the burst length, the base address, and the memory subsystem attribute data; the memory subsystem attribute data includes at least one of the cache line length and the interface data width.

[0035] In some embodiments, determining the traversal range of the test address size based on the starting address, the burst length, the base address, and memory subsystem attribute data includes:

[0036] If the burst length is greater than the interface data width, the traversal interval is determined based on the starting address, the burst length, the base address, and the interface data width.

[0037] If the address range from the starting address to the first address crosses the cache line boundary, the traversal interval is determined based on the starting address, the burst length, the base address, and the cache line length, where the first address is the address obtained by subtracting one from the sum of the starting address and the burst length.

[0038] In some embodiments, determining the standard request and standard data at least according to the test command includes:

[0039] The standard request and standard data are determined based on the test command and the interface data width, wherein,

[0040] If the burst length is greater than the interface data width, the standard request is determined, the standard request includes multiple standard sub-requests segmented with the interface data width as the granularity, and the standard data is determined, the standard data includes standard sub-data corresponding to the standard sub-requests, and the data width of each standard sub-data is not greater than the interface data width.

[0041] In some embodiments, determining the standard request and standard data at least according to the test command includes:

[0042] The standard request and standard data are determined based on the test command and the cache line length, wherein,

[0043] If the address range from the starting address to the first address crosses the cache line boundary, the standard request is determined, the standard request includes multiple standard sub-requests divided with the cache line length as the granularity, and the standard data is determined, the standard data includes standard sub-data corresponding to the standard sub-requests, the data width of each standard sub-data is not greater than the cache line length, and the first address is the address obtained by subtracting one from the sum of the starting address and the burst length.

[0044] In some embodiments, the testing method further includes:

[0045] When the minimum value of the traversal range of the starting address is equal to the minimum value of the traversal range of the base address, the starting address is shifted to the right using a predetermined offset parameter.

[0046] According to a second aspect of the embodiments of this application, a testing apparatus for a memory system is provided, the testing apparatus comprising:

[0047] A receiving unit receives a test command, the test command including at least a start address, burst length, base address, and test address size;

[0048] The determining unit determines the traversal interval of the test address size based at least on the starting address, the burst length, and the base address;

[0049] The acquisition unit traverses the starting address, the burst length, the base address, and the test address size according to the traversal interval of the test address size, and acquires the test request and test data corresponding to the test command.

[0050] The comparison unit compares the test request with the standard request, and / or compares the test data with the standard data to obtain the test result.

[0051] According to a third aspect of the embodiments of this application, a computer-readable storage medium is provided, the computer-readable storage medium storing a computer program, which, when executed by a processor, implements the test method described in any embodiment of the first aspect.

[0052] According to a fourth aspect of the present application, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the testing method described in any embodiment of the first aspect.

[0053] According to a fifth aspect of the embodiments of this application, a computer program product is provided, the computer program product including a computer program, which, when executed by a processor, implements the test method described in any embodiment of the first aspect.

[0054] One of the beneficial effects of this application embodiment is that: determining the traversal interval of the test address size based on the starting address, burst length, and base address enables the mapping of the request range determined by the starting address and burst length to the traversal interval of the test address size. By traversing the starting address, burst length, base address, and test address size according to the traversal interval of the test address size, the request range corresponding to the traversal interval of the test address size can be traversed when traversing the robust range (RB range) determined by the base address and test address size. This covers all possible cases of the request range and robust range in robustness testing, obtains the test results under the corresponding conditions, and improves testing efficiency.

[0055] Referring to the following description and accompanying drawings, specific implementation methods of the embodiments of this application are disclosed in detail, indicating how the principles of the embodiments of this application can be adopted. It should be understood that the implementation methods of this application are not limited in scope. Within the spirit and scope of the appended claims, the implementation methods of this application include many changes, modifications, and equivalents.

[0056] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0057] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components. Attached Figure Description

[0058] The accompanying drawings, which form part of the specification, are used to provide a further understanding of the embodiments of this application and illustrate the implementation methods of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other implementation methods based on these drawings without creative effort. In the drawings:

[0059] Figure 1 This is a schematic diagram of a testing method according to an embodiment of this application;

[0060] Figure 2 This is a schematic diagram illustrating the robustness testing function of the memory system;

[0061] Figure 3 This is a schematic diagram of the flow of the testing method according to an embodiment of this application;

[0062] Figure 4 This is a diagram showing the comparison between the first and second address ranges during the traversal of the base address and test address sizes.

[0063] Figure 5 This is a diagram showing the comparison between the first and second address ranges during the traversal of the base address and test address sizes.

[0064] Figure 6 This is a diagram showing the comparison between the first and second address ranges during the traversal of the base address and test address sizes.

[0065] Figure 7 This is a diagram showing the comparison between the first and second address ranges during the traversal of the base address and test address sizes.

[0066] Figure 8 This is a diagram showing the comparison between the first and second address ranges during the traversal of the base address and test address sizes.

[0067] Figure 9 This is a schematic diagram of a test apparatus according to an embodiment of this application. Detailed Implementation

[0068] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the embodiments of this application will be further described in detail below with reference to the accompanying drawings. Here, the illustrative embodiments and descriptions of this application are used to explain this application, but are not intended to limit this application.

[0069] Example 1

[0070] This application provides a method for testing a memory system. Figure 1 This is a schematic diagram of a testing method according to an embodiment of this application.

[0071] like Figure 1 As shown, the test method described in this application embodiment includes:

[0072] 100: Receive test command, the test command includes at least the start address (start byte), burst length, buffer base address, and test address size (buffer size);

[0073] 101: Determine the traversal range of the test address size (buffer size) based at least on the start address (start byte), the burst length, and the buffer base address;

[0074] 103: Traverse the start address, burst length, buffer base, and buffer size according to the traversal interval of the test address size (buffer size), and obtain the test request and test data corresponding to the test command;

[0075] 105: Compare the test request with the standard request, and / or compare the test data with the standard data to obtain the test result.

[0076] It is worth noting that the above appendix Figure 1 The embodiments of this application have only been illustrated schematically, and the application is not limited thereto. For example, some of the above steps can be performed simultaneously or in a specific order, and the execution order between the various operations can be appropriately adjusted. Furthermore, other operations can be added or some operations can be removed. Those skilled in the art can make appropriate modifications based on the above description, and are not limited to the above-described embodiments. Figure 1 The records.

[0077] In this embodiment, the traversal interval of the test address size is determined based on the starting address, burst length, and base address. This allows the request range determined by the starting address and burst length to be mapped to the traversal interval of the test address size. By traversing the starting address, burst length, base address, and test address size according to the traversal interval of the test address size, the request range corresponding to the traversal interval of the test address size can be traversed while traversing the robust range (RB range) determined by the base address and test address size. This covers all possible situations where the request range and robust range may exist in robustness testing, obtains test results for the corresponding scenarios, and improves testing efficiency.

[0078] In addition, the traversal range of the test address size can be further determined based on the cache line length, thereby constructing a scenario where the request range overlaps with the robustness range while crossing the cache line. That is, the coverage of the test scenario is further expanded, and the robustness detection function of the system is tested in more complex scenarios, thereby realizing the testing of the robustness detection function of the memory subsystem in all scenarios.

[0079] The following is a detailed explanation.

[0080] For example, a memory system can be defined using the following parameters:

[0081] M: The maximum allowed burst length.

[0082] N: Interface data width, which must satisfy N≤M.

[0083] L: Length of the cache line.

[0084] In some embodiments, the traversal range of the start address (start byte) is [0, L-1], the traversal range of the burst length (burst length) is [1, M], the traversal range of the buffer base (buffer base) is [0, L-1], and the traversal range of the test address (buffer size) gradually increases from 0. By changing the value of the test address (buffer size), the RB range (RB range is [buffer base, buffer base + buffer size - 1]) can be changed, thereby constructing various scenarios that robustness detection may encounter based on the corresponding start address (start byte), burst length (burst length), and buffer base (buffer base). This will be explained in detail below.

[0085] For example, given a request, the following symbols are used to represent request parameters:

[0086] n: starting address (start byte)

[0087] m: burstlength

[0088] b: Base address (buffer base)

[0089] s: Test address size (buffer size)

[0090] Let (n, m, b, s) represent a request sent from upstream. The request can be a read request or a write request. A read request needs to return data based on the request information n, m, b, s. A write request, in addition to containing the request information n, m, b, s, also carries the corresponding data.

[0091] Figure 2 This is a schematic diagram illustrating the robustness testing function of a memory system.

[0092] For a request (n, m, b, s), the starting address of the request is n, and the ending address (end byte) can be represented as n+m-1. The range of RB is [b, b+s-1]. According to the definition of robustness testing, only the portion of the request within the address range [b, b+s-1] is processed normally. For example, if it is a read request, only the portion within the address range [max(n, b), min(n+m-1, b+s-1)] returns valid data, and the rest is 0 by convention; if it is a write request, only the data within the address range [max(n, b), min(n+m-1, b+s-1)] is valid and can be sent downstream, while the rest is marked as invalid data in the memory merging module before being sent to the downstream module.

[0093] like Figure 2 As shown, for example, if n is less than b, and n+m-1 is greater than b and less than b+s-1, taking a read request as an example, the data in the address range [b, n+m-1] of cache line 201 will be returned (i.e., response1), while for the remaining part, i.e., the part in the address range [n, b-1], 0 will be returned (i.e., response0). In this case, it can be considered that the golden data (standard data) includes the data corresponding to the address range [b, n+m-1] and the 0 corresponding to the address range [n, b-1]. Taking a write request as an example, the data in the request carried within the address range [b, n+m-1] will be written into the address range [b, n+m-1] of cache line 201, while the remaining part, i.e., the data in the request carried within the address range [n, b-1], will be marked in the memory merging module and then sent to the downstream module.

[0094] In some embodiments, the testing method may further include:

[0095] The standard request and standard data (golden) are determined at least according to the test command.

[0096] In some embodiments, standard requests and standard data can be determined based on test commands. For example, standard requests and standard data can be determined based on the overlap of a first address range determined by the starting address and the burst length, and a second address range determined by the base address and the test address size, as well as the command type (read command or write command).

[0097] In this embodiment of the application, the first address range includes the address range from the starting address to the first address, where the first address is the address obtained by subtracting one from the sum of the starting address and the burst length, and the first address range can be represented as [n, n+m-1]; the second address range includes the address range from the base address to the second address, where the second address is the address obtained by subtracting one from the sum of the base address and the test address size, and the second address range can also be referred to as the RB range, which can be represented as [b, b+s-1].

[0098] In other embodiments, the standard request and standard data can be determined jointly based on the test command and memory subsystem attribute data, whereby the memory subsystem attribute data includes at least one of the cache line length and the interface data width. For example, the standard request and standard data can be determined based on the burst length and the interface data width, or they can be determined based on the first address range and the cache line length.

[0099] The following is based on Figure 2 The test method described in the embodiments of this application will be illustrated using an example.

[0100] In operation 100, the received test command may be issued by the upstream. For example, a test command includes a test request and a request type. The request type may include a read request and a write request. In addition, when the test request is a write request, the test command also includes the associated write data. In this case, the associated write data is used as the test data. When the test request is a read request, the test data corresponding to the test request is the returned data.

[0101] The following explanation uses a read request as an example. In operation 101, the traversal range of s can be determined based on the request information n, m, and b contained in the read request. For example, the traversal range of s can start from 0 and gradually increase. If it increases to the point where the range RB [b, b+s-1] crosses the boundary 203 between cache line 201 and cache line 202, then the test scenario can cover scenarios that cross cache lines. For example, as... Figure 2 As shown, assuming s increases to s', and the traversal range of s is from 0 to s', then the traversal interval of s can include [0, n+mb] and [n+m-b+1, s'].

[0102] When the traversal interval of s is [0, n+mb], such as Figure 2As shown, the RB range is within the address range of cache line 201. The standard request is (n, m, b, s). The standard data includes 0 corresponding to the address range [n, b-1] and the data of the corresponding address range [b, n+m-1] pre-stored in cache line 201. The test data are response0 and response1. Then, the test data is compared with the standard data. When the traversal interval of s is [n+m-b+1, s'], the RB range includes both the part of cache line 201 and the part of cache line 202. Since the address range [n, n+m-1] is still within cache line 201, there is no problem of cross-line reading. Therefore, the standard data corresponding to the standard request (n, m, b, s) is still 0 corresponding to the address range [n, b-1] and the data of the corresponding address range [b, n+m-1] pre-stored in cache line 201.

[0103] On the other hand, when the traversal interval of s is [n+m-b+1, s'], if the values ​​of n and m cause the address range [n, n+m-1] to cross the boundary 203 between cache line 201 and cache line 202, for example, ... Figure 2 As shown, assuming m is m', the address range [n, n+m'-1] crosses the boundary 203 between cache line 201 and cache line 202, requiring two cacheline requests to be sent downwards. The first request's address range is [n, L-1] (assuming the starting address of cache line 201 is 0), and the second request's address range is [L, n+m'-1]. Furthermore, in the first request, only the address range [b, L-1] returns valid data; the address range [n, b-1] returns 0. That is, the standard data at this time includes the 0 corresponding to address range [n, b-1] and the data pre-stored in cache line 201 corresponding to address range [b, L-1]. In the second request, the address range [L, n+m'-1] is entirely within the RB range, and the standard data at this time includes the data pre-stored in cache line 202 corresponding to address range [L, n+m'-1].

[0104] For the testing method of this application embodiment, after obtaining the golden data, the testing process can be represented by the following pseudocode:

[0105]

[0106] Ideally, the value of n should be in the range [0, L-1]. However, this could lead to negative values ​​in the robust buffer. For example, to cover all scenes, the value of the buffer base should ideally be smaller than the start byte. Therefore, shifting the range of n to the right by x (x>0) bytes ensures that all scenes are traversed. x can be any integer greater than 0, such as 4, 8, 16, etc. This application does not impose any restrictions on the value of x.

[0107] Figure 3 This is a schematic diagram of the test method flow according to an embodiment of this application.

[0108] The following uses Figure 3 The testing methods of the embodiments of this application will be further described.

[0109] like Figure 3 As shown, process 300 may include:

[0110] Step 301: Pre-set M, N, L, x;

[0111] Step 302: Iterate through n, where the range of n is [x, x+L-1];

[0112] Step 303: Iterate through m, where the value of m is in the range [1, M];

[0113] Step 304: Iterate through b, where the range of b is [x-1, L+x];

[0114] Step 305: Determine whether b > n + m - 1. If yes, proceed to step 306; if no, proceed to step 307.

[0115] Step 306: Restrict the range of values ​​for s to [0, 1];

[0116] Step 307: Restrict the range of values ​​for s to [0, n+m-1-b];

[0117] Step 308: Generate or write data according to the rules;

[0118] Step 309: Generate a request to the next level cache according to the rules;

[0119] Step 310: Compare with model / RTL;

[0120] Step 311: Test passed;

[0121] Step 312: Test failed;

[0122] Step 313: End.

[0123] In step 301, a memory system is defined by setting M, N, and L, which allows for testing the robustness of any memory system. Additionally, x is predefined as a number greater than 0; for example, x is set to 8, which shifts the starting address n to the right by 8 bytes.

[0124] In steps 302 and 303, n is iterated according to the range of n values, and m is iterated according to the range of m values.

[0125] In step 304, the value of b starts from x-1, which ensures that the beginning of the first address range precedes the beginning of the second address range. This covers scenarios where the requested address range is outside the RB range and overlaps with the first half of the RB range. The value of b ends at L+x, ensuring that the beginning of the RB range traverses the entire cache line.

[0126] In some embodiments, when the first address range and the second address range overlap, addresses within the first address range but located within the second address range are designated as the third address range, and addresses within the first address range but located outside the second address range are designated as the fourth address range.

[0127] When the test command is a read command, the address range of the standard request includes the first address range, and the standard data includes data pre-stored in the memory system within the third address range corresponding to the third address range and data 0 corresponding to the fourth address range.

[0128] When the test command is a write command, the address range of the standard request includes the first address range, and the standard data includes the data in the third address range carried by the test command corresponding to the third address range and the data to be discarded corresponding to the fourth address range.

[0129] In some embodiments, if the first address range and the second address range do not overlap, the standard request is discarded.

[0130] When the test command is a read command, the standard data includes data 0 corresponding to the first address range.

[0131] When the test command is a write command, the standard data includes data that will be discarded corresponding to the first address range.

[0132] For example,

[0133] In step 305, the size of b is compared with that of n+m-1, that is, the size relationship between the end of the first address range (n+m-1) and the beginning of the second address range (b) is determined. If b is greater than n+m-1, it means that the entire RB range is located outside the right side of the requested address range, and the request is invalid. If b is less than or equal to n+m-1, it means that the RB range overlaps with the requested address range, and the request is at least partially valid.

[0134] In step 306, that is, when the entire RB range is outside the right side of the requested address range, s takes the values ​​0 and 1, where 0 represents a special scenario and 1 represents all scenarios where s > 0. Thus, even when the entire RB range is outside the right side of the requested address range, all possible scenarios are traversed.

[0135] In step 307, when the RB range overlaps with the requested address range, the value range of s is [0, n+m-1-b]. When traversing s, the RB range can gradually shift to the right from the right end of the RB range, which is located to the left of the right end of the requested address range, until it coincides with the right end of the requested address range. During this process, initially only the middle part of the requested address range that coincides with the RB range (i.e., the part in [b, b+s-1]) is valid, while the rest (i.e., the parts on both sides outside [b, b+s-1]) is outside the RB range and is invalid. This continues until the right end of the RB range coincides with the right end of the requested address range, at which point the right part of the requested address range (i.e., the part in [b, n+m-1]) becomes valid, while the rest (i.e., the parts on the left outside [b, n+m-1]) is outside the RB range and is invalid.

[0136] In steps 308 and 309, according to the robustness detection rules, the system will generate a request to the next level cache and the corresponding write data, or receive the corresponding return data. Here, the generated write data or the received return data can be used as "test data", and the generated request to the next level cache can be used as "test request".

[0137] In step 310, the test data is compared with standard data, and the test request is compared with the standard request. The standard data and standard request are obtained by the memory subsystem to be verified (which is, for example, the code to be verified implemented in model / RTL) according to the corresponding n, m, b, and s. If the comparison results are the same, it means that the robustness detection function of the system is complete, and the test can be considered to have passed. If the comparison results are different, it means that the robustness detection function of the system has defects, and the test can be considered to have failed.

[0138] In this way, all possible scenarios that robustness testing may encounter can be traversed for memory systems with different configurations, and the robustness testing function of the system can be tested in these scenarios, avoiding the problem of insufficient testing due to missed scenarios.

[0139] In some embodiments, when determining the traversal range of the test address size (buffer size), the traversal range can also be determined based on memory subsystem attribute data. Memory subsystem attribute data includes, for example, at least one of cacheline length and interface data width.

[0140] For example, if the burst length is greater than the interface data width, the traversal interval is determined based on the starting address, the burst length, the base address, and the interface data width.

[0141] If the address range from the starting address to the first address crosses the cache line boundary, the traversal interval is determined based on the starting address, the burst length, the base address, and the cache line length, where the first address is the address obtained by subtracting one from the sum of the starting address and the burst length.

[0142] In some embodiments, when determining the standard request and standard data based at least on the test command, the standard request and standard data can also be determined based on the test command and memory subsystem attribute data.

[0143] For example, if the burst length is greater than the interface data width, the standard request includes multiple standard sub-requests segmented with the interface data width as the granularity. The standard data includes standard sub-data corresponding to the standard sub-requests, and the data width of each standard sub-data is no greater than the interface data width.

[0144] When the address range from the starting address to the first address crosses the cache line boundary, the standard request includes multiple standard sub-requests segmented with the cache line length as the granularity, the standard data includes standard sub-data corresponding to the standard sub-requests, the data width of each standard sub-data is not greater than the cache line length, and the first address is the address obtained by subtracting one from the sum of the starting address and the burst length.

[0145] Figures 4 to 8 This is a schematic diagram comparing the first and second address ranges during the traversal of the base address and test address sizes.

[0146] The following is combined Figures 4 to 8 The testing methods of the embodiments of this application will be further described.

[0147] The memory system is defined using the following configuration as an example:

[0148] 1. M=32 indicates that the allowed burstlength range for the requested direction is [1,32];

[0149] 2. N=16, indicating that the data width in the return direction is 16 bytes;

[0150] 3. L=32 indicates that the memory cacheline width is 32 bytes.

[0151] To iterate through all burst lengths, we need to test all scenarios with burst lengths from 1 to 32.

[0152] Next, the start byte needs to be traversed. The traversal range of the start byte is an entire cache line, that is, the traversal range is [0, 31]. In addition, in order to facilitate the setting of the robust buffer (i.e., to avoid negative values ​​in the buffer base), the setting of the start byte is shifted 8 bytes to the right (this still ensures that all scenarios are traversed), so the traversal range of the start byte is [8, 39]. The following gives a more complex test case with start byte=13 and burstlength=25 to illustrate how to generate golden data, and uses a read request as an example to illustrate how the test method of this application embodiment traverses all robustness test scenarios.

[0153] When start byte = 13 and burst length = 25, since the return direction data bit width is 16 bytes, the returned data needs to be segmented in units of 16 bytes. That is, this request needs to return two pieces of data. Response 0 is [13, 28] bytes, and response 1 is [29, 37] bytes. Also, since the memory cacheline width is 32 bytes and the requested data crosses the cacheline boundary, two requests need to be sent to the next-level cache to request the data returned from two cache lines of the next-level cache respectively. That is, requests 0 (the first sub-request) and request1 (the second sub-request) need to be sent to the next-level cache. The starting address in the first sub-request request 0 is the start byte, that is, 13 bytes, and the ending address satisfies the address of the last byte of the cache line corresponding to this starting address, that is, 31 bytes. The starting address in the second sub-request request1 is the starting address of the next cache line, that is, 32 bytes, and the ending address is the end byte of the request, that is, 37 bytes. The traversal process will be specifically described in different cases below.

[0154] The first case is when buffer base < start byte, that is, buffer base < 13. For example, as Figure 4 shown, take buffer base = 10, and then take [0, 30] for buffer size. Then, during the process of continuously increasing buffer size, it will experience:

[0155] 1. buffer size ∈ [0, 3], corresponding to the address range of RB 1). In this case, both response 0 and response 1 are 0, and both request 0 and request 1 are discarded;

[0156] 2. buffer size ∈ [4, 19], corresponding to the address range of RB 2). In this case, [13, 10 + buffer_size - 1] in response 0 is valid data, and the rest is 0. Response 1 is 0. Request 0 is valid, and request 1 is discarded;

[0157] 3. If the buffer size ∈ [20, 22], corresponding to the address range of RB 3), then response 0 is all valid data, and in response 1, [29, 10 + buffer_size - 1] is valid data, and the rest is 0. Request 0 is valid, and request 1 is discarded.

[0158] 4. Buffer size ∈ [23, 28], corresponding to the address range of RB 4). In this case, the RB range crosses the cache line boundary. At this time, response 0 is all valid data, response 1 has [29, 10 + buffer_size - 1] as valid data, and the rest is 0. Both request 0 and request 1 are valid.

[0159] 5. Buffer size ∈ [29, 30], corresponding to the RB 5) address range. In this case, the RB range covers the entire request range (i.e., the first address range), response 0 and response 1 are all valid data, and request 0 and request 1 are both valid.

[0160] Then, starting from 10, the buffer base is incremented by 1 step, taking values ​​of 11 and 12. The traversal of the buffer size is similar to... Figure 4 Similar to the example shown.

[0161] The second case is when start byte ≤ buffer base ≤ start byte + N-1 (i.e., the address of the last byte of response 0), that is, when the buffer base value is between 13 bytes and 28 bytes, for example, Figure 5 As shown, if we set the buffer base to 17 and then set the buffer size to [0, 23], then as the buffer size continuously increases, it will experience the following:

[0162] 1. When buffer size = 0, both response 0 and response 1 are 0, and both request 0 and request 1 are discarded.

[0163] 2. If buffer size ∈ [1, 12], corresponding to the address range of RB 1), in this case, [17, 17 + buffer_size - 1] in response 0 are valid data, and the rest are 0. If response 1 is 0, request 0 is valid, and request 1 is discarded.

[0164] 3. Buffer size ∈ [13, 15], corresponding to the address range of RB 2). In this case, [17, 28] in response 0 are valid data and the rest are 0. In response 1, [29, 17 + buffer_size - 1] are valid data and the rest are 0. Request 0 is valid and request 1 is discarded.

[0165] 4. Buffer size ∈ [15, 16], corresponding to the address range of RB 3). In this case, the RB range crosses the cache line boundary. At this time, [17, 28] in response 0 is valid data and the rest is 0. In response 1, [29, 17 + buffer_size - 1] is valid data and the rest is 0. Both request 0 and request 1 are valid.

[0166] 5. The buffer size ∈ [17, 23] corresponds to the address range of RB 4). In this case, [17, 28] in response 0 is valid data and the rest is 0. Response 1 is valid data. Both request 0 and request 1 are valid.

[0167] The third case is where `start byte + N ≤ buffer base ≤ address of the first cacheline`, meaning `bufferbase` is between 29 and 31 bytes, and the range of `response 0` is entirely outside the range of `RB`, so `response 0` is always 0. For example, ... Figure 6 As shown, if we set the buffer base to 29 and then set the buffer size to [0, 11], then as the buffer size continuously increases, it will experience the following:

[0168] 1. When buffer size = 0, both response 0 and response 1 are 0, and both request 0 and request 1 are discarded.

[0169] 2. If buffer size ∈ [1, 3], corresponding to the address range of RB 1), in this case, response 0 is all 0, response 1 has [29, 29 + buffer_size - 1] as valid data, and the rest are 0. Request 1 is valid and is discarded.

[0170] 4. Buffer size ∈ [4, 9], corresponding to the address range of RB 2). In this case, the RB range crosses the cache line boundary. At this time, response 0 is all 0, response 1 has [29, 29 + buffer_size - 1] as valid data, and the rest are 0. Both request 0 and request 1 are valid.

[0171] 5. Buffer size ∈ [10, 11], corresponding to the address range of RB 3). In this case, response 0 is all 0, response 1 is valid data, and both request 0 and request 1 are valid.

[0172] The fourth case is where the address of the first cacheline is less than the buffer base and less than the end byte. That is, the buffer base is between 32 and 37 bytes, the entire range of RB is located to the right of the first cacheline, and the response is all zeros. For example, ... Figure 7 As shown, if we set the buffer base to 32 and the buffer size to [0, 8], then as the buffer size continuously increases, it will experience the following:

[0173] 1. When buffer size = 0, both response 0 and response 1 are 0, and both request 0 and request 1 are discarded.

[0174] 2. The buffer size ∈ [1, 6] corresponds to the address range of RB 1). In this case, response 0 is all 0, and in response 1, [32, 32 + buffer_size - 1] is valid data, and the rest is 0. Request 0 is discarded, and request 1 is valid.

[0175] 3. Buffer size ∈ [7,8], corresponding to the address range of RB 2). In this case, response 0 is all 0, response 1 has [32,37] as valid data and the rest as 0. Request 0 is discarded and request 1 is valid.

[0176] The fifth case is when buffer base > end byte, meaning the buffer base is 38 bytes. This means the entire request range (i.e., the first address range) is outside the RB range (to the left), response 0 and response 1 are both 0, and request 0 and request 1 are discarded. For example, ... Figure 8 As shown, the buffer size ∈ [0,1] corresponds to the address range of RB 1). In this case, response 0 and response 1 are both 0, and request 0 and request 1 are discarded.

[0177] Thus, when the request has start byte=13 and burst length=25, by traversing the buffer size according to the above interval, all possible scenarios that robustness detection might encounter can be traversed. Then, by continuing to traverse the start byte and burst length, and dividing the traversal interval of the buffer size according to the interface data width and cacheline length, all possible scenarios that robustness detection might encounter under the (M, N, L) configuration can be obtained.

[0178] According to the embodiments of this application, the traversal interval of the test address size is determined based on the starting address, burst length, and base address. This allows the request range determined by the starting address and burst length to be mapped to the traversal interval of the test address size. By traversing the starting address, burst length, base address, and test address size according to the traversal interval of the test address size, the request range corresponding to the traversal interval of the test address size can be traversed when traversing the robust range (RB range) determined by the base address and test address size. This covers all possible situations where the request range and robust range may exist in robustness testing, obtains test results in the corresponding scenarios, and improves testing efficiency.

[0179] Example 2

[0180] This application also provides a memory system testing device, which corresponds to the testing method described in Embodiment 1, and the same content is incorporated herein. Figure 9 This is a schematic diagram of a testing apparatus according to an embodiment of this application. Figure 9As shown, the testing apparatus 900 includes:

[0181] The receiving unit 906 receives a test command, which includes at least a start byte, a burst length, a buffer base, and a test address size.

[0182] The first determining unit 901 determines the traversal range of the test address size (buffer size) based at least on the start address (start byte), the burst length (burst length), and the buffer base address (buffer base);

[0183] The acquisition unit 902 traverses the start address, burst length, buffer base, and buffer size according to the traversal interval of the test address size, and acquires the test request and test data corresponding to the test command.

[0184] The comparison unit 903 compares the test request with the standard request, and / or compares the test data with the standard data to obtain the test result.

[0185] In some embodiments, the testing apparatus further includes:

[0186] The second determining unit 904 determines the standard request and standard data (golden) at least according to the test command.

[0187] In some embodiments,

[0188] In the case where the first address range and the second address range overlap, the addresses within the first address range that are located within the second address range are designated as the third address range, and the addresses within the first address range that are located outside the second address range are designated as the fourth address range. The first address range includes the address from the starting address to the first address, where the first address is the address obtained by subtracting one from the sum of the starting address and the burst length. The second address range includes the address from the base address to the second address, where the second address is the address obtained by subtracting one from the sum of the base address and the test address size.

[0189] The second determining unit 904 is also configured as follows:

[0190] When the test command is a read command, the address range of the standard request is determined, which includes the first address range. The standard data is also determined, which includes data pre-stored in the memory system corresponding to the third address range and data 0 corresponding to the fourth address range.

[0191] When the test command is a write command, the address range of the standard request is determined, the address range of the standard request includes the first address range, and the standard data is determined, the standard data includes the data in the third address range carried by the test command corresponding to the third address range, and the data to be discarded corresponding to the fourth address range.

[0192] In some embodiments, the second determining unit 904 is further configured to:

[0193] If the first address range and the second address range do not overlap, the standard request is discarded.

[0194] When the test command is a read command, the standard data is determined, and the standard data includes data 0 corresponding to the first address range.

[0195] When the test command is a write command, the standard data is determined, which includes data that will be discarded corresponding to the first address range.

[0196] In some embodiments, the first determining unit 901 is configured to:

[0197] The traversal range of the test address size is determined based on the starting address, the burst length, the base address, and the memory subsystem attribute data; the memory subsystem attribute data includes at least one of the cache line length and the interface data width.

[0198] In some embodiments, the first determining unit 901 is further configured to:

[0199] If the burst length is greater than the interface data width, the traversal interval is determined based on the starting address, the burst length, the base address, and the interface data width.

[0200] If the address range from the starting address to the first address crosses the cache line boundary, the traversal interval is determined based on the starting address, the burst length, the base address, and the cache line length, where the first address is the address obtained by subtracting one from the sum of the starting address and the burst length.

[0201] In some embodiments, the second determining unit 904 is further configured to:

[0202] The standard request and standard data are determined based on the test command and the interface data width, wherein,

[0203] If the burst length is greater than the interface data width, the standard request is determined, the standard request includes multiple standard sub-requests segmented with the interface data width as the granularity, and the standard data is determined, the standard data includes standard sub-data corresponding to the standard sub-requests, and the data width of each standard sub-data is not greater than the interface data width.

[0204] In some embodiments, the second determining unit 904 is further configured to:

[0205] The standard request and standard data are determined based on the test command and the cache line length, wherein,

[0206] If the address range from the starting address to the first address crosses the cache line boundary, the standard request is determined, the standard request includes multiple standard sub-requests divided with the cache line length as the granularity, and the standard data is determined, the standard data includes standard sub-data corresponding to the standard sub-requests, the data width of each standard sub-data is not greater than the cache line length, and the first address is the address obtained by subtracting one from the sum of the starting address and the burst length.

[0207] In some embodiments, the testing apparatus further includes:

[0208] The bias unit 905 shifts the start address (start byte) to the right using a predetermined offset parameter when the minimum value of the traversal range of the start address is equal to the minimum value of the traversal range of the base address.

[0209] In this embodiment, the specific implementation methods of the above-mentioned devices are the same as those described in Embodiment 1, and will not be repeated here.

[0210] It is worth noting that the above description only covers the components or modules relevant to this application, but this application is not limited thereto. The test apparatus 900 may also include other components or modules, and for details regarding these components or modules, please refer to relevant technologies.

[0211] For the sake of simplicity, Figure 9 The diagram only exemplifies the connection relationships or signal flow between various components or modules; however, those skilled in the art should understand that various related technologies, such as bus connections, can be employed. The aforementioned components or modules can be implemented using hardware facilities such as processors and memory; this application does not limit the scope of the embodiments.

[0212] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the test method described in any one of Embodiment 1.

[0213] This application also provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the test method described in any one of Embodiments 1.

[0214] This application also provides a computer program product, which includes a computer program that, when executed by a processor, implements the test method described in any one of Embodiment 1.

[0215] The above embodiments are merely illustrative examples of embodiments of this application, but this application is not limited thereto, and appropriate modifications can be made based on the above embodiments. For example, the above embodiments can be used alone, or one or more of the above embodiments can be combined.

[0216] The present application has been described above with reference to specific embodiments. However, those skilled in the art should understand that these descriptions are exemplary and not intended to limit the scope of protection of the present application. Those skilled in the art can make various modifications and variations to the present application based on its spirit and principles, and these modifications and variations are also within the scope of the present application.

[0217] Preferred embodiments of this application have been described above with reference to the accompanying drawings. Many features and advantages of these embodiments are apparent from this detailed description, and therefore the appended claims are intended to cover all such features and advantages of these embodiments that fall within their true spirit and scope. Furthermore, since many modifications and variations will readily occur to those skilled in the art, the embodiments of this application are not intended to be limited to the precise structures and operations illustrated and described, but rather to encompass all suitable modifications, variations, and equivalents falling within their scope.

Claims

1. A test method of a memory system, characterized by, The test method comprises: receiving a test command, the test command comprising at least a start address, a burst length, a base address and a test address size; determining a traversal interval of the test address size according to at least the start address, the burst length and the base address; traversing the start address, the burst length, the base address and the test address size respectively according to the traversal interval of the test address size, and obtaining a test request and test data corresponding to the test command; comparing the test request with a standard request, and / or comparing the test data with standard data to obtain a test result.

2. The test method of claim 1, wherein, The test method further comprises: determining the standard request and standard data according to at least the test command.

3. The test method of claim 2, wherein, The determining the standard request and standard data according to at least the test command comprises: in a case where a first address range and a second address range overlap, regarding an address in the first address range and located in the second address range as a third address range, and regarding an address in the first address range and located out of the second address range as a fourth address range, the first address range comprising from the start address to a first address, the first address being an address obtained by subtracting one from a sum of the start address and the burst length, and the second address range comprising from the base address to a second address, the second address being an address obtained by subtracting one from a sum of the base address and the test address size; in a case where the test command is a read command, determining an address range of the standard request, the address range of the standard request comprising the first address range, and determining the standard data, the standard data comprising data in the third address range corresponding to the third address range pre-stored in the memory system, and data 0 corresponding to the fourth address range, in a case where the test command is a write command, determining an address range of the standard request, the address range of the standard request comprising the first address range, and determining the standard data, the standard data comprising data in the third address range corresponding to the third address range in write data carried by the test command, and data to be discarded corresponding to the fourth address range.

4. The test method of claim 3, wherein, The determining the standard request and standard data according to at least the test command further comprises: in a case where the first address range and the second address range do not overlap, the standard request being discarded, in a case where the test command is a read command, determining the standard data, the standard data comprising data 0 corresponding to the first address range, in a case where the test command is a write command, determining the standard data, the standard data comprising data to be discarded corresponding to the first address range.

5. The test method according to claim 1, wherein the determining the traversal interval of the test address size according to at least the start address, the burst length and the base address comprises: determining a traversal range of the test address size according to the start address, the burst length, the base address and memory subsystem attribute data, the memory subsystem attribute data comprising at least one of a cache line length and an interface data width.

6. The test method of claim 5, wherein, The determining a traversal range of the test address size according to the start address, the burst length, the base address and memory subsystem attribute data comprises: in a case that the burst length is greater than the interface data width, determining the traversal range based on the start address, the burst length, the base address and the interface data width, in a case that an address range from the start address to a first address crosses a cache line boundary, determining the traversal range based on the start address, the burst length, the base address and the cache line length, the first address being an address obtained by subtracting one from a sum of the start address and the burst length.

7. The test method of claim 2, wherein The determining the standard request and the standard data according to at least the test command comprises: determining the standard request and the standard data according to the test command and an interface data width, wherein in a case that the burst length is greater than the interface data width, determining the standard request, the standard request comprising a plurality of standard sub-requests split in a granularity of the interface data width, and determining the standard data, the standard data comprising standard sub-data corresponding to the standard sub-requests, a data width of each standard sub-data being not greater than the interface data width.

8. The test method of claim 2, wherein The determining the standard request and the standard data according to at least the test command comprises: determining the standard request and the standard data according to the test command and a cache line length, wherein in a case that an address range from the start address to a first address crosses a cache line boundary, determining the standard request, the standard request comprising a plurality of standard sub-requests split in a granularity of the cache line length, and determining the standard data, the standard data comprising standard sub-data corresponding to the standard sub-requests, a data width of each standard sub-data being not greater than the cache line length, the first address being an address obtained by subtracting one from a sum of the start address and the burst length.

9. The test method according to any one of claims 1 to 8, characterized in that, The test method further comprises: in a case that a minimum value of a traversal range of the start address is equal to a minimum value of a traversal range of the base address, right shifting the start address by using a predetermined offset parameter.

10. A test apparatus for a memory system, characterized by comprising: The test apparatus comprises: a receiving unit configured to receive a test command, the test command comprising at least a start address, a burst length, a base address and a test address size; a determining unit configured to determine a traversal range of the test address size according to at least the start address, the burst length and the base address; an obtaining unit configured to traverse the start address, the burst length, the base address and the test address size respectively according to the traversal range of the test address size, and obtain a test request and test data corresponding to the test command. a comparison unit configured to compare the test request with a standard request and / or to compare the test data with standard data to obtain a test result.

11. A computer readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and the computer program, when executed by a processor, implements the test method in any one of claims 1 to 9.

12. A computer device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the test method in any one of claims 1 to 9.

13. A computer program product, characterised in that, The computer program product comprises a computer program, and the computer program, when executed by a processor, implements the test method in any one of claims 1 to 9.

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