Memory bank installation self-checking method

Abstract

The invention discloses a memory bank installation self-checking method, and belongs to the technical field of computer storage equipment detection. The method comprises the following steps of: separating a test signal adaptive to the working state of the memory to obtain an incident signal and a reflected signal, acquiring voltage of the incident signal and the reflected signal, converting the voltage into digital information, calculating a reflection coefficient and actual link impedance and deviation of each detection frequency point, comparing a set deviation threshold value to generate a detection result, analyzing abnormal information, and sending out a prompt of re-plugging or re-replacing. And meanwhile, synchronizing a result to a memory training process. According to the method, the installation state and the link impedance of the memory bank are accurately detected, the problem of poor contact caused by vibration or improper installation is timely checked, equipment operation faults are reduced, the memory training effect is optimized, and the equipment operation stability and the maintenance convenience are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer storage device detection, in particular to a memory bank installation self-checking method. BACKGROUND

[0002] With the popularization and performance upgrade of data centers, servers and various computing devices, as the core storage component, the application scenarios of memory banks are increasingly widespread, and the requirements for installation stability and link transmission quality are also continuously improved. At present, the installation of memory banks mainly relies on two modes of manual operation and mechanical jig assistance, and the physical level fixation is achieved through the structure design such as buckle locking to ensure the preliminary connection of the memory bank and the mainboard slot. In the product shipment stage, the manufacturer will verify the overall operation state of the device through pressure test, power-on self-test and other ways to confirm that the basic functions of the core components such as memory bank are normal; some device systems also have memory initialization detection function, which can identify obvious faults such as particle failure and complete installation out of place; in the process of device running, some monitoring mechanisms can record bit flip, CE exception, UCE exception and other situations to provide post-reference for troubleshooting. These technical means and application modes jointly constitute the current industry status of memory bank installation and detection field, and provide certain guarantee for the basic operation of the device.

[0003] However, the existing technical system still has technical problems that are difficult to avoid in actual application. The server and other devices will inevitably be affected by external forces such as vibration and jolt in the process of transportation, shelving and migration, which may cause the contact between the memory bank and the slot PIN to be poor. This poor contact often cannot be identified by traditional structure fixation inspection or initialization process, which may cause the device to suddenly stop running due to abnormal link impedance after a period of operation, seriously affecting business continuity. The existing memory initialization process can only screen out completely failed or obviously not installed memory banks, and lacks effective detection means for the case where the initialization is passed but the link signal transmission quality is poor, and cannot accurately judge whether the link impedance is within the normal range; the abnormal monitoring in the running is a post-alarm mechanism, which can only record relevant information after the fault occurs, cannot predict potential risks in advance, and requires maintenance personnel to continuously pay attention to log data, which has high maintenance cost. In addition, the existing technology lacks quantitative detection capability for link impedance characteristics, and cannot analyze the link state through systematic processes such as signal separation, voltage acquisition, impedance calculation and threshold comparison, which cannot timely locate the impedance abnormality caused by poor contact, vibration interference and other factors, and cannot issue early warning and guide maintenance operation, which seriously restricts the stability and reliability of the device running. SUMMARY

[0004] The purpose of the present application is to overcome the deficiencies of the prior art and provide a memory bank installation self-checking method.

[0005] The object of the application is achieved by the following technical solutions: A memory bank installation self-checking method is provided, which comprises the following steps: S1. Separate the test signal adapted to the working state of the memory to obtain incident signals and reflected signals, collect the voltages corresponding to the two signals and convert them into digital information to obtain complete voltage data covering all detection frequency points; S2. Calculate the reflection coefficient according to the ratio of the incident signal voltage to the reflected signal voltage, substitute the reflection coefficient into the reflection method impedance calculation formula, combine the link design impedance, obtain the link actual impedance corresponding to each detection frequency point, and then calculate the deviation between the link actual impedance and the link design impedance; S3. Set the deviation threshold value based on the link design standard and the transmission line impedance variation law, compare the impedance deviation of each frequency point with the deviation threshold value one by one, and generate impedance detection results containing impedance values of each frequency point, deviation data and overall link impedance evaluation; S4. Analyze the impedance detection results, identify abnormal conditions exceeding the deviation threshold value, specify the link and frequency point information corresponding to the abnormal conditions, issue a prompt to re-plug or replace the related memory bank, and synchronize the impedance detection results to the memory training process.

[0006] Further, step S1 comprises the following sub-steps: S1.1. Determine the detection frequency point range based on the memory working frequency, generate a sweep signal covering the frequency point range, and the sweep signal is adapted to the working state of the memory; S1.2. Separate the sweep signal to obtain incident signals and reflected signals; S1.3. Collect the voltages corresponding to the incident signals and reflected signals respectively, convert the collected analog voltage signals into digital information, and form voltage data covering all detection frequency points.

[0007] Further, step S2 comprises the following sub-steps: S2.1. Divide the reflected signal voltage by the incident signal voltage at each detection frequency point to obtain the reflection coefficient corresponding to each frequency point; S2.2. Substitute the reflection coefficient of each frequency point into the reflection method impedance calculation formula, combine the preset link design impedance, and obtain the link actual impedance corresponding to each frequency point through logical operation; S2.3. Take the link design impedance as the reference to calculate the deviation between the link actual impedance of each frequency point and the link design impedance, and record the deviation data of each frequency point.

[0008] Further, step S3 comprises the following sub-steps: S3.1. Set the deviation threshold value to distinguish between normal and abnormal impedance according to the link design standard, the transmission line impedance variation law and the actual application scenario; S3.2. According to the order of the detection frequency points, compare the impedance deviation recorded by each frequency point with the deviation threshold value respectively, and mark the comparison result of each frequency point; S3.3. Summarize the impedance values, deviation data and comparison results of all frequency points to generate impedance detection results containing overall link impedance evaluation, and determine whether there is an abnormality in the overall link.

[0009] Further, step S4 includes the following sub-steps: S4.1. Extract the frequency point information marked as abnormal from the impedance detection results, and associate the link identification and physical connection path corresponding to the abnormal frequency point; S4.2. According to the link information associated with the abnormal frequency point, locate the memory bank corresponding to the link; S4.3. Issue a prompt containing the abnormal memory bank association information and operation instruction, and the operation instruction is to re-plug or replace; S4.4. Synchronize the complete impedance detection results to the memory training process.

[0010] Further, in step S1.1, the generation of the sweep signal combines the frequency requirements of different working modes of the memory to determine the detection frequency point range, and the amplitude and phase parameters of the sweep signal are adapted to the working state of the memory, so that the sweep signal can truly reflect the link signal transmission characteristics when the memory is working.

[0011] Further, in step S2.3, before calculating the deviation, the actual impedance of the link corresponding to each frequency point and the designed impedance of the link are matched, and then a statistical method is used to calculate the deviation, including average deviation and standard deviation. When calculating the average deviation, the absolute value of the impedance difference of each frequency point is first calculated, and then all the absolute values are averaged. When calculating the standard deviation, the sum of the squares of the impedance differences of each frequency point is first calculated, and then the square root is taken after the average operation.

[0012] Further, in step S3.1, the setting method of the deviation threshold value includes a specified threshold and a proportional threshold. The specified threshold determines a fixed value by referring to the allowable error range of the link design, and the proportional threshold determines a threshold range based on a fixed proportion of the designed impedance of the link. Both setting methods are fine-tuned in combination with the differences in transmission characteristics of different frequency points.

[0013] Further, in step S4.4, when synchronizing the impedance detection results to the memory training process, first format the actual impedance data and deviation data of each frequency point link in the impedance detection results, encapsulate the data in a protocol format recognizable by the memory training process, and then transmit it to the memory training process.

[0014] Further, after step S4, the impedance detection result, impedance value of each frequency point, deviation data, abnormality identification and located memory bank information are stored, and the time of detection execution, corresponding device identification and memory channel information are stored, the information is organized in a structured data format and stored in a designated storage unit to form a complete detection record.

[0015] The beneficial effects of the present application are: (1) By separating the test signal adapted to the memory working state, collecting voltage data, calculating impedance and deviation and comparing with the threshold value, the memory bank installation and link abnormality are accurately identified, and prompt is sent in time to reduce equipment operation failure; (2) The complete data formed by the link impedance detection provides reliable reference for memory training parameter adjustment, optimizes the memory initialization process and reduces the training failure probability; (3) With the integrated design of chip interface and detection record storage mechanism, the normal detection without external equipment is realized, data support is provided for equipment maintenance, and the overall operation reliability is improved. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is a specific step flow chart of a memory bank installation self-checking method; Figure 2 is a CPU DDR interface topology diagram provided by the embodiment; Figure 3 is an IO unit topology diagram provided by the embodiment; Figure 4 is an IO unit optimization topology diagram provided by the embodiment. DETAILED DESCRIPTION

[0017] The technical solutions of the present application will be described in detail below with reference to the embodiments. Obviously, the described embodiments are only part of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0018] Embodiment 1 Referring to Figure 1 A memory bank installation self-checking method, the method comprising the following steps: S1. Separate the test signal adapted to the memory working state, obtain the incident signal and the reflected signal, collect the voltage corresponding to the two kinds of signals and convert them into digital information, and obtain complete voltage data covering all detection frequency points; S2. Calculate the reflection coefficient based on the ratio of the incident signal voltage to the reflected signal voltage. Substitute the reflection coefficient into the reflection method impedance calculation formula and combine it with the link design impedance to obtain the actual link impedance corresponding to each detection frequency point. Then calculate the deviation between the actual link impedance and the link design impedance. S3. Based on the link design standards and the transmission line impedance variation law, set the deviation threshold, compare the impedance deviation of each frequency point with the deviation threshold one by one, and generate the impedance detection result containing the impedance value of each frequency point, the deviation data and the overall link impedance evaluation. S4. Analyze the impedance detection results, identify abnormal situations that exceed the deviation threshold, clarify the link and frequency information corresponding to the abnormality, issue a prompt to re-insert or replace the relevant memory module, and synchronize the impedance detection results to the memory training process.

[0019] Step S1 includes the following sub-steps: S1.1. Determine the detection frequency range based on the memory operating frequency, generate a sweep signal covering the frequency range, and adapt the sweep signal to the memory operating state; S1.2. The swept frequency signal is separated to obtain the incident signal and the reflected signal; S1.3. Collect the voltages corresponding to the incident and reflected signals respectively, convert the collected analog voltage signals into digital information, and form voltage data covering all detection frequency points.

[0020] Step S2 includes the following sub-steps: S2.1. Using each detection frequency point as a unit, divide the reflected signal voltage at that frequency point by the incident signal voltage to obtain the reflection coefficient corresponding to each frequency point; S2.2. Substitute the reflection coefficient of each frequency point into the reflection method impedance calculation formula, combine it with the preset link design impedance, and obtain the actual link impedance corresponding to each frequency point through logical operation; S2.3. Using the link design impedance as a benchmark, calculate the deviation between the actual link impedance and the link design impedance at each frequency point, and record the deviation data for each frequency point.

[0021] Step S3 includes the following sub-steps: S3.1. Based on link design standards, transmission line impedance variation patterns, and actual application scenarios, set a deviation threshold to distinguish between normal and abnormal impedance. S3.2. According to the order of the detection frequency points, compare the impedance deviation recorded at each frequency point with the deviation threshold respectively, and mark the comparison result of each frequency point; S3.3. Summarize the impedance values, deviation data and comparison results of all frequency points to generate impedance detection results that include overall link impedance evaluation, and clarify whether there are any abnormalities in the overall link.

[0022] Step S4 includes the following sub-steps: S4.1. Extract the frequency point information marked as abnormal from the impedance detection result, associate the link identification and physical connection path corresponding to the abnormal frequency point; S4.2. According to the link information associated with the abnormal frequency point, locate the memory bank corresponding to the link; S4.3. Issue a prompt containing abnormal memory bank association information and operation instructions, and the operation instructions are re-plug or replace; S4.4. Synchronize the complete impedance detection result to the memory training process.

[0023] In step S1.1, the generation of the sweep signal combines the frequency requirements of different working modes of the memory to determine the detection frequency point range, and the amplitude and phase parameters of the sweep signal are adapted to the working state of the memory, so that the sweep signal can truly reflect the link signal transmission characteristics when the memory is working.

[0024] In step S2.3, before calculating the deviation, the actual impedance of each frequency point corresponding to the link and the designed impedance of the link are matched, and then a statistical method is used to calculate the deviation, including average deviation and standard deviation. When calculating the average deviation, the absolute value of the impedance difference of each frequency point is first calculated, and then the average operation is performed on all absolute values. When calculating the standard deviation, the sum of the squares of the impedance differences of each frequency point is first calculated, and then the square root is taken after the average operation.

[0025] In step S3.1, the setting method of the deviation threshold includes a specified threshold and a proportional threshold. The specified threshold determines a fixed value by referring to the allowable error range of the link design, and the proportional threshold determines the threshold range based on a fixed proportion of the designed impedance of the link. Both setting methods are fine-tuned in combination with the transmission characteristic differences of different frequency points.

[0026] In step S4.4, when synchronizing the impedance detection result to the memory training process, the actual impedance data and deviation data of each frequency point link in the impedance detection result are first formatted, and then the data is encapsulated according to the protocol format recognizable by the memory training process, and then transmitted to the memory training process.

[0027] After step S4, the impedance detection result, the impedance values of each frequency point, the deviation data, the abnormal identification and the located memory bank information are stored, and the time of detection execution, the corresponding device identification and the memory channel information are also stored. Organize these information according to the structured data format and store it in the specified storage unit to form a complete detection record.

[0028] Example 2 The embodiment provides a memory bank installation self-checking method, realizes link impedance detection after memory bank installation through systematic steps, investigates poor contact problems caused by factors such as installation out of position and transportation vibration, provides guarantee for memory running stability, and the specific implementation process is as follows: S1. Separate the test signal suitable for the working state of the memory, obtain the incident signal and the reflected signal, collect the voltages corresponding to the two signals and convert them into digital information, and obtain complete voltage data covering all detection frequency points; S1.1. Determine the detection frequency point range based on the memory working frequency, generate a sweep signal covering the frequency point range, and the sweep signal is suitable for the working state of the memory: The generation of the sweep signal combines the frequency requirements corresponding to different working modes of the memory to demarcate the detection frequency point range, ensures that all working frequency points supported by the memory are covered, the amplitude and phase parameters of the sweep signal are adapted to the working state of the memory, and the sweep signal can truly reflect the link signal transmission characteristics when the memory works. Impedance testing needs to be based on the actual working frequency of the memory, create a sweep signal corresponding to the frequency point range for testing, the sweep signal needs to be consistent with the signal characteristics when the memory normally works, provide a signal source conforming to the actual working condition for subsequent separation and collection of the incident signal and the reflected signal, and ensure that the subsequent detection results can accurately reflect the link state of the memory in actual operation.

[0029] S1.2. Separate and process the sweep signal to obtain the incident signal and the reflected signal: The directional coupler is designed in the chip interface unit to realize the separation processing of the sweep signal. The directional coupler is a device that can separate incident waves and reflected waves, and is not a device of a certain type, a certain material or a certain specific structure. Its function is to accurately separate the sweep signal in the transmission process into incident signals and reflected signals, so that the two signals are not interfered and can be separately collected and processed. Through the integrated design of the directional coupler, the signal separation can be completed in the chip without additional external test equipment, the built-in detection of the link impedance is realized, and the compatibility and operation complexity problems caused by the access of external equipment are avoided.

[0030] S1.3. Collect the voltages corresponding to the incident signal and the reflected signal respectively, convert the collected analog voltage signals into digital information, and form voltage data covering all detection frequency points: The voltage corresponding to the separated incident signal and reflected signal is collected by an ADC device. The ADC device mainly refers to a device for collecting and measuring voltage signals and converting them into digital information that can be processed by a computer, and does not refer to a specific model or specific device width. The collection process covers all set detection frequencies to ensure that the voltage of the incident signal and the reflected signal at each frequency point can be completely collected. The analog voltage signals collected are converted by the ADC device to form digital information, which is organized in the order of detection frequencies to ultimately form complete voltage data covering all detection frequencies, providing basic data support for subsequent reflection coefficient calculation and impedance derivation. The collection process needs to ensure the accuracy and integrity of the voltage data to avoid affecting the subsequent detection results due to data loss or distortion.

[0031] S2. Calculate the reflection coefficient according to the ratio of the incident signal voltage to the reflected signal voltage, substitute the reflection coefficient into the reflection method impedance calculation formula, and combine the link design impedance to obtain the link actual impedance corresponding to each detection frequency, and then calculate the deviation of the link actual impedance from the link design impedance; S2.1. Divide the reflected signal voltage by the incident signal voltage at each detection frequency to obtain the reflection coefficient corresponding to each frequency point: The reflection coefficient is the ratio of the incident wave voltage to the reflected wave voltage of the port. In this embodiment, the incident signal digital voltage information and the reflected signal digital voltage information converted by the ADC at each detection frequency are extracted one by one as an independent calculation unit, and the reflection coefficient corresponding to each frequency point is obtained through division operation. During the calculation process, it is necessary to ensure that the incident signal voltage and the reflected signal voltage of each frequency point correspond one by one to avoid confusion of the frequency points and cause errors in the calculation of the reflection coefficient. The calculation result of the reflection coefficient is directly related to the accuracy of the subsequent impedance data, so the operation needs to be strictly performed according to the corresponding relationship of the voltage data.

[0032] S2.2. Substitute the reflection coefficient of each frequency point into the reflection method impedance calculation formula, combine the preset link design impedance, and obtain the link actual impedance corresponding to each frequency point through logical operation: The reflection method impedance calculation formula is: , wherein Z represents the link actual impedance, is the default impedance value of the link or chip design, S11 is the (voltage) reflection coefficient calculated in step S2.1, representing the ratio of the incident wave voltage (a1) to the reflected wave voltage (b1) of port 1, and the calculation formula is: .

[0033] Link design impedance is an inherent parameter determined by the link or chip in the design stage, and there is usually a fixed design standard for single-ended signals, but the present method does not make specific impedance constraints and can adapt to the design requirements of different chip manufacturers. The reflection coefficient S11 of each frequency point and the preset link design impedance The above formula is substituted in turn, and the actual impedance of each frequency point is obtained one by one through logical operation. The impedance calculation corresponds to the frequency point one by one, ensuring that the link state of each frequency point can be reflected through the impedance data. The impedance calculation method mainly refers to the working principle of the vector network analyzer, and its innovation lies in integrating the directional coupler and ADC device into the chip to realize the internalization and integration of impedance measurement without relying on external professional test instruments.

[0034] S2.3. Take the link design impedance as the reference to calculate the deviation between the actual impedance of each frequency point and the link design impedance, and record the deviation data of each frequency point: Before calculating the deviation, the actual impedance of each frequency point and the link design impedance are matched correspondingly to ensure that the actual impedance of each frequency point is compared and calculated with the design impedance corresponding to the frequency point. The statistical method includes average deviation and standard deviation. When calculating the average deviation, the absolute value of the impedance difference of each frequency point is first calculated, and then the average of all absolute values is calculated to obtain the average deviation. When calculating the standard deviation, the sum of the squares of the impedance difference of each frequency point is first calculated, and then the square root of the average is taken to obtain the standard deviation. Through such statistical methods, complete deviation data corresponding to each frequency point is obtained, and the deviation results of each frequency point are recorded to provide data basis for subsequent threshold comparison and abnormal identification. The recording of deviation data needs to be in the order of detection frequency points to ensure the corresponding relationship with the voltage data, reflection coefficient data and actual impedance data in the previous stage, which is convenient for subsequent data tracing and analysis.

[0035] S3. Based on the link design standard and the impedance variation law of the transmission line, set the deviation threshold, compare the impedance deviation of each frequency point with the deviation threshold one by one, and generate the impedance detection result containing the impedance value of each frequency point, the deviation data and the overall link impedance evaluation; S3.1. Set the deviation threshold to distinguish between normal and abnormal impedance according to the link design standard, the impedance variation law of the transmission line and the actual application scene: The setting mode of the deviation threshold value includes a specified threshold and a proportional threshold. The specified threshold is set by referring to the allowable error range of the link design to determine a fixed value, and the proportional threshold is set based on a fixed proportion of the impedance of the link design to determine a threshold range. Both setting modes are based on the link design standard and the impedance variation law of the transmission line, and are fine-tuned in combination with the transmission characteristic differences of different frequency points, to ensure that the set deviation threshold value can accurately distinguish between normal and abnormal states of impedance within the entire detection frequency range. The setting of the threshold value needs to comprehensively consider the physical characteristics of the link and the environmental influence factors in actual application, so as to neither cause abnormal cases to be missed due to too loose threshold value, nor cause normal links to be misjudged due to too strict threshold value, and to ensure that the threshold value can truly reflect the reasonable fluctuation range of the link impedance.

[0036] S3.2. According to the order of the detection frequency points, the impedance deviation recorded by each frequency point is compared with the deviation threshold value respectively, and the comparison results of each frequency point are marked: According to the pre-set detection frequency point order, the impedance deviation data of each frequency point is extracted one by one, and compared with the pre-set deviation threshold value. During the comparison process, if the impedance deviation of a certain frequency point is less than or equal to the deviation threshold value, the link state of the frequency point is marked as normal; if the impedance deviation of a certain frequency point is greater than the deviation threshold value, the link state of the frequency point is marked as abnormal. The comparison results of each frequency point need to be clearly marked, and the marking information is associated with the impedance value and deviation data of the frequency point, to ensure that the link state of each frequency point can be clearly reflected through the comparison results. The comparison process needs to strictly follow the set threshold standard to avoid inconsistent comparison results caused by human intervention, and to ensure the objectivity and accuracy of the comparison process.

[0037] S3.3. Summarize the impedance values, deviation data and comparison results of all frequency points to generate impedance detection results containing overall link impedance evaluation, and clearly determine whether the overall link exists abnormity: The related data of all detection frequency points are summarized, including the incident signal voltage digital information, the reflected signal voltage digital information, the reflection coefficient, the actual impedance of the link, the impedance deviation data and the comparison marking results of each frequency point, and these data are organized in a structured format. Based on the summarized data, the impedance detection results are generated, which need to contain the detailed data information of each frequency point and the overall link impedance evaluation. The overall link impedance evaluation needs to be comprehensively judged according to the comparison results of all frequency points. If one or more frequency points are marked as abnormal, the overall link impedance evaluation is abnormal; if all frequency points are marked as normal, the overall link impedance evaluation is normal. The impedance detection results need to clearly determine whether the overall link exists abnormity, to provide clear basis for subsequent abnormal analysis and processing, and to ensure the information integrity of the detection results, to facilitate subsequent query and application.

[0038] S4. Analyze the impedance detection result, identify abnormal situations exceeding the deviation threshold, determine the link and frequency point information corresponding to the abnormality, issue a prompt for re-plugging or replacing the related memory bank, and synchronize the impedance detection result to the memory training process; S4.1. Extract the frequency point information marked as abnormal from the impedance detection result, and associate the link identifier and physical connection path corresponding to the abnormal frequency point: From the generated impedance detection result, filter out the frequency point information marked as abnormal, including the serial number of the abnormal frequency point, the corresponding reflection coefficient, the actual impedance of the link, the impedance deviation data, and other detailed information. According to the serial number of the abnormal frequency point, associate the link identifier and physical connection path corresponding to the frequency point. The link identifier is used to distinguish different memory links, and the physical connection path is used to determine the memory bank slot position and connection relationship corresponding to the link. Through the association of link identifier and physical connection path, the abnormal link can be accurately located, providing basic information for subsequent memory bank positioning and ensuring accurate identification of abnormal links.

[0039] S4.2. According to the link information associated with the abnormal frequency point, locate the memory bank corresponding to the link: Based on the link identifier and physical connection path information associated in step S4.1, trace back to the memory bank corresponding to the link, and determine the specific memory bank corresponding to the abnormal situation. The positioning process needs to combine the design topology of the memory link to ensure the accuracy of the link information and the corresponding relationship of the memory bank, avoiding maintenance errors caused by incorrect link and memory bank correspondence. By accurately positioning the memory bank corresponding to the abnormality, clear directions can be provided for subsequent maintenance operations, allowing maintenance personnel to quickly lock the components that need to be handled, improving maintenance efficiency.

[0040] S4.3. Issue a prompt containing the associated information of the abnormal memory bank and operation instructions, and the operation instructions are re-plugging or replacement: After locating the memory bank corresponding to the abnormality, issue the corresponding prompt information, which contains the associated information of the abnormal memory bank, such as link identifier, physical connection path, abnormal frequency point data, etc., and clearly indicates the operation instructions, which are re-plugging or replacement. The issuance of prompt information does not need to rely on manual monitoring, and is automatically triggered through the built-in detection mechanism, ensuring that abnormal situations can be timely known, avoiding the aggravation of link faults due to undetected abnormalities, and further causing whole machine operation problems. The clarity of the operation instructions can provide clear action basis for maintenance personnel, reducing uncertainty in the maintenance process.

[0041] S4.4. Synchronize the complete impedance detection result to the memory training process: The complete impedance detection result including detailed data of each frequency point, deviation data, comparison result and overall evaluation is synchronized to the memory training process. During the synchronization process, the actual impedance data and deviation data of each frequency point link in the impedance detection result are first formatted, the data is encapsulated according to the protocol format recognizable by the memory training process, and then transmitted to the memory training process. In the memory bar initialization stage, it is usually necessary to adjust the write clock duty cycle to train a suitable parameter for ensuring the stable operation of the memory at high speed. The impedance detection result can be used as a reference for memory training to assist in optimizing the memory training process. By combining the impedance detection result with the memory training process, the adjustment of the memory training parameter can be more in line with the actual impedance state of the current link, improving the pertinence and effectiveness of the memory training.

[0042] In some embodiments, after step S4, a data storage process is started to store the impedance detection result, impedance values of each frequency point, deviation data, abnormality identification and located memory bar information, as well as the time of detection execution, corresponding device identification and memory channel information. These information is organized in a structured data format and stored in a designated storage unit to form a complete detection record. The detection record supports retrieval by device identification, detection time and memory channel information, and is used for problem tracing and troubleshooting queries in subsequent device maintenance processes, providing data support for long-term device maintenance and performance analysis.

[0043] In the memory training process, the impedance detection result synchronized is combined to adjust the related parameters of the memory training, including the write clock duty cycle, signal amplitude and timing compensation parameters. By referring to the actual impedance data and deviation data of each frequency point, the actual situation of the link transmission characteristics can be determined, and the training parameters can be adjusted accordingly to avoid training failure caused by mismatch between parameter setting and actual link state. When the memory training fails, the impedance detection record stored can be used to troubleshoot the failure cause and determine whether the failure is caused by link problem or other factors, providing a basis for problem delimitation.

[0044] At the same time, the impedance detection process of the present method can be performed in the memory initialization stage after the device is powered on, or can be performed periodically during the device operation to form a normalized detection mechanism. After the device is transported, shelved, etc., the method can be used to quickly detect whether the memory bar is in poor contact due to vibration, to timely find potential problems and handle them, and to avoid faults caused by link impedance abnormalities during device operation. The detection process does not need to interrupt the normal operation of the device and can be automatically completed in the background, taking into account the effectiveness of the detection and the continuity of the device operation.

[0045] In addition, the integrated design of the directional coupler and the ADC device does not need to change the overall architecture of the existing chip, only needs to make local optimization in the chip interface unit, has good compatibility and realizability. The integrated design makes the impedance detection function become the built-in function of the chip, without the need of additional external hardware devices, reduces the hardware cost and integration complexity of the device, and reduces the signal interference and compatibility problems caused by the access of external devices.

[0046] In the deviation calculation process, the selection of the statistical method can be flexibly adjusted according to the actual detection needs, and the application of the average deviation and the standard deviation can reflect the dispersion degree of the impedance data from different dimensions, providing more comprehensive data support for the comparison of the deviation threshold. The parallel application of the two statistical methods can avoid the limitations of a single method and improve the accuracy of the deviation judgment.

[0047] In the sweep signal generation process, the detection frequency point range determined based on the memory working frequency can comprehensively cover all possible working conditions of the memory, ensuring that the link impedance can be effectively detected in different working modes. The adaptability of the amplitude and phase parameters of the sweep signal to the memory working state ensures that the detection signal can truly simulate the signal transmission during memory operation, making the detection result more valuable.

[0048] The method realizes accurate detection of the memory bar installation state and the link transmission quality through a systematic link impedance detection process, and the technical effects mainly reflect in the following aspects: First, it can effectively detect whether the memory bar is installed in place and whether the link impedance is normal. Through comprehensive detection and deviation analysis of the link impedance of each frequency point, it can timely find the poor contact problem caused by improper installation, transportation vibration and other factors, and reduce the device failure caused by link abnormalities. Second, by combining the impedance detection result with the memory training process, the effectiveness and pertinence of the memory training are improved, the memory initialization process is optimized, and the probability of memory training failure is reduced. Third, the complete detection record formed provides rich data support for device maintenance, facilitates problem tracing and fault troubleshooting, and improves the efficiency and accuracy of device maintenance. Fourth, the built-in detection design does not need external device support, reduces the detection cost and operation complexity, and the normal detection mechanism can realize early discovery and early processing of potential problems, improving the stability and reliability of device operation. Fifth, by clearly defining the cause of memory training failure, the accuracy of problem definition is improved, providing a clear direction for subsequent fault handling and reducing the time cost of problem troubleshooting. Sixth, it is compatible with different chip designs and memory working modes, has wide applicability, and can meet the memory bar detection needs of various servers and other devices.

[0049] The effective detection of the memory bank installation state and the link impedance normality is directly realized through a core detection step, and the effect directly comes from a complete process of collection of incident signals and reflected signals, impedance calculation, threshold comparison and abnormality identification, which ensures the timely discovery and processing of link problems and provides a basic guarantee for the stable operation of the device.

[0050] Embodiment 3 In some embodiments, by optimizing the CPU interface design and signal processing process, the link impedance detection after the installation of the memory bank is realized, and potential problems such as poor contact are checked. The implementation of this method is based on a specific hardware topology, and the following is the specific hardware connection and steps: Referring to Figure 2 , the CPU establishes a signal connection with the IO unit through the DDR controller, the IO unit forms a transmission link with the memory bank slot through the PHY module, and the memory bank is inserted into the slot and contacts the PIN pin in the slot to form a complete signal path between the CPU and the memory bank. This topology provides a basic hardware support for subsequent impedance detection, ensuring that the test signal can be stably transmitted between the CPU and the memory bank, laying a hardware foundation for the accuracy of the detection data.

[0051] Referring to Figure 3 , the original IO unit topology is composed of a TX transmitting end, a RX receiving end and a PHY module, and can only realize the function of regular signal transmission and reception, and cannot separate incident signals and reflected signals, which makes it difficult to meet the needs of impedance detection. In order to realize the signal separation and collection function required for impedance detection, the IO unit topology needs to be optimized.

[0052] As shown in Figure 4 , the IO unit optimized topology adds a directional coupler and two groups of ADC devices on the basis of the original structure, the input end of the directional coupler is connected to the TX transmitting end, the output end is connected to the incident wave sampling branch and the reflected wave sampling branch respectively, and the two groups of ADC devices are connected to the two sampling branches respectively, and the end is connected to the calculation unit of the CPU. The directional coupler, as a device that can separate incident waves and reflected waves, is not specific to a certain model or material, its function is to accurately separate the test signal output by the TX transmitting end into incident signals and reflected signals, ensuring that the two signals enter the corresponding sampling branches without interference.

[0053] After the detection process is started, first, the detection frequency range is determined based on the memory working frequency, a sweep signal covering the range is generated, the amplitude and phase parameters of the sweep signal are adapted to the memory working state, and can truly reflect the link signal transmission characteristics when the memory is working. After the sweep signal is output by the TX transmitting end, it enters the directional coupler, and the directional coupler separates the incident signal and the reflected signal, the separated incident signal is transmitted along the incident wave sampling branch, and the reflected signal is transmitted along the reflected wave sampling branch.

[0054] Two groups of ADC devices respectively collect the voltages of the incident signal and the reflected signal. The ADC devices can convert the collected analog voltage signals into digital information that can be processed by a computer, without being specific to a certain model or bit width. The collection process covers all detection frequencies, ensuring that the incident signal voltage and the reflected signal voltage at each frequency point can be completely collected. The collected digital voltage information is organized in frequency order to form a complete voltage dataset and transmitted to the computing unit of the CPU.

[0055] The computing unit first divides the reflected signal voltage by the incident signal voltage at each detection frequency point to obtain the reflection coefficient S11 corresponding to each frequency point, where S11 is the voltage reflection coefficient of port 1, equal to the ratio of the incident wave voltage to the reflected wave voltage at port 1. Subsequently, the computing unit substitutes the reflection coefficient S11 into the reflection method impedance calculation formula, combines the preset link design impedance Z0, and obtains the actual impedance of the link corresponding to each frequency point through logical operations. The core logic of this calculation formula is that the actual impedance of the link is equal to the product of the design impedance of the link, the sum of 1 and the reflection coefficient, divided by the difference between 1 and the reflection coefficient.

[0056] After obtaining the actual impedance of the link at each frequency point, the computing unit uses statistical methods to calculate the deviation of the actual impedance from the design impedance based on the link design impedance. Statistical methods include average deviation and standard deviation, and complete deviation data for each frequency point is obtained through these methods. At the same time, combined with the link design standard, the impedance variation law of the transmission line, and the actual application scenario, the deviation threshold for distinguishing between normal and abnormal impedance is set, including the specified threshold and the proportional threshold. Both methods are fine-tuned in combination with the differences in transmission characteristics of different frequency points.

[0057] The computing unit compares the impedance deviation of each frequency point with the deviation threshold in order according to the detection frequency, marks the comparison result of each frequency point, and then summarizes the impedance values, deviation data, and comparison results of all frequency points to generate impedance detection results containing overall link impedance evaluation, and determines whether there is an abnormality in the overall link. If there is an abnormal frequency point, the computing unit extracts the abnormal frequency point information from the detection results, associates the corresponding link identifier and physical connection path, and locates the corresponding memory bar based on the link information.

[0058] Once the location is determined, the system automatically issues a prompt containing information about the abnormal memory module and operational instructions, including reseating or replacing it. Simultaneously, the calculation unit organizes and encapsulates the complete impedance detection results according to a protocol format recognizable by the memory training process, synchronizing it to the memory training process to provide a reference for adjusting memory training parameters. After the steps are completed, the system structurally stores the impedance detection results, frequency data, anomaly identifiers, memory module information, detection time, and device identifiers, forming a complete detection record for easy retrieval during subsequent maintenance.

[0059] This method is achieved through Figure 4 The optimized I / O unit topology shown achieves effective separation and accurate acquisition of incident and reflected signals. Combined with data analysis and processing by the computing unit, it completes comprehensive detection of link impedance. The implementation process does not rely on external testing equipment. Through the collaborative work of the built-in hardware and software processes, it improves the convenience and timeliness of testing, enabling timely detection of problems such as improper memory module installation or poor contact caused by transportation vibrations. This reduces the risk of downtime caused by link anomalies during device operation, while providing a reliable reference for memory training and improving the stability and reliability of memory operation.

[0060] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A self-test method for installing a memory module, characterized in that, Includes the following steps: S1. Separate the test signal that adapts to the working state of the memory to obtain the incident signal and the reflected signal, collect the voltage corresponding to the two signals and convert them into digital information to obtain complete voltage data covering all detection frequency points; S2. Calculate the reflection coefficient based on the ratio of the incident signal voltage to the reflected signal voltage. Substitute the reflection coefficient into the reflection method impedance calculation formula and combine it with the link design impedance to obtain the actual link impedance corresponding to each detection frequency point. Then calculate the deviation between the actual link impedance and the link design impedance. S3. Based on the link design standards and the transmission line impedance variation law, set the deviation threshold, compare the impedance deviation of each frequency point with the deviation threshold one by one, and generate the impedance detection result containing the impedance value of each frequency point, the deviation data and the overall link impedance evaluation. S4. Analyze the impedance detection results, identify abnormal situations that exceed the deviation threshold, clarify the link and frequency information corresponding to the abnormality, issue a prompt to re-insert or replace the relevant memory module, and synchronize the impedance detection results to the memory training process.

2. The method according to claim 1, characterized in that, Step S1 includes the following sub-steps: S1.

1. Determine the detection frequency range based on the memory operating frequency, generate a sweep signal covering the frequency range, and adapt the sweep signal to the memory operating state; S1.

2. The swept frequency signal is separated to obtain the incident signal and the reflected signal; S1.

3. Collect the voltages corresponding to the incident and reflected signals respectively, convert the collected analog voltage signals into digital information, and form voltage data covering all detection frequency points.

3. The method according to claim 1, characterized in that, Step S2 includes the following sub-steps: S2.

1. Using each detection frequency point as a unit, divide the reflected signal voltage at that frequency point by the incident signal voltage to obtain the reflection coefficient corresponding to each frequency point; S2.

2. Substitute the reflection coefficient of each frequency point into the reflection method impedance calculation formula, combine it with the preset link design impedance, and obtain the actual link impedance corresponding to each frequency point through logical operation; S2.

3. Using the link design impedance as a benchmark, calculate the deviation between the actual link impedance and the link design impedance at each frequency point, and record the deviation data for each frequency point.

4. The method according to claim 1, characterized in that, Step S3 includes the following sub-steps: S3.

1. Based on link design standards, transmission line impedance variation patterns, and actual application scenarios, set a deviation threshold to distinguish between normal and abnormal impedance. S3.

2. According to the order of the detection frequency points, compare the impedance deviation recorded at each frequency point with the deviation threshold respectively, and mark the comparison result of each frequency point; S3.

3. Summarize the impedance values, deviation data and comparison results of all frequency points to generate impedance detection results that include overall link impedance evaluation, and clarify whether there are any abnormalities in the overall link.

5. The method according to claim 1, characterized in that, Step S4 includes the following sub-steps: S4.

1. Extract the frequency point information marked as abnormal from the impedance detection results, and associate the link identifier and physical connection path corresponding to the abnormal frequency point; S4.

2. Locate the memory module corresponding to the abnormal frequency point based on the link information associated with it; S4.

3. Issue a prompt containing information about the abnormal memory module and operation instructions, which include re-inserting or replacing it; S4.

4. Synchronize the complete impedance detection results to the memory training process.

6. The method according to claim 2, characterized in that, In step S1.1, the generation of the sweep frequency signal is combined with the frequency requirements corresponding to different working modes of the memory to define the detection frequency range. The amplitude and phase parameters of the sweep frequency signal are adapted to the working state of the memory so that the sweep frequency signal can truly reflect the link signal transmission characteristics when the memory is working.

7. The method according to claim 3, characterized in that, In step S2.3, before calculating the deviation, the actual impedance of the link and the design impedance of the link corresponding to each frequency point are matched accordingly. Then, the deviation is calculated using statistical methods, including average deviation and standard deviation. When calculating the average deviation, the absolute value of the impedance difference at each frequency point is first obtained, and then the average of all absolute values ​​is calculated. When calculating the standard deviation, the sum of the squares of the impedance differences at each frequency point is first obtained, and then the average is calculated and the square root is taken.

8. The method according to claim 4, characterized in that, In step S3.1, the deviation threshold can be set in two ways: a specified threshold and a proportional threshold. The specified threshold is determined by a fixed value based on the allowable error range of the link design, while the proportional threshold is determined by a fixed proportion of the link design impedance. Both methods are fine-tuned by taking into account the differences in transmission characteristics at different frequencies.

9. The method according to claim 5, characterized in that, In step S4.4, when synchronizing the impedance detection results to the memory training process, the actual impedance data and deviation data of each frequency link in the impedance detection results are first formatted, and the data is encapsulated according to the protocol format that the memory training process can recognize before being transmitted to the memory training process.

10. The method according to claim 1, characterized in that, After step S4, the impedance detection results, impedance values ​​at each frequency point, deviation data, anomaly indicators, and the location of the memory module are stored. At the same time, the detection execution time, the corresponding device identifier, and the memory channel information are also stored. This information is organized in a structured data format and stored in a designated storage unit to form a complete detection record.

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