Transmission channel conversion device and method

Abstract

The embodiment of the invention provides a transmission channel conversion device and method. The transmission channel conversion device comprises a first buffer and a processing module, the first buffer is used for receiving first data sent by a first target module through M transmission channels and storing the first data; the processing module is used for converting the first data into second data of N transmission channels according to a preset arrangement sequence corresponding to a channel proportional relationship, and sending the second data to a second target module; the channel proportional relation is a proportional relation between M transmission channels and N transmission channels; wherein the first target module is a PCIe (Peripheral Component Interconnect Express) module, and the second target module is a serial transceiver; or, the first target module is a serial transceiver, and the second target module is a PCIe module.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of high-speed communication, and in particular to a transmission channel conversion device and method. BACKGROUND

[0002] The Peripheral Component Interconnect Express (PCIe) bus standard is a mainstream high-speed serial communication technology architecture in the current global electronic information field, aiming to solve the high-speed data interaction needs between processors and peripherals, peripherals and peripherals, and has become a key technology cornerstone supporting the efficient operation of modern electronic devices, with core advantages of high bandwidth, low latency, flexible expansion, and strong compatibility.

[0003] At present, in the existing PCIe technology system, the design of the uplink and downlink protocol standards adopts the principle of forced symmetry, but in the scenario of highly asymmetric uplink and downlink load, the use of the principle of forced symmetry will cause serious waste of physical size cost, pin number cost, design cost, and power consumption.

[0004] In summary, how to avoid resource waste caused by the use of PCIe technology in the scenario of highly asymmetric uplink and downlink load is a technical problem that needs to be solved at present. SUMMARY

[0005] The embodiments of the present application provide a transmission channel conversion device and method to solve the problem of serious waste of physical size cost, pin number cost, design cost, and power consumption caused by the use of the PCIe technology system in the scenario of highly asymmetric uplink and downlink load in the prior art.

[0006] In a first aspect, the embodiments of the present application provide a transmission channel conversion device, comprising a first buffer and a processing module; the first buffer is used to receive first data sent by a first target module through M transmission channels and store the first data; the processing module is used to convert the first data into second data of N transmission channels according to a preset arrangement order corresponding to a channel proportion relationship, and send the second data to a second target module; the channel proportion relationship is the proportion relationship between the M transmission channels and the N transmission channels; wherein the first target module is a Peripheral Component Interconnect Express (PCIe) module, and the second target module is a serial transceiver; or, the first target module is a serial transceiver, and the second target module is a PCIe module.

[0007] In the above technical solution, by modifying the number of transmission channels between the first target module and the second target module, the number of transmission channels can be modified without modifying the number of transmission channels of the first target module.

[0008] Optionally, the first target module is a Peripheral Component Interconnect Express (PCIe) module, and the second target module is a serial transceiver; the processing module comprises a first classification module and an interleaving module; the first classification module is configured to classify the first data to obtain data corresponding to each data type; and the interleaving module is configured to convert the first data into second data of N transmission channels according to a first preset arrangement sequence corresponding to each data type.

[0009] Optionally, the processing module further comprises a broadcasting module and a selection module; the broadcasting module is configured to copy or extract data of a first data type from M transmission channels to N transmission channels; the first data type indicates that data transmitted in the M transmission channels is the same; the interleaving module is specifically configured to distribute data of a second data type from the M transmission channels to the N transmission channels; the second data type indicates that data transmitted in the M transmission channels is different; and the selection module is configured to receive data sent by the interleaving module or data sent by the broadcasting module, and generate second data of the N transmission channels from the received data.

[0010] Optionally, the first data type comprises FTS and EIOS; the second data type comprises TLP, DLLP, TS1 / TS2; and the third data type comprises SKP.

[0011] Optionally, the processing module further comprises a second buffer; the second buffer is configured to store data with a data type output by the first classification module; and the broadcasting module and the interleaving module are configured to obtain data of respective required data types from the second buffer.

[0012] Optionally, the processing module further comprises a deletion module and an insertion module; the deletion module is located between the first classification module and the second buffer, and is configured to set a state of data of a third data type in the first data to an invalid state; the data type comprises the first data type, the second data type and the third data type; the third data type is used to indicate clock compensation; the second buffer is specifically configured to store data other than the third data type; and the insertion module is located after the selection module, and is configured to insert data of the third data type into data output by the selection module, so as to obtain second data of the N transmission channels.

[0013] Optionally, the processing module further comprises a counter; the counter is configured to record a frequency of occurrence of the data of the third data type; and the insertion module is configured to insert the data of the third data type into the data output by the selection module according to the frequency of occurrence.

[0014] Optionally, the second buffer is further configured to receive a back pressure signal sent by the interleaving module or the broadcasting module, and pause data output according to the back pressure signal until a ready signal sent by the interleaving module or the broadcasting module is received.

[0015] Optionally, the first target module is a serial transceiver, and the second target module is a PCIe module; the processing module comprises a second classification module and an interleaving module; the second classification module is configured to classify the first data to obtain data corresponding to each data type; and the interleaving module is configured to convert the first data into second data of N transmission channels according to a second preset arrangement order corresponding to each data type.

[0016] Optionally, the processing module further comprises a correction module located before the second classification module; the correction module is configured to perform synchronous correction on the first data of M transmission channels sent by the serial transceiver.

[0017] Optionally, the processing module further comprises a broadcasting module and a selection module; the broadcasting module is configured to copy or extract data of a first data type from N transmission channels to M transmission channels; the first data type represents that data transmitted in the N transmission channels is the same; the interleaving module is specifically configured to distribute data of a second data type from the N transmission channels to the M transmission channels; the second data type represents that data transmitted in the M transmission channels is different; and the selection module is configured to receive data sent by the interleaving module or data sent by the broadcasting module to obtain second data of the M transmission channels.

[0018] Optionally, the method further comprises a register; and the register is configured to store the configured channel proportion relationship.

[0019] In a second aspect, an embodiment of the present application provides a transmission channel conversion method applied to a transmission channel conversion device; first data sent by a first target module through M transmission channels is received, and the first data is stored; the first data is converted into second data of N transmission channels according to a preset arrangement order corresponding to a channel proportion relationship, and the second data is sent to a second target module; the channel proportion relationship is a proportion relationship between the M transmission channels and the N transmission channels; wherein the first target module is a Peripheral Component Interconnect Express (PCIe) module, and the second target module is a serial transceiver; or the first target module is a serial transceiver, and the second target module is a PCIe module.

[0020] Optionally, the first target module is a Peripheral Component Interconnect Express (PCIe) module, and the second target module is a serial transceiver; and the first data is converted into second data of N transmission channels according to a preset arrangement order corresponding to a channel ratio relationship, including: classifying the first data to obtain data corresponding to each data type; and converting the first data into second data of N transmission channels according to a first preset arrangement order corresponding to each data type.

[0021] Optionally, converting the first data into second data of N transmission channels according to a first preset arrangement order corresponding to each data type includes: copying or extracting data of a first data type to meet transmission of N transmission channels; the first data type represents that data transmitted in M transmission channels is the same; dividing data of a second data type to meet distribution to N transmission channels; the second data type represents that data transmitted in M transmission channels is different; and merging the processed data of the first type and the second type to obtain second data of N transmission channels.

[0022] Optionally, the method further includes: deleting data of a third data type from the first data; the third data type is used to represent clock compensation; and merging the processed data of the first type and the second type to obtain second data of N transmission channels includes: merging the processed data of the first type and the second type, and inserting data of the third data type in the merged data, thereby obtaining second data of N transmission channels.

[0023] In a third aspect, an electronic device is provided, including: a Peripheral Component Interconnect Express (PCIe) module, a serial transceiver, and a transmission channel conversion device located between the PCIe module and the serial transceiver.

[0024] In a fourth aspect, a computer-readable nonvolatile storage medium is provided, including a computer-readable program, when the computer-readable program is read and executed by a computer, the computer-readable program causes the computer to perform steps of a transmission channel conversion method according to the second aspect.

[0025] In a fifth aspect, a computer program product is provided, including a computer program stored in a computer-readable storage medium, the computer program including program instructions, when the program instructions are executed by a computer device, the program instructions cause the computer device to perform steps of a transmission channel conversion method according to the second aspect. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0027] Figure 1 A structural schematic diagram of a PCIe module provided by an embodiment of the present application is shown in FIG. 1. Figure 2 A method flowchart of a method for configuring an asymmetric channel provided by an embodiment of the present application is shown in FIG. 2. Figure 3 A structural schematic diagram of a transmission channel conversion device provided by an embodiment of the present application is shown in FIG. 3. Figure 4 A structural schematic diagram of a target device provided by an embodiment of the present application is shown in FIG. 4. Figure 5 A structural schematic diagram of another target device provided by an embodiment of the present application is shown in FIG. 5. Figure 6 A schematic diagram of data interaction between a first device and a second device provided by an embodiment of the present application is shown in FIG. 6. Figure 7 A structural schematic diagram of a processing module provided by an embodiment of the present application is shown in FIG. 7. Figure 8 A structural schematic diagram of another processing module provided by an embodiment of the present application is shown in FIG. 8. Figure 9 A schematic diagram of signal interaction between a second buffer, an interleaving module and a broadcasting module provided by an embodiment of the present application is shown in FIG. 9. Figure 10 A structural schematic diagram of another processing module provided by an embodiment of the present application is shown in FIG. 10. Figure 11 A schematic diagram of inserting SKP according to frequency of occurrence provided by an embodiment of the present application is shown in FIG. 11. Figure 12 A structural schematic diagram of a processing module provided by an embodiment of the present application is shown in FIG. 12. Figure 13 A structural schematic diagram of a processing module provided by an embodiment of the present application is shown in FIG. 13. Figure 14 A method flowchart of a transmission channel conversion method provided by an embodiment of the present application is shown in FIG. 14. Figure 15 An interaction diagram of data transmission between a first device and a second device provided by an embodiment of the present application is shown in FIG. 15. Figure 16 A structural schematic diagram of an electronic device provided by an embodiment of the present application is shown in FIG. 16. DETAILED DESCRIPTION

[0028] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present application.

[0029] In the following, some terms in the present application are generally explained to facilitate the understanding of those skilled in the art, and the terms in the present application are not limited.

[0030] Peripheral Component Interconnect Express (PCIe) module: the module includes a transaction layer, a data link layer and a physical layer, wherein the physical layer includes a link training and status state machine (LTSSM), which can be referred to Figure 1 . The transaction layer is responsible for generating and analyzing standard PCIe packets, the data link layer manages the link state, and the link training state machine processes the physical layer control sequence. The transaction layer, the data link layer and the link training state machine are implemented by hardware logic, such as the PCIe hard core IP of FPGA, the PCIe controller IP for ASIC, and the configuration thereof can be implemented by firmware.

[0031] Serial transceiver: the serial transceiver is a key component of the chip, and the core thereof is SerDes technology. In the field of FPGA, Xilinx and Intel are respectively called GT series and Tile series transceivers; and in ASIC design, the function is usually realized by integrating SerDes PHY IP core. The sending end is responsible for encoding, serializing parallel data, and finally converting into differential electrical signals for transmission on physical media such as PCB wiring and cable. The receiving end is responsible for receiving differential signals and deserializing and decoding serial data. In the embodiments of the present application, the serial transceiver only transmits and receives signals of N channels in physics.

[0032] Transaction Layer Packet (TLP): TLP is the uppermost and most core packet in the PCIe module. TLP carries the specific "intent" or "command" issued by the system software, such as the driver, for example, reading data from the memory, writing configuration information to the device, etc. TLP is the only packet that can carry user data.

[0033] Data Link Layer Packet (DLLP): DLLP is a control packet used to manage the status of the link between two directly connected PCIe devices. DLLP does not carry user data and is only passed between two adjacent components, such as a Root Port and an Endpoint, or two ports of a Switch.

[0034] Training Sequence (TS1 / TS2): TS1 and TS2 are special Ordered Sets. TS1 / TS2 is not strictly a packet and is only used in the process of link initialization or recovery, i.e. in the LTSSM state machine, to train the physical link to reach a state of normal communication (L0 state).

[0035] Skip Ordered Set (SKP): SKP is also a special Ordered Set. SKP is periodically inserted into the data stream after the link enters the stable L0 state.

[0036] Fast Training Sequence (FTS): composed of 1 COM symbol (K28.5) and 3 FTS symbols (K28.1). FTS is a mechanism for bit and symbol lock when transitioning from L0s to L0. The receiver uses FTS to detect exit from the electrical idle state and align the receiver's bit / symbol reception circuit with the input data.

[0037] Electrical Idle Ordered Set (EIOS): composed of 1 COM symbol (K28.5) and 3 IDL symbols (K28.3). Before entering the electrical idle state, the transmitter must send 1 (at 2.5GT / s rate) or 2 (at rates greater than 2.5GT / s) EIOS. After sending the last symbol of the last EIOS, the transmitter must be in the valid electrical idle state. The transmitter is required to send FTS and EIOS synchronously on all valid lanes.

[0038] In the current global electronic information field, the PCIe bus standard has become the mainstream high-speed serial communication technology architecture, and its core value lies in solving the high-speed data interaction needs between processors and peripherals, and peripherals.

[0039] Under the support of high bandwidth, low latency and flexible expansion technology characteristics, PCIe bus standard not only covers the general electronic field, but also becomes the core architecture to ensure efficient data transmission in many professional scenarios. In the asymmetric transmission demand scenario of uplink data-intensive and downlink data-simplified, it has certain technical advantages. The following will introduce the asymmetric transmission demand scenario of uplink data-intensive and downlink data-simplified.

[0040] In one possible scenario, the front-end device needs to continuously collect massive data generated by sensors or signal processing, which can be high-frequency electrical signals, waveform data, gene sequence fragments, etc., without limitation. And push these data to the main processor for real-time analysis and processing at high speed, and the main processor only issues a small amount of control instructions to the front-end, such as acquisition parameter configuration, start-stop signal, etc., without limitation. In this process, PCIe can carry continuous massive uplink data transmission with single-channel high bandwidth to avoid data accumulation. At the same time, the end-to-end low latency can ensure that the collected data is sent to the main processor in real time, ensuring the timeliness of signal analysis and sequence comparison. Its typical applications include high-speed oscilloscopes, radar / sonar systems, and gene sequencers.

[0041] In another possible scenario, the device needs to perform real-time preprocessing on multiple high-definition video streams, such as AI enhancement, noise reduction filtering, and format conversion, and then upload the massive frame data after processing to the GPU at high speed, and the GPU completes subsequent rendering, feature extraction or storage operations. The downlink direction only needs to transmit a small amount of video parameter configuration and processing instructions. The high bandwidth characteristics of PCIe can meet the medical imaging system of multiple high-definition video streams. Specifically, the massive image data generated by CT / MRI is preprocessed and then transmitted to the GPU by PCIe for three-dimensional reconstruction and lesion analysis. It can also be applied to high-end security monitoring. Specifically, after preprocessing multiple 4K monitoring pictures, they are uploaded to the GPU through PCIe to realize real-time target tracking and anomaly recognition.

[0042] In another possible scenario, the coprocessor mainly performs data generation or data expansion type computing tasks. Specifically, the input parameters or data set size issued by the host processor to the coprocessor is small, but the result data generated after the coprocessor completes the calculation is exponentially or multiple increased, and needs to be returned to the upstream host processor or storage device at high speed. PCIe plays a role in the uplink channel of massive computing results in this scenario. Its high bandwidth can efficiently carry the large-scale data output by the coprocessor, avoid computing result backlog, and flexible channel configuration can match x2 / x4 / x8 channel specifications according to the computing power and output data volume of the coprocessor, balance bandwidth demand and resource occupation, and at the same time, the downward compatibility feature can adapt to coprocessors and host processors of different generations, reducing the cost of device upgrade. For example, in a large-scale scientific computing scenario, after the FPGA coprocessor completes complex simulation calculation based on a small amount of input parameters, it uploads massive simulation results to the CPU for summary analysis through PCIe. Or in the data encryption scenario, after the ASIC coprocessor receives a small amount of plaintext data and encryption keys, it generates massive ciphertext data which is returned to the storage system through PCIe at high speed, ensuring efficient connection of data encryption and storage.

[0043] In summary, since the existing PCIe protocol standard adopts the principle of forced symmetry in the design of uplink and downlink, in the scenario of highly asymmetric uplink and downlink load introduced above, the principle of forced symmetry will cause the problem of resource waste.

[0044] In order to solve the above problem, the current method is to introduce a non-standard extension step, so as to realize the asymmetry of the uplink and downlink transmission channels, and to be applicable to the scenario of highly asymmetric uplink and downlink load. The following introduces two cases to illustrate how to introduce a non-standard extension step to be applicable to the scenario of highly asymmetric uplink and downlink load.

[0045] In a possible case, a non-standard extension step is introduced in the initial stage of PCIe link establishment, that is, in the negotiation process of the link training state machine. The following will specifically introduce how to introduce a non-standard extension step.

[0046] As shown in Figure 2 Fig. 1 is a flow chart of a method for configuring an asymmetric channel provided by an embodiment of the present application. The method comprises the following steps: Step 201, detecting a device connected to a host device across a multi-channel link.

[0047] In the embodiment of the present application, the host device detects the peripheral device connected through the multi-channel link, confirms that the communication device to be communicated has been accessed, and provides a premise for subsequent link configuration.

[0048] Step 202, initializing a link training process for the device.

[0049] In the embodiment of the present application, the PCIe controller initializes the link training process for the access device, and prepares for determining the link communication parameters.

[0050] In step 203, the capability announcement indicating the expansibility of the uplink and / or downlink is detected.

[0051] In the embodiment of the present application, the host device detects the capability announcement indicating the expansibility of the uplink and downlink sent by the device, and determines the range of the flexible adjustment of the channel supported by the device.

[0052] In the embodiment of the present application, through detecting the capability announcement, the devices at both ends of the link can identify the support capability of the asymmetric channel.

[0053] In step 204, the number of uplink or downlink paths to be added is determined during the link training.

[0054] In the embodiment of the present application, during the link training, the devices at both ends of the link negotiate the number of asymmetric uplink and downlink channels. For example, the devices at both ends of the link negotiate to determine 6 sending channels and 2 receiving channels.

[0055] In step 205, the channel allocation for all channels of the link is performed.

[0056] In the embodiment of the present application, the PCIe controller performs the allocation operation for all channels of the multi-channel link, and determines the corresponding physical resources of the uplink and downlink channels, so as to avoid resource conflicts.

[0057] In step 206, the channel equalization is performed.

[0058] In the embodiment of the present application, the PCIe controller performs the channel equalization for the allocated channels, optimizes the signal integrity of each channel, reduces the transmission interference, and guarantees the high-bandwidth transmission quality.

[0059] In step 207, the multi-channel link is initialized.

[0060] In the embodiment of the present application, the PCIe controller initializes the multi-channel link whose channel allocation and equalization have been completed, so that the link enters the ready state and the data transmission can be formally started.

[0061] In step 208, the indication for re-adjusting the width of the link is received.

[0062] In the embodiment of the present application, the host device receives the indication for re-adjusting the width of the link, and triggers the link parameter updating process.

[0063] In step 209, the link configuration process is initialized.

[0064] In the embodiment of the application, the PCIe controller initializes a new link configuration process according to the adjustment indication to adapt to the changed load communication requirement.

[0065] As can be seen from the above steps 201 to 209, the number of uplink and downlink channels can be adjusted through negotiation of the devices at both ends of the link, so that an asymmetric number of uplink and downlink channels is determined, which can be applied to a highly asymmetric uplink and downlink application load scenario, thereby solving the problem of resource waste caused by the use of the PCIe technology in a highly asymmetric uplink and downlink load scenario.

[0066] However, the above Figure 2 The method mentioned above has some problems. Specifically, first Figure 2 The method involves high implementation cost because the method is realized by invasive modification at the core protocol layer, and a complex protocol soft core needs to be redeveloped. The entire computer ecosystem, from the physical layer controller to the upper layer driver, must be modified.

[0067] Moreover Figure 2 The link width adjustment mechanism proposed in the method involves interrupting the current data transmission and reconfiguring or training the link. This interruption will cause millisecond-level service suspension, which is not applicable to real-time applications that require continuous and uninterrupted data flow, such as video processing and high-frequency data acquisition.

[0068] In addition Figure 2 The method involves redefining the transmission direction of the physical channel, for example, using the original receiving channel as a sending channel to realize asymmetric configuration. This approach destroys the signal integrity optimization design of the PCIe connector and PCB wiring for standard symmetric links, which may introduce additional crosstalk and power noise, posing potential risks to the stability and reliability of the system.

[0069] In another possible case, control software is set on the host, which continuously monitors the data flow of the entire system and learns and predicts the future bandwidth requirement of the link based on historical data and current workload. For example, the uplink is much larger than the downlink. Then when the asymmetric demand is predicted, the software makes a decision to determine an optimal TX / RX channel ratio, and the software issues a non-standard control instruction to command the underlying PCIe hardware to dynamically reconfigure the physical channel to match the predicted asymmetric ratio.

[0070] However, this case has the same problems as the method involved in Figure 2 The method has the problems of high implementation cost, service interruption during channel adjustment, and impact on the stability and reliability of the system.

[0071] In summary, the embodiment of the present application provides a transmission channel conversion device to solve the above problems of high implementation cost, service interruption during channel adjustment, and influence on system stability and reliability for adapting to uplink and downlink load height asymmetry scenarios.

[0072] As shown in Figure 3 Fig. 1 is a structural schematic diagram of a transmission channel conversion device provided by an embodiment of the present application. The device comprises a first buffer 310 and a processing module 320; the first buffer 310 is used to receive first data sent by a first target module 330 through M transmission channels and store the first data; the processing module 320 is used to convert the first data into second data of N transmission channels according to a preset arrangement order corresponding to a channel proportion relationship and send the second data to a second target module 340; the channel proportion relationship is a proportion relationship between the M transmission channels and the N transmission channels; wherein the first target module 330 is a Peripheral Component Interconnect Express (PCIe) module, and the second target module 340 is a serial transceiver; or, the first target module 330 is a serial transceiver, and the second target module 340 is a PCIe module.

[0073] In the embodiment of the present application, the first device and the second device are respectively deployed at both ends of the data transmission link, and the transmission channel conversion device is arranged in both the first device and the second device. Next, the transmission channel conversion device is introduced, and how the transmission channel conversion device adjusts the number of transmission channels is introduced.

[0074] Next, the transmission channel conversion device is introduced, and how the transmission channel conversion device adjusts the number of transmission channels is introduced.

[0075] As shown in Figure 4As shown, the structure of the target device provided by the embodiment of the present application is shown. The target device comprises a first target module, a transmission channel conversion device and a second target module, wherein the first target module is a PCIe module, and the second target module is a serial transceiver. The transmission channel conversion device is located between the PCIe module and the serial transceiver. The first buffer in the transmission channel conversion device is used to receive the first data sent by the PCIe module through M transmission channels and store the first data, so as to avoid data loss when the burst bandwidth exceeds the transmission capacity of the compressed channel. Then the first data is sent to the processing module. The processing module is used to convert the first data into second data of N transmission channels according to the preset arrangement order corresponding to the channel ratio relationship, and send the second data to the serial transceiver. In this way, the PCIe module still performs data transmission according to M transmission channels. By setting the transmission channel conversion device, M transmission channels are converted into N transmission channels, so that the serial transceiver receives data of N transmission channels. In this way, the number of serial transceivers can be reduced by reducing the number of transmission channels while ensuring normal data transmission.

[0076] Optionally, the channel ratio relationship is used to compress or expand the number of N. The following examples are used to introduce how to determine the value of N.

[0077] For example, if the first device and the second device negotiate according to the symmetric protocol to determine that the transmission channel is 4, then the first device and the second device correspond to 4 transmission channels respectively. In actual application, the amount of data to be transmitted between the first device and the second device is small, and 4 transmission channels are not needed for data transmission, and 4 serial transceivers are not needed for data transmission and reception. By setting the transmission channel conversion device in the first device and the second device, the transmission channel conversion device in the first device converts the data of 4 transmission channels into the data of 2 transmission channels according to the channel ratio relationship and sends the data to the serial transceiver. The channel ratio relationship is used to compress the value of N to 1 / X of M, wherein X is configurable, that is, the channel ratio relationship is configurable. In this way, only two serial transceivers are needed to transmit the data of 2 transmission channels to the receiving device, so that the cost can be reduced while ensuring normal data transmission.

[0078] For example, 4 serial transceivers are set in the first device and the second device, wherein two idle serial transceivers are used for transmission of other data, so as to improve the utilization rate of the idle serial transceivers.

[0079] For another example, if the first device and the second device negotiate according to the symmetric protocol and determine that there are four transmission channels, with each device having four channels and eight serial transceivers, in practical applications, the amount of data to be transmitted between the two devices is relatively large. The bandwidth of four transmission channels is insufficient to handle such a large data volume, requiring more serial transceivers for transmission and reception. By setting up a transmission channel conversion device in both devices, the data from the four transmission channels in the first device can be converted in this way, thus improving the efficiency of data transmission by using eight serial transceivers.

[0080] like Figure 5 The diagram shows a structural schematic of another target device provided in an embodiment of the present invention. The receiving device includes a first target module, a second target module, and a transmission channel conversion device, wherein the first target module is a serial transceiver, and the second target module is a PCIe module. The serial transceiver of the receiving device receives first data from M transmission channels sent by the serial transceiver of the transmitting device, and then sends the data from the M transmission channels to the first buffer of the transmission channel conversion device. The first buffer stores the data from the M transmission channels and sends it to the processing module. The processing module converts the first data into second data from N transmission channels according to a preset arrangement order corresponding to the channel ratio relationship, and sends it to the PCIe module. It should be noted that the channel ratio relationship at the transmitting end of the first device is inversely proportional to the channel ratio relationship at the receiving end of the second device.

[0081] For example, if the first device and the second device negotiate according to the symmetric protocol and determine that there are 4 transmission channels, the first device and the second device each correspond to 4 transmission channels, and each of the first device and the second device includes 4 serial transceivers. The transmission channel conversion device in the first device converts four transmission channels into two transmission channels according to the channel ratio. The first data from these two transmission channels is then sent to the serial transceiver in the second device. The serial transceiver then sends the first data from the two transmission channels back to the transmission channel conversion device, which converts it into second data for four transmission channels and sends it to the PCIe module. Since the channel ratio is used to compress the value of N to 1 / X times M (where X is configurable), the channel ratio is configurable. Therefore, the conversion of the number of channels can be achieved without the PCIe modules of the first and second devices being aware of it. This ensures that the entire link logically maintains full PCIe protocol compliance while converting transmission channels. It also solves the problem of dynamically adjusting the number of transmission channels based on the amount of data transmitted, thereby dynamically adjusting the number of serial transceivers used and improving the utilization rate of the serial transceivers.

[0082] The following describes how to realize channel conversion between the first device and the second device through the transmission channel conversion device without sensing the PCIe module of the two devices.

[0083] The first device and the second device both have the ability to send and receive data, so both the first device and the second device include two transmission channel conversion devices, which are a first transmission channel conversion device for sending data and a second transmission channel conversion device for receiving data. It should be noted that the first device and the second device both include a PCIe module, a serial transceiver, a transmission channel device for sending data, and a transmission channel conversion device for receiving data. In order to facilitate understanding of the present scheme, the following describes how the first device and the second device realize channel conversion through the transmission channel conversion device.

[0084] As shown in Figure 6 Fig. 1 is a schematic diagram of data interaction between a first device and a second device according to an embodiment of the present application. The first device includes a first PCIe module, N first serial transceivers, a first transmission channel conversion device for sending data, and a second transmission channel conversion device for receiving data. The second device includes a second PCIe module, N second serial transceivers, a third transmission channel conversion device for sending data, and a fourth transmission channel conversion device for receiving data.

[0085] Since the first PCIe module of the first device has the same function as the second PCIe module of the second device, the first transmission channel conversion device of the first device has the same function as the third transmission channel conversion device of the second device, and the second transmission channel conversion device of the first device has the same function as the fourth transmission channel conversion device of the second device. The first device can not only be used to send data to the second device, but also be used to receive data sent by the second device. Since it has been described above how to adjust the transmission channel between the sending device and the receiving device, it is not limited here.

[0086] In order to facilitate understanding of the present scheme, the following first describes how the transmission channel conversion device converts the transmission channel when the first target module is a PCIe module and the second target module is a serial transceiver.

[0087] In this embodiment of the invention, the first buffer in the transmission channel conversion module is used to receive and store the first data from the M transmission channels sent by the PCIe module, thus preventing data loss when sudden bandwidth exceeds the transmission capacity of the compressed channels. The first buffer sends the first data to the processing module, facilitating the subsequent processing module to convert the first data from the M transmission channels into second data from the N transmission channels. The first buffer can be physically implemented as a first input first output (FIFO) storage structure. For example, in an FPGA, this FIFO is typically constructed using on-chip memory resources such as block random access memory (BRAM), while in an ASIC, it is typically implemented using static random access memory (SRAM) macrocells or register files from a standard cell library.

[0088] Next, we will introduce how the processing module converts the first data from M transmission channels into the second data from N transmission channels.

[0089] like Figure 7 The diagram shows a structural schematic of a processing module provided in an embodiment of the present invention. The processing module 320 includes a first classification module 321 and an interleaving module 322. The first classification module 321 is used to classify the first data to obtain data corresponding to each data type. The interleaving module 322 is used to convert the first data into second data for N transmission channels according to a first preset arrangement order corresponding to each data type.

[0090] In this embodiment of the invention, the first classification module can classify the first data to obtain data corresponding to multiple data types. The first classification module then sends the data of these multiple data types to the interleaving module. The interleaving module converts the first data into second data for N transmission channels according to a first preset arrangement order corresponding to each data type.

[0091] For example, the first classification module classifies the first data from the four transmission channels into data corresponding to data type A, data corresponding to data type B, and data corresponding to data type C. Then, the first classification module sends the data corresponding to data type A, data type B, and data type C to the interleaving module. The interleaving module converts the data corresponding to data type A, data type B, and data type C into the second data from the four transmission channels according to the first preset arrangement order corresponding to the data types.

[0092] Optionally, the first classification module classifies the first data from the M transmission channels to obtain data corresponding to multiple data types. These data types are divided into a first data type, a second data type, and a third data type. The first data type includes FTS and EIOS; the second data type includes TLP, DLLP, and TS1 / TS2; and the third data type is SKP. The first data type indicates that the data transmitted in the M transmission channels is the same, the second data type indicates that the data transmitted in the M transmission channels is different, and the third data type is inserted into the data in any transmission channel according to its frequency of occurrence.

[0093] As can be seen from the three different data types, if the first data is interleaved using the interleaving module, a large amount of identical data will be interleaved, resulting in a large amount of duplicate data in the N transmission channels. This makes the data in each transmission channel longer due to the duplicate data, affecting the efficiency and speed of data transmission. Furthermore, during the interleaving process, the change in the number of transmission channels may cause the third data type to not be inserted into the data according to its frequency of occurrence.

[0094] Depending on the data type, different processing methods are required for different data types. To facilitate understanding of this solution, the following section describes how to process data based on data type, thereby converting the first data from M transmission channels into the second data from N transmission channels.

[0095] First, we will introduce how to process the data corresponding to TLP, DLLP, TS1 / TS2, FTS, and EIOS to obtain the second data of N transmission channels.

[0096] like Figure 8 The diagram shows another processing module provided in an embodiment of the present invention. Processing module 320 includes a first classification module 321, an interleaving module 222, a broadcasting module 223, and a selection module 224. The function of the first classification module has been described above and will not be limited here. The broadcasting module is used to copy or extract data of the first data type from M transmission channels to N transmission channels. The interleaving module is specifically used to distribute data of the second data type from the M transmission channels to the N transmission channels. The selection module is used to receive data sent by the interleaving module or the broadcasting module, and generate second data for N transmission channels from the received data.

[0097] In this embodiment of the invention, considering that the data of the first data type is identical in each transmission channel, interleaving would result in a lot of duplicate data. Therefore, a broadcast module is introduced. The first data is classified by the first classification module. The data of the first data type is copied or extracted by the broadcast module to convert the data of M transmission channels into data of N transmission channels. The data of the second data type is interleaved by the interleaving module to convert the data of M transmission channels into data of N transmission channels. In this way, the selection module receives data sent by the interleaving module or the broadcast module at the same time and generates the second data of N transmission channels from the received data.

[0098] Considering that the broadcast and interleaving modules need to convert data from M transmission channels into data from N transmission channels, in one possible scenario where M is greater than N, the broadcast and interleaving modules can acquire data from the M transmission channels more quickly. However, during the conversion to data from the N transmission channels, issues such as data loss, data interleaving, or copying / extraction errors may occur.

[0099] Optionally, a second buffer 330 is provided between the first classification module 321, the broadcast module 323, and the interleaving module 322. The second buffer 330 is used to store data with data types output by the first classification module. The broadcast module and the interleaving module are used to retrieve data of their respective required data types from the second buffer. The caching function of the second buffer is implemented in the same way as that of the first buffer.

[0100] Optionally, the second buffer is also used to receive the back pressure signal sent by the interleaving module or the broadcasting module, pause data output according to the back pressure signal, and continue to provide data to the interleaving module or the broadcasting module after receiving the ready signal sent by the interleaving module or the broadcasting module.

[0101] like Figure 9 The diagram illustrates signal interaction between a second buffer, an interleaving module, and a broadcast module according to an embodiment of the present invention. The second buffer sets the status of data of a second data type sent to the interleaving module to a valid state, and sets the status of data of a first data type sent to the broadcast module to a valid state. When the broadcast module and / or the interleaving module sends a ready signal to the second buffer via pin A, this ready signal indicates that the interleaving module and / or the broadcast module can acquire data, wherein the broadcast module and / or the interleaving module acquires the data that is set to a valid state for that module. Figure 9The data in the first valid state is the valid data sent from the second buffer to the interleaving module, wherein the data type of the data in the first valid state is the second data type. The data in the second valid state is the valid data sent from the second buffer to the broadcast module, wherein the data type of the data in the second valid state is the first data type.

[0102] In one possible scenario, if the broadcast module and / or interleaving module cannot process the data obtained from the second buffer in a timely manner, the broadcast module and / or interleaving module send a backpressure signal to the second buffer. This backpressure signal indicates a pause in data output. After receiving the backpressure signal, in order to prevent data loss, the second buffer will not update the content of the output data until it receives a ready signal from the broadcast module and / or interleaving module. Therefore, the second buffer needs to send a backpressure signal to the upper-level module to remind it to pause data transmission.

[0103] Secondly, the process of processing the data corresponding to SKP is introduced to obtain the second data of N transmission channels.

[0104] like Figure 10 The diagram shown is a structural schematic of another processing module provided in an embodiment of the present invention. The processing module 320 includes a first classification module 321, a deletion module 325, an interleaving module 322, a broadcast module 323, a selection module 324, and an insertion module 326.

[0105] Considering that SKPs are inserted into the data according to their frequency of occurrence, when M transmission channels are converted to N transmission channels, the amount of data in each transmission channel will change, resulting in an incorrect frequency of SKP occurrence in the N transmission channels, affecting the accuracy of the data. Therefore, it is necessary to delete the SKPs first, and then re-insert the data in selection module 324 according to their frequency of occurrence. The following section first describes how to delete SKPs.

[0106] The deletion module 325 is located between the first classification module 321 and the second buffer 330. The deletion module 325 sets the status of the third data type in the first data to invalid, and sets the status of the first data type and the second data type to valid. In this way, the deletion module 325 sends the first data to the second buffer 330, and the second buffer 330 stores the data in the valid state, that is, stores the data other than SKP.

[0107] Then introduce how to insert SKP. Specifically, the insertion module 326 is located after the selection module 324, for inserting the data of SKP in the data output by the selection module 324, thereby obtaining the second data of N transmission channels. It should be noted that when inserting SKP, it is necessary to insert according to the frequency of occurrence. In order to facilitate the understanding of the scheme, how to insert SKP according to the frequency of occurrence is introduced below.

[0108] Optionally, the processing module 320 further includes a counter 327, wherein the counter is used to record the frequency of occurrence of the data of the third data type of the single transmission channel. The insertion module 326 is used to insert the data of SKP into the data output by the selection module according to the frequency of occurrence. Taking symbol_num_between_SKP = 250, M = 4, N = 2 as an example, referring to Figure 11 The insertion of the ordered set of SKP in the data stream before and after channel compression can be determined.

[0109] The following introduces how the transmission channel conversion device converts the transmission channel when the first target module is a serial transceiver and the second target module is a PCIe module.

[0110] As shown in Figure 12 The processing module 320 includes a second classification module 340 and a de-weaving module 350. The second classification module 240 is used to classify the first data to obtain data corresponding to each data type. The de-weaving module 350 is used to convert the first data into second data of N transmission channels according to a second preset arrangement order corresponding to each data type.

[0111] The function of the second classification module is similar to that of the first classification module, which is not limited here. The principle of the de-weaving module is similar to that of the interleaving module, except that the channel ratio relationship of the de-weaving module is inversely proportional to that of the interleaving module.

[0112] Since the first target module is a serial transceiver, the serial transceiver will delete the SKP in the first data after receiving the first data of M transmission channels. Therefore, the data sent to the second classification module subsequently does not include SKP.

[0113] In a possible case, the data transmission of some transmission channels is faster, and the data transmission of some transmission channels is slower. When de-weaving, the data of M transmission channels needs to be aligned, and then de-weaved according to the preset arrangement order to obtain the second data of N transmission channels. Therefore, before de-weaving, the data of M transmission channels needs to be aligned.

[0114] Optionally, the processing module further comprises a correction module before the second classification module, wherein the correction module is configured to synchronize and correct the first data of the M transmission channels transmitted by the serial transceiver, so that the first data of the M transmission channels are aligned.

[0115] As shown in Figure 13 , it is a structural schematic diagram of a processing module provided by an embodiment of the present application. The processing module further comprises a broadcast module 360 and a selection module 370.

[0116] The broadcast module 360 is configured to copy or extract the data of the first data type from the N transmission channels to the M transmission channels; the first data type represents that the data transmitted in the N transmission channels is the same; The disentangling module 370 is specifically configured to distribute the data of the second data type from the N transmission channels to the M transmission channels; the second data type represents that the data transmitted in the M transmission channels is different; The selection module is configured to receive the data transmitted by the disentangling module or the data transmitted by the broadcast module, to obtain the second data of the M transmission channels.

[0117] As shown in Figure 14 , it is a method flowchart of a transmission channel conversion method provided by an embodiment of the present application. The method comprises the following steps: Step 1401, receiving the first data transmitted by the first target module through the M transmission channels, and storing the first data.

[0118] Step 1402, converting the first data into the second data of the N transmission channels according to the preset arrangement order corresponding to the channel proportion relationship, and transmitting the second data to the second target module.

[0119] As can be seen from the above steps 1401 to 1402, by modifying the number of transmission channels between the first target module and the second target module, the number of transmission channels can be modified without modifying the number of transmission channels of the first target module.

[0120] Optionally, the first target module is a Peripheral Component Interconnect Express (PCIe) module, and the second target module is a serial transceiver; converting the first data into the second data of the N transmission channels according to the preset arrangement order corresponding to the channel proportion relationship comprises: classifying the first data to obtain data corresponding to each data type; and converting the first data into the second data of the N transmission channels according to the first preset arrangement order corresponding to each data type.

[0121] Optionally, the first data is converted into second data of the N transmission channels according to the first preset arrangement sequence corresponding to each data type, including: copying or extracting the data of the first data type to meet the transmission of the N transmission channels; the first data type represents that the data transmitted in the M transmission channels is the same; dividing the data of the second data type to meet the distribution to the N transmission channels; the second data type represents that the data transmitted in the M transmission channels is different; and merging the processed first type data and the second type data to obtain the second data of the N transmission channels.

[0122] Optionally, the method further includes: deleting the data of a third data type from the first data; the third data type is used to represent clock compensation; and merging the processed first type data and the second type data to obtain the second data of the N transmission channels, including: merging the processed first type data and the second type data, and inserting the data of the third data type in the merged data, so as to obtain the second data of the N transmission channels.

[0123] As shown in FIG. 1, a first device and a second device are provided according to an embodiment of the present application. Figure 15 As shown in FIG. 1, a first device and a second device are provided according to an embodiment of the present application. Figure 15 Taking M=4 and N=2 as an example, the change process of different types of data packets from the sending end of the first device to the receiving end of the second device is described. In the figure, ①→② describes the data sending process of the sending end of the first device. In ①, the format of the SKP, FTS, EIOS, TS1 / TS2, TLP / DLLP data packets on the 4 lanes after passing through the MUX is shown before the channel conversion (4lane→2lane) of the sending end of the first device. In ②, the format of the SKP, FTS, EIOS, TS1 / TS2, TLP / DLLP on the 2 lanes is shown after the channel conversion (4lane→2lane) of the sending end. Among them, the FTS and EIOS pass through the broadcast module and still maintain the complete FTS and EIOS sequence form on the 2 lanes. TS1 / TS2, TLP / DLLP pass through the interleaving module, and the data originally transmitted on lane0 and lane2 is alternately placed on lane0 in symbol units; the data originally transmitted on lane1 and lane3 is alternately placed on lane1 in symbol units.

[0124] Figure 15The middle ③→④ describes the data receiving process of the receiving end, and the ③ shows various data packet formats transmitted on the 2lane physical link before the channel conversion (2lane→4ane) of the receiving end. The ④ shows the data format prepared for demux after the channel conversion (2lane→4ane) of the receiving end. Among them, the FTS and the EIOS pass through the broadcast module and have complete FTS and EIOS sequence forms on the 4lane. The TLP / DLLP and the TS1 / TS2 pass through the disentangling module, and the data on the lane0 is placed on the lane0 and the lane2 in turn in symbol units. The data on the lane1 is placed on the lane1 and the lane3 in turn in symbol units. The selection module selects the output signals from the two modules according to the valid signals output by the disentangling module and the broadcast module and outputs the signals to the data link layer and the LTSSM.

[0125] Based on the same technical concept, as shown in Figure 16 A structural schematic diagram of an electronic device provided by an embodiment of the present application is shown in FIG. 16. The electronic device 1600 includes a peripheral component interconnect express (PCIe) module 1601, a serial transceiver 1602, and a transmission channel conversion device 1603 between the PCIe module and the serial transceiver.

Claims

1. A transport channel conversion apparatus, characterized by comprising: Includes a first buffer and a processing module; The first buffer is used to receive first data sent by the first target module through M transmission channels and to store the first data; The processing module is used to convert the first data into second data of N transmission channels according to a preset arrangement order corresponding to the channel ratio relationship, and send it to the second target module; the channel ratio relationship is the ratio between M transmission channels and N transmission channels; Wherein, the first target module is a high-speed peripheral component interconnect PCIe module, and the second target module is a serial transceiver; or, the first target module is a serial transceiver, and the second target module is a PCIe module.

2. The apparatus as claimed in claim 1, characterized in that, The first target module is a high-speed peripheral component interconnect (PCIe) module, and the second target module is a serial transceiver; The processing module includes a first classification module and an interleaving module; The first classification module is used to classify the first data to obtain data corresponding to each data type; The interleaving module is used to convert the first data into second data of N transmission channels according to the first preset arrangement order corresponding to each data type.

3. The apparatus as described in claim 2, characterized in that, The processing module also includes a broadcast module and a selection module; The broadcast module is used to copy or extract data of the first data type from M transmission channels into N transmission channels; the first data type indicates that the data transmitted in the M transmission channels is the same. The interleaving module is specifically used to distribute data of the second data type from M transmission channels to N transmission channels; the second data type indicates that the data transmitted in the M transmission channels are different. The selection module is used to receive data sent by the interleaving module or the broadcast module, and generate second data for N transmission channels from the received data.

4. The apparatus as claimed in claim 2, characterized in that, The first data type includes Fast Training Ordered Set (FTS) and Electrically Idle Ordered Set (EIOS); the second data type includes Transaction Layer Packet (TLP), Data Link Layer Packet (DLLP), and Training Sequences (TS1 / TS2); the third data type includes Skip Ordered Set (SKP).

5. The apparatus as described in claim 3, characterized in that, The processing module also includes a second buffer; The second buffer is used to store the data with data type output by the first classification module; The broadcast module and the interleaving module are used to obtain data of their respective required data types from the second buffer.

6. The apparatus as claimed in claim 5, characterized in that, The processing module also includes a deletion module and an insertion module; The deletion module is located between the first classification module and the second buffer, and is used to set the state of the third data type in the first data to an invalid state; the data type is divided into a first data type, a second data type and the third data type; the third data type is used to represent clock compensation. The second buffer is specifically used to store data other than the third data type; The insertion module is located after the selection module and is used to insert data of a third data type into the data output by the selection module, thereby obtaining the second data of N transmission channels.

7. The apparatus as claimed in claim 6, characterized in that, The processing module also includes a counter; The counter is used to record the frequency of occurrence of data of the third data type; The insertion module is used to insert the data of the third data type into the data output by the selection module according to the frequency of occurrence.

8. The apparatus as claimed in claim 5, characterized in that, The second buffer is also used to receive the back pressure signal sent by the interleaving module or the broadcast module, and to pause data output according to the back pressure signal until a ready signal is received from the interleaving module or the broadcast module.

9. The apparatus as claimed in claim 1, characterized in that, The first target module is a serial transceiver, and the second target module is a PCIe module; The processing module includes a second classification module and a deweaving module; The second classification module is used to classify the first data to obtain data corresponding to each data type; The unweaving module is used to convert the first data into second data of N transmission channels according to the second preset arrangement order corresponding to each data type.

10. The apparatus as claimed in claim 9, characterized in that, The processing module also includes a correction module located before the second classification module; The correction module is used to perform synchronous correction on the first data of the M transmission channels sent by the serial transceiver.

11. The apparatus as claimed in claim 9, characterized in that, The processing module also includes a broadcast module and a selection module; The broadcast module is used to copy or extract data of the first data type from N transmission channels into M transmission channels; the first data type indicates that the data transmitted in the N transmission channels is the same; The unweaving module is specifically used to distribute data of the second data type from N transmission channels to M transmission channels; the second data type indicates that the data transmitted in the M transmission channels are different. The selection module is used to receive data sent by the unweaving module or the broadcasting module to obtain the second data of M transmission channels.

12. The apparatus according to any one of claims 1 to 11, characterized in that, It also includes registers; The register is used to store the configured channel ratio relationship.

13. A transmission channel conversion method, characterized in that, Applications in transmission channel conversion devices; Receive the first data sent by the first target module through M transmission channels, and store the first data; According to the preset arrangement order corresponding to the channel ratio relationship, the first data is converted into second data of N transmission channels and sent to the second target module; the channel ratio relationship is the ratio between M transmission channels and N transmission channels; Wherein, the first target module is a high-speed peripheral component interconnect PCIe module, and the second target module is a serial transceiver; or, the first target module is a serial transceiver, and the second target module is a PCIe module.

14. The method as described in claim 13, characterized in that, The first target module is a high-speed peripheral component interconnect (PCIe) module, and the second target module is a serial transceiver; According to a preset arrangement order corresponding to the channel ratio, the first data is converted into second data for N transmission channels, including: The first data is categorized to obtain data corresponding to each data type; According to the first preset arrangement order corresponding to each data type, the first data is converted into second data of N transmission channels.

15. The method as described in claim 13, characterized in that, According to the first preset arrangement order corresponding to each data type, the first data is converted into second data for N transmission channels, including: Data of the first data type is copied or extracted to satisfy the transmission of N transmission channels; the first data type indicates that the data transmitted in M ​​transmission channels is the same; The data of the second data type is divided to distribute it to N transmission channels; the second data type indicates that the data transmitted in the M transmission channels are different. The processed first type of data and the second type of data are merged to obtain the second data for N transmission channels.

16. The method as described in claim 15, characterized in that, Also includes: The data of the third data type is deleted from the first data; the third data type is used to characterize clock compensation. The processed data of the first type and the second type are merged to obtain the second data of N transmission channels, including: The processed first-type and second-type data are merged, and third-type data is inserted into the merged data to obtain the second data for N transmission channels.

17. An electronic device, characterized in that, include: A high-speed peripheral component interconnection PCIe module, a serial transceiver, and a transmission channel conversion device located between the PCIe module and the serial transceiver, wherein the transmission channel conversion device is the device according to any one of claims 1 to 12.

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