Dynamic partitioning method and device for integrated circuit, medium and product
By constructing a target design tree model and dividing the timing critical path, the problems of excessive synthesis time and insufficient timing optimization in VLSI design are solved, achieving efficient synthesis processing and optimization results.
Patent Information
- Application Number
- CN202511873511.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-12
- Publication Date
- 2026-02-27
AI Technical Summary
Existing technologies cannot effectively balance partitioning efficiency and synthesis quality in VLSI design, leading to problems such as uncontrolled synthesis time, increased timing violations, and decreased resource utilization.
By constructing a target design tree model, identifying timing critical paths, and dividing the design tree model into multiple partitions based on clock parameter information and preset partition constraints, synthesis processing is performed on each partition to generate a gate-level netlist, and finally the complete netlist is reconstructed.
It significantly improves the overall efficiency and quality of integrated circuit design, reduces synthesis time, and ensures the optimization goals of timing and area.
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Figure CN121580927A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of integrated circuits, and in particular to a dynamic partitioning method, device, medium and product of an integrated circuit. BACKGROUND
[0002] With the continuous evolution of semiconductor technology to the nanometer scale, the number of transistors integrated on a modern system-on-chip has broken through the 10 billion mark, and the design scale of very large scale integrated circuits has shown exponential growth, and the electronic design automation tool chain is facing unprecedented processing pressure. In the post-Moore era, the design complexity growth rate has exceeded the single-core processor performance improvement curve, and how to break through the time bottleneck of the synthesis stage has become a decisive factor affecting the product launch cycle.
[0003] In the prior art, a partitioning synthesis strategy based on preset boundaries or structural features is mainly adopted, that is, the design is divided into multiple sub-modules for independent processing by manual specification or simple rules before the synthesis process begins. However, the implementation of the prior art cannot effectively balance partitioning efficiency and synthesis quality, resulting in a series of problems such as uncontrolled synthesis time consumption, increasing timing violations, and decreased resource utilization due to key path cutting, constraint loss, and local optimization limitations in the synthesis process of very large scale circuits. SUMMARY
[0004] The embodiments of the present application provide a dynamic partitioning method, device, medium and product of an integrated circuit, which can significantly improve the synthesis efficiency and quality of integrated circuit design.
[0005] According to an aspect of the embodiments of the present application, a dynamic partitioning method of an integrated circuit is provided, the method comprising:
[0006] According to the Verilog source code, very high speed integrated circuit hardware description language (VHDL) source code and constraint file corresponding to the target integrated circuit, an abstract syntax tree and clock parameter information are formed, and a target design tree model corresponding to the target integrated circuit is constructed according to the abstract syntax tree and the clock information;
[0007] The target design tree model has modules as vertices and wires between corresponding ports in two modules as edges, the edges include instantiation relationships between nodes, and multiple signal transmission paths are formed between the modules through corresponding ports, and each module includes multiple gate logic devices;
[0008] According to the clock parameter information, each timing critical path included in the design tree model is identified, and the design tree model is divided into multiple partitions according to the model structure of the design tree model, each timing critical path and a preset partitioning restriction condition, wherein a timing critical path is completely included in a partition;
[0009] According to the comprehensive processing of each partition, a gate net list corresponding to each partition is obtained, and a complete net list of the target integrated circuit is reconstructed according to the gate net lists.
[0010] According to another aspect of the embodiment of the present application, a dynamic partitioning device of an integrated circuit is provided, and the device comprises:
[0011] A target design tree model generation module is configured to form an abstract syntax tree and clock parameter information according to Verilog source code, VHDL source code and a constraint file corresponding to the target integrated circuit, and construct a target design tree model corresponding to the target integrated circuit according to the abstract syntax tree and the clock information.
[0012] The target design tree model takes a module as a vertex and a connection line between corresponding ports in two modules as an edge, the edge contains instantiation relationships between nodes, a plurality of signal transmission paths are formed between the modules through the corresponding ports, and a plurality of gate logic devices are contained in each module.
[0013] A dynamic partitioning module is configured to identify each timing critical path included in the design tree model according to the clock parameter information, and divide the design tree model into a plurality of partitions according to a model structure of the design tree model, the timing critical paths and a preset partitioning restriction condition, wherein a timing critical path is completely included in one partition.
[0014] A net list generation module is configured to perform comprehensive processing on each partition, obtain a gate net list corresponding to each partition, and reconstruct a complete net list of the target integrated circuit according to the gate net lists.
[0015] According to another aspect of the embodiment of the present application, an electronic device is provided, and the electronic device comprises:
[0016] at least one processor; and
[0017] a memory connected with the at least one processor in communication; wherein
[0018] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to execute the dynamic partitioning method of the integrated circuit according to any one of the embodiments of the present application.
[0019] According to another aspect of the embodiment of the present application, a computer readable storage medium is provided, and the computer readable storage medium stores computer instructions for enabling a processor to implement the dynamic partitioning method of the integrated circuit according to any one of the embodiments of the present application when executed.
[0020] According to another aspect of the present invention, a computer program product is also provided, including computer instructions that, when executed by a processor, implement the steps of the method as described in any embodiment of the present invention.
[0021] The technical solution of this invention solves the problems of excessively long synthesis time, insufficient timing optimization, and slow iteration cycle caused by the increase in scale in VLSI design. It effectively reduces synthesis time and ensures that the synthesis results achieve the optimization goals in terms of timing and area.
[0022] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description
[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0024] Figure 1 This is a flowchart of a dynamic partitioning method for an integrated circuit according to Embodiment 1 of the present invention;
[0025] Figure 2 This is a schematic diagram of a complete design tree model constructed according to Embodiment 1 of the present invention;
[0026] Figure 3 This is a flowchart of another dynamic partitioning of an integrated circuit according to Embodiment 2 of the present invention;
[0027] Figure 4 This is a schematic diagram of a partitioned parallel synthesis and result integration provided in Embodiment 2 of the present invention;
[0028] Figure 5is a flow chart of dynamic partition of an integrated circuit according to the third embodiment of the present application;
[0029] Figure 6 is a schematic diagram of a dynamic partition principle according to the third embodiment of the present application;
[0030] Figure 7 is a structural schematic diagram of a dynamic partition device of an integrated circuit according to the fourth embodiment of the present application;
[0031] Figure 8 is a structural schematic diagram of an electronic device implementing a dynamic partition method of an integrated circuit according to the embodiment of the present application. DETAILED DESCRIPTION
[0032] In order to make the personnel in the art better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should belong to the scope of protection of the present application.
[0033] It should be noted that the terms "first", "second", and the like in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0034] Embodiment One
[0035] Figure 1 is a flow chart of a dynamic partition method of an integrated circuit according to the first embodiment of the present application. The embodiment can be applicable to the case of super large scale integrated circuit design synthesis optimization. The method can be executed by a dynamic partition device of an integrated circuit. The device can be realized in the form of hardware and / or software, and can generally be configured in an electronic device.
[0036] Correspondingly, as shown in Figure 1 , the method comprises:
[0037] S110, forming an abstract syntax tree and clock parameter information according to the Verilog source code corresponding to the target integrated circuit, the super-high-speed integrated circuit hardware description language VHDL source code and the constraint file, and constructing a target design tree model corresponding to the target integrated circuit according to the abstract syntax tree and the clock information;
[0038] The target design tree model takes a module as a vertex and a connection line between corresponding ports in two modules as an edge to form a graph, the edge contains instantiation relationships between nodes, and a plurality of gate logic devices are contained in each module.
[0039] The Verilog source code is a hardware description language, and the source code describes the functions and connection relationships of the integrated circuit through a modular structure. The code clearly defines the input and output ports, internal signal connections and logic behaviors (such as combinational logic or sequential logic) of the module, and constructs a hierarchical design through instantiation. The VHDL (VHSIC Hardware Description Language) source code adopts a highly abstract syntax specification, and describes the functions and structures of the circuit through entities and architectures. Its strong type feature can accurately define signal data types and timing behaviors, and supports complex modeling methods such as process statements and concurrent assignments. In the parsing process, the port mapping relationship between entities and the internal component interconnection topology are extracted to form an intermediate representation equivalent to Verilog, ensuring unified processing of mixed language design.
[0040] The constraint file can be understood as defining the timing, power consumption and physical limitation conditions of the design in the form of commands. The core content includes key parameters such as clock frequency, clock domain relationship, input and output delay, and timing exception. The clock parameter information can be understood as being extracted from the constraint file, including the source point, frequency, duty cycle and phase relationship of the main clock and the generated clock. These parameters are used to construct a clock domain topology model to guide the identification and partitioning of the timing critical path. The design tree model can be understood as expressing the hierarchical organization of the design in a tree structure, the root node corresponds to the top module, and the child node represents the instantiated sub-module. The instantiation relationship between nodes can be understood as the core embodiment of module calling in the hardware description language, specifically referring to the hierarchical connection relationship established when the high-level module creates a copy of the low-level module through instantiation statements. In this embodiment, the hardware description language source file and the constraint file of the target integrated circuit need to be parsed and processed first. Through lexical analysis and syntax analysis of Verilog and VHDL, an abstract syntax tree that can reflect the hierarchical structure of the code is generated, and key clock definition information including clock domain division, clock frequency and other parameters is extracted from the constraint file. Based on these analysis results, a complete target design tree model is constructed.
[0041] Correspondingly,Figure 2 A complete design tree model is constructed as shown in FIG. 1. Figure 2 As shown in FIG. 1, the root node of the tree represents the top-level module (i.e., the Top_Module module), and each sub-module instance is a child node of its parent module node. The tree structure clearly expresses the hierarchical organization of the design. It should be particularly noted that the "edges" connecting the nodes in the model not only represent simple signal connections, but more importantly, include instantiation relationships between the nodes. This instantiation relationship is embodied in that when a parent module calls a sub-module through an instantiation statement, a complete connection mapping is established between the two, including key information such as corresponding relationships of port signals, parameter passing values, and instance namespace. For example, when the ALU module instantiates the register file, the corresponding edge will accurately record all interaction details of the data bus, address line, and control signal. The model not only stores the parent-child relationship, but also records the connection relationship of each node with other nodes. The model is the core of the entire synthesis process, and subsequent optimization and partitioning operations are carried out around this model.
[0042] In S120, each timing critical path included in the design tree model is identified according to the clock parameter information, and the design tree model is divided into multiple partitions according to the model structure of the design tree model, each timing critical path, and a preset partitioning restriction condition, wherein each timing critical path is completely included in one partition.
[0043] The timing critical path can be understood as a signal transmission path that violates the timing constraint (such as the setup time and the hold time) in the design, and the delay thereof exceeds the range allowed by the clock period. These paths are usually located in a high-frequency clock domain or complex logic across modules, and their identification is based on the static timing analysis result and is sorted according to the severity of the violation. The preset partitioning restriction condition can be understood as a set of multi-dimensional optimization criteria set for the dynamic partitioning algorithm, and the core goal is to balance the synthesis efficiency and the result quality in the partitioning process.
[0044] In this embodiment, after the design tree model is constructed, the dynamic partitioning stage is entered. In this stage, global timing analysis is first performed using the clock parameter information to identify the critical paths that violate the timing constraint in the design. Then, considering the structural characteristics such as the module size and the tightness of port connection, and combining the identified timing critical paths and the preset partitioning restriction condition, the design tree model is intelligently divided into multiple synthesis partitions using a graph partitioning algorithm. In the partitioning process, it is ensured that each timing critical path is completely included in the same partition, and the sizes of the partitions are kept relatively balanced.
[0045] In S130, synthesis processing is performed on each partition obtained in the division, respectively, to obtain a gate netlist corresponding to each partition, and a complete netlist of the target integrated circuit is reconstructed according to the gate netlists.
[0046] The gate-level netlist can be understood as a circuit structure description file generated after logic synthesis, and represents the logic function of a specific partition in standard gate-level units (such as AND gates, OR gates, and flip-flops) and their connection relationships. The netlist contains process library mapping information, each logic unit is bound to specific physical characteristics (such as delay and area), and the timing constraints and optimization results within the partition are retained. The complete netlist can be understood as a global circuit description reconstructed by integrating all partition gate netlists, which not only includes the optimized gate-level circuit within each partition, but also restores the signal interconnection relationship between partitions.
[0047] In the embodiment, the final stage is to perform synthesis processing on each partition after division. Different optimization strategies are adopted according to the characteristics of each partition. For partitions containing critical paths, timing performance optimization is emphasized, and for other partitions, area and power consumption optimization is emphasized. The synthesis process of each partition is performed in parallel, and after generating the corresponding gate-level netlist, the complete target integrated circuit netlist is finally reconstructed through integration and consistency check, and the entire synthesis process is completed.
[0048] The technical scheme of the embodiment of the application forms an abstract syntax tree and clock parameter information according to the Verilog source code corresponding to the target integrated circuit, the very high speed integrated circuit hardware description language VHDL source code and the constraint file, and constructs a target design tree model corresponding to the target integrated circuit based on the abstract syntax tree and the clock parameter information. Then, according to the clock parameter information, each timing critical path included in the design tree model is identified, and the design tree model is divided into multiple partitions in combination with the model structure of the design tree model, each timing critical path and a preset partition restriction condition. Then, according to each partition divided, synthesis processing is performed to obtain a gate netlist corresponding to each partition, respectively, and a complete netlist of the target integrated circuit is reconstructed according to each gate netlist. The problems of long synthesis time, insufficient timing optimization and slow iteration cycle caused by the increase in the scale of the very large scale integrated circuit design are solved, and the beneficial effects of effectively reducing the synthesis time and ensuring that the synthesis result achieves the optimization target in terms of timing and area are achieved.
[0049] Embodiment two
[0050] Figure 3 The flowchart of another dynamic partitioning method of an integrated circuit provided by the second embodiment of the application is based on the above-mentioned embodiments. The operation of "constructing a target design tree model corresponding to the target integrated circuit according to the abstract syntax tree and the clock information" is refined.
[0051] Correspondingly, as shown in Figure 3 The method comprises the following steps.
[0052] S210, forming an abstract syntax tree and clock parameter information according to the Verilog source code, the VHDL source code and the constraint file corresponding to the target integrated circuit.
[0053] S220, initializing a primitive design tree model corresponding to the target integrated circuit according to the abstract syntax tree and the clock information.
[0054] In the embodiment, a tree structure with a top-level module as a root node and sub-modules as hierarchical nodes is established by parsing the module definition and instantiation relationship in the hardware description language. The model completely retains the original organization form of the design, records not only the parent-child hierarchical relationship between modules but also the signal connection path between all ports, and provides a structured data basis for subsequent optimization operations.
[0055] S230, traversing each signal transmission path in the primitive design tree model, identifying all target gate logic devices driven by constant logic values, and simplifying the downstream gate logic devices of each target gate logic device in the primitive design tree model according to the identification result to obtain a simplified design tree model.
[0056] The constant logic value can be understood as a signal value maintaining a fixed level in a digital circuit, which is usually generated by a power supply, a ground or a specific configuration circuit and is expressed as a constant high level (logic 1) or low level (logic 0). The gate-level logic device can be understood as a basic unit constituting a digital circuit, including basic gate circuits such as AND gate, OR gate and NOT gate, and sequential elements such as flip-flop and latch.
[0057] In the embodiment, by traversing the signal transmission path in the model, gate-level devices driven by constant logic values are identified, and these fixed values are propagated to the downstream associated logic for simplification. For example, when one input of an AND gate is constantly low, the output is necessarily low, and at this time, the gate and its downstream associated logic can be optimized and removed. This process can effectively eliminate the redundant circuit structure caused by constant signals.
[0058] S240, positioning key backtracking positions in the simplified design tree model, wherein the key backtracking positions include positions of top-level output ports and / or registers.
[0059] In the embodiment, the design model after completing logic simplification needs to determine the starting position of optimization analysis. These key backtracking positions include all top-level output ports in the design and register units that must be retained. These positions are selected because they represent the final output points or state storage units of the circuit function, and all signal paths that affect the final result must pass through these nodes for backtracking. The positioning operation establishes a complete inspection boundary for subsequent redundant analysis.
[0060] S250, traversing the simplified design tree model in reverse from the starting point of the positioning key backtracking position to obtain all predecessor nodes matched with the positioning key backtracking positions.
[0061] In this embodiment, after the key backtracking positions are determined, the entire design model is traversed in reverse from these positions. During the traversal process, all predecessor logic nodes that contribute to the output result are identified and marked step by step, including combinational logic gates and timing elements. This process uses a recursive algorithm to ensure full coverage until no new predecessor node can be found. Through this reverse tracking mechanism, all necessary logic elements in the design can be systematically determined.
[0062] S260, performing de-redundancy processing on the simplified design tree model according to all the obtained predecessor nodes to obtain a target design tree model;
[0063] The target design tree model has modules as vertices and connections between corresponding ports in two modules as edges, and multiple signal transmission paths are formed between the modules through the corresponding ports. Each module includes multiple gate logic devices.
[0064] In this embodiment, based on the marking results, the design model is finally optimized, and all unmarked nodes are determined as redundant logic and removed from the model. This operation significantly reduces the circuit size and optimizes the area and power consumption indicators. The target design model after de-redundancy processing retains the complete signal transmission path and hierarchical structure, providing a refined and efficient data basis for subsequent timing analysis and dynamic partitioning.
[0065] S270, identifying each timing critical path included in the design tree model according to the clock parameter information, and dividing the design tree model into multiple partitions according to the model structure of the design tree model, each timing critical path, and a preset partitioning limit condition, wherein a timing critical path is completely included in a partition.
[0066] S280, performing synthesis processing on each partition respectively to obtain a gate netlist corresponding to each partition respectively, and reconstructing a complete netlist of the target integrated circuit according to the gate netlists.
[0067] Optionally, based on the above embodiments, performing synthesis processing on each partition respectively to obtain a gate netlist corresponding to each partition respectively can include:
[0068] According to the inclusion of each partition in the timing critical path, a boundary constraint file corresponding to each partition is generated, and an optimization strategy corresponding to each partition is generated;
[0069] According to the boundary constraint file and the optimization strategy of each partition, a comprehensive processing is performed on each partition by multiple parallel threads to obtain a gate netlist corresponding to each partition.
[0070] Generally, after completing the design partitioning, a dedicated boundary constraint file needs to be generated for each partition, which accurately describes the clock definition, frequency and timing constraint conditions within the partition, to ensure that the partition maintains the consistent timing environment with the global design in the independent synthesis process. Meanwhile, based on the characteristics of whether the partition contains a timing critical path, a differentiated optimization strategy is automatically assigned: for a partition containing a high-frequency path or a large number of critical paths, an optimization scheme focusing on timing performance is adopted, and for a partition without a non-critical path, an optimization strategy focusing on area and power consumption is adopted, thereby realizing accurate matching of resource allocation.
[0071] Generally, the partition synthesis execution stage utilizes a parallel computing architecture to synchronously process the partition synthesis tasks by multiple independent threads. Each thread respectively loads the design model, boundary constraint file and optimization strategy of the corresponding partition, and completes the logic mapping and optimization in an independent process to generate a corresponding gate netlist. After the synthesis of all partitions is completed, the multiple gate netlists generated are integrated and consistency verified, and finally a complete and design specification-compliant gate-level circuit description is reconstructed.
[0072] Optionally, on the basis of the above embodiments, the complete netlist of the target integrated circuit is reconstructed according to the gate netlists, which can include:
[0073] According to the partition scheme generated by dynamic partitioning, the design files and corresponding boundary constraint files of each partition are loaded in parallel on a multi-core server to simultaneously run multiple synthesis processes;
[0074] After all the partition synthesis processes are completed, the gate-level netlists generated by each partition are integrated, and the integrated complete netlist is checked for result consistency, and finally a top-level netlist that complies with the design specification is reconstructed and a complete integrated circuit design result is generated.
[0075] Generally, after completing the dynamic partitioning of the partitions, the synthesis process enters a parallel execution stage. Based on the determined partition scheme, the design data files and their exclusive boundary constraint files corresponding to each partition are loaded in a multi-core computing environment. Each partition is allocated independent computing resources, and parallel processing is achieved by concurrently starting multiple synthesis processes. This parallelization mechanism converts the originally serial synthesis task into a distributed computing mode, so that the synthesis time of a large-scale design changes from linear accumulation to being dominated by the processing time of the most complex partition.
[0076] Generally, after all partition synthesis processes are completed, the gate-level netlists generated in a distributed manner need to be integrated and verified. This process first reconstructs the netlists generated by each partition according to the original design hierarchy, restoring the complete circuit connections. Then, a consistency check is performed on the integrated netlist, focusing on verifying the integrity of cross-partition signal connections, the inheritance of timing constraints, and the equivalence of logical functions. Through this systematic merging and verification mechanism, a top-level netlist that conforms to the original design specifications and has undergone optimization is finally reconstructed, forming a complete integrated circuit design deliverable to the back-end physical design stage.
[0077] Generally, the entire parallel processing and result integration process employs a pipelined scheduling strategy, which ensures both the independence of each partition's synthesis and the integrity of the final result through a unified integration framework. This approach significantly improves the synthesis efficiency of VLSI circuit design by parallel scheduling of computing resources while maintaining the consistency of the design logic.
[0078] Figure 4 This is a schematic diagram of partitioned parallel synthesis and result integration, as shown below. Figure 4 As shown, the left side presents multiple parallel partition synthesis processes. Each process independently loads its corresponding partition design file and boundary constraints, achieving synchronous processing through multi-core computing resources. Each partition employs a differentiated optimization strategy; partitions containing critical paths focus on timing performance optimization, while other partitions prioritize area and power consumption optimization. The diagram's center uses mesh connections to represent the signal interaction relationships between partitions, with arrows clearly indicating the data flow paths at partition boundaries. This connection topology maintains the complete interconnect structure of the original design, ensuring that independent partition synthesis does not disrupt global logic functionality. The right side of the diagram shows the netlist integration stage. After consistency checks, the sub-netlists generated by each partition are reconstructed into a complete top-level netlist according to hierarchical relationships. The entire process demonstrates an orderly transition from distributed processing to centralized integration, ultimately outputting a synthesis result that conforms to design specifications through a collaborative mechanism of parallel acceleration and quality control.
[0079] The technical scheme of the embodiment of the present application forms an abstract syntax tree and clock parameter information according to the Verilog source code corresponding to the target integrated circuit, the super-high-speed integrated circuit hardware description language VHDL source code and the constraint file, initializes and constructs an original design tree model based on the abstract syntax tree and the clock parameter information, then traverses each signal transmission path in the original design tree model to identify all target gate logic devices driven by constant logic values and performs simplification processing on the downstream gate logic devices to obtain a simplified design tree model, subsequently locates key backtracking positions in the simplified design tree model, including positions of top-level output ports and registers, takes these positions as starting points to reversely traverse to obtain all predecessor nodes matched with each located key backtracking position, and further performs de-redundancy processing on the simplified design tree model according to the obtained all predecessor nodes to obtain a target design tree model, the target design tree model has modules as vertices, lines between corresponding ports in two modules as edges, and multiple signal transmission paths are formed between the modules through the corresponding ports and each module contains multiple gate logic devices, then each timing critical path included in the target design tree model is identified according to the clock parameter information, and the target design tree model is divided into multiple partitions according to the model structure of the target design tree model, each timing critical path and a preset partition restriction condition, and it is ensured that one timing critical path is completely in one partition, finally, synthesis processing is respectively performed on each partition to obtain a gate netlist corresponding to each partition, and a complete netlist of the target integrated circuit is reconstructed according to the gate netlists, which solves the problem of long synthesis time and slow iteration cycle of super-large scale integrated circuit design caused by the increase in scale, and effectively reduces the synthesis time and ensures that the synthesis result reaches the optimization target in terms of timing and area.
[0080] Embodiment three
[0081] Figure 5 The flowchart of another dynamic partitioning method of an integrated circuit provided by the third embodiment of the present application is based on the optimization of the above-mentioned embodiments. The operation of "identifying each timing critical path included in the design tree model according to the clock parameter information" is refined.
[0082] Correspondingly, as shown in Figure 5 , the method comprises:
[0083] S310, according to the Verilog source code corresponding to the target integrated circuit, the super-high-speed integrated circuit hardware description language VHDL source code and the constraint file, forming an abstract syntax tree and clock parameter information, and constructing a target design tree model corresponding to the target integrated circuit according to the abstract syntax tree and the clock information;
[0084] The target design tree model has modules as vertices and connections between corresponding ports in two modules as edges, and each module includes a plurality of gate logic devices.
[0085] S320, extracting clock constraint information from the clock parameter information, and identifying a violation path that violates the setup time and / or the hold time constraint in all signal transmission paths according to the clock constraint information.
[0086] In this embodiment, first, the specific timing constraint requirements need to be parsed from the extracted clock parameter information, including the frequency period of each clock domain, the setup time and hold time specifications, and other key parameters. Based on these constraint conditions, static timing analysis is performed on all signal transmission paths in the design tree model, and the matching relationship between path delay and clock period is checked piece by piece, so as to accurately identify the path segment with timing violation, i.e. the fault path whose signal transmission time cannot meet the setup time or hold time requirement.
[0087] S330, calculating the violation degree of each violation path, and obtaining a timing critical path in each violation path according to the violation degree of each violation path.
[0088] In this embodiment, after the violation path identification is completed, the severity of each violation path needs to be quantitatively evaluated. By calculating the deviation value between the actual path delay and the constraint requirement, all violation paths are sorted and graded according to the violation amplitude. The path that deviates from the constraint standard most significantly and has the most serious impact on the circuit performance is marked as the timing critical path. These critical paths will be the key protection objects of the subsequent partition strategy.
[0089] S340, dividing the design tree model into a plurality of partitions according to the model structure of the design tree model, the timing critical paths, and the preset partition limit conditions, wherein a timing critical path is completely included in a partition.
[0090] Optionally, on the basis of the above embodiments, the design tree model is divided into a plurality of partitions according to the model structure of the design tree model, the timing critical paths, and the preset partition limit conditions, which can include:
[0091] According to the model structure of the design tree model, the vertices and / or edges in the design tree model are valued;
[0092] According to the valuation result of the design tree model, the timing critical paths, and the preset partition limit conditions, the design tree model is divided into a plurality of partitions;
[0093] The preset partition restriction condition includes a constraint condition that a time sequence critical path needs to be completely included in one partition, and at least one constraint condition that is matched with the assignment content of the vertex and / or the edge.
[0094] Generally, after the design tree model is constructed, the elements in the graph need to be quantitatively assigned based on the hierarchical structure of the model. Specifically, the vertex corresponds to each functional module in the design, and the assignment of the vertex is usually based on the size index such as the number of basic logic units contained in the module; the edge corresponds to the signal connection relationship between the modules, and the assignment of the edge can be based on factors such as port interaction density and time sequence criticality. Such assignment provides quantifiable optimization basis for subsequent partition algorithms.
[0095] Generally, after the weight assignment is completed, the graph partition algorithm is used for intelligent partition in combination with the distribution characteristics of the time sequence critical path and the preset partition restriction condition. The partition process needs to strictly follow the critical path integrity constraint to ensure that any time sequence critical path completely belongs to the same partition, and to meet the optimization targets such as balance of partition size and aggregation of high-coupling modules. Through the weight-guided partition strategy, the time sequence performance is guaranteed while reducing the cutting cost of the partition boundary.
[0096] Optionally, on the basis of each of the above embodiments, the assignment of the vertex and / or the edge in the design tree model according to the model structure of the design tree model can include:
[0097] According to the number of gate logic devices included in each module in the design tree model, a module size value corresponding to each module is calculated;
[0098] According to the model structure of the design tree model, the connection signal number and the fan-in and fan-out value of each port in each module are obtained;
[0099] According to the module size value of each module and the connection signal number and the fan-in and fan-out value of each port in each module, the port coupling degree of each port in each module is calculated;
[0100] According to the module size value, the vertices in the design tree model are assigned, and according to the port coupling degree of each port, the edges in the design tree model are assigned;
[0101] Correspondingly, the preset partition restriction condition further includes a constraint condition on the maximum module size value contained in each partition, and a constraint condition on the maximum port coupling degree contained in each partition.
[0102] Generally speaking, in the dynamic partition preparation stage, first of all, the module in the design tree model needs to be scaled quantitative evaluation. By counting the total number of gate logic devices contained in each module, the corresponding module size value is generated, which directly reflects the circuit complexity and resource occupation of the module, and provides data basis for subsequent partition load balancing.
[0103] Among them, the fan-in value can be understood as the number of signal sources connected to the module input terminal, reflecting the diversity of module data receiving, and the fan-out value refers to the load size of the module output terminal driving downstream logic, embodying the signal distribution ability.
[0104] Generally speaking, the quantitative analysis of the connection relationship between modules needs to be realized by analyzing the port interconnection characteristics. Specifically, it includes counting the number of signal lines connected to each module port, calculating the fan-in value and fan-out value of the port, and these parameters jointly represent the interaction intensity of the module and other modules. The more the connection signals and the higher the fan-in and fan-out values of the port, the stronger the coupling strength.
[0105] Among them, the port coupling degree can be understood as a quantitative index that integrates module size, connection signal number and fan-in and fan-out value, which is used to measure the tightness of the functional dependence between modules.
[0106] Generally speaking, the calculation of port coupling degree needs to consider multiple factors. After obtaining the module size value and port connection data, the connection signal number, module size and fan-in and fan-out value are fused and calculated by a weighted algorithm to generate a quantitative index of port coupling degree that reflects the tightness of the association between modules. High coupling degree indicates frequent data interaction between modules.
[0107] Generally speaking, after completing the quantitative analysis, the design tree model needs to be assigned weights. The module size value is assigned to the corresponding vertex as the weight, and the port coupling degree is assigned to the corresponding connection edge as the edge weight, so that the circuit structure characteristics are converted into a numerical model that can be processed by the graph partitioning algorithm.
[0108] Generally speaking, the preset partition limit conditions need to be set in combination with the quantitative indicators. Including limiting the maximum module size value of a single partition to prevent load imbalance, limiting the maximum port coupling degree in the partition to ensure the aggregation of high correlation modules, these constraint conditions cooperate with the assignment content of the vertex and edge, and jointly guide the optimization direction of partition division.
[0109] In an optional implementation of the embodiment, taking a design comprising five functional modules of arithmetic logic unit (12, 300 gates), instruction decoder (2, 800 gates), register file (28, 500 gates), data cache controller (15, 600 gates) and system controller (8, 200 gates) as an example, first, the number of gate logic devices of each module is counted by traversing the design tree model to complete the scale quantization; then, taking the connection between the ALU module and the RegFile module as an example, the port coupling degree is calculated, there are 40 connection signals between the two modules, combined with the fan-out value of the ALU 35 and the fan-in value of the RegFile 28, the quantization result of 0.83 is calculated through the coupling degree formula; based on the preset partitioning limit conditions (the maximum scale threshold of a single partition is 25,000 gates, and the high coupling degree threshold is 0.7), the partition decision shows that the register file needs to be divided into two sub-modules due to the oversize threshold, the ALU and the register file must be divided in the same region due to the high coupling degree, and the small-scale decoder needs to be merged with the system controller. The design tree model provides a hierarchical basic framework for the above-mentioned quantization analysis, and by converting the abstract design features into specific numerical indicators, an optimized partitioning scheme is finally formed which meets the timing constraints and realizes load balancing.
[0110] Figure 6 For the schematic diagram of dynamic partitioning principle, as shown in Figure 6 , the partitioning result based on module size, coupling degree and critical path is shown, and the middle arrow represents the critical path. In the figure, the functional modules in the design are represented by different geometric shapes, and the size of the module reflects the difference in logic scale, and the density of the connection line between the modules reflects the strength of the port coupling degree. The critical path identified by the arrow in the schematic diagram runs through multiple associated modules, clearly showing the transmission path of the timing critical signal between the modules. The partition boundary is divided by the dashed line, showing how the algorithm divides the high-coupling-degree module cluster into the same partition while ensuring that the critical path integrity is not damaged. The partitioning result in the figure obviously follows the principle of scale balancing, and the large-scale modules are appropriately divided and the small-scale modules are reasonably merged. The schematic diagram effectively verifies the three core principles of the dynamic partitioning algorithm: maintaining the continuity of the critical path, optimizing the coupling aggregation of the modules, and realizing the balance of the partition scale. The structure of the diagram provides an intuitive basis for understanding how the partitioning strategy balances the timing performance and computational efficiency.
[0111] S350, respectively performing comprehensive processing according to each partition divided out, obtaining a gate netlist corresponding to each partition respectively, and reconstructing a complete netlist of the target integrated circuit according to the gate netlists.
[0112] The technical scheme of the embodiment of the application forms an abstract syntax tree and clock parameter information according to the Verilog source code, the super-high-speed integrated circuit hardware description language VHDL source code and the constraint file corresponding to the target integrated circuit, and constructs a target design tree model, then extracts clock constraint information in the clock parameter information and identifies a violation path that violates the setup time or hold time constraint, further calculates the violation degree of the violation path and obtains a timing critical path, then divides the design tree model into a plurality of partitions that ensure the integrity of the critical path according to the design tree model structure timing critical path and a preset partition limit condition, and finally generates a gate netlist through partition synthesis processing and reconstructs a complete netlist, thereby solving the problem of long synthesis time and slow iteration cycle caused by the increase in the scale of the super-large-scale integrated circuit design, and achieving the beneficial effects of effectively reducing the synthesis time and ensuring that the synthesis result reaches the optimization target in terms of timing and area.
[0113] Embodiment four
[0114] Figure 7 The device for dynamically partitioning an integrated circuit provided in the fourth embodiment of the application comprises:
[0115] The target design tree model generation module 710 is configured to form an abstract syntax tree and clock parameter information according to the Verilog source code, the super-high-speed integrated circuit hardware description language VHDL source code and the constraint file corresponding to the target integrated circuit, and construct a target design tree model corresponding to the target integrated circuit according to the abstract syntax tree and the clock information;
[0116] The target design tree model takes a module as a vertex and a connection line between corresponding ports in two modules as an edge, and the edge contains an instantiation relationship between nodes, a plurality of signal transmission paths are formed between the modules through the corresponding ports, and a plurality of gate logic devices are contained in each module;
[0117] The dynamic partitioning module 720 is configured to identify each timing critical path included in the design tree model according to the clock parameter information, and divide the design tree model into a plurality of partitions according to the model structure of the design tree model, each timing critical path and a preset partition limit condition, wherein each timing critical path is completely included in one partition;
[0118] The netlist generation module 730 is configured to perform synthesis processing on each partition respectively to obtain a gate netlist corresponding to each partition respectively, and reconstruct a complete netlist of the target integrated circuit according to the gate netlists.
[0119] The technical scheme of the embodiment of the application forms an abstract syntax tree and clock parameter information according to the Verilog source code corresponding to the target integrated circuit, the super-high-speed integrated circuit hardware description language VHDL source code and the constraint file, and constructs a target design tree model corresponding to the target integrated circuit based on the abstract syntax tree and the clock parameter information, then identifies each timing critical path included in the design tree model according to the clock parameter information, and divides the design tree model into multiple partitions in combination with the model structure of the design tree model, each timing critical path and a preset partition restriction condition, and then performs synthesis processing on each partition to obtain a gate netlist corresponding to each partition, and reconstructs the complete netlist of the target integrated circuit according to each gate netlist, thereby solving the problems of long synthesis time, insufficient timing optimization and slow iteration cycle caused by the increase in the scale of the super-large-scale integrated circuit design, and achieving the beneficial effects of effectively reducing the synthesis time and ensuring that the synthesis result achieves the optimization target in terms of timing and area.
[0120] On the basis of the above embodiments, the target design tree model generation module 710 is specifically configured to:
[0121] initialize to construct an original design tree model corresponding to the target integrated circuit according to the abstract syntax tree and the clock information;
[0122] traverse each signal transmission path in the original design tree model, identify all target gate logic devices driven by constant logic values, and perform simplification processing on the downstream gate logic devices of each target gate logic device in the original design tree model according to the identification result, to obtain a simplified design tree model;
[0123] locate critical backtracking positions in the simplified design tree model, wherein the critical backtracking positions include the positions of the top-level output port and / or the register;
[0124] reverse traverse the simplified design tree model from the located critical backtracking positions as the starting points, to obtain all predecessor nodes matched with the located critical backtracking positions;
[0125] perform de-redundancy processing on the simplified design tree model according to the obtained all predecessor nodes, to obtain the target design tree model.
[0126] On the basis of the above embodiments, the dynamic partition module 720 is specifically configured to:
[0127] extract clock constraint information from the clock parameter information, and identify exception paths that violate the setup time and / or the hold time constraint in all signal transmission paths according to the clock constraint information;
[0128] calculate the exception degrees of the exception paths, and obtain timing critical paths in the exception paths according to the exception degrees of the exception paths.
[0129] Further, on the basis of the above embodiments, the dynamic partition module 720 can further include:
[0130] an assignment sub-module, configured to assign values to vertices and / or edges in the design tree model according to a model structure of the design tree model;
[0131] a partition sub-module, configured to partition the design tree model into a plurality of partitions according to the assignment results of the design tree model, the timing critical paths, and preset partition restriction conditions;
[0132] wherein the preset partition restriction conditions include a constraint condition that a timing critical path needs to be completely included in one partition, and at least one constraint condition that is adapted to the assignment content of the vertices and / or edges.
[0133] On the basis of the above embodiments, the assignment sub-module is specifically configured to:
[0134] calculate a module size value corresponding to each module according to the number of gate logic devices included in each module in the design tree model;
[0135] obtain the connection signal number and the fan-in and fan-out value of each port in each module according to the model structure of the design tree model;
[0136] calculate the port coupling degree of each port in each module according to the module size value of each module and the connection signal number and the fan-in and fan-out value of each port in each module;
[0137] assign values to the vertices in the design tree model according to the module size value, and assign values to the edges in the design tree model according to the port coupling degree of each port;
[0138] Correspondingly, the preset partition restriction conditions further include a constraint condition on the maximum module size value included in each partition, and a constraint condition on the maximum port coupling degree included in each partition.
[0139] On the basis of the above embodiments, the netlist generation module 730 is specifically configured to:
[0140] generate a boundary constraint file corresponding to each partition according to the inclusion of each partition to the timing critical path, and generate an optimization strategy corresponding to each partition;
[0141] perform comprehensive processing on each partition through a plurality of parallel threads according to the boundary constraint file and the optimization strategy of each partition, to obtain a gate netlist corresponding to each partition.
[0142] On the basis of the above embodiments, the netlist generation module 730 is specifically configured to:
[0143] According to the partition scheme generated by dynamic partition, the design files and corresponding boundary constraint files of each partition are loaded in parallel on the multi-core server to simultaneously run multiple synthesis processes;
[0144] After all the partition synthesis processes are completed, the generated gate-level netlists are integrated, the integrated complete netlist is subjected to result consistency check, and finally the top-level netlist conforming to the design specification is reconstructed and the complete integrated circuit design result is generated.
[0145] The dynamic partition device of the integrated circuit provided in the embodiment of the application has the functions and advantages of the dynamic partition method of the integrated circuit provided in any embodiment of the application.
[0146] In the technical scheme of the disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information comply with relevant laws and regulations and do not violate public order and good customs.
[0147] Embodiment five
[0148] Figure 8 A structural schematic diagram of an electronic device 10 that can be used to implement embodiments of the application is shown. The electronic device is intended to represent various forms of digital computers, such as laptops, desktops, tablets, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular telephones, smartphones, wearable devices (e.g., headsets, glasses, watches, etc.), and other similar computing devices. The components shown here, their connections and relationships, and their functions, are meant to be examples only, and are not meant to limit implementations of the applications described and / or claimed in this document.
[0149] As Figure 8 As shown, the electronic device 10 includes at least one processor 11, and a memory, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., which is communicatively connected to the at least one processor 11, wherein the memory stores a computer program that can be executed by the at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.
[0150] A plurality of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a magnetic disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network, such as the Internet, and / or various telecommunication networks.
[0151] The processor 11 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 performs various methods and processes described above, such as performing a dynamic partitioning method of an integrated circuit as described in any one of the embodiments of the present application, i.e.:
[0152] According to the Verilog source code, the very high speed integrated circuit hardware description language VHDL source code and the constraint file corresponding to the target integrated circuit, an abstract syntax tree and clock parameter information are formed, and a target design tree model corresponding to the target integrated circuit is constructed according to the abstract syntax tree and the clock information;
[0153] The target design tree model has modules as vertices and connections between corresponding ports in two modules as edges, and a plurality of signal transmission paths are formed between the modules through the corresponding ports. Each module includes a plurality of gate logic devices.
[0154] According to the clock parameter information, each timing critical path included in the design tree model is identified, and the design tree model is divided into a plurality of partitions according to the model structure of the design tree model, the timing critical paths and a preset partitioning restriction condition. One timing critical path is completely included in one partition.
[0155] Synthesis processing is performed on each partition respectively to obtain a gate netlist corresponding to each partition, and a complete netlist of the target integrated circuit is reconstructed according to the gate netlists.
[0156] In some embodiments, the dynamic partitioning method of an integrated circuit as described in any of the embodiments of the application can be implemented as a computer program tangibly embodied in a computer readable storage medium, e.g., storage unit 18. In some embodiments, parts or all of the computer program can be loaded and / or installed onto electronic device 10 via, e.g., ROM 12 and / or communication unit 19. When the computer program is loaded onto RAM 13 and executed by processor 11, one or more steps of the dynamic partitioning method of an integrated circuit as described in any of the embodiments of the application can be performed. Alternatively, in other embodiments, processor 11 can be configured to perform the dynamic partitioning method of an integrated circuit as described in any of the embodiments of the application by way of other suitable means, e.g., by way of firmware.
[0157] Various implementations of the systems and techniques described above can be realized in digital electronic circuitry, integrated circuitry, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on a chip (SOC), a programmable logic device (PLD), a computer hardware, firmware, software, and / or combinations thereof. These various implementations can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.
[0158] Computer programs used to implement the processes of the application can be written in any combination of one or more programming languages. These computer programs can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the computer program, when executed, implements the functions / acts specified in the flowcharts and / or block diagrams. The computer program can be executed entirely on a machine, partially on a machine and partially on a remote machine or entirely on a remote machine or server.
[0159] In the context of the present application, a computer-readable storage medium can be a tangible medium that can contain or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. A computer-readable storage medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium can be a machine-readable signal medium. More specific examples of a machine-readable storage medium will include one or more lines of a program of instructions in a transitory signal, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
[0160] To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the electronic device. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.
[0161] The systems and techniques described here can be implemented in a computing system that includes a back end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front end component (e.g., a user computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.
[0162] The computing system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system, to solve the defects of large management difficulty and weak business scalability in traditional physical host and VPS service.
[0163] It should be understood that the various forms of flow shown above can be reordered, added to, or have steps deleted. For example, the steps described in the present application can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions of the present application can be achieved, which are not limited herein.
[0164] The above detailed description does not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application shall be included in the protection scope of the present application.
Claims
1. A dynamic partitioning method for integrated circuits, characterized in that, The method includes: Based on the Verilog source code, VHDL source code and constraint file corresponding to the target integrated circuit, an abstract syntax tree and clock parameter information are formed, and a target design tree model corresponding to the target integrated circuit is constructed based on the abstract syntax tree and clock information. The target design tree model is composed of modules as vertices and the lines connecting corresponding ports in each module as edges. The edges contain the instantiation relationships between nodes. Multiple signal transmission paths are formed between modules through corresponding ports. Each module contains multiple gate logic devices. Based on the clock parameter information, identify each timing critical path included in the design tree model, and divide the design tree model into multiple partitions according to the model structure, each timing critical path and the preset partition constraints. In this case, a timing critical path completely falls into one partition. Synthesis is performed on each partition to obtain a gate netlist corresponding to each partition. Based on the gate netlists, the complete netlist of the target integrated circuit is reconstructed.
2. The method according to claim 1, characterized in that, Based on the abstract syntax tree and clock information, construct the target design tree model corresponding to the target integrated circuit, including: Based on the abstract syntax tree and clock information, initialize and construct the original design tree model corresponding to the target integrated circuit; Traverse each signal transmission path in the original design tree model, identify all target gate logic devices driven by constant logic values, and simplify the downstream gate logic devices of each target gate logic device in the original design tree model based on the identification results to obtain the simplified design tree model. Locate the key backtracking locations in the simplified design tree model. The key backtracking locations include: the location of the top-level output port and / or register. Starting from the key backtracking position, a simplified tree model is designed by traversing backwards to obtain all predecessor nodes that match each key backtracking position. Based on all the obtained predecessor nodes, the simplified design tree model is deredundant to obtain the target design tree model.
3. The method according to claim 1, characterized in that, Based on the clock parameter information, identify the timing critical paths included in the design tree model, including: Extract clock constraint information from clock parameter information, and identify violation paths that violate setup time and / or hold time constraints in all signal transmission paths based on the clock constraint information. Calculate the violation severity of each violation path, and based on the violation severity of each violation path, obtain the time-critical path from each violation path.
4. The method according to claim 3, characterized in that, Based on the design tree model's structure, critical paths at each time stage, and preset partition constraints, the design tree model is divided into multiple partitions, including: Assign values to the vertices and / or edges in the design tree model based on its structure. Based on the assignment results of the design tree model, the critical paths of each time series and the preset partition constraints, the design tree model is divided into multiple partitions; The preset partitioning constraints include a constraint that a time-critical path must fall entirely within a partition, and at least one constraint that is compatible with the assignment of vertices and / or edges.
5. The method according to claim 4, characterized in that, Based on the design tree model's structure, assign values to the vertices and / or edges in the design tree model, including: Calculate the module size value corresponding to each module based on the number of gate logic devices included in each module in the design tree model; Based on the design tree model structure, obtain the number of connection signals and fan-in / fan-out values for each port in each module; Based on the module size value of each module, as well as the number of connected signals and fan-in and fan-out values of each port in each module, calculate the port coupling degree of each port in each module; Based on the module size value, assign values to each vertex in the design tree model, and based on the port coupling degree of each port, assign values to each edge in the design tree model; Accordingly, the preset partitioning constraints further include: constraints on the maximum module size value contained in each partition, and constraints on the maximum port coupling degree contained in each partition.
6. The method according to any one of claims 1-5, characterized in that, Perform synthesis processing on each partition to obtain a gate netlist corresponding to each partition, including: Based on the inclusion of each partition in the time-critical path, generate boundary constraint files corresponding to each partition, and generate optimization strategies corresponding to each partition. Based on the boundary constraint file and optimization strategy for each partition, synthesis processing is performed on each partition separately through multiple parallel threads to obtain the gate netlist corresponding to each partition.
7. The method according to any one of claims 1-5, characterized in that, Based on the netlists of each gate, the complete netlist of the target integrated circuit is reconstructed, including: Based on the partitioning scheme generated by dynamic partitioning, the design files and corresponding boundary constraint files of each partition are loaded in parallel on a multi-core server to run multiple synthesis processes simultaneously. After all partition synthesis processes are completed, the generated gate-level netlists are integrated, and the consistency of the integrated netlist is checked. Finally, the top-level netlist that conforms to the design specifications is reconstructed, and the complete integrated circuit design results are generated.
8. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the dynamic partitioning method of the integrated circuit according to any one of claims 1-7.
9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed by a processor, implement the dynamic partitioning method of the integrated circuit according to any one of claims 1-7.
10. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the dynamic partitioning method for an integrated circuit according to any one of claims 1-7.