Chip verification method and device, electronic equipment, storage medium and program

Abstract

The embodiment of the invention discloses a chip verification method and device, electronic equipment, a storage medium and a program.The method comprises the steps that current configuration text information of a current verification chip is extracted, and a reconstruction configuration text file of the current verification chip is generated according to the current configuration text information; comparing and checking the original configuration text file of the current verification chip according to the reconstructed configuration text file of the current verification chip; and determining a current verification result of the current verification chip according to a comparison verification result of the reconstructed configuration text file and the original configuration text file. According to the technical scheme provided by the embodiment of the invention, the chip verification efficiency and accuracy can be improved.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a chip verification method, apparatus, electronic device, storage medium and program. Background Technology

[0002] As the complexity of integrated circuits continues to increase, the number of registers integrated into chips is growing exponentially. These registers control various functions, modes, and operating states of the chip, and their correct configuration is fundamental to the proper functioning of the chip. In modern chip design flows, chip verification is a critical step in ensuring the correctness of chip functionality, accounting for more than 70% of the entire design cycle. Among these steps, register model verification is of paramount importance. Verification engineers need to create numerous test sequences, using driver programs within the verification methodology to frequently read and write registers to test their reset values, read / write permissions, field relationships, and functional correctness.

[0003] Register configuration information is typically passed between chip verification teams in the form of text files, and is used by hardware, software, and verification engineers in different verification processes. One of the core tasks of verification engineers is to transform this text-based configuration data into test sequences with specific timing and protocols that can be run directly on the chip verification platform.

[0004] In the process of developing this invention, the inventors discovered the following shortcomings in the existing technology: In the chip verification process, chip configuration typically requires engineers to manually maintain multiple forms of files. Any modification to configuration information necessitates the synchronous updating of other configuration files. Engineers must manually ensure that the generated test sequences are updated synchronously, a process highly susceptible to omissions and human error. This can lead to inconsistencies between the configuration used for testing and the latest specifications, resulting in verification vulnerabilities that are difficult to debug. Furthermore, existing chip verification processes primarily generate the required test sequences based on configuration files, essentially implementing a one-way processing method from configuration text to test sequences. When the test sequence dynamically modifies register values ​​during simulation, or when it is necessary to analyze the original configuration corresponding to a failed test case, verification engineers find it difficult to quickly trace back to the original configuration intent from the complex test sequences, making the debugging process like a "black box" and resulting in extremely low verification efficiency. Summary of the Invention

[0005] This invention provides a chip verification method, apparatus, electronic device, storage medium, and program, which can improve the efficiency and accuracy of chip verification.

[0006] According to one aspect of the present invention, a chip verification method is provided, comprising:

[0007] Extract the current configuration text information of the current verification chip, and generate the reconstruction configuration text file of the current verification chip based on the current configuration text information;

[0008] The original configuration text file of the current verification chip is compared and verified based on the reconstructed configuration text file of the current verification chip.

[0009] The current verification result of the current verification chip is determined based on the comparison and verification results between the reconstructed configuration text file and the original configuration text file.

[0010] According to another aspect of the present invention, a chip verification apparatus is provided, comprising:

[0011] The configuration text information extraction module is used to extract the current configuration text information of the current verification chip and generate the reconstruction configuration text file of the current verification chip based on the current configuration text information.

[0012] The configuration text comparison and verification module is used to compare and verify the original configuration text file of the current verification chip with the reconstructed configuration text file of the current verification chip.

[0013] The chip verification result determination module is used to determine the current verification result of the current verification chip based on the comparison and verification result between the reconstructed configuration text file and the original configuration text file.

[0014] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0015] At least one processor; and

[0016] A memory communicatively connected to the at least one processor; wherein,

[0017] The memory stores a computer program that can be executed by the at least one processor, which enables the at least one processor to perform the chip verification method according to any embodiment of the present invention.

[0018] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the chip verification method according to any embodiment of the present invention.

[0019] According to another aspect of the present invention, a computer program product is also provided, comprising a computer program that, when executed by a processor, implements the chip verification method described in any embodiment of the present invention.

[0020] This invention extracts the current configuration text information of the current verification chip and generates a reconstructed configuration text file for the current verification chip based on the current configuration text information. Then, it compares and verifies the original configuration text file of the current verification chip based on the reconstructed configuration text file. The current verification result of the current verification chip is determined based on the comparison and verification results of the reconstructed configuration text file and the original configuration text file. This solves the problem that existing chip verification methods cannot trace back to verify in reverse, resulting in low efficiency, and can improve the efficiency and accuracy of chip verification.

[0021] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a flowchart of a chip verification method provided in Embodiment 1 of the present invention;

[0024] Figure 2 This is a flowchart of a chip verification method provided in Embodiment 2 of the present invention;

[0025] Figure 3 This is a schematic diagram of chip verification using a core processing engine, provided in Embodiment 2 of the present invention.

[0026] Figure 4 This is a schematic diagram of a chip verification device provided in Embodiment 3 of the present invention;

[0027] Figure 5 This is a schematic diagram of the structure of an electronic device provided in Embodiment 4 of the present invention. Detailed Implementation

[0028] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0029] It should be noted that the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product or device.

[0030] Example 1

[0031] Figure 1 This is a flowchart of a chip verification method provided in Embodiment 1 of the present invention. This embodiment is applicable to situations where configuration text information is extracted from the chip in real time during the verification process, and the extracted configuration text information is used to verify the chip currently being verified. This method can be executed by a chip verification device, which can be implemented in software and / or hardware, and is generally integrated into an electronic device. This electronic device can be a terminal device or a server device, as long as it can execute the chip verification method. The embodiments of the present invention do not limit the specific device type of the electronic device. Accordingly, as... Figure 1 As shown, the method includes the following operations:

[0032] S110. Extract the current configuration text information of the current verification chip, and generate the reconstruction configuration text file of the current verification chip based on the current configuration text information.

[0033] The current verification chip can be any type of chip requiring functional verification. For example, the current verification chip can include, but is not limited to, CPUs (Central Processing Units), GPUs (Graphics Processing Units), TPUs (Tensor Processing Units), NPUs (Neural Processing Units), FPGAs (Field Programmable Gate Arrays), and ASICs (Application Specific Integrated Circuits), as long as there is a functional verification requirement. This embodiment of the invention does not limit the specific chip type of the current verification chip. The current configuration text information can be the configuration text information extracted in real time by the current verification chip during the verification process. The reconstructed configuration text file can be the configuration text file obtained by reconstructing and summarizing the configuration text information extracted in real time by the current verification chip during the verification process.

[0034] In this embodiment of the invention, a chip requiring functional verification can be used as the current verification chip, and its functionality is verified using a pre-generated test sequence. During the verification process of the current verification chip, its configuration text information can be extracted in real time, and this extracted configuration text information can be organized, reconstructed, and summarized to generate a reconstructed configuration text file matching the current verification chip. Optionally, the current configuration text information of the current verification chip can be extracted from each test sequence used to verify the current verification chip. Since the reconstructed configuration text file is dynamically generated based on the configuration text information extracted in real time during the verification process, it can reflect the configuration information used by the current verification chip during the verification process in real time, achieving reverse tracing from chip test results to configuration intent.

[0035] S120. The original configuration text file of the current verification chip is compared and verified according to the reconstructed configuration text file of the current verification chip.

[0036] The original configuration text file can be the initial configuration text file of the current verification chip, which can be used as the baseline configuration information of the current verification chip.

[0037] Correspondingly, after extracting and generating the reconfiguration configuration text file from the current verification chip in real time, the original configuration text file of the current verification chip can be obtained, and the text information of the reconfiguration configuration text file and the original configuration text file can be compared and verified. During the configuration text file comparison and verification process, the bidirectional correlation between a certain configuration and the test sequence can be clearly obtained, that is, the correlation between the test sequence and the corresponding part of the configuration information in the reconfiguration configuration text file, and the correlation between the test sequence and the corresponding part of the configuration information in the original configuration text file. This bidirectional traceability capability greatly reduces the difficulty and time cost of debugging.

[0038] S130. Determine the current verification result of the current verification chip based on the comparison and verification results of the reconstructed configuration text file and the original configuration text file.

[0039] Specifically, the original configuration text file of the current verification chip can be used as a benchmark to compare and verify the reconstructed configuration text file, thus eliminating any problems in the reconstructed configuration text file. Therefore, when testing the current verification chip using test sequences fails, the comparison and verification results between the reconstructed and original configuration text files can quickly pinpoint which test sequences in the verification process are using problematic or incorrect configuration text information, thereby improving the efficiency of anomaly localization and verification testing. Furthermore, the abnormal test sequences can be updated to restore their normal testing functionality, preventing anomalies in chip verification testing and thus improving the accuracy of chip verification.

[0040] Therefore, the chip verification method provided in this invention possesses reverse parsing capabilities for chip configuration information. It can extract configuration information from the test sequence of a chip in the verification process and reconstruct the configuration text, thereby establishing a reverse tracing channel from design intent to chip verification execution. This fundamentally eliminates verification vulnerabilities caused by configuration inconsistencies. Furthermore, the comparison and verification process between the reconstructed configuration text file and the original configuration text file of the currently verified chip provides a global verification perspective, greatly improving the understandability and debugging efficiency of the chip verification process. It can also instantly pinpoint failed test operations to the original configuration or associate the configuration with all relevant tests, reducing manual intervention in the chip verification process and lowering the labor costs and human error risks associated with chip verification.

[0041] This invention extracts the current configuration text information of the current verification chip and generates a reconstructed configuration text file for the current verification chip based on the current configuration text information. Then, it compares and verifies the original configuration text file of the current verification chip based on the reconstructed configuration text file. The current verification result of the current verification chip is determined based on the comparison and verification results of the reconstructed configuration text file and the original configuration text file. This solves the problem that existing chip verification methods cannot trace back to verify in reverse, resulting in low efficiency, and can improve the efficiency and accuracy of chip verification.

[0042] Example 2

[0043] Figure 2 This is a flowchart of a chip verification method provided in Embodiment 2 of the present invention. This embodiment is based on the above embodiment and is further specified. In this embodiment, various specific optional implementation methods are given, including extracting the current configuration text information of the current verification chip, generating the reconstructed configuration text file of the current verification chip, comparing and verifying the current verification chip, generating a test sequence based on the initial configuration text information of the current verification chip, and visually displaying the test information of the current verification chip. Correspondingly, as... Figure 2As shown, the method in this embodiment may include:

[0044] S210. Obtain the current test sequence of the current verification chip.

[0045] The current test sequence can be the test sequence currently used to verify the current verification chip.

[0046] S220. Extract the register operation information of the current verification chip based on the configuration information in the current test sequence of the current verification chip, and use it as the current configuration text information of the current verification chip.

[0047] Specifically, the existing test sequence of the current verification chip can be reverse-analyzed to obtain the configuration information in the current test sequence. Furthermore, based on the configuration information in the current test sequence, the address, data, and read / write commands of the current verification chip can be extracted as the current configuration text information of the current verification chip.

[0048] S230. Determine each local configuration text information in the current configuration text information and the test sequence corresponding to each local configuration text information.

[0049] The local configuration text information can be a portion of the current configuration text information.

[0050] After extracting the current configuration text information of the current verification chip, the configuration text information corresponding to each test sequence can be determined based on the test sequences. The configuration text information corresponding to each test sequence can be considered as a partial configuration text information. The partial configuration text information of each test sequence constitutes the complete current configuration text information.

[0051] S240. Adjust and splice the local configuration text information according to the test order of the test sequence corresponding to each local configuration text information to obtain the reconstruction configuration text file of the current verification chip.

[0052] In the chip verification process, each test sequence needs to verify the chip according to its corresponding test order. Therefore, for the current chip being verified, the order in which each test sequence is performed can be determined. Then, based on the test order of the test sequences corresponding to each local configuration text information, the local configuration text information is adjusted and concatenated to ensure that the sorting order of the local configuration text information matches the test order of each test sequence. This reconstructs and summarizes the information to obtain the reconstructed configuration text file for the current chip being verified. The advantage of this setup is that it ensures that the sorting order of the local configuration text information in the reconstructed configuration text file matches the test order of each test sequence. This improves the rapid joint processing of the bidirectional correlation between the original configuration information, test sequences, and the reconstructed configuration text file, and also increases the speed of troubleshooting abnormal test sequences.

[0053] S250. Calculate the similarity between each local configuration text information in the reconstructed configuration text file and each local configuration text information in the original configuration text file.

[0054] S260. Determine local configuration text information pairs based on the similarity between each set of local configuration text information pairs, and compare and verify the text information of each set of local configuration text information pairs.

[0055] The local configuration text information pair may include a local configuration text information in the reconstructed configuration text file and a local configuration text information in the original configuration text file, and the two local configuration text information are highly similar or identical.

[0056] Accordingly, during the comparison and verification process between the reconstructed configuration text file and the original configuration text file of the current verification chip, the similarity between each piece of local configuration text information in the reconstructed configuration text file and each piece of local configuration text information in the original configuration text file can be calculated based on the local configuration text information. Two types of local configuration text information with similarity exceeding a certain threshold are then configured as a pair. It can be understood that the two types of local configuration text information included in a pair have a corresponding relationship; that is, the test sequence corresponding to the locally extracted local configuration text information in a pair is constructed based on the information of a portion of the original configuration text file corresponding to that pair.

[0057] S270. Determine the current verification result of the current verification chip based on the comparison and verification results of the reconstructed configuration text file and the original configuration text file.

[0058] After pairing all the local configuration text information in the reconstructed configuration text file with the local configuration text information in the original configuration text file, the text information of the two sets of local configuration text information can be compared and verified for each pair. If the text information of the two sets of local configuration text information is exactly the same, it indicates that the test sequence corresponding to this set of local configuration text information is correct and can be used to test and verify the chip function normally. If the text information of the two sets of local configuration text information is different, it indicates that the test sequence corresponding to this set of local configuration text information is abnormal, and the verification of the chip by this test sequence has failed. After locking the abnormal test sequence, it can be debugged and updated according to the local configuration text information in the original configuration text file corresponding to the abnormal test sequence to restore its normal verification and testing function.

[0059] In an optional embodiment of the present invention, the chip verification method may further include: reading the original configuration text file of the current verification chip and extracting target key configuration information from the original configuration text file; filling a target sequence template according to the target key configuration information to automatically generate a test sequence for the current verification chip.

[0060] The target key configuration information can be configuration information in the original configuration text file that can be used to generate test sequences. The target sequence template can be a pre-configured template that can generate test sequences.

[0061] Figure 3 This is a schematic diagram illustrating chip verification using a core processing engine, as provided in Embodiment 2 of the present invention. In a specific example, such as... Figure 3As shown, the chip verification method provided in this embodiment of the invention can be executed by a core processing engine including a bidirectional conversion engine. Specifically, the bidirectional conversion engine can communicate with a verification platform that uses UVM (Universal Verification Methodology) to verify the current chip, and send a configuration information acquisition request to the verification platform to obtain the original configuration text file of the current chip, and read the address, data, and read / write type included in the register configuration text file of the original configuration text file as target key configuration information. Optionally, the configuration text file can be in txt (Plain Text) format. Further, a matching target sequence template is determined for the test sequence to be generated. It is understood that different test sequences may have different corresponding target sequence templates. Pre-configuring the target sequence templates corresponding to each test sequence can improve the generation efficiency of the test sequence. Further, by filling the target sequence template with the target key configuration information extracted from the verification platform, the test sequence of the current chip can be automatically generated, i.e. Figure 3 The seq is shown.

[0062] At the same time, such as Figure 3 As shown, the bidirectional conversion engine also possesses reverse parsing capabilities, enabling it to extract register operations from test sequences and reconstruct configuration text, thus establishing a reverse tracing channel from design intent to verification execution. Therefore, the bidirectional correlation capability of the bidirectional conversion engine allows engineers to quickly locate the configuration intent from a single line of code during debugging, or to view all related test operations from a single configuration, thereby significantly improving the progress of chip verification and debugging.

[0063] In an optional embodiment of the present invention, the chip verification method may further include: obtaining the associated configuration text information and test sequence of the current verification chip; generating a timing diagram based on the bidirectional correspondence between the associated configuration text information and the test sequence and displaying it.

[0064] The associated configuration text information may include the original configuration text file and the reconstructed configuration text file of the current verification chip.

[0065] For example, such as Figure 3As shown, the core processing engine can also include a visualization generator to automatically generate an interactive visualization webpage that uniformly presents the register configuration of the current verification chip, the corresponding test sequences, and their association with associated configuration text information. Specifically, the visualization generator can be based on a unified data model or data structure, organizing the relationships between the obtained original configuration text file, reconstructed configuration text file, and related test sequences of the current verification chip. The automatically generated interactive visualization webpage displays the register list of the current verification chip and can clearly show the bidirectional relationship between each configuration and its corresponding test sequence in the form of timing diagrams, etc.

[0066] By establishing a visual relationship between the chip's configuration text information and test sequences—two distinctly different representations—in a unified, intuitive, and interactive web interface, it facilitates global observation and analysis of the entire chip verification process. This further improves chip verification and debugging efficiency, team collaboration efficiency, and reduces the risk of human error.

[0067] The aforementioned technical solution provides a unified, intuitive, and real-time chip verification information sharing platform that is compatible with different tools and documents used by hardware engineers, software engineers, and verification engineers to understand the register configurations in the chip. The chip verification method provided by this platform can automatically convert between chip configuration text and test sequences bidirectionally, breaking down information barriers and ensuring data consistency and real-time compatibility between configuration text, test sequences, and visualization views throughout the entire chip verification process. The chip verification method provided by this invention completely solves the industry pain points of traditional chip verification processes, such as data inconsistency, low debugging efficiency, and lack of visualization and traceability methods caused by the separation of text configuration and test sequences. It achieves automated, consistent, and closed-loop management of the chip verification process, improving the efficiency and accuracy of chip verification.

[0068] It should be noted that all information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for display, data used for analysis, etc.) involved in this disclosure are information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data comply with the relevant laws, regulations and standards of the relevant regions.

[0069] It should be noted that any arrangement or combination of the technical features in the above embodiments also falls within the protection scope of this invention.

[0070] Example 3

[0071] Figure 4 This is a schematic diagram of a chip verification device provided in Embodiment 3 of the present invention, as shown below. Figure 4As shown, the device includes: a configuration text information extraction module 410, a configuration text comparison and verification module 420, and a chip verification result determination module 430, wherein:

[0072] The configuration text information extraction module 410 is used to extract the current configuration text information of the current verification chip and generate the reconstruction configuration text file of the current verification chip based on the current configuration text information.

[0073] The configuration text comparison and verification module 420 is used to compare and verify the original configuration text file of the current verification chip based on the reconstructed configuration text file of the current verification chip.

[0074] The chip verification result determination module 430 is used to determine the current verification result of the current verification chip based on the comparison and verification result of the reconstructed configuration text file and the original configuration text file.

[0075] This invention extracts the current configuration text information of the current verification chip and generates a reconstructed configuration text file for the current verification chip based on the current configuration text information. Then, it compares and verifies the original configuration text file of the current verification chip based on the reconstructed configuration text file. The current verification result of the current verification chip is determined based on the comparison and verification results of the reconstructed configuration text file and the original configuration text file. This solves the problem that existing chip verification methods cannot trace back to verify in reverse, resulting in low efficiency, and can improve the efficiency and accuracy of chip verification.

[0076] Optionally, the configuration text information extraction module 410 is further configured to: obtain the current test sequence of the current verification chip; extract the register operation information of the current verification chip according to the configuration information in the current test sequence of the current verification chip, and use it as the current configuration text information of the current verification chip.

[0077] Optionally, the configuration text information extraction module 410 is further configured to: determine each local configuration text information in the current configuration text information and the test sequence corresponding to each local configuration text information; adjust and splice each local configuration text information according to the test order of the test sequence corresponding to each local configuration text information to obtain the reconstructed configuration text file of the current verification chip.

[0078] Optionally, the configuration text comparison and verification module 420 is further configured to: calculate the similarity between each local configuration text information in the reconstructed configuration text file and each local configuration text information in the original configuration text file; determine local configuration text information pairs based on the similarity between each local configuration text information; and perform comparison and verification on the text information of each pair of local configuration text information pairs.

[0079] Optionally, the above apparatus further includes a test sequence generation module, used to read the original configuration text file of the current verification chip and extract the target key configuration information from the original configuration text file; fill the target sequence template according to the target key configuration information to automatically generate the test sequence of the current verification chip.

[0080] Optionally, the above device further includes an information display module, used to acquire the associated configuration text information and test sequence of the current verification chip; generate a timing diagram based on the bidirectional correspondence between the associated configuration text information and the test sequence, and display it.

[0081] The chip verification apparatus described above can execute the chip verification method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects for executing the method. Technical details not described in detail in this embodiment can be found in the chip verification method provided in any embodiment of the present invention.

[0082] Since the chip verification device described above is capable of executing the chip verification method in the embodiments of the present invention, those skilled in the art can understand the specific implementation and various variations of the chip verification device in this embodiment based on the chip verification method described in the embodiments of the present invention. Therefore, how the chip verification device implements the chip verification method in the embodiments of the present invention will not be described in detail here. Any device used by those skilled in the art to implement the chip verification method in the embodiments of the present invention falls within the scope of protection of this application.

[0083] Example 4

[0084] Figure 5 A schematic diagram of an electronic device 10, which can be used to implement embodiments of the present invention, is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0085] like Figure 5As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0086] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0087] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as chip verification methods.

[0088] Optionally, the chip verification method may include: extracting the current configuration text information of the current verification chip, and generating a reconfiguration configuration text file of the current verification chip based on the current configuration text information; comparing and verifying the original configuration text file of the current verification chip based on the reconfiguration configuration text file of the current verification chip; and determining the current verification result of the current verification chip based on the comparison and verification result of the reconfiguration configuration text file and the original configuration text file.

[0089] In some embodiments, the chip verification method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or mounted on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the chip verification method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform the chip verification method by any other suitable means (e.g., by means of firmware).

[0090] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0091] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0092] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0093] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0094] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0095] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0096] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0097] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A chip verification method characterized by, The method comprises the following steps: extracting current configuration text information of a current verification chip, and generating a reconstructed configuration text file of the current verification chip according to the current configuration text information; comparing and verifying an original configuration text file of the current verification chip according to the reconstructed configuration text file of the current verification chip; determining a current verification result of the current verification chip according to a comparison and verification result of the reconstructed configuration text file and the original configuration text file.

2. The method of claim 1, wherein, The step of extracting the current configuration text information of the current verification chip comprises the following steps: obtaining a current test sequence of the current verification chip; extracting register operation information of the current verification chip as the current configuration text information of the current verification chip according to configuration information in the current test sequence of the current verification chip.

3. The method of claim 1, wherein, The step of generating the reconstructed configuration text file of the current verification chip according to the current configuration text information comprises the following steps: determining each local configuration text information in the current configuration text information and a test sequence corresponding to each local configuration text information; adjusting and splicing each local configuration text information according to a test order of the test sequence corresponding to each local configuration text information to obtain the reconstructed configuration text file of the current verification chip.

4. The method of claim 1, wherein, The step of comparing and verifying the original configuration text file of the current verification chip according to the reconstructed configuration text file of the current verification chip comprises the following steps: calculating a similarity between each local configuration text information in the reconstructed configuration text file and each local configuration text information in the original configuration text file; determining a local configuration text information pair according to the similarity between each local configuration text information; comparing and verifying text information of each local configuration text information pair.

5. The method of claim 1, wherein, The method further comprises the following steps: reading an original configuration text file of the current verification chip, and extracting target key configuration information in the original configuration text file; filling a target sequence template according to the target key configuration information to automatically generate a test sequence of the current verification chip.

6. The method of claim 1, wherein, The method further comprises the following steps: obtaining associated configuration text information and a test sequence of the current verification chip; generating and displaying a timing diagram according to a bidirectional correspondence between the associated configuration text information and the test sequence.

7. A chip verification apparatus characterized by comprising: The method comprises the following steps: a configuration text information extraction module is configured to extract current configuration text information of a current verification chip, and generate a reconstructed configuration text file of the current verification chip according to the current configuration text information; a configuration text comparison and verification module is configured to compare and verify an original configuration text file of the current verification chip according to the reconstructed configuration text file of the current verification chip; a chip verification result determination module is configured to determine a current verification result of the current verification chip according to a comparison and verification result of the reconstructed configuration text file and the original configuration text file.

8. An electronic device, comprising: The electronic device comprises: at least one processor; and a memory connected in communication with the at least one processor; wherein The memory stores a computer program executed by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to perform the chip verification method in any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer instructions for enabling a processor to implement the chip verification method in any one of claims 1-6 when executed.

10. A computer program product, characterised in that, The computer program / instructions are executed by a processor to implement the chip verification method in any one of claims 1-6.

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