Chip function module operation path verification method and system based on graph model

Abstract

The invention discloses a chip function module running path verification method and system based on a graph model, and the method comprises the steps: abstracting basic units in a function module into nodes based on the design structure of the function module in a chip, and constructing a directed network graph based on the logic relation or connection relation between the basic units; determining a starting node and a termination node in the directed network graph, traversing the directed network graph to identify all possible paths from the starting node to the termination node, and storing the obtained paths in a preset data structure; and based on the stored path, simulating the operation behavior of the function module, driving the basic unit to execute corresponding logic operation or transmission operation according to the path sequence, and detecting whether the operation behavior accords with a preset design specification or not. According to the verification method, directed network graph construction, path traversal and behavior simulation are combined, and efficient and accurate verification of the chip function module path is achieved.

Description

Technical Field

[0001] This invention relates to the field of chip front-end design verification technology, and in particular to a method and system for verifying the running path of chip functional modules based on a graph model. Background Technology

[0002] In modern chip design, especially during the front-end design verification phase, engineers need to ensure that the chip's functionality and performance meet design specifications and perform chip product spec (system performance evaluation test). Chips often contain complex functional modules, such as state machines (Finite State Machines, FSMs) or routing paths in network-on-chips (NOCs). A state machine is a logical structure used to control the transitions between different states of the chip, such as from a "standby" state to a "running" state, and then to a "shutdown" state. NOC routing, on the other hand, involves the path planning for data transmission between a large number of nodes within the chip.

[0003] To verify the correctness of these state transitions or routing paths, engineers typically use EDA (Electronic Design Automation) tools to simulate and check whether the chip design meets expectations. Specifically, the verification process requires traversing all possible state transition paths in the state machine, or all possible routing paths in the NOC, ensuring that each path is error-free. This traversal verification is crucial because if any path contains errors, the chip may malfunction during actual operation, or even cause the entire system to fail.

[0004] However, in existing technologies, this verification process often relies on manual operation. Engineers need to manually analyze state machine transition diagrams or routing diagrams, summarize all possible paths, and then check them one by one.

[0005] While this method is feasible, manually summarizing state transition paths or routing paths is an extremely tedious task, especially in complex chip designs. State machines may have dozens or even hundreds of states, and each state may have multiple transition relationships, forming a large number of paths. Manually sorting out these paths one by one requires a significant amount of time and effort. As chip complexity increases, this workload grows exponentially.

[0006] Furthermore, due to the sheer number and complexity of the paths, it's easy to overlook some during manual summarization. This is especially true for hidden or infrequently used jump paths, which engineers might not notice during analysis. If certain paths are not verified, triggering them during actual chip operation could lead to unpredictable errors, severely impacting the chip's reliability and stability. Summary of the Invention

[0007] The purpose of this invention is to provide a method and system for verifying the running path of chip functional modules based on a graph model, which can automatically extract and verify the path, thereby improving verification efficiency and reducing the risk of missed tests.

[0008] To achieve the above objectives, this invention provides a method for verifying the operational path of a chip functional module based on a graph model. The method includes: based on the design structure of the functional modules in the chip, abstracting the basic units in the functional modules as nodes, and constructing a directed network graph based on the logical or connection relationships between the basic units; determining a start node and an end node in the directed network graph, traversing the directed network graph to identify all possible paths from the start node to the end node, and storing the obtained paths in a preset data structure; based on the stored paths, simulating the operational behavior of the functional module, driving the basic units to execute corresponding logical operations or transmission operations according to the path sequence, and detecting whether the operational behavior conforms to preset design specifications.

[0009] Preferably, the basic unit includes the state unit of a state machine or the routing unit of a network chip, and the logical relationship or connection relationship includes state transition relationship or data transmission relationship.

[0010] Preferably, for the case where the directed network graph contains only large loop paths returning from the starting node to the starting node, the method for traversing the directed network graph includes: The directed network graph is viewed as a tree structure with the starting node as the root node and leaf nodes, and a depth-first search algorithm is used for path search. If the starting node is not returned to, each time a node is reached, that node is pushed onto a preset path stack to record the current path; When returning to the starting node via the large loop path, the nodes involved in the current path are pushed onto the path stack in traversal order; Continue searching for downstream nodes of the starting node, pushing newly arrived nodes onto the path stack in sequence, until all paths in the directed network graph have been traversed, and all paths are stored in the path stack.

[0011] Preferably, for the directed network graph, which contains both large loop paths returning from the starting node to the starting node and multiple internal small loop paths, the method for traversing the directed network graph includes: A recursive traversal algorithm is used to perform path search on the directed network graph. When a small loop is detected where a node points to itself through a path, a return operation is triggered, and the path stack is traced upwards to process the loop path. The path stack is used as a data structure to store the path. During the upward tracing of the path stack, the push method is determined based on the position of the most recently incompletely traversed node, and the path is pushed onto the path stack. Repeat the above process until all paths in the directed network graph have been traversed.

[0012] Preferably, methods for determining the stack push method based on the position of the most recently incompletely traversed node include: If the node that has not been traversed recently is located inside the small loop, then the path from the current small loop node to the node that has not been traversed recently is pushed onto the path stack, and the downstream nodes are traversed from the node that has not been traversed recently. If the node that was least recently traversed is located outside the small loop, then the path stack is traced upwards again. The path starting from the current small loop node, passing through the relevant nodes of the large loop path, and ending at the node that was least recently traversed, is pushed into the path stack, and the downstream nodes are traversed from the node that was least recently traversed.

[0013] Preferably, the method for simulating the operational behavior of the functional module based on the stored path includes: For each stored path, the path is loaded into the simulation environment in sequence, and the basic units of the functional module are driven to perform logical operations or transmission operations in the order of the path. During the simulation, the output behavior of the basic unit is monitored to see if it conforms to the preset design specifications. If a deviation is detected, the error path is recorded and fed back to the verification system.

[0014] Preferably, the method for traversing the directed network graph includes: During the traversal, whenever a complete path is identified, the path is stored in a preset data structure in node order, and potential loop paths are marked. After completing the traversal, verify the integrity of the path stored in the preset data structure.

[0015] The present invention also provides a chip functional module operation path verification system based on a graph model, which includes a verification server, the verification server operating based on the chip functional module operation path verification method described above.

[0016] The present invention also provides a verification system, comprising: One or more processors; Memory; And one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the programs including instructions for performing the chip functional module run path verification method as described above.

[0017] The present invention also provides a computer-readable storage medium comprising a computer program that can be executed by a processor to perform the chip functional module operation path verification method as described above.

[0018] Compared with existing technologies, the chip functional module operation path verification method provided by the above technical solution systematizes the verification process by constructing a directed network graph and traversing all possible paths, avoiding repetitive work or inefficiencies that may occur in traditional manual analysis or random testing. Secondly, path-based simulation can accurately reproduce the behavior of functional modules under specific paths, driving basic units to execute logical or transmission operations sequentially, ensuring that the verification results are consistent with actual operation. Combined with the detection of design specifications, this method can discover potential path-related design defects (such as state transition errors or data transmission delays), thereby improving verification accuracy. Furthermore, this method is applicable to different types of chip functional modules (such as state machines and network chips), exhibiting strong versatility and scalability. Attached Figure Description

[0019] Figure 1 This is a flowchart of the verification method in an embodiment of the present invention.

[0020] Figure 2 This is a directed network graph in one embodiment of the present invention.

[0021] Figure 3 This is a directed network graph in another embodiment of the present invention. Detailed Implementation

[0022] To illustrate the technical content, structural features, objectives, and effects of the present invention in detail, the following description is provided in conjunction with the embodiments and accompanying drawings.

[0023] This embodiment discloses a method for verifying the running path of chip functional modules based on a graph model, which can be used for system performance evaluation in the front-end design process of chip products to ensure that the chip meets the design requirements.

[0024] like Figure 1 The verification method includes the following steps: S11: Based on the design structure of functional modules in the chip, the basic units in the functional modules are abstracted into nodes, and a directed network graph is constructed based on the logical or connection relationships between the basic units. S12: In a directed network graph, determine the start node and the end node, traverse the directed network graph to identify all possible paths from the start node to the end node, and store the obtained paths in a preset data structure. S13: Based on the stored path, simulate the running behavior of the functional module, drive the basic unit to execute the corresponding logical operation or transmission operation according to the path sequence, and detect whether the running behavior conforms to the preset design specifications, so as to realize the correctness verification of the chip functional module path.

[0025] Specifically, the basic units include the state units of a state machine or the routing units of a network chip, and the logical or connection relationships include state transition relationships or data transmission relationships.

[0026] Chip functional modules typically contain a large number of basic units (such as logic units, memory units, or routing units), and the logical or connection relationships between these units are intricate. This embodiment abstracts the basic units as nodes and constructs a directed network graph based on logical or connection relationships, transforming the complex hardware design into a graph model. This abstraction method reduces the complexity of the problem and makes the path verification process more intuitive and operable.

[0027] Furthermore, during chip operation, there may be multiple possible paths from the starting point to the ending point, especially for state machines or network chips, which may contain loops or branches. This embodiment identifies all possible paths by traversing the directed network graph, ensuring comprehensive path coverage and thus avoiding incomplete verification due to the omission of critical paths.

[0028] State machines, as common functional modules in chip design, rely on the transition logic between state units for their operation. Path verification aims to ensure that state transition paths conform to design specifications and avoid problems such as infinite loops, unreachable states, or erroneous transitions. The following section uses a specific example of path verification applied to a state machine functional module to explain the operation process of the above verification method in detail.

[0029] Step 1: Construct a directed network graph Based on the design structure of the state machine functional module in the chip, the basic units of the state machine (i.e., each state unit) are abstracted as nodes in a directed network graph. Each state unit represents the running state of the state machine at a certain moment, such as "idle state," "waiting state," and "executing state." Based on the logical relationships between state units, i.e., state transition relationships, a directed network graph is constructed, where directed edges represent the direction and conditions of state transitions. For example, if state unit A transitions to state unit B under specific input conditions, a directed edge from node A to node B is drawn in the directed network graph, and the corresponding transition conditions (such as input signal or clock trigger) are labeled.

[0030] In this embodiment, it is assumed that the state machine contains 5 state units, namely P1 (initial state), P2, P3, P4 and P5, and the transition relationship is as follows: P1 jumps to P2 under condition C1; P2 jumps to P3 under condition C2, or jumps to P4 under condition C3; P3 jumps to P5 under condition C4; P4 jumps to P5 under condition C5, or returns to P1 under condition C6; P5 returns to P1 under condition C7.

[0031] The directed network graph constructed through the above jump relationships clearly shows the logical dependencies between the state units in the state machine, laying the foundation for subsequent path identification.

[0032] Step 2: Traverse the directed network graph and store the paths In the constructed directed network graph, the starting node and the ending node are determined. Taking this embodiment as an example, assume that the starting node is P1 (initial state) and the ending node is P5 (target state). Subsequently, a traversal algorithm is used to search the directed network graph to identify all possible paths from the starting node P1 to the ending node P5, and the obtained paths are stored in a preset data structure.

[0033] In this embodiment, a depth-first search (DFS) algorithm is used for path traversal. Starting from the initial node S1, all possible jump paths are explored layer by layer along the directed edges, while recording the sequence of nodes traversed during the traversal. When a path is detected to reach the terminal node S5, the path is stored in a preset data structure (such as a path list or stack); when a cycle is detected (such as returning from S4 to S1), the path is marked to avoid repeated traversal. Through traversal, the following possible paths from S1 to S5 are identified: Path 1: S1→S2→S3→S5; Path 2: S1→S2→S4→S5; Path 3: S1→S2→S4→S1→S2→S3→S5 (including loop).

[0034] The aforementioned paths are stored in a preset data structure, with each path recording a complete sequence of nodes and corresponding jump conditions, facilitating subsequent simulation and verification.

[0035] Step 3: Simulate the running behavior and check its correctness Based on the stored paths, the operational behavior of the state machine functional modules is simulated. Specifically, for each stored path, the node sequence in the path is loaded into the simulation environment, and the state units are driven to execute corresponding logical operations according to the path order, i.e., the state transition process is simulated. During the simulation, the operational behavior of the state machine is checked to see if it conforms to the preset design specifications, thereby verifying the correctness of the state machine paths.

[0036] In this embodiment, it is assumed that the design specifications require the state machine to reach the target state S5 from the initial state S1 within a finite number of steps, and that there must be no infinite loop or unreachable state. For path 1 (S1→S2→S3→S5), the simulation process sequentially drives the state unit to jump from S1 to S2, S3, and finally to S5, while checking whether each jump meets the corresponding conditions (such as C1, C2, C4). The simulation results show that path 1 conforms to the design specifications. For path 3 (S1→S2→S4→S1→S2→S3→S5), the simulation found a loop (S1→S2→S4→S1). Further testing is conducted to see if this loop will lead to an infinite loop. If the number of loop jumps exceeds a preset threshold, it is marked as a potential error path and fed back to the design optimization stage.

[0037] Through the above simulations and tests, it was verified whether the operating behavior of the state machine functional module under different paths met expectations, and the correctness of the state machine path was finally verified.

[0038] The following section will use the routing module of a Network on Chip (NoC) as an example to explain the above verification method in detail.

[0039] As a key technology for on-chip communication in chip design, NoC's routing module is responsible for the transmission of data packets between different units. The purpose of path verification is to ensure the efficiency and correctness of data transmission paths and avoid problems such as data loss, deadlock or routing conflicts.

[0040] Step 1: Construct a directed network graph Based on the design structure of the NoC routing function module in the chip, the basic units (i.e., each routing unit) in the routing function module are abstracted as nodes in a graph model. Each routing unit represents a node in the NoC responsible for data forwarding, such as routers R1, R2, and R3, which are distributed in different locations on the on-chip network. Based on the connection relationships between routing units, i.e., data transmission relationships, a directed network graph is constructed, where directed edges represent the direction of data packet transmission from one routing unit to another and possible transmission conditions (such as bandwidth limitations or priority rules). For example, if routing unit R1 is connected to routing unit R2 through a physical link, and data packets can be forwarded from R1 to R2 under specific conditions, then a directed edge from node R1 to node R2 is drawn in the directed network graph, and the corresponding transmission conditions can be labeled.

[0041] In this embodiment, it is assumed that NoC contains 6 routing units, namely R1 (data source), R2, R3, R4, R5 and R6 (data destination), and the data transmission relationship is as follows: R1 can transfer data to R2 or R3; R2 can transfer data to R4; R3 can transfer data to R4 or R5; R4 can transfer data to R6; R5 can transmit data to R6, or back to R3 under certain conditions.

[0042] The directed network graph constructed through the above data transmission relationships clearly shows the communication dependencies between routing units in NoC, laying the foundation for subsequent path identification.

[0043] Step 2: Traverse the directed network graph and store the paths In the constructed directed network graph, the starting node and the ending node are determined. Taking this embodiment as an example, assume the starting node is R1 (data source routing unit) and the ending node is R6 (data destination routing unit). Subsequently, a traversal algorithm is used to search the directed network graph to identify all possible data transmission paths from the starting node R1 to the ending node R6, and the obtained paths are stored in a preset data structure.

[0044] In this embodiment, a depth-first search (DFS) algorithm is also used for path traversal. Starting from the initial node R1, all possible transmission paths are explored layer by layer along the directed edges, while recording the sequence of nodes traversed during the traversal. When a path is detected to reach the terminal node R6, the path is stored in a preset data structure (such as a path list or queue); when a loop is detected (such as a loop back from R5 to R3), the path is marked to avoid repeated traversal or deadlock risks. Through traversal, the following possible paths from R1 to R6 are identified: Path 1: R1→R2→R4→R6; Path 2: R1→R3→R4→R6; Path 3: R1→R3→R5→R6; Path 4: R1→R3→R5→R3→R4→R6 (including loop).

[0045] The aforementioned paths are stored in a preset data structure, with each path recording a complete sequence of nodes and corresponding transmission conditions (such as link bandwidth or delay) to facilitate subsequent simulation and verification.

[0046] Step 3: Simulate the running behavior and check its correctness Based on the stored paths, the operational behavior of the NoC routing function module is simulated. Specifically, for each stored path, the node sequence in the path is loaded into the simulation environment, and the routing units are driven to perform corresponding transmission operations according to the path order, i.e., simulating the forwarding process of data packets between routing units. During the simulation, the operational behavior of the routing function module is checked to see if it conforms to the preset design specifications, thereby verifying the correctness of the NoC routing paths.

[0047] In this embodiment, it is assumed that the design specifications require data packets to be transmitted from data source R1 to data destination R6 within a finite time, and that the transmission path must not experience deadlock, data loss, or exceed the maximum delay threshold. For path 1 (R1→R2→R4→R6), the simulation process sequentially drives the routing unit to forward data packets from R1 to R2, R4, and finally to R6, while checking whether each transmission step meets the corresponding conditions (such as sufficient link bandwidth and delay within the threshold). The simulation results show that path 1 conforms to the design specifications. For path 4 (R1→R3→R5→R3→R4→R6), the simulation found a loop (R3→R5→R3). Further testing is conducted to determine whether this loop will cause deadlock or exceed the transmission delay limit. If the number of loop forwardings exceeds the preset threshold or the delay exceeds the specification, it is marked as a potential error path and fed back to the design optimization stage.

[0048] Through the above simulations and tests, it was verified whether the data transmission behavior of the NoC routing module under different paths met expectations, and the correctness of the routing path was finally verified.

[0049] This embodiment abstracts the NoC routing function module into a directed network graph, comprehensively identifies all possible transmission paths from the data source to the data target, and detects the correctness of the path by simulating data transmission behavior, successfully discovering potential design problems (such as deadlock or delay risks caused by loops).

[0050] Therefore, the above path verification method firstly systematizes the verification process by constructing a directed network graph and traversing all possible paths, thus avoiding the repetitive work or inefficiency that may occur in traditional manual analysis or random testing.

[0051] Secondly, path-based simulation can accurately reproduce the behavior of functional modules along specific paths, driving basic units to execute logical or transmission operations sequentially, ensuring that verification results are consistent with actual operation. Combined with the inspection of design specifications, this method can uncover potential path-related design flaws (such as state transition errors or data transmission delays), thereby improving verification accuracy.

[0052] Furthermore, this method is applicable to different types of chip functional modules (such as state machines and network chips), and has strong versatility and scalability.

[0053] On the other hand, methods for traversing directed network graphs include: S21: During the traversal, whenever a complete path is identified, the path is stored in a preset data structure in node order, and potential loop paths are marked to avoid repeated traversal; S22: After completing the traversal, verify the integrity of the paths stored in the preset data structure to ensure that all possible paths from the start node to the end node are covered.

[0054] Timely identification of potential loops (such as small loops or local loops) during traversal helps distinguish between normal paths and problematic paths, preventing the traversal algorithm from getting stuck in infinite loops or repeating calculations. A marking mechanism allows recording loop characteristics (such as loop node sequences) without interrupting traversal, providing a basis for subsequent optimization. Therefore, marking potential loop paths improves verification accuracy and reduces the risk of false negatives or negatives. For example, in NoC routing verification, early marking of loop paths can prevent data transmission deadlocks, improve chip reliability and stability, and provide design engineers with targeted optimization guidance.

[0055] In addition, a post-validation mechanism is introduced to verify the integrity of the paths stored in the preset data structure. This mechanism checks whether the stored paths cover all possible paths and whether there are any missing or redundant paths. Through this dual protection (real-time storage during traversal plus post-validation), the integrity and consistency of the output data are ensured, avoiding potential vulnerabilities in path validation.

[0056] On the other hand, for directed network graphs where only large loop paths exist (and no other loop paths), methods for traversing directed network graphs include: S31: Treat the directed network graph as a tree structure with the starting node as the root node and leaf nodes, and use the depth-first search algorithm for path search; S32: If the starting node is not returned, each time a node is reached, push that node onto the preset path stack to record the current path; S33: When returning to the starting node through the large loop path, push the nodes involved in the current path into the path stack in the order of traversal; S34: Continue searching for downstream nodes of the starting node, pushing newly arrived nodes onto the path stack in sequence, until all paths in the directed network graph have been traversed, and all paths are stored in the path stack.

[0057] like Figure 2 In this directed network graph, the starting node is root. During traversal, whenever a node is reached before returning to root, that node is pushed onto the path stack. Taking root ---> a ---> root as an example, when the large cycle returns to root, root and a are pushed onto the path stack, meaning the last four elements in the path stack are {...,root,a,root,a}. Then, the traversal function for a continues searching for the downstream node b, and the path stack becomes {...,root,a,root,a,b}.

[0058] On the other hand, for directed network graphs, which contain both large loop paths returning from the starting node to the starting node and multiple internal small loop paths, methods for traversing directed network graphs include: S41: A recursive traversal algorithm is used to perform path search on the directed network graph. When a small loop is detected where a node points to itself through a path, a return operation is triggered, and the preset path stack is traced upwards to handle the loop path; the path stack is used as a data structure to store the path. S42: During the upward tracing of the path stack, determine the push method based on the position of the most recently incomplete traversal node, and push the path onto the path stack; S43: Repeat the above steps until all paths in the directed network graph have been traversed.

[0059] Specifically, methods for determining the push method based on the position of the most recently traversed node include: If the node that has not been traversed the most recently is inside a small loop, then the path from the current small loop node to the node that has not been traversed the most recently is pushed onto the path stack, and the downstream nodes will continue to be traversed from the node that has not been traversed the most recently. If the node that was not recently traversed is outside the small loop, then trace the path stack upwards again. Push the path starting from the current small loop node, passing through the relevant nodes of the large loop path, and ending at the node that was not recently traversed, onto the path stack, and continue traversing the downstream nodes from the node that was not recently traversed.

[0060] like Figure 3 In the directed network graph, there are both large loop paths and multiple internal small loop paths, which can be categorized into the following two cases.

[0061] 1. For the case where the node that was not recently traversed is located inside a small loop: During the upward tracing of the path stack, if a node that has not been traversed recently (i.e., a node whose downstream nodes have not yet been traversed) is found to be inside a small loop, the following stack operation is performed: Detecting small loops: Suppose that the state of the path stack at a certain moment is {..., c, a, b, ..., d}, which records the small loops from node a to node a.

[0062] Tracing upwards: Starting from the top of the stack, trace backwards through the nodes in the path stack to find the first node that still has untraversed downstream nodes. Assume the tracing result is node b (located inside the small loop, and b still has untraversed downstream nodes).

[0063] Push operation: Push the path segment from node a to node b (i.e., a→b) onto the path stack. After pushing, the path stack state is updated to {..., c, a, b, ..., d, a, b}.

[0064] Continue traversing: Using node b as the current node, continue traversing its unexplored downstream nodes and record the new path.

[0065] By performing the above operations, we can ensure that unfinished traversed nodes inside the small loop can be re-explored, thus avoiding interruption of path traversal due to the existence of the small loop.

[0066] 2. For the case where the node whose traversal was least recently completed is located outside the small loop: During the upward tracing of the path stack, if a node that has not been traversed recently (i.e., a node whose downstream nodes have not yet been traversed) is found to be outside the small loop, the following stack operation is performed: Detecting small loops: Suppose that the state of the path stack at a certain moment is {..., a, ..., root, ..., c, a,b, ..., d}, which records the small loops from node a to node a.

[0067] Tracing upwards: Starting from the top of the stack, trace backwards through the nodes in the path stack to find the first node that still has untraversed downstream nodes. Assume the tracing result is node c (located outside the small loop, and c still has untraversed downstream nodes).

[0068] Path copying and stack pushing: Retrace upwards through the path stack, extract the path segment starting from node a, passing through node root, and ending at node c (i.e., a→...→root→...→c), and push this path segment onto the path stack. After pushing, the path stack state is updated to {..., a, ..., root, ..., c, a, b, ..., d, a, ..., root, ...,c}.

[0069] Continue traversing: Taking node c as the current node, continue traversing its downstream unexplored nodes and record the new path.

[0070] The above operations ensure that unfinished nodes outside the small loop can be re-explored, while retaining the path information related to the small loop to avoid omissions in path traversal.

[0071] On the other hand, methods for simulating the operational behavior of functional modules based on storage paths include: S51: For each stored path, load the path into the simulation environment in sequence, and drive the basic units of the functional modules to perform logical operations or transmission operations in the order of the paths. S52: During the simulation, monitor whether the output behavior of the basic unit conforms to the preset design specifications. If a deviation is detected, record the error path and feed it back to the verification system to optimize the design of the functional module. It should be noted that, for state machine scenarios, state transition paths are simulated first; for network chip scenarios, data transmission paths are simulated first, until the simulation and verification of all paths are completed.

[0072] In another embodiment of the present invention, a chip functional module operation path verification system based on a graph model is also disclosed. The verification system includes a verification server, which operates based on the chip functional module operation path verification method in the above embodiment.

[0073] The present invention also discloses another verification system, which includes one or more processors, a memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the programs including instructions for performing the verification method as described above. The processor may be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, used to execute the relevant programs to implement the functions required by the modules in the verification system of the embodiments of this application, or to execute the verification method of the method embodiments of this application.

[0074] The present invention also discloses a computer-readable storage medium comprising a computer program executable by a processor to perform the verification method described above. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center integrating one or more available media. The available medium can be read-only memory (ROM), random access memory (RAM), or magnetic media, such as floppy disks, hard disks, magnetic tapes, magnetic disks, or optical media, such as digital versatile discs (DVDs), or semiconductor media, such as solid-state drives (SSDs).

[0075] This application also discloses a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of an electronic device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the electronic device to perform the verification method described above.

[0076] The above-disclosed embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. Therefore, any equivalent variations made in accordance with the claims of the present invention are still within the scope of the present invention.

Claims

1. A method for verifying the execution path of chip functional modules based on a graph model, characterized in that, include: Based on the design structure of functional modules in the chip, the basic units in the functional modules are abstracted as nodes, and a directed network graph is constructed based on the logical or connection relationships between the basic units. In the directed network graph, a start node and an end node are determined, and the directed network graph is traversed to identify all possible paths from the start node to the end node, and the obtained paths are stored in a preset data structure. Based on the stored path, the operation behavior of the functional module is simulated, the basic unit is driven to execute the corresponding logical operation or transmission operation in the path sequence, and the operation behavior is detected to ensure that it conforms to the preset design specifications.

2. The verification method according to claim 1, characterized in that, The basic unit includes the state unit of a state machine or the routing unit of a network chip, and the logical relationship or connection relationship includes state transition relationship or data transmission relationship.

3. The verification method according to claim 1, characterized in that, For the case where the directed network graph contains only large loop paths returning from the starting node to the starting node, the method for traversing the directed network graph includes: The directed network graph is viewed as a tree structure with the starting node as the root node and leaf nodes, and a depth-first search algorithm is used for path search. If the starting node is not returned to, each time a node is reached, that node is pushed onto a preset path stack to record the current path; When returning to the starting node via the large loop path, the nodes involved in the current path are pushed onto the path stack in traversal order; Continue searching for downstream nodes of the starting node, pushing newly arrived nodes onto the path stack in sequence, until all paths in the directed network graph have been traversed, and all paths are stored in the path stack.

4. The verification method according to claim 1, characterized in that, For the directed network graph, which contains both large loop paths returning from the starting node to the starting node and multiple internal small loop paths, the method for traversing the directed network graph includes: A recursive traversal algorithm is used to perform path search on the directed network graph. When a small loop is detected where a node points to itself through a path, a return operation is triggered, and the path stack is traced upwards to process the loop path. The path stack is used as a data structure to store the path. During the upward tracing of the path stack, the push method is determined based on the position of the most recently incompletely traversed node, and the path is pushed onto the path stack. Repeat the above process until all paths in the directed network graph have been traversed.

5. The verification method according to claim 4, characterized in that, Methods for determining the push method based on the position of the least recently traversed node include: If the node that has not been traversed recently is located inside the small loop, then the path from the current small loop node to the node that has not been traversed recently is pushed onto the path stack, and the downstream nodes are traversed from the node that has not been traversed recently. If the node that was least recently traversed is located outside the small loop, then the path stack is traced upwards again. The path starting from the current small loop node, passing through the relevant nodes of the large loop path, and ending at the node that was least recently traversed, is pushed into the path stack, and the downstream nodes are traversed from the node that was least recently traversed.

6. The verification method according to claim 1, characterized in that, The method for simulating the operational behavior of the functional module based on the stored path includes: For each stored path, the path is loaded into the simulation environment in sequence, and the basic units of the functional module are driven to perform logical operations or transmission operations in the order of the path. During the simulation, the output behavior of the basic unit is monitored to see if it conforms to the preset design specifications. If a deviation is detected, the error path is recorded and fed back to the verification system.

7. The verification method according to claim 1, characterized in that, Methods for traversing the directed network graph include: During the traversal, whenever a complete path is identified, the path is stored in a preset data structure in node order, and potential loop paths are marked. After completing the traversal, verify the integrity of the path stored in the preset data structure.

8. A chip functional module operation path verification system based on a graph model, characterized in that, It includes a verification server, which operates based on the chip functional module operation path verification method according to any one of claims 1 to 7.

9. A verification system, characterized in that, include: One or more processors; Memory; And one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the programs including instructions for performing the chip functional module run path verification method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, It includes a computer program that can be executed by a processor to perform the chip functional module operation path verification method as described in any one of claims 1 to 7.

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