Large-area ai embedded computing system and glass panel level package method

Abstract

The application discloses a large-area AI embedded computing system, and relates to the technical field of semiconductor packaging.The system comprises function layers of perception, calculation and facilities arranged in a stack from top to bottom.The perception layer is used for accepting light rays to be detected and generating a perception signal.The calculation layer is used for data processing of the perception signal and outputting data.The facility layer is used for providing energy and communication support for the system.Each function layer is independently arranged on a glass panel, and the glass panel is provided with an optical waveguide channel and / or a vertical conductive channel.An optical I / O chip is integrated between each layer and encapsulated through three-dimensional stacking to form an interlayer optical interconnection network, realize collaborative interconnection of electricity and optics, and realize high-speed and low-power optical and electrical data transmission.The computing system can significantly reduce parasitic capacitance and signal loss, improve heat dissipation efficiency and packaging reliability, simplify manufacturing process and reduce cost, and is suitable for high-computing-power and large-area AI embedded computing application scenarios.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a large-area AI embedded computing system and a glass panel-level integrated packaging method. Background Technology

[0002] With the rapid development of emerging technologies such as artificial intelligence (AI), the Internet of Things (IoT), and augmented / virtual reality (AR / VR), computing systems are evolving towards large-area, high-pixel-density, low-power, and embedded AI function integration, requiring multi-chip, multi-function collaborative optimization on the same packaging platform.

[0003] However, traditional silicon-based semiconductor packaging has gradually encountered the slowdown of Moore's Law and system-level performance bottlenecks: the continuous increase in chip size, the increase in computing frequency, and the simultaneous growth in the demand for high-speed signal transmission and thermal management make it difficult for traditional packaging structures to balance high computing power, low power consumption and reliability.

[0004] In recent years, the industry has proposed new technologies such as Panel Level Packaging (PLP) and 3D stacked packaging, attempting to utilize the insulation, low parasitic capacitance, and large area characteristics of glass substrates to achieve high-density integration of multi-chip modules. Through Glass Via (TGV), as a vertical interconnect structure that penetrates the glass substrate, can effectively reduce parasitic capacitance and improve high-frequency signal transmission capabilities compared to Through Silicon Via (TSV). Panel-level packaging draws on the manufacturing ideas of display panels and achieves efficient packaging of multiple chips and passive devices through fan-out wiring, which is expected to achieve a balance between cost and integration.

[0005] Despite the progress made in the aforementioned technologies, existing advanced packaging solutions still have significant shortcomings. With existing silicon interposer packaging structures, while increasing wiring density, the high parasitic capacitance of the silicon interposer (approximately 50 fF or more) remains a problem, leading to significant signal loss at high frequencies and limiting AI computing power output. While existing silicon-based and optical glass substrate combinations enable logic chip stacking, the significant difference in thermal expansion coefficients between silicon (CTE≈2.6 ppm / ℃) and optical glass substrates (CTE≈7 ppm / ℃) makes the bonding interface prone to failure after thermal cycling. Furthermore, OLED display modules utilize a combination of high thermal conductivity metal plates and low thermal conductivity polymer layers for heat dissipation and vibration damping, but in high power density scenarios (>3W), surface or junction temperatures may still exceed 150℃, leading to device performance degradation. Clearly, differences in material thermophysical properties and insufficient heat dissipation have become core obstacles to improving the reliability of 3D integration.

[0006] Furthermore, current through-silicon via (TSV) packaging structures are still limited by signal transmission performance under high integration: the high parasitic capacitance of the silicon interposer causes high-frequency signal distortion and bandwidth reduction, directly affecting AI inference response; in terms of thermal reliability, the mismatch of thermal expansion coefficients between silicon, glass, and organic materials (such as Cu vs SiLK) leads to interface cracks and bond delamination; while the low thermal conductivity of the organic layer causes the temperature to rise rapidly under high power, inducing frequency reduction or device failure. At the same time, the complex multilayer process and material combination also drive up manufacturing costs, with excessively high process costs per square centimeter, restricting its promotion in large-area, low-cost commercial applications.

[0007] The existing technology has at least the following technical problems: First, high-frequency signal transmission is still limited by parasitic capacitance and transmission loss, making it difficult to meet the needs of high-computing-power AI systems; second, the reliability problems caused by low heat dissipation efficiency and thermal expansion mismatch of multiple materials have not been effectively solved; and third, the complex manufacturing process and high cost per unit area limit the popularization of glass panel-level packaging in large-scale commercial applications.

[0008] In summary, the existing technology has at least the following technical problems:

[0009] Existing packaging technologies suffer from several technical problems, including limitations in high-frequency signal transmission due to parasitic capacitance and transmission loss, low heat dissipation efficiency, low reliability due to thermal expansion mismatch of multiple materials, and high packaging costs due to complex manufacturing processes. Summary of the Invention

[0010] The purpose of this invention is to provide a large-area AI embedded computing system and a glass panel-level integrated packaging method to solve the technical problems in existing packaging technologies, such as high-frequency signal transmission still being limited by parasitic capacitance and transmission loss, low heat dissipation efficiency, low reliability caused by thermal expansion mismatch of multiple materials, and high packaging cost caused by complex manufacturing processes.

[0011] The preferred technical solutions among the many technical solutions provided by this invention can produce a variety of technical effects, which are described in detail below.

[0012] To address the aforementioned technical problems, the present invention provides the following technical solution:

[0013] This invention provides a large-area AI embedded computing system, comprising a sensing layer, a computing layer, and a facility layer arranged sequentially from top to bottom. The sensing layer receives incident light to be detected and generates a sensing signal. The sensing signal enters the computing layer for data processing and outputs data. The facility layer supports the operation of the sensing layer and the computing layer through optoelectronic interconnects, receives data output by the computing layer, and transmits data to external devices. The sensing layer, computing layer, and facility layer are each independently disposed on a glass panel. Optical waveguide paths and / or vertical conductive paths are provided in each of the glass panels. Optical I / O chips are integrated between each layer and packaged through three-dimensional stacking to form an interlayer optical interconnect network for electrical and optical interconnection, enabling high-speed, low-power optoelectronic collaborative data transmission.

[0014] In one embodiment, the sensing layer includes an absorber and a detector; the absorber is laid on the matrix detection unit to receive the light to be detected; a plurality of detectors are laid in a matrix on the glass panel of the sensing layer to form a matrix detection unit, the matrix detection unit is interconnected with the absorber to amplify the incident light signal and convert it into the sensing signal in the form of an electrical signal, and the sensing signal is transmitted to the optical I / O chip between the computing layer and the sensing layer in the form of optical conduction through the interlayer optical interconnect network, the optical I / O chip performs photoelectric conversion and communicates with the module of the computing layer.

[0015] In one embodiment, the computing layer includes a computing chipset composed of an AI-FPGA module, a CPU module, and a GPU module; the computing chipset is connected to optical I / O chips between the computing layer and the sensing layer, and between the computing layer and the facility layer, for optical and electrical communication between the computing layer and the sensing layer and the facility layer; the computing chipset of the computing layer receives instructions from the facility layer and sensing signals from the sensing layer through the optical I / O chips between the layers, for performing real-time data processing, machine learning inference and algorithm acceleration, and for completing high-speed optical signal communication and photoelectric conversion between the layers through the optical I / O chips.

[0016] In one embodiment, the facility layer includes a power management module, a micro battery, a memory chip, and a high-speed interface module. The micro battery is disposed within a battery cavity in the glass panel of the facility layer and is electrically connected to the power management module, the memory chip, and the high-speed interface module. The high-speed interface module communicates with the memory chip, the optical I / O chip between the computing layer and the facility layer, and external devices to be connected. The battery cavity is formed by dry etching, the micro battery is embedded within the battery cavity, and a nickel sealing sheet is placed on top of the battery cavity to encapsulate the micro battery within the facility layer.

[0017] In one embodiment, the battery cavity has a depth of 250-350 μm; the micro battery is a solid-state thin-film lithium battery with a thickness of 180-280 μm and an energy density of 350 Wh / L; the nickel sealing sheet covering the top of the battery cavity is fused to the glass panel around the battery cavity by nickel-glass laser ring welding, so as to help reduce the resistance of the power supply path with an extremely short power supply path.

[0018] In one embodiment, a PMIC chip is embedded in the glass panel of the facility layer. The PMIC chip is electrically connected to the micro battery and the power management module to achieve dynamic voltage regulation from +0.8V to -1.2V for the power management module to perform module-level dynamic power scheduling.

[0019] In one embodiment, a glass via with a diameter ≤10μm is formed on the glass panel, a Ti / Cu composite seed layer is deposited inside the via wall, and copper is electroplated into the glass via to form the vertical conductive path; the optical waveguide path is disposed within a region of 15μm outside the structure of the glass via, and the optical waveguide path is a silicon nitride optical waveguide to reduce electromagnetic crosstalk and optical loss; a TGV pad is provided at the glass via, and the optical I / O chip is flip-chip bonded to the TGV pad. The optical I / O chip senses the optical communication information of the silicon nitride optical waveguide and converts it into an electrical signal, forming electrical communication through the vertical conductive path to realize high-speed photoelectric signal conversion.

[0020] In one embodiment, a flexible thin film layer, which is a polyimide flexible interposer layer, is hot-pressed onto the surface of the glass panel. A Cu / Ni / Au multilayer wiring is constructed on the flexible thin film layer between the glass panel of the computing layer and the computing chipset. The electrical signals of the computing chipset and the optical I / O chip are transmitted through the Cu / Ni / Au multilayer wiring.

[0021] A glass panel-level integrated packaging method is also provided, which includes a large-area AI embedded computing system and the following steps: (1) fabricating optical waveguide paths and vertical conductive paths on a multi-layer glass panel respectively; (2) fabricating functional panels of a sensing layer, a computing layer and a facility layer respectively; including fabricating an absorber and a detector in the sensing layer, fabricating a computing chipset and an optical I / O chip in the computing layer, and fabricating a power management module, a battery cavity, a memory chip and a high-speed interface module in the facility layer; (3) stacking the sensing layer, the computing layer and the facility layer sequentially using a high-precision alignment and 3D hybrid bonding process to achieve optoelectronic integrated interconnection; (4) after glass-to-glass thermo-press bonding, embedding a micro battery in the battery cavity of the facility layer and fusion welding a nickel sealing sheet to the battery cavity by nickel-glass laser ring welding to form a packaging structure.

[0022] In one embodiment, the 3D hybrid bonding process includes two stages: low-temperature bonding and high-temperature annealing. In the low-temperature bonding stage, at a temperature of ≤250°C, the glass panels of the sensing layer, computing layer, and facility layer are first thermo-bonded to the flexible film, then the optical I / O chips are welded, and finally the optical waveguide path and optical I / O chips are encapsulated using low-temperature curing epoxy resin. In the high-temperature annealing stage, at a temperature of ≥300°C, the glass vias are annealed in an H2 atmosphere to repair electroplating defects and reduce resistivity. The computing chipset is selectively annealed using infrared laser to avoid thermal damage to the encapsulated optoelectronic devices.

[0023] The large-area AI embedded computing system proposed in this invention achieves optical and electrical synergistic interconnection and communication between layers by independently setting glass panel structures for the sensing layer, computing layer, and facility layer, and forming optical waveguide paths and vertical conductive paths in the glass panels. Compared with existing silicon-based or organic packaging structures, it has the following significant advantages:

[0024] (1) Significantly reduce signal transmission loss and parasitic capacitance, and improve high-speed interconnect performance.

[0025] Integrating optical waveguides and through-glass vias (TGVs) within glass panels creates an interlayer optical interconnect network, replacing traditional metal wiring methods. Glass materials possess low dielectric constants and excellent electrical insulation properties, effectively reducing parasitic capacitance and electromagnetic crosstalk. Simultaneously, high-speed conversion between interlayer optical and electrical signals is achieved through optical I / O chips, significantly reducing high-frequency data transmission losses and significantly increasing system bandwidth to meet the demands of high-performance and high-response AI applications.

[0026] (2) Improve heat dissipation efficiency and packaging reliability

[0027] The functional layers of the perception layer, computing layer, and facility layer are distributed on independent glass panels, and spatial layered heat dissipation is achieved through three-dimensional stacking. The thermal conductivity of the glass panels is better than that of traditional organic carriers, and the coefficient of thermal expansion is close to that of optoelectronic chip materials, which can effectively alleviate the problems of thermal stress concentration and interface delamination.

[0028] Furthermore, the layered packaging structure facilitates the integration of microchannel cooling, heat diffusion layers, or metal thin-film heat sinks, thereby reducing the overall thermal resistance of the package and maintaining temperature equilibrium, thus improving the long-term reliability of the system.

[0029] (3) Realize a three-dimensional packaging structure for optoelectronic collaboration to improve system integration.

[0030] The architecture employs a structural design that combines optical I / O chips with three-dimensional stacked packaging to achieve optoelectronic dual-channel interconnection between layers, forming a collaborative computing network for sensing, computing, and output. This architecture enables efficient collaboration between the sensing layer, computing layer, and facility layer within a single system, supports the integrated operation of large-area array-type sensing and AI inference computing, and enhances the system's modularity and functional expansion capabilities.

[0031] (4) Reduce manufacturing complexity and cost, and improve process compatibility.

[0032] The glass panel adopts panel-level processing technology, which can simultaneously manufacture multiple functional modules on a large-size substrate. Compared with silicon interposers or organic multilayer boards, glass materials have lower processing temperatures, lower costs, and higher dimensional stability, making them suitable for large-area production. In the three-dimensional stacked packaging process, the number of interposers and complex wiring structures is reduced, and the number of packaging process steps is reduced by about 30%, which significantly reduces manufacturing costs and improves yield.

[0033] In summary, this invention achieves a high-bandwidth, low-power, high-heat-dissipation-efficiency, and low-cost compatible AI embedded computing system through glass panel-level optoelectronic interconnection and three-dimensional stacking structure, which can meet the application needs of future high-computing-power, large-area integration, and high-frequency operating scenarios. Attached Figure Description

[0034] To more clearly illustrate the technical solution of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of the integrated structure of the large-area AI embedded computing system of the present invention;

[0036] Figure 2 This is a top view of the computing layer structure of the present invention;

[0037] Figure 3 This is a top view of the facility layer of the present invention.

[0038] The accompanying figure is labeled as follows:

[0039] 1. Perception layer; 11. Absorber; 12. Detector;

[0040] 2. Computing Layer; 21. Computing Chipset; 211. AI-FPGA Module; 212. CPU Module; 213. GPU Module;

[0041] 3. Facility layer; 31. Power management module; 32. Micro battery; 33. Storage chip; 34. High-speed interface module; 35. Battery cavity;

[0042] 4. Optical interconnect network; 41. Optical waveguide path;

[0043] 5. Vertical conductive path; 51. Glass via; 52. TGV pad;

[0044] 6. Optical I / O chip;

[0045] 7. Glass panel;

[0046] 8. PMIC chip. Detailed Implementation

[0047] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0048] This embodiment provides a large-area AI embedded computing system and a glass panel-level integrated packaging method. The system includes functional layers of sensing, computing, and facilities arranged sequentially from top to bottom. The sensing layer is used to receive incident light to be detected and generate sensing signals. The computing layer is used to process the sensing signals and output data. The facilities layer is used to provide power and communication support for the system. Each functional layer is independently set on a glass panel, which has optical waveguide paths and / or vertical conductive paths. Optical I / O chips are integrated between the layers and packaged through three-dimensional stacking to form an interlayer optical interconnect network, realizing the coordinated interconnection of electrical and optical properties, thereby achieving high-speed, low-power optoelectronic data transmission. This computing system can significantly reduce parasitic capacitance and signal loss, improve heat dissipation efficiency and packaging reliability, simplify manufacturing processes, and reduce costs. It is suitable for high-bandwidth, high-computing-power, and large-area AI embedded computing application scenarios. It effectively solves the technical problems in existing packaging technologies, such as high-frequency signal transmission still being limited by parasitic capacitance and transmission loss, low heat dissipation efficiency, low reliability caused by thermal expansion mismatch of multiple materials, and high packaging costs caused by complex manufacturing processes.

[0049] The first implementation of a large-area AI embedded computing system, for example Figures 1 to 3As shown, the system includes a sensing layer 1, a computing layer 2, and a facility layer 3 arranged in a stacked manner from top to bottom. The sensing layer 1 is used to receive incident light to be detected and generate a sensing signal. The sensing signal enters the computing layer 2 for data processing and outputs data. The facility layer 3 supports the operation of the sensing layer 1 and the computing layer 2 through optoelectronic interconnection, receives the data output by the computing layer 2, and transmits data to external devices. The sensing layer 1, the computing layer 2, and the facility layer 3 are all independently set on glass panels 7. Optical waveguide paths 41 and, or vertical conductive paths 5, are set in their respective glass panels 7. Optical I / O chips 6 are integrated between each layer and packaged through three-dimensional stacking to form an interlayer optical interconnection network 4 for electrical and optical interconnection, which is used to realize high-speed, low-power optoelectronic collaborative data transmission.

[0050] Specifically, the large-area AI embedded computing system independently sets up glass panel 7 structures in the perception layer 1, computing layer 2, and facility layer 3, forming optical waveguide paths 41 and vertical conductive paths 5 within the glass panel 7. This enables inter-layer optical and electrical collaborative interconnection and communication, offering several technical advantages compared to existing silicon-based or organic packaging structures: significantly reducing signal transmission loss and parasitic capacitance, and improving high-speed interconnect performance; integrating optical waveguides and vertical conductive paths 5 (Through Glass Via, TGV) within the glass panel 7 to construct an inter-layer optical interconnect network 4, replacing traditional metal wiring methods. The glass material has a low dielectric constant and excellent electrical insulation properties, effectively reducing parasitic capacitance and electromagnetic crosstalk; simultaneously, the optical I / O chip 6 enables high-speed conversion between inter-layer optical and electrical signals, significantly reducing high-frequency data transmission loss and significantly increasing system bandwidth, meeting the high computing power and high-response requirements of AI applications.

[0051] To improve heat dissipation efficiency and packaging reliability, the functional layers of sensing layer 1, computing layer 2 and facility layer 3 are distributed on independent glass panels 7, and spatial layered heat dissipation is achieved through three-dimensional stacking. The thermal conductivity of glass panel 7 is better than that of traditional organic carriers, and its coefficient of thermal expansion is close to that of optoelectronic chip materials, which can effectively alleviate the problems of thermal stress concentration and interface delamination. In addition, the layered packaging structure also facilitates the integration of microchannel cooling, heat diffusion layer or metal thin film heat sink, which reduces the overall thermal resistance of the packaging and maintains temperature balance, thereby improving the long-term reliability of the system.

[0052] A three-dimensional packaging structure for optoelectronic collaboration is achieved, improving system integration. The structure design combines optical I / O chip 6 with three-dimensional stacked packaging to achieve optoelectronic dual-channel interconnection between layers, forming a collaborative computing network for sensing, computing, and output. This architecture enables efficient collaboration between sensing layer 1, computing layer 2, and facility layer 3 in a single system, supports the integrated operation of large-area array sensing and AI inference computing, and enhances the system's modularity and functional expansion capabilities.

[0053] Reduce manufacturing complexity and cost, and improve process compatibility; the glass panel 7 adopts panel-level processing technology, which can simultaneously manufacture multiple functional modules on large-size substrates; compared with silicon interposers or organic multilayer boards, glass materials have lower processing temperatures, lower costs, and higher dimensional stability, making them suitable for large-area production; in the three-dimensional stacked packaging process, the number of interposers and complex wiring structures is reduced, and the number of packaging process steps is reduced by about 30%, significantly reducing manufacturing costs and improving yield.

[0054] In summary, by using a 7-level optoelectronic interconnection and a 3D stacking structure on the glass panel, a high-bandwidth, low-power, high-heat-dissipation-efficiency, and low-cost compatible AI embedded computing system has been achieved, which can meet the application needs of future high-computing-power, large-area integration, and high-frequency operating scenarios.

[0055] As one alternative implementation method:

[0056] Regarding the specific structural configuration of the aforementioned perception layer 1, this implementation is as follows: Figures 1 to 3 As shown, the sensing layer 1 includes an absorber 11 and a detector 12. The absorber 11 is laid on the matrix detection unit to receive the light to be detected. Multiple detectors 12 are laid in a matrix on the glass panel 7 of the sensing layer 1 to form a matrix detection unit. The matrix detection unit is interconnected with the absorber 11 to amplify the incident light signal and convert it into a sensing signal in the form of an electrical signal. The sensing signal is transmitted to the optical I / O chip 6 between the computing layer 2 and the sensing layer 1 in the form of optical conduction through the interlayer optical interconnection network 4. The optical I / O chip 6 performs photoelectric conversion and communicates with the module of the computing layer 2.

[0057] The matrix detection unit is a TFT optoelectronic array manufactured on the glass panel 7 using a back-illuminated etching process, and the absorber 11 is a grating enhancement unit constructed using a microlens photolithography process to amplify the incident light signal and improve the collection efficiency.

[0058] In application, the absorber 11 in the sensing layer 1 efficiently absorbs, enhances, and amplifies light signals of different wavelengths under incident light illumination. The matrix detector array below responds to changes in light intensity in real time and generates corresponding electrical signals. After the absorber 11 is optically interconnected with the matrix detection unit, it amplifies the light signals and converts them into sensing signals in the form of electrical signals. These signals are then transmitted to the optical I / O chip 6 in the form of optical signals through the interlayer optical interconnection network 4. After the optical I / O chip 6 completes the photoelectric conversion, it transmits the sensing data to the corresponding module in the computing layer 2, achieving high-speed, low-latency data reading.

[0059] This structure enables large-area, high-pixel-density optical signal acquisition and real-time sensing, solving the problems of limited acquisition range and high response delay of traditional silicon-based sensing units; at the same time, it reduces transmission noise and power consumption through optical signal transmission, improving the system's signal-to-noise ratio and overall computing response speed.

[0060] Alternatively, the detection matrix can also employ a stacked photodetector array structure to achieve multispectral imaging or depth imaging functions.

[0061] Regarding the specific structural configuration of the aforementioned computing layer 2, this implementation is as follows: Figures 1 to 3 As shown, the computing layer 2 includes a computing chipset 21 composed of an AI-FPGA module 211, a CPU module 212, and a GPU module 213. The computing chipset 21 is connected to the optical I / O chip 6 between the computing layer 2 and the perception layer 1 and between the computing layer 2 and the facility layer 3, for optical and electrical communication between the computing layer 2 and the perception layer 1 and the facility layer 3. The computing chipset 21 of the computing layer 2 receives instructions from the facility layer 3 and perception signals from the perception layer 1 through the interlayer optical I / O chip 6, for performing real-time data processing, machine learning inference and algorithm acceleration, and completes high-speed optical signal communication and photoelectric conversion between layers through the optical I / O chip 6.

[0062] When applied, the AI-FPGA module 211, CPU module 212 and GPU module 213 in the computing layer 2 work together to achieve optical communication and synchronous control of electrical signals with the upper and lower layers using the optical I / O chip 6. The computing layer 2 receives sensing signals from the sensing layer 1 and system instructions from the facility layer 3, and performs neural network calculations, machine learning inference and algorithm optimization through the on-chip parallel acceleration structure. The processed results are returned to the facility layer 3 for output at high speed through the optical I / O chip 6.

[0063] This layer structure realizes an optoelectronic integrated on-chip computing architecture, solving the signal latency and power consumption bottleneck problems of traditional electrically interconnected AI systems under high-frequency operation; it realizes multi-channel data interaction with Tb / s-level bandwidth through optical interconnect links, significantly improving AI inference efficiency and energy efficiency.

[0064] In addition, an on-chip quantum dot acceleration unit or AI-NPU submodule is introduced in AI computing layer 2 to enable reconfigurable computing in different task scenarios. At the same time, the optical waveguide path 41 can be coupled to the microlens array of sensing layer 1 through the optical interconnect path, and the sensing layer 1 and facility layer 3 can realize a multimode optical communication structure across layers to further improve data throughput.

[0065] Regarding the specific structural configuration of the aforementioned facility layer 3, this implementation is as follows: Figures 1 to 3As shown, facility layer 3 includes a power management module 31, a micro battery 32, a memory chip 33, and a high-speed interface module 34. The micro battery 32 is disposed in the battery cavity 35 of the glass panel 7 of facility layer 3 and is electrically connected to the power management module 31, the memory chip 33, and the high-speed interface module 34. The high-speed interface module 34 communicates with the memory chip 33, the optical I / O chip 6 between computing layer 2 and facility layer 3, and the external device to be connected. The battery cavity 35 is formed by dry etching, the micro battery 32 is embedded in the battery cavity 35, and a nickel sealing sheet is covered on the top of the battery cavity 35 to encapsulate the micro battery 32 in facility layer 3.

[0066] Specifically, regarding the structure of the micro battery 32 and the encapsulation structure of the battery cavity 35, this embodiment is, for example... Figures 1 to 3 As shown, the battery cavity 35 has a depth of 250-350μm; the micro battery 32 is a solid-state thin-film lithium battery with a thickness of 180-280μm and an energy density of 350Wh / L; the nickel sealing sheet covering the top of the battery cavity 35 is fused to the glass panel 7 around the battery cavity 35 by nickel-glass laser ring welding, so as to help reduce the resistance of the power supply path with an extremely short power supply path.

[0067] When applying the technology, by increasing the depth of the battery cavity 35 to at least 250-350 μm, it is ensured that the micro battery 32 still has enough space (at least 70 μm) for battery placement and encapsulation even with the thinnest battery thickness (180 μm), thus avoiding the impact of mechanical stress on the battery.

[0068] The power management module 31 of facility layer 3 detects and dynamically allocates power to the embedded micro battery 32. During system startup, the power management module 31 adjusts the output voltage according to the power consumption requirements of computing layer 2 to ensure stable power supply to sensing layer 1 and computing layer 2. The micro battery 32 is directly connected to the power supply network via a vertical conductive path 5 (TGV), resulting in extremely low power loss. The high-speed interface module 34 is responsible for data communication with external devices, transmitting the output results processed by computing layer 2.

[0069] This structure significantly improves the continuity of on-chip power supply and system integration, avoiding the delay and energy consumption problems caused by traditional external power supply wiring; by encapsulating the micro battery 32 with a nickel sealing sheet, the airtightness of the cavity and the reliability of the structure are improved, and resistance and heat accumulation are effectively reduced under extremely short power supply paths.

[0070] In addition, the high-speed interface module 34 supports PCIe or fiber optic communication standards to enable multi-module cascading and external system expansion; the material of the micro battery 32 is selected from solid lithium, lithium sulfur or thin-film sodium ion system according to application requirements to adapt to high temperature or high frequency operating environments.

[0071] Regarding the specific structure and arrangement of the aforementioned vertical conductive path 5 and optical waveguide path 41, this embodiment is as follows: Figures 1 to 3 As shown, a glass via 51 with a aperture ≤10μm is formed on the glass panel 7. A Ti / Cu composite seed layer is deposited inside the via wall, and copper is filled into the glass via 51 by electroplating to form a vertical conductive path 5. An optical waveguide path 41 is set in a region within 15μm of the outer periphery of the glass via 51, and the optical waveguide path 41 is a silicon nitride optical waveguide to reduce electromagnetic crosstalk and optical loss. A TGV pad 52 is set at the glass via 51, and an optical I / O chip 6 is flip-chip soldered to the TGV pad 52. The optical I / O chip 6 senses the optical communication information of the silicon nitride optical waveguide and converts it into an electrical signal, forming an electrical communication through the vertical conductive path 5 to realize high-speed photoelectric signal conversion.

[0072] In application, the vertical conductive path 5 formed in the glass panel 7 serves as the interlayer vertical interconnect for electrical signals, while the silicon nitride optical waveguide path 41 serves as the interlayer optical signal transmission. The optical I / O chip 6 is flip-chip bonded to the TGV pad 52, capable of simultaneously sensing optical signals from the optical waveguide and converting them into electrical signals, or converting electrical signals into optical signals for transmission to adjacent layers. Through this dual-channel optical-electrical interconnect structure, the system achieves cross-layer optical and electrical collaborative communication, enabling parallel processing of multiple tasks with low latency between different functional layers. Furthermore, this structure significantly reduces parasitic capacitance and signal crosstalk, achieves physical isolation between electrical and optical paths, solves the loss and heat accumulation problems that occur in traditional TSV interconnect methods during high-frequency signal transmission, and improves signal integrity and system stability.

[0073] Since the integration of the optical waveguide path 41 and the vertical conductive path 5 (TGV) in the glass panel 7 may cause electromagnetic crosstalk problems; although silicon nitride optical waveguides can reduce optical loss, electromagnetic crosstalk may still affect signal integrity during high-frequency signal transmission; therefore, the optical waveguide path 41 must be located within a region of at least 15μm outside the structure of the glass via 51 to minimize electromagnetic crosstalk and reduce optical loss as much as possible.

[0074] Furthermore, an insulating material, such as silicon dioxide, can be added between the optical waveguide path 41 and the vertical conductive path 5 to further reduce electromagnetic crosstalk between them. Alternatively, by optimizing the wiring design and adjusting the layout of the optical waveguide path and the vertical conductive path to increase the distance between them and reduce electromagnetic coupling, the impact of electromagnetic crosstalk between the optical waveguide path 41 and the vertical conductive path 5 on the integrity of high-frequency signals can be reduced.

[0075] In addition, the material of the optical waveguide can be selected from a multilayer composite system of silicon nitride, silicon dioxide or oxide nitride according to the wavelength of the optical signal to achieve optical signal transmission with different bandwidths; the metal filling material of the vertical conductive path 5 can also be Cu-Al or Cu-Mo alloy to optimize conductivity and thermal diffusion performance.

[0076] Among them, a microchannel cooling structure is added around the vertical conductive path 5 (TGV) of computing layer 2 to facilitate dynamic thermal management of large-area AI embedded computing systems during high power density operation.

[0077] A second implementation example of a large-area AI embedded computing system Figure 3 As shown, the difference between this embodiment and the first embodiment is that a PMIC chip 8 is embedded in the glass panel 7 of the facility layer 3. The PMIC chip 8 is electrically connected to the micro battery 32 and the power management module 31 to realize dynamic voltage regulation from positive 0.8V to negative 1.2V for the power management module 31 to perform module-level dynamic power scheduling.

[0078] When applied, the PMIC chip 8 embedded in facility layer 3 works in conjunction with the micro battery 32 and power management module 31 to achieve dynamic voltage regulation within the range of +0.8 V to -1.2 V through the bidirectional power scheduling logic integrated on the PMIC chip 8. During the operation of the large-area AI embedded computing system, the PMIC chip 8 dynamically adjusts the output voltage according to the load power changes of computing layer 2, so that each functional module is at the optimal energy efficiency point.

[0079] When the AI ​​computing chip enters high computing power mode, the PMIC chip 8 quickly increases the power supply voltage to ensure computing stability; in standby or low power mode, it automatically reduces the output voltage to reduce energy waste; this design can effectively solve the problems of high power consumption, slow response and unbalanced power supply under traditional fixed power supply methods, and significantly improve the system's energy efficiency ratio and power supply reliability.

[0080] The second embodiment of the large-area AI embedded computing system differs from the first embodiment in that the electrical communication of the glass panel 7 is achieved by arranging a flexible thin film and wiring, reducing or eliminating the setting of vertical conductive paths 5; a flexible thin film layer is thermo-bonded to the surface of the glass panel 7, and the flexible thin film layer is a flexible polyimide interlayer; a Cu / Ni / Au multilayer wiring is constructed on the flexible thin film layer between the glass panel 7 of the computing layer 2 and the computing chipset 21, and the electrical signals of the computing chipset 21 and the optical I / O chip 6 are transmitted through the Cu / Ni / Au multilayer wiring.

[0081] In applications, the electrical communication structure in large-area AI embedded computing systems can also be achieved by thermo-bonding a flexible polyimide (PI) thin film layer to the surface of the glass panel 7. This flexible thin film layer contains pre-fabricated Cu / Ni / Au multilayer wiring for transmitting high-speed electrical signals between the computing chipset 21 and the optical I / O chip 6. This structure effectively replaces the traditional vertical conductive path 5 (TGV) wiring method, and also reduces signal path inductance and parasitic capacitance, thereby reducing high-frequency signal loss.

[0082] During system operation, the flexible thin film layer serves as a horizontal electrical connection and stress buffer. It can undergo micro-deformation with temperature changes to absorb the difference in thermal expansion between layers and prevent cracks from appearing in the glass panel 7 due to thermal stress concentration. This structural solution also simplifies the filling process of the glass through-hole 51 in the glass panel 7, significantly improving yield and maintainability.

[0083] Based on the above embodiments of large-area AI embedded computing systems, a glass panel-level integrated packaging method is provided, which includes the structure of a large-area AI embedded computing system and comprises the following steps:

[0084] (1) Optical waveguide paths and vertical conductive paths are fabricated on multilayer glass panels respectively;

[0085] (2) Prepare functional panels for the sensing layer, computing layer and facility layer respectively; including the fabrication of absorbers and detectors in the sensing layer, the fabrication of computing chipsets and optical I / O chips in the computing layer, and the fabrication of power management modules, battery cavities, memory chips and high-speed interface modules in the facility layer;

[0086] (3) The sensing layer, the computing layer and the facility layer are stacked sequentially using a high-precision alignment and 3D hybrid bonding process to achieve optoelectronic integrated interconnection;

[0087] (4) After glass-to-glass thermo-press bonding, a package structure is formed by embedding a micro battery in the battery cavity of the facility layer and by welding a nickel sealing sheet to the battery cavity by nickel-glass laser ring welding.

[0088] Specifically, in step (3), the 3D hybrid bonding process includes two stages: low-temperature bonding and high-temperature annealing. In the low-temperature bonding stage, at a temperature of ≤250℃, the glass panels of the sensing layer, computing layer and facility layer are first hot-pressed bonded to the flexible film, then the optical I / O chip is welded, and finally the optical waveguide path and optical I / O chip are encapsulated using low-temperature curing epoxy resin. In the high-temperature annealing stage, at a temperature of ≥300℃, the glass vias are annealed in an H2 atmosphere to repair electroplating defects and reduce resistivity. The computing chipset is selectively annealed using infrared laser to avoid thermal damage to the encapsulated optoelectronic devices.

[0089] When applied, the entire packaging process includes the following steps in sequence: photoelectric path fabrication, functional layer fabrication, 3D hybrid bonding, and micro-battery packaging.

[0090] Before the large-area AI embedded computing system is stacked, optical waveguide paths and vertical conductive paths are first fabricated on each glass panel, and device modules are embedded on the corresponding functional layers. Then, three-dimensional hybrid bonding is performed using high-precision alignment technology to stack the sensing layer, computing layer, and facility layer layer by layer to achieve optoelectronic interconnection.

[0091] In the low-temperature bonding stage (≤250℃), the glass substrate and flexible film are hot-pressed and bonded together, and the optical I / O chip is welded. Low-temperature curing epoxy resin is used to seal the optical waveguide and the chip to ensure structural integrity and optical signal stability. In the high-temperature annealing stage (≥300℃), the vertical conductive path (TGV) is annealed and repaired in an H2 atmosphere to reduce the resistivity of the metal via. The computing chipset is selectively annealed using infrared laser to ensure performance recovery without damaging the optoelectronic devices.

[0092] This process path achieves multi-layer optoelectronic heterogeneous integration while taking into account low thermal stress and high connection strength, solving the problems of interface peeling and optical waveguide mismatch caused by the thermal expansion mismatch of multiple materials in traditional packaging.

[0093] In addition, the 3D hybrid bonding process can incorporate vacuum-assisted pressing and local laser reflow control technology to further improve the alignment accuracy between layers; after annealing, plasma cleaning and SiO2 surface activation processes can be used to enhance the bonding strength; microchannel cooling structures can be embedded between the packaging layers for local thermal management of high-power modules.

[0094] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described.

Claims

1. A large-area AI embedded computing system, characterized in that, It includes a sensing layer, a computing layer and a facility layer arranged in a stacked manner from top to bottom. The sensing layer is used to receive the incident light to be detected and generate a sensing signal. The sensing signal enters the computing layer for data processing and outputs data. The facility layer supports the operation of the sensing layer and the computing layer through optoelectronic interconnection, receives the data output by the computing layer and transmits data to external devices. The sensing layer, the computing layer, and the facility layer are each independently mounted on a glass panel. Optical waveguide paths and / or vertical conductive paths are provided in each of the glass panels. Optical I / O chips are integrated between each layer and packaged through three-dimensional stacking to form an interlayer optical interconnect network for electrical and optical interconnection, thereby realizing high-speed, low-power optoelectronic collaborative data transmission.

2. The large-area AI embedded computing system according to claim 1, characterized in that, The sensing layer includes an absorber and a detector; Multiple detectors are arranged in a matrix on the glass panel of the sensing layer to form a matrix detection unit, and the absorber is arranged on the matrix detection unit to receive the light to be detected; The matrix detection unit, interconnected with the absorber, amplifies the incident light signal and converts it into the sensing signal in the form of an electrical signal. The sensing signal is then transmitted to the optical I / O chip between the computing layer and the sensing layer via the interlayer optical interconnect network in the form of optical conduction. The optical I / O chip performs photoelectric conversion and communicates with the modules of the computing layer.

3. The large-area AI embedded computing system according to claim 1, characterized in that, The computing layer includes a computing chipset consisting of an AI-FPGA module, a CPU module, and a GPU module; The computing chipset is connected to the optical I / O chip between the computing layer and the sensing layer, and between the computing layer and the facility layer, for optical and electrical communication connections between the computing layer and the sensing layer and the facility layer; The computing chipset of the computing layer receives instructions from the facility layer and sensing signals from the sensing layer through the optical I / O chip between layers, and is used to perform real-time data processing, machine learning inference and algorithm acceleration, and completes high-speed optical signal communication and photoelectric conversion between layers through the optical I / O chip.

4. The large-area AI embedded computing system according to claim 1, characterized in that, The facility layer includes a power management module, a micro battery, a memory chip, and a high-speed interface module. The micro battery is disposed in the battery cavity of the glass panel of the facility layer and is electrically connected to the power management module, the memory chip, and the high-speed interface module. The high-speed interface module is connected and communicates with the memory chip, the optical I / O chip between the computing layer and the facility layer, and the external device to be connected. The battery cavity is formed by dry etching, the microcell is embedded in the battery cavity, and a nickel sealing sheet is placed on top of the battery cavity to encapsulate the microcell in the facility layer.

5. The large-area AI embedded computing system according to claim 4, characterized in that, The depth of the battery cavity is 250-350μm; The micro battery is a solid-state thin-film lithium battery with a thickness of 180-280μm and an energy density of 350Wh / L; The nickel sealing sheet covering the top of the battery cavity is fused to the glass panel surrounding the battery cavity by nickel-glass laser ring welding, thereby reducing the resistance of the power supply path by matching the length of the power supply path with the depth of the battery cavity.

6. The large-area AI embedded computing system according to claim 5, characterized in that, A PMIC chip is embedded in the glass panel of the facility layer. The PMIC chip is electrically connected to the micro battery and the power management module to realize dynamic voltage regulation from positive 0.8V to negative 1.2V for the power management module to perform module-level dynamic power scheduling.

7. The large-area AI embedded computing system according to claim 1, characterized in that, Glass vias with a diameter ≤10μm are formed on the glass panel, a Ti / Cu composite seed layer is deposited inside the via wall, and copper is filled into the glass vias by electroplating to form the vertical conductive path. The optical waveguide path is located within 15 μm of the outer periphery of the glass through-hole structure, and the optical waveguide path is a silicon nitride optical waveguide, which is used to reduce electromagnetic crosstalk and reduce optical loss. A TGV pad is provided at the glass through-hole, and the optical I / O chip is flip-chip soldered to the TGV pad. The optical I / O chip senses the optical communication information of the silicon nitride optical waveguide and converts it into an electrical signal. Electrical communication is formed through the vertical conductive path to realize high-speed photoelectric signal conversion.

8. The large-area AI embedded computing system according to claim 3, characterized in that, A flexible film layer is hot-pressed onto the surface of the glass panel, and the flexible film layer is a polyimide flexible interlayer. A Cu / Ni / Au multilayer wiring is constructed on the flexible thin film layer between the glass panel of the computing layer and the computing chipset, and the electrical signals of the computing chipset and the optical I / O chip are transmitted through the Cu / Ni / Au multilayer wiring.

9. A glass panel-level integrated packaging method, applied to the large-area AI embedded computing system according to any one of claims 1 to 8, characterized in that, Includes the following steps: (1) Optical waveguide paths and vertical conductive paths are fabricated on multilayer glass panels respectively; (2) Prepare functional panels for the sensing layer, computing layer and facility layer respectively; including the fabrication of absorbers and detectors in the sensing layer, the fabrication of computing chipsets and optical I / O chips in the computing layer, and the fabrication of power management modules, battery cavities, memory chips and high-speed interface modules in the facility layer; (3) The sensing layer, the computing layer and the facility layer are stacked sequentially using a high-precision alignment and 3D hybrid bonding process to achieve optoelectronic integrated interconnection; (4) After glass-to-glass thermo-press bonding, a micro battery is embedded in the battery cavity of the facility layer and a nickel sealing sheet is welded to the battery cavity by nickel-glass laser ring welding to form an encapsulation structure.

10. The glass panel-level integrated packaging method according to claim 9, characterized in that, The 3D hybrid bonding process includes two stages: low-temperature bonding and high-temperature annealing. In the low-temperature bonding stage, at a temperature of ≤250℃, the glass panels of the sensing layer, computing layer and facility layer are first thermo-press bonded to the flexible film, then the optical I / O chip is welded, and finally the optical waveguide path and optical I / O chip are encapsulated using low-temperature curing epoxy resin. During the high-temperature annealing stage, the glass vias are annealed in an H2 atmosphere at a temperature of ≥300℃ to repair electroplating defects and reduce resistivity. The computing chipset is selectively annealed using infrared laser to avoid thermal damage to the packaged optoelectronic devices.

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