Multi-branch cooperative current limiting hybrid DC circuit breaker and control method

Abstract

The invention discloses a multi-branch collaborative current-limiting hybrid direct current circuit breaker and a control method, the circuit breaker adopts a thyristor and diode hybrid commutation structure, a double-capacitor collaborative charging mechanism and a series current-limiting inductor are combined, and rapid current limiting and reliable breaking of fault current are realized. The circuit breaker comprises seven branches including a current-carrying branch, a current-limiting branch, a commutation branch, a transfer branch, a drainage branch, a charging and discharging branch and a breaking branch, and three working modes including a fault clearing mode, a current-limiting recovery mode and a maintenance power-off mode are provided through cooperation of the multiple branches. According to the charging and discharging branch, through a C1 and C2 series connection charging mechanism, reasonable model selection is combined, and the same topology is adapted to different voltage grades from + / -10kV to + / -500kV; the transfer branch realizes one-path multi-purpose, and the use amount of IGBTs is reduced by more than 70%.

Description

Technical Field

[0001] This invention relates to the field of power system protection device technology, and in particular to a hybrid DC circuit breaker with multi-branch coordinated current limiting and its control method. Background Technology

[0002] As the proportion of renewable energy in the global energy mix continues to increase, its inherent intermittent and volatile characteristics pose unprecedented challenges to the stable operation of power systems. Especially in long-distance, high-capacity transmission scenarios, traditional high-voltage alternating current (HVAC) transmission methods, limited by synchronicity, capacitance effects, and power flow control capabilities, are struggling to meet the flexibility and stability requirements of the new energy structure. In contrast, high-voltage direct current (HVDC) transmission, with its significant advantages such as high transmission efficiency, low line loss, strong controllability, and low system inertia requirements, has become a crucial technological path supporting the future energy internet and large-scale clean energy transmission, and has seen widespread application and rapid development in recent years.

[0003] However, due to their inherent characteristics such as low impedance and low inertia, DC systems experience a rapid surge in fault current within a very short time when a fault occurs. Furthermore, the lack of a natural zero-crossing point makes it difficult for the fault current to be interrupted naturally, severely testing the system's protection and circuit-breaking capabilities. As a key piece of equipment for fault isolation in DC systems, the performance of high-voltage DC circuit breakers directly affects the system's safety and reliability.

[0004] Currently, high-voltage DC circuit breakers are mainly classified into three types: mechanical, all-solid-state, and hybrid. Mechanical circuit breakers have slow breaking speeds, making it difficult to meet the requirements for rapid fault isolation; all-solid-state circuit breakers have fast breaking speeds, but suffer from high on-state losses and high costs; hybrid circuit breakers combine the advantages of both, but still have the following technical problems: The commutation branch often uses a large number of pure thyristors in series structure. A single circuit breaker requires 16 to 30 thyristors, which is expensive and the large number of thyristors in series leads to a decrease in reliability.

[0005] Transfer branches, commutation branches, and recovery branches are usually designed independently, resulting in complex current paths, a large number of IGBT groups, high conduction losses, and high device costs.

[0006] Poor voltage level adaptability. In existing technologies, the pre-charge voltage of the breaking capacitor is usually fixed, making it difficult to adapt to the application requirements of different voltage levels. This results in the same topology not being flexibly applicable to different voltage levels such as ±10kV to ±500kV, requiring the redesign of capacitor parameters for different levels, increasing R&D costs and time.

[0007] Fourth, energy absorption mainly relies on a single metal oxide surge arrester (MOA), which has a long energy leakage time and is prone to voltage rebound. Furthermore, MOAs are subjected to high-energy surges for extended periods, limiting their lifespan.

[0008] To address the aforementioned issues, there is an urgent need to develop a novel hybrid high-voltage DC circuit breaker topology and its control method that combines rapid disconnection, effective current limiting, low cost, high reliability, and strong adaptability. Summary of the Invention

[0009] Technical objective: To address the deficiencies in existing technologies, this invention discloses a hybrid DC circuit breaker and control method with multi-branch coordinated current limiting. Through the coordinated operation of multiple branches, three operating modes are available, enabling rapid current limiting and reliable interruption of fault current, while significantly reducing device costs and improving voltage level adaptability.

[0010] Technical solution: To achieve the above technical objectives, the present invention adopts the following technical solution.

[0011] A hybrid DC circuit breaker with multi-branch coordinated current limiting includes: a current-carrying branch, a current-limiting branch, a commutation branch, a transfer branch, a current-diverting branch, a charging / discharging branch, and a disconnecting branch. The current-carrying branch includes an ultra-fast mechanical switch (UFD) and a load transfer switch (LCS) connected in series. One end of the current-carrying branch is connected to the high-voltage DC line interface, and the other end is connected to the current-limiting branch interface. The current limiting circuit includes a current limiting inductor L dc Current-limiting inductor L dc It is connected in series with the load transfer switch LCS and is located between the right end of the current-carrying branch and the high-voltage DC line; The commutation branch includes four sets of thyristor-diode hybrid components Q1, Q2, Q3, and Q4. Q1, Q2, Q3, and Q4 form an H-bridge topology. Q1 and Q3 are connected in series to the positive DC side, and Q2 and Q4 are connected in series to the negative DC side. The connection point of Q1 and Q2 is the first internal node A, and the connection point of Q3 and Q4 is the second internal node B. The transfer branch includes a series-connected thyristor T2 and m series-connected IGBT groups T3, and is connected between the first internal node A and the second internal node B, wherein, m≥1 The transfer branch is used to achieve three functions: in the pre-charge mode, it participates in the series charging circuit of C1 and C2; in the fault disconnection mode, it provides a controllable switching path; and in the current limiting recovery mode, it provides a temporary channel. The current-draining branch includes a thyristor T5 connected in series and an energy-absorbing resistor R. d The entire system is connected in parallel to the current-limiting inductor L. dc At both ends, the energy-absorbing resistor R d The resistance value depends on the current-limiting inductor L. dc The parameters of the breaking capacitor C1 are determined to further release the inductor L after the MOA discharges energy. dc Stored energy; The charging / discharging circuit includes capacitor C1 and two sub-branches. One sub-branch consists of a pre-charge capacitor C2 connected in series with switch K1, and the other sub-branch consists of a resistor R1 connected in series with switch K2. The two sub-branches are connected in parallel, with one end connected to capacitor C1 and the other end grounded, forming a C1-C2 series charging circuit. The pre-charge voltage U of C1 is controlled by adjusting the capacitance of C2 and the resistance of R1. C1 ; The disconnected branch includes a first disconnected branch and a second disconnected branch connected in parallel between the first internal node A and the second internal node B. The first disconnected branch includes a thyristor T4 connected in series and k series diodes D1. The first disconnected branch is connected in series with capacitor C1. k≥3 The second branch includes the metal oxide surge arrester (MOA).

[0012] Preferably, the current-limiting inductor L dc The inductance value ranges from 10mH to 500mH, and the current-limiting inductor L... dc The inductance value is determined based on the fault current rise rate limit requirement and satisfies the following relationship: , Among them, U dc Let (di / dt) be the system DC voltage. max The maximum allowable rate of rise of fault current.

[0013] Preferably, each thyristor-diode hybrid assembly consists of one thyristor and n diodes connected in series, and n≥ 3 The number of diodes, n, is determined according to the following formula: , Among them, U dc U is the system DC voltage, k is the safety margin factor, and U is the system DC voltage. d This represents the rated voltage of a single diode, and ⌈⌉ indicates rounding up.

[0014] Preferably, the energy-absorbing resistor R d The formula for calculating the resistance value is as follows: , is the damping coefficient.

[0015] Preferably, the pre-charge voltage U of C1 C1 Satisfying the relation U C1 =U C2 +U Forward , among which, U C1 U is the pre-charge voltage of capacitor C1. C2 U is the pre-charge voltage of capacitor C2. Forward It is the sum of the forward voltage drops of Q1 and T2.

[0016] Preferably, capacitor C1 is used as the breaking capacitor, and its capacitance value is determined according to the energy balance principle, satisfying the following relationship: , Among them, L dc I is the current-limiting inductance value. f U is the expected peak fault breaking current. MOA U is the operating voltage of the metal oxide surge arrester (MOA). dc This is the system DC voltage.

[0017] Preferably, the charging resistor R1 satisfies: ; where τ takes values ​​from 100ms to 1000ms.

[0018] The present invention also discloses a control method for a hybrid DC circuit breaker with multi-branch cooperative current limiting, used to control any of the hybrid DC circuit breakers with multi-branch cooperative current limiting described above. The control method includes three working modes and control timing. Pre-charge mode: When the system is powered on, if the circuit breaker is placed at the left end of the high voltage DC transmission line, the current direction is to the right. This stage belongs to the normal operation stage. Q1 in the commutation branch, thyristor T2 and IGBT group T3 in the transfer branch, and switches K1 and K2 in the charging branch are turned on to form a charging circuit: positive terminal → Q1 → T2 → T3 → C1 → C2 → K1 → ground. C1 and C2 are charged in series. After charging is completed, Q1 and T2 are turned off naturally, and K1 and K2 are turned off. Fault clearing mode: The fault clearing mode is divided into the initial stage t0~t2, the disconnection stage t2~t7, and the energy release stage t7~t8, which are executed sequentially according to the time sequence; Current-limiting recovery mode: After the fault current is transferred to the transfer branch at time t2, if the system determines that it is a transient fault and does not require fault clearing, current recovery is required. This is achieved using the current-limiting inductor L.dc While continuously limiting the current, the UFD is closed. After the closing is completed, the LCS switch is turned on, and the IGBT group T3 of the transfer branch is turned off. At this time, the current is completely restored to the current-carrying branch.

[0019] Preferably, during the initial stage t0~t2, when a fault occurs in the DC line on the right side of the circuit breaker at time t0, and the system detects the fault current at time t1, a fault clearing command is sent to the circuit breaker, a tripping request is output, and the current-carrying branch T is immediately shut off. 1b Immediately, the thyristors T2 and T3 in the commutation branch Q1, Q4, and transfer branch of the circuit breaker are turned on. At the same time, the UFD starts to trip when the current in the current-carrying branch is 0, and the current-limiting inductor L... dc Limit the rate of current rise, provide the first stage of current limiting, and complete the tripping after reaching the rated opening distance at time t2, thus completing the initial stage and entering the disconnection stage. During the breaking phase (t2~t7), if the system completes fault determination, the circuit breaker receives the fault current clearing command. At t3, a trigger signal is given to thyristor T4 in the first branch of the breaking branch, turning on T4 and capacitor C1 begins to discharge. At this time, thyristor T2 in the transfer branch turns off under the action of reverse voltage, and the fault current is transferred to the first branch of the breaking branch. The discharge of C1 generates reverse voltage, further suppressing current growth. At t4, capacitor C1 enters reverse charging state, with the voltage across capacitor C1 being positive at the top and negative at the bottom. At t5, it charges to the system voltage. After the fault current reaches its peak, it begins to decay but continues to charge until it reaches the MOA operating voltage at t6. The metal oxide arrester MOA is then put into use, along with L. dc Together, they work to release energy. Due to the nonlinear characteristics of the MOA, the MOA is in a low-resistance state when it is turned on, which can release a large amount of overvoltage energy in a short time. The current decreases rapidly. When the current drops to zero at time t7, the MOA is in a high-resistance state. The fault disconnection stage is completed and the energy release stage begins. During the energy dissipation phase t7~t8, the dissipation inductance L is at time t7. dc The remaining energy is used to turn on the thyristor T5 in the current-carrying branch, and the current is guided to Q4→L. dc →R d →T5 circuit provides third-stage current limiting to prevent voltage rebound, and completes all energy discharge at time t8.

[0020] Preferably, in the fault clearing mode, fault detection employs a combination of current rise rate criterion and current amplitude criterion: Criteria for rate of rise of current include: di / dt>(di / dt) set Where di / dt is the rate of rise of the fault current, (di / dt) set The current rise rate threshold is the set value. Current amplitude criteria include: I>I set ,in, I For fault current, I set The current amplitude threshold value is the set value. When both the current rise rate criterion and the current amplitude criterion are met and the duration is ≥50μs, it is determined to be a permanent fault, and the fault clearing mode is activated; when only the current amplitude criterion is met but the current rise rate criterion is not met, it is determined to be a transient fault, and the current limiting recovery mode is activated.

[0021] Beneficial effects: 1. Dual-capacitor collaborative charging mechanism; the charging and discharging branch uses a series charging circuit with C1 and C2 to achieve adjustable pre-charge voltage of C1. U C1 =U C2 +U forward Strong voltage adaptability: By adjusting the capacitance value of C2 and the resistance value of R1, the same topology can be adapted to different voltage levels from ±10kV to ±500kV without replacing the main capacitor C1. It has a high degree of modularity, shortens the R&D cycle by 50%, and reduces R&D costs. 2. Multi-purpose transfer branch: The transfer branch functions in three modes: pre-charging, fault disconnection, and current limiting recovery. Compared with the traditional solution that requires three independent branches, the number of IGBTs is reduced by 70%, the topology is simplified, and the reliability is improved. Fast disconnection speed: The total disconnection time is 5~10ms, which is 50%~67% shorter than the traditional solution (15~30ms), meeting the requirements of fast protection for DC systems. Rich working modes: It has three working modes: fault clearing, current limiting recovery, and maintenance power-off, which can flexibly meet the needs of various working conditions in DC transmission projects. 3. Series current-limiting inductor in conjunction with the current-leading branch; current-limiting inductor L dc Connected in series with the main path to limit the rate of rise of fault current. di / dt=U dc / L dc It can be controlled at 5~50A / μs, which is 80%~97% lower than the infinite current solution; the diversion branch (R d -T5) further releases L after MOA energy release. dc Energy storage to prevent voltage rebound; 4. In the thyristor-diode hybrid commutation structure, each group of the commutation branch consists of one thyristor and n diodes connected in series. Through functional separation design (the thyristor provides controllable conduction, and the diode group provides reverse withstand voltage), the number of thyristors used is reduced by more than 60% compared to traditional solutions, and the device cost is reduced by 40% to 60%. Low device cost: Thyristors are reduced by more than 60%, IGBTs by more than 70%, and device cost is reduced by 40% to 60%, resulting in good economic efficiency. 5. High reliability: Multiple branches work together, and the failure of a single device will not cause the system to fail. The system reliability MTBF is ≥100k hours. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the overall circuit topology of Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the current loop during normal operation of DC power transmission according to the present invention; Figure 3 This is a schematic diagram of the pre-charging current loop of the built-in capacitor in this invention; Figures 4 to 8 The diagram shows the current loop of each operating sequence of the DC circuit breaker of the present invention in fault clearing mode. Figures 9 to 10 This is a schematic diagram of the current loop for each operating sequence of the DC circuit breaker of the present invention in current-limiting recovery mode; Figures 11 to 15 This is a schematic diagram of the current loop for each operating sequence of the DC circuit breaker of the present invention in maintenance power-off mode. Figure 16 This is a schematic diagram of the fault clearing mode current waveform in an example of the present invention; Figure 17 This is a schematic diagram of the voltage waveform of C1 in Example C of the present invention; Figure 18 This is a partial magnified (0-3ms) diagram of the voltage waveform of C1 in Example C of the present invention. Detailed Implementation

[0023] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application. Example

[0024] As attached Figure 1 As shown, a hybrid DC circuit breaker with multi-branch cooperative current limiting in this embodiment includes: a current-carrying branch, a current-limiting branch, a commutation branch, a transfer branch, a current-diverting branch, a charging / discharging branch, and a disconnecting branch. The current-carrying branch includes an ultra-fast mechanical switch (UFD) and a load transfer switch (LCS) connected in series. One end of the current-carrying branch is connected to the high-voltage DC line interface, and the other end is connected to the current-limiting branch interface.

[0025] In this embodiment, the load transfer switch LCS is composed of IGBT group T 1aand IGBT group T 1b The components are connected in reverse series. The ultra-fast mechanical switch (UFD) has a tripping time ≤2ms and a contact distance ≥50mm. The load transfer switch (LCS) uses IGBT groups T. 1a and T 1b For IGBT modules using anti-parallel diodes, the on-state current of a single IGBT is greater than or equal to the system's rated current.

[0026] The current limiting circuit includes a current limiting inductor L dc Current-limiting inductor L dc It is connected in series with the load transfer switch LCS and located between the right end of the current-carrying branch and the high-voltage DC line; wherein, the current-limiting inductor L dc The inductance value ranges from 10mH to 500mH, preferably from 50mH to 200mH, and is used to limit the rate of rise of fault current di / dt over the entire time period, which can be controlled within the range of 5 to 50A / μs. In this embodiment, the current-limiting inductor L dc The inductance value is determined based on the fault current rise rate limit requirement and satisfies the following relationship: , Among them, U dc The system DC voltage is expressed in kV (di / dt). max The maximum permissible fault current rise rate, in A / μs, with a range of 5~50A / μs.

[0027] The commutation branch includes four sets of thyristor-diode hybrid components Q1, Q2, Q3, and Q4. Q1, Q2, Q3, and Q4 form an H-bridge topology. Q1 and Q3 are connected in series to the DC positive side, and Q2 and Q4 are connected in series to the DC negative side. The connection point of Q1 and Q2 is the first internal node A, and the connection point of Q3 and Q4 is the second internal node B.

[0028] In this embodiment, each thyristor-diode hybrid assembly consists of one thyristor and n series-connected diodes, and n≥3 In each thyristor-diode group of the commutation branch, the rated current of the thyristor is 1.2 to 2 times the rated current of the system, and the total withstand voltage of the series diodes is 1.5 to 3 times the reverse peak voltage of the thyristor. The number of diodes n is determined according to the following formula: , Among them, U dc U is the system DC voltage, k is the safety margin factor, and its value ranges from 1.5 to 2.0. d This represents the rated voltage of a single diode, and ⌈⌉ indicates rounding up.

[0029] The transfer branch includes a series-connected thyristor T2 and m series-connected IGBT groups T3, and is connected between the first internal node A and the second internal node B, wherein, m≥1 In this embodiment, m=1 The transfer branch is used to achieve three functions: in the pre-charge mode, it participates in the series charging circuit of C1 and C2; in the fault disconnection mode, it provides a controllable switching path; and in the current limiting recovery mode, it provides a temporary channel. In this embodiment, the thyristor T2 in the transfer branch is a fast thyristor with a turn-off time ≤100μs. The total on-state current capacity of the IGBT group T3 is 1.5 to 3 times the rated current of the system, and the switching frequency is ≤5kHz. After T2 and T3 are connected in series, the total withstand voltage is ≥1.2 times the rated voltage of the system.

[0030] The current-draining branch includes a thyristor T5 connected in series and an energy-absorbing resistor R. d The entire system is connected in parallel to the current-limiting inductor L. dc At both ends, the energy-absorbing resistor R d The resistance value depends on the current-limiting inductor L. dc With the parameters of the breaking capacitor C1 determined, the energy-absorbing resistor R... d The formula for calculating the resistance value is as follows: Used to further release inductance L after MOA energy dissipation. dc Stored energy; of which, The damping coefficient ranges from 2 to 5, preferably from 3 to 4; this resistance value causes the current-draining branch and the current-limiting inductor to form an underdamped or critically damped oscillating circuit, with a discharge time constant. τ=L dc / R d The value ranges from 1 to 10 ms, with 2 to 5 ms being preferred.

[0031] The charging / discharging circuit includes capacitor C1 and two sub-branches. One sub-branch consists of a pre-charge capacitor C2 connected in series with switch K1, and the other sub-branch consists of a resistor R1 connected in series with switch K2. The two sub-branches are connected in parallel, with one end connected to capacitor C1 and the other end grounded, forming a C1-C2 series charging circuit. The pre-charge voltage U of C1 is controlled by adjusting the capacitance of C2 and the resistance of R1. C1 Satisfying the relation U C1 =U C2 +U Forward , among which, U C1 U is the pre-charge voltage of capacitor C1. C2 U is the pre-charge voltage of capacitor C2. Forward It is the sum of the forward voltage drops of Q1 and T2, typically 2~5V; In this embodiment, the charging and discharging branch includes a pre-charge capacitor C2 and a resistor R1, which are connected in series with control switches K1 and K2 respectively, and then connected in parallel between the upper end of capacitor C1 and the ground point, forming a C1-C2 series charging circuit. The pre-charge voltage U of C1 is controlled by adjusting the capacitance value of C2 and the resistance value of R1. C1 Satisfying the relation U C1 =U C2 +U Forward U Forward The sum of the forward voltage drops of Q1 and T2; the charging time constant of C2 is controlled by adjusting the resistance of resistor R1 in the charging / discharging branch. τ=R 1 ×C 2 And thus regulate U C2 The size of C2 is 0.5 to 2 times the capacitance of C1.

[0032] Charging resistor R1 satisfies: ; where τ ranges from 100ms to 1000ms; and the resistance of R1 ranges from 100Ω to 2000Ω. By adjusting the capacitance of C2 and the resistance of R1, the same topology can be adapted to different voltage levels from ±10kV to ±500kV without replacing the main capacitor C1, resulting in a high degree of modularity and reduced R&D costs.

[0033] Capacitor C1 serves as a breaking capacitor, and its capacitance value is determined based on the energy balance principle, satisfying the following relationship: , Among them, L dc This is the current-limiting inductance value, in mH, I. f The expected peak fault breaking current is expressed in kA, U. MOA U is the operating voltage of a metal oxide surge arrester (MOA), measured in kV, and is typically 1.5 to 2 times the DC system voltage. dc The system DC voltage is in kV; C1 is in mF and its value ranges from 100μF to 5000μF, preferably from 500μF to 2000μF.

[0034] The disconnected branch includes a first disconnected branch and a second disconnected branch connected in parallel between the first internal node A and the second internal node B. The first disconnected branch includes a thyristor T4 connected in series and k series diodes D1. The first disconnected branch is connected in series with capacitor C1. k≥3 The second breaking branch includes a metal oxide surge arrester (MOA); in this embodiment, the first breaking branch consists of a thyristor T4 and k series-connected diodes D1 ( k≥3The first internal node A and the second internal node B are connected in parallel with the breaking capacitor C1 in series and then in parallel with the charging and discharging branch. The second breaking branch is composed of a metal oxide surge arrester (MOA). The breaking branch is connected in parallel between the first internal node A and the second internal node B.

[0035] In this invention, the key component selection process for a hybrid DC circuit breaker with multi-branch coordinated current limiting includes the following steps: Step 1: Based on the system DC voltage U dc Maximum permissible rate of current rise (di / dt) max Calculate the current-limiting inductor L dc : , Step 2: Based on the expected peak fault breaking current I f MOA operating voltage U MOA Calculate the breaking capacitor C1: , Step 3: Select pre-charge capacitor C2 based on capacitor C1: , where β takes values ​​from 0.5 to 2; Step 4: Calculate the charging resistance R1 based on the required charging time τ. , where τ takes values ​​from 100ms to 1000ms; Step 5: Based on the current-limiting inductor L dc Given capacitor C1, calculate the current-carrying resistance R. d : ,in The value can be 2 to 5, preferably 3 to 4.

[0036] This invention also discloses a control method for a hybrid DC circuit breaker with multi-branch coordinated current limiting, including the following three operating modes and control timing: Pre-charge mode: When the system is powered on, if the circuit breaker is placed at the left end of the high voltage DC transmission line, the current direction is to the right. This stage belongs to the normal operation stage. The commutation branch Q1, the thyristor T2 and IGBT group T3 in the transfer branch, and the switches K1 and K2 in the charging branch are turned on to form a charging circuit: positive terminal → Q1 → T2 → T3 → C1 → C2 → K1 → ground. C1 and C2 are charged in series. After charging is completed, Q1 and T2 are turned off naturally, and K1 and K2 are turned off. Fault Clearing Mode: The fault clearing mode is divided into three stages: initial stage t0~t2, disconnection stage t2~t7, and energy leakage stage t7~t8. (See attached diagram.) Figure 4 To be continued Figure 8 The DC circuit breaker of this invention operates in fault clearing mode. A schematic diagram of the current loop for each operating sequence is shown, with the dark path representing the current flow path for each operating sequence. It is executed according to the following timing sequence: Initial stage t0~t2, such as Figure 4 As shown, when a fault occurs in the DC line on the right side of the circuit breaker at time t0, and the system detects the fault current at time t1, it sends a fault clearing command to the circuit breaker, outputs a tripping request, and immediately shuts off the T current of the current-carrying branch. 1b Immediately, the thyristors T2 and T3 in the commutation branch Q1, Q4, and transfer branch of the circuit breaker are turned on. At the same time, the UFD starts to trip when the current in the current-carrying branch is 0, and the current-limiting inductor L... dc Limit the rate of current rise, provide the first stage of current limiting, and complete the tripping after reaching the rated opening distance at time t2, thus completing the initial stage and entering the disconnection stage. The separation phases t2~t7, such as Figure 5 As shown, if the system completes fault determination, the circuit breaker receives the fault current clearing command. At time t3, it immediately sends a trigger signal to the thyristor T4 of the first branch of the disconnecting branch, turning on T4 and causing capacitor C1 to discharge. At this time, the thyristor T2 in the transfer branch turns off under the action of reverse voltage, and the fault current is transferred to the first branch of the disconnecting branch. The discharge of C1 generates reverse voltage, further suppressing the current increase. At time t4, capacitor C1 enters the reverse charging state. At this time, the voltage across capacitor C1 is positive at the top and negative at the bottom. At time t5, it charges to the system voltage. After the fault current reaches its peak, it begins to decay, but continues to charge until time t6 when it reaches the MOA operating voltage. The metal oxide arrester MOA is then put into use, along with L. dc Together, they work to release energy. Due to the nonlinear characteristics of the MOA, the MOA is in a low-resistance state when it is turned on, which can release a large amount of overvoltage energy in a short time. The current decreases rapidly. When the current drops to zero at time t7, the MOA is in a high-resistance state. The fault disconnection stage is completed and the energy release stage begins. in, Figure 6 The attached figure shows the process of charging to the MOA operating voltage at time t6 during the disconnection phase of the fault clearing mode, when the metal oxide surge arrester MOA is put into use, and the instantaneous fault current is transferred from the first branch of the disconnection branch to the second MOA branch. Figure 7 During the fault clearing mode's disconnection phase, at times t6~t7, the fault current has been transferred to the MOA branch, and the metal oxide surge arrester MOA is put into operation, along with L. dc Together, they work to release energy. Due to the nonlinear characteristics of the MOA, the MOA is in a low-resistance state when it is turned on, which can release a large amount of overvoltage energy in a short time. The current decreases rapidly. When the current drops to zero at time t7, the MOA is in a high-resistance state. The fault disconnection stage is completed and the energy release stage begins. During the energy release phase t7~t8, such as Figure 8 As shown, at time t7, the dissipation inductance L dc The remaining energy is used to turn on the thyristor T5 in the current-carrying branch, and the current is guided to Q4→L. dc→R d →T5 circuit provides third-stage current limiting to prevent voltage rebound, and completes all energy discharge at time t8; Current-limiting recovery mode: After the fault current is transferred to the transfer branch at time t2, if the system determines that it is a transient fault and does not require fault clearing, current recovery is required. This is achieved using the current-limiting inductor L. dc While continuously limiting the current, the UFD is closed. After the closing is completed, the LCS switch is turned on, and the IGBT group T3 of the transfer branch is turned off. At this time, the current is completely restored to the current-carrying branch. See attached document Figure 9 To be continued Figure 10 The high-voltage DC circuit breaker of this invention operates in current-limiting recovery mode. The schematic diagram of the current loop for each operating sequence is shown below; the dark path represents the current flow path for each operating sequence. Among them, the appendix Figure 9 The working sequence steps based on the fault clearing mode are as follows: Figure 4 As shown, the transfer branch provides a temporary channel in current-limiting recovery mode. If the fault current is transferred at time t2, the system determines that fault clearing is not required and current recovery is necessary. (See attached diagram) Figure 10 At time t2, it is determined that current limiting recovery is required. The current limiting branch limits the current while closing the UFD. After the closing is completed, the LCS switch is turned on and the IGBT group T3 of the transfer branch is turned off. At this time, the current has been fully restored to the current-carrying branch.

[0037] Maintenance power outage mode: When the line needs to be de-energized for maintenance, the system sends a maintenance command to the circuit breaker. The circuit breaker then triggers the trip control signal. After the current is transferred to the transfer branch, there is no need to wait for the system to determine the fault. The circuit breaker then enters the above-mentioned disconnection stage to release energy.

[0038] See attached document Figure 11 To be continued Figure 15 The high-voltage DC circuit breaker of this invention operates in maintenance power-off mode. A schematic diagram of the current loop for each operating sequence is provided, with the dark path representing the current flow path for each operating sequence: (The diagram includes...) Figure 11 This indicates that when a line needs to be de-energized for maintenance, the system sends a maintenance command to the circuit breaker at time t1. The circuit breaker then triggers a tripping control signal. After the current is transferred to the transfer branch, the transfer steps are based on the fault clearing mode and the working sequence steps are as follows: Figure 4 As shown; Appendix Figure 12 To be continued Figure 15 In step t2, there is no need to wait for system fault diagnosis; proceed directly to the subsequent steps outlined above. Figure 5 To be continued Figure 8 The process described in detail involves energy release.

[0039] See attached document Figure 2In one example, the DC circuit breaker is placed at the left end of the DC transmission line. The present invention provides a schematic diagram showing that, during normal operation of the DC transmission line, current flows directly from the left end of the circuit breaker through the current-carrying branch to the right end of the circuit breaker. This includes the ultra-fast mechanical switch UFD in the current-carrying branch and T1 in the load transfer switch LCS group, and the inductor L in the current-limiting branch. dc .

[0040] See attached document Figure 3 Before any operating mode, this invention pre-charges the internal capacitors of the circuit breaker during normal DC system operation. This involves turning on the commutation branch Q1, the thyristor T2 and IGBT group T3 in the transfer branch, and switches K1 and K2 in the charging branch, forming a charging circuit: positive terminal → Q1 → T2 → T3 → C1 → C2 → K1 → ground. This charges C1 and C2 in series. At this time, the voltage across C1 is negative at the top and positive at the bottom, while the voltage across C2 is positive at the top and negative at the bottom. After charging is complete, Q1 and T2 naturally turn off, and K1 and K2 turn off. 2。 The pre-charge voltage U of C1 is controlled by adjusting the capacitance of C2 and the resistance of R1. C1 .

[0041] In fault clearing mode, fault detection uses a combination of current rise rate criterion and current amplitude criterion: Criteria for rate of rise of current include: di / dt>(di / dt) set Where di / dt is the rate of rise of the fault current, (di / dt) set The current rise rate threshold is set to a value of 3 to 10 times the rated current rise rate. Current amplitude criteria include: I>I set ,in, I For fault current, I set The threshold value for the set current amplitude is set to 1.2 to 1.5 times the rated current. When both the current rise rate criterion and the current amplitude criterion are met and the duration is ≥50μs, it is determined to be a permanent fault, and the fault clearing mode is activated; when only the current amplitude criterion is met but the current rise rate criterion is not met, it is determined to be a transient fault, and the current limiting recovery mode is activated. Example

[0042] The present invention will be further illustrated below with specific embodiments.

[0043] Calculations were performed on a ±110kV / 3kA flexible DC transmission system, where the system parameters are: rated DC voltage: U dc =±110kV, rated current: I n =3kA expected peak fault current: I f =15kA, fault current rise rate limit: (di / dt)max =20A / μs.

[0044] The key component selection method for the multi-branch cooperative current limiting hybrid DC circuit breaker based on the present invention includes the following steps: Step 1: Based on the system DC voltage U dc Maximum permissible rate of current rise (di / dt) max Calculate the current-limiting inductor L dc : , Substitute data: U dc For 110kV, (di / dt) max 20 A / μs, yielding L dc ≥5.5mH, current-limiting inductor L within the preferred range dc The inductance value range is 50mH~200mH, so select L. dc =150mH.

[0045] Step 2: Based on the expected peak fault breaking current I f MOA operating voltage U MOA Calculate the breaking capacitor C1: , Substitute data U MOA =198kV(1.8U) dc Since C1≥872μF, we choose C1=1200μF, withstand voltage 250kV, and safety margin 1.37 times.

[0046] Step 3: Select pre-charge capacitor C2 based on capacitor C1: Where β takes values ​​from 0.5 to 2, β is 0.75, and C2 = 800 μF is chosen; the relationship is met: U C1 =U C2 +U Forward Setting U C1 =78V (pre-charge voltage), U Forward =2V(Q1)+2V(T2)=4V, then U C2 =78V-4V=74V; Step 4: Calculate the charging resistance R1 based on the required charging time τ. Where τ takes values ​​from 100ms to 1000ms, and τ takes 600ms, and R1 = 500Ω is substituted into the data; Step 5: Based on the current-limiting inductor L dc Given capacitor C1, calculate the current-carrying resistance R. d : ,in The value is between 2 and 5. Based on the preferred range, α is set to 3.5. Substituting the data, we get R. d =39.1Ω, choose R d =40Ω; High-voltage thyristors are expensive. This solution uses a series structure of thyristors and diodes to save costs. Compared with the traditional pure thyristor solution (which requires 4 thyristors in series per group), this solution only requires 1 thyristor per group, and a total of 4 thyristors for four groups. The traditional solution requires 16 thyristors. The reduction in thyristors is: (16-4) / 16=75%.

[0047] Configuration of transfer branch T2+T3: Thyristor T2: rated current 5kA, withstand voltage 8kV, turn-off time 80μs; ​​IGBT group T3: 2 groups of IGBTs in parallel, each group 6.5kV / 3kA.

[0048] Thyristor T4 for disconnecting branch circuit: rated current 5kA, withstand voltage 8kV; diode D1: several connected in series, each 5kA / 4.5kV.

[0049] Configuration of the current-carrying branch: Ultra-fast mechanical switch (UFD): Opening time: 2ms, Contact distance: 50mm, Rated current: 3kA, IGBT group T 1a / T 1b Rated current of a single IGBT: 3kA, rated voltage: 6.5kV, turn-off time: 5μs.

[0050] The system was simulated using MATLAB / Simulink, with simulation parameters as described above. The simulation time ranged from 0 to 15 ms, and the time step was 1 μs. The simulation results are as follows: Figure 16 As shown, the total break time is 7.8ms: Initial phase (t0-t2): t0=0ms: Fault occurs, current I=3.0kA; t1=0.5ms: Fault detected (di / dt>20A / μs, I>3.6kA), current I=3.8kA; t1+0.05ms: T is turned off. 1b When Q1, Q4, T2, and T3 are turned on, the current begins to transfer; t1+0.2ms: the UFD begins to trip, with a current I=4.5kA; t2=2.5ms: the UFD tripping is complete, with a current I=9.73kA.

[0051] Disconnection phase (t2-t7): t2=2.5ms: UFD tripping completed, I=9.73kA, U C1 =78V, then t3=2.5ms: T4 is turned on, C1 begins to discharge, t3+0.15ms: T2 is turned off due to reverse voltage, current transfers to the disconnected branch, t4=3.2ms: C1 discharge ends (U C1=0), I=10.52kA; t4~t5: At time t4, C1 is reverse-charged, and the current continues to rise; t5=5.8ms: U C1 =-110kV (system voltage), I=14.82kA (peak value), t5~t6: current begins to decay, C1 continues to charge, t6=7.1ms: U C1 =-198kV, MOA is turned on, I=13.20kA, t6~t7: MOA rapidly dissipates energy, t7=8.3ms: current crosses zero, I=0, MOA is turned off; Energy dissipation phase (t7~t8): Energy dissipation begins at t7=8.3ms and is basically completed at t8=12.5ms.

[0052] The simulation results are in high agreement with the theoretical design, and all performance indicators meet the design requirements, verifying the correctness and effectiveness of the technical solution of this invention.

[0053] like Figure 17 As shown, in this example of the present invention, the voltage waveform of C1 is t3 = 2.5ms, T4 is turned on, and at this time U C1 =0.078kV, which is the pre-charge voltage, t=2.6ms, U C1 =0.050kV, which is the voltage during the discharge process, t4=3.2ms, U C1 =0.078kV, discharge ended, t=4.0ms, U C1 =70kV, which is the voltage during reverse charging, t5=5.8ms, U C1 =-145KV, charged to system voltage, t6=7.1ms, U C1 =-198kV, reaching the MOA operating voltage, the MOA is turned on; if Figure 18 As shown, the voltage waveform of C1 in this invention is partially magnified (0-3ms). Due to display scale issues, the local magnification was performed, and the local process is as described above.

[0054] Voltage level adaptability verification: By adjusting C2 and R1, the same topology is adapted to different voltage levels. The results can be obtained by analysis, as shown in the table below.

[0055] Table 1. Ranges of C2 and R1 for different voltage levels , By adjusting C2 and R1, the same topology can be adapted to a full range of voltage levels from ±10kV to ±500kV without replacing the main capacitor C1 and other major components, demonstrating a high degree of modularity.

[0056] In the embodiments of this application, the terms "first" and "second" (if they exist) are used only as name identifiers and do not represent the order of first and second.

[0057] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A hybrid DC circuit breaker with multi-branch coordinated current limiting, characterized in that, include: Current-carrying branch, current-limiting branch, commutation branch, transfer branch, current-draining branch, charging / discharging branch, disconnecting branch; The current-carrying branch includes an ultra-fast mechanical switch (UFD) and a load transfer switch (LCS) connected in series. One end of the current-carrying branch is connected to the high-voltage DC line interface, and the other end is connected to the current-limiting branch interface. The current limiting circuit includes a current limiting inductor L dc Current-limiting inductor L dc It is connected in series with the load transfer switch LCS and is located between the right end of the current-carrying branch and the high-voltage DC line; The commutation branch includes four sets of thyristor-diode hybrid components Q1, Q2, Q3, and Q4. Q1, Q2, Q3, and Q4 form an H-bridge topology. Q1 and Q3 are connected in series to the positive DC side, and Q2 and Q4 are connected in series to the negative DC side. The connection point of Q1 and Q2 is the first internal node A, and the connection point of Q3 and Q4 is the second internal node B. The transfer branch includes a series-connected thyristor T2 and m series-connected IGBT groups T3, and is connected between the first internal node A and the second internal node B, wherein, m≥1 The transfer branch is used to achieve three functions: in the pre-charge mode, it participates in the series charging circuit of C1 and C2; in the fault disconnection mode, it provides a controllable switching path; and in the current limiting recovery mode, it provides a temporary channel. The current-draining branch includes a thyristor T5 connected in series and an energy-absorbing resistor R. d The entire system is connected in parallel to the current-limiting inductor L. dc At both ends, the energy-absorbing resistor R d The resistance value depends on the current-limiting inductor L. dc The parameters of the breaking capacitor C1 are determined to further release the inductor L after the MOA discharges energy. dc Stored energy; The charging / discharging circuit includes capacitor C1 and two sub-branches. One sub-branch consists of a pre-charge capacitor C2 connected in series with switch K1, and the other sub-branch consists of a resistor R1 connected in series with switch K2. The two sub-branches are connected in parallel, with one end connected to capacitor C1 and the other end grounded, forming a C1-C2 series charging circuit. The pre-charge voltage U of C1 is controlled by adjusting the capacitance of C2 and the resistance of R1. C1 ; The disconnected branch includes a first disconnected branch and a second disconnected branch connected in parallel between the first internal node A and the second internal node B. The first disconnected branch includes a thyristor T4 connected in series and k series diodes D1. The first disconnected branch is connected in series with capacitor C1. k≥3 The second branch includes the metal oxide surge arrester (MOA).

2. The hybrid DC circuit breaker with multi-branch coordinated current limiting according to claim 1, characterized in that: Current-limiting inductor L dc The inductance value ranges from 10mH to 500mH, and the current-limiting inductor L... dc The inductance value is determined based on the fault current rise rate limit requirement and satisfies the following relationship: ， Among them, U dc Let (di / dt) be the system DC voltage. max The maximum allowable rate of rise of fault current.

3. A hybrid DC circuit breaker with multi-branch coordinated current limiting as described in claim 1, characterized in that: Each thyristor-diode hybrid assembly consists of one thyristor and n diodes connected in series, and n≥3 The number of diodes, n, is determined according to the following formula: ， Among them, U dc U is the system DC voltage, k is the safety margin factor, and U is the system DC voltage. d This represents the rated voltage of a single diode, and ⌈⌉ indicates rounding up.

4. A hybrid DC circuit breaker with multi-branch coordinated current limiting as described in claim 1, characterized in that: Energy absorption resistor R d The formula for calculating the resistance value is as follows: , is the damping coefficient.

5. A hybrid DC circuit breaker with multi-branch coordinated current limiting as described in claim 1, characterized in that: C1's precharge voltage U C1 Satisfying the relation U C1 =U C2 +U Forward , among which, U C1 U is the pre-charge voltage of capacitor C1. C2 U is the pre-charge voltage of capacitor C2. Forward It is the sum of the forward voltage drops of Q1 and T2.

6. A hybrid DC circuit breaker with multi-branch coordinated current limiting as described in claim 1, characterized in that: Capacitor C1 serves as a breaking capacitor, and its capacitance value is determined based on the energy balance principle, satisfying the following relationship: ， Among them, L dc I is the current-limiting inductance value. f U is the expected peak fault breaking current. MOA U is the operating voltage of the metal oxide surge arrester (MOA). dc This is the system DC voltage.

7. A hybrid DC circuit breaker with multi-branch coordinated current limiting as described in claim 1, characterized in that: Charging resistor R1 satisfies: ; where τ takes values ​​from 100ms to 1000ms.

8. A control method for a hybrid DC circuit breaker with multi-branch cooperative current limiting, used to control the hybrid DC circuit breaker with multi-branch cooperative current limiting as described in any one of claims 1-7, characterized in that, The control method includes three operating modes and control timing; Pre-charge mode: When the system is powered on, if the circuit breaker is placed at the left end of the high voltage DC transmission line, the current direction is to the right. This stage belongs to the normal operation stage. Q1 in the commutation branch, thyristor T2 and IGBT group T3 in the transfer branch, and switches K1 and K2 in the charging branch are turned on to form a charging circuit: positive terminal → Q1 → T2 → T3 → C1 → C2 → K1 → ground. C1 and C2 are charged in series. After charging is completed, Q1 and T2 are turned off naturally, and K1 and K2 are turned off. Fault clearing mode: The fault clearing mode is divided into the initial stage t0~t2, the disconnection stage t2~t7, and the energy release stage t7~t8, which are executed sequentially according to the time sequence; Current-limiting recovery mode: After the fault current is transferred to the transfer branch at time t2, if the system determines that it is a transient fault and does not require fault clearing, current recovery is required. This is achieved using the current-limiting inductor L. dc While continuously limiting the current, the UFD is closed. After the closing is completed, the LCS switch is turned on, and the IGBT group T3 of the transfer branch is turned off. At this time, the current is completely restored to the current-carrying branch.

9. The control method for a hybrid DC circuit breaker with multi-branch coordinated current limiting according to claim 8, characterized in that: During the initial phase t0~t2, when a fault occurs on the DC line on the right side of the circuit breaker at time t0, and the system detects the fault current at time t1, a fault clearing command is sent to the circuit breaker, a tripping request is output, and the current-carrying branch T is immediately disconnected. 1b Immediately, the thyristors T2 and T3 in the commutation branch Q1, Q4, and transfer branch of the circuit breaker are turned on. At the same time, the UFD starts to trip when the current in the current-carrying branch is 0, and the current-limiting inductor L... dc Limit the rate of current rise, provide the first stage of current limiting, and complete the tripping after reaching the rated opening distance at time t2, thus completing the initial stage and entering the disconnection stage. During the breaking phase (t2~t7), if the system completes fault determination, the circuit breaker receives the fault current clearing command. At t3, a trigger signal is given to thyristor T4 in the first branch of the breaking branch, turning on T4 and capacitor C1 begins to discharge. At this time, thyristor T2 in the transfer branch turns off under the action of reverse voltage, and the fault current is transferred to the first branch of the breaking branch. The discharge of C1 generates reverse voltage, further suppressing current growth. At t4, capacitor C1 enters reverse charging state, with the voltage across capacitor C1 being positive at the top and negative at the bottom. At t5, it charges to the system voltage. After the fault current reaches its peak, it begins to decay but continues to charge until it reaches the MOA operating voltage at t6. The metal oxide arrester MOA is then put into use, along with L. dc Together, they work to release energy. Due to the nonlinear characteristics of the MOA, the MOA is in a low-resistance state when it is turned on, which can release a large amount of overvoltage energy in a short time. The current decreases rapidly. When the current drops to zero at time t7, the MOA is in a high-resistance state. The fault disconnection stage is completed and the energy release stage begins. During the energy dissipation phase t7~t8, the dissipation inductance L is at time t7. dc The remaining energy is used to turn on the thyristor T5 in the current-carrying branch, and the current is guided to Q4→L. dc →R d →T5 circuit provides third-stage current limiting to prevent voltage rebound, and completes all energy discharge at time t8.

10. The control method for a hybrid DC circuit breaker with multi-branch coordinated current limiting according to claim 8, characterized in that: In fault clearing mode, fault detection uses a combination of current rise rate criterion and current amplitude criterion: Criteria for rate of rise of current include: di / dt>(di / dt) set Where di / dt is the rate of rise of the fault current, (di / dt) set The current rise rate threshold is the set value. Current amplitude criteria include: I>I set ,in, I For fault current, I set The current amplitude threshold value is the set value. When both the current rise rate criterion and the current amplitude criterion are met and the duration is ≥50μs, it is determined to be a permanent fault, and the fault clearing mode is activated; when only the current amplitude criterion is met but the current rise rate criterion is not met, it is determined to be a transient fault, and the current limiting recovery mode is activated.

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