High-voltage domain self-starting power supply generation system and method for high-side switch

Abstract

The invention provides a high-voltage domain self-starting power supply generation system and method for a high-side switch, and relates to the field of integrated circuits, and the system comprises a bias generation module, an offset control module and an operational amplifier output module. The bias generation module is used for outputting a reference voltage, a first bias voltage and a second bias voltage based on an input low-voltage enable signal and a high-voltage power supply voltage; the offset control module is used for outputting offset control voltage based on the input first bias voltage; and the operational amplifier output module is used for outputting an output voltage within a preset voltage range based on the input second bias voltage, the reference voltage, the offset control voltage and the high-voltage power supply voltage. According to the system, high-voltage starting is directly driven through a bias generation module by utilizing a low-voltage enable signal, and dependence on an auxiliary power supply is eliminated; the imbalance control module automatically adjusts imbalance control voltage through output voltage feedback and dynamically controls access of a third resistor; and the operational amplifier output module is combined with a clamping protection mechanism to lock the output pressure difference.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, in particular, to a high-voltage domain self-starting power generation system and method for high-side switches. BACKGROUND

[0002] In the field of high-voltage integrated circuit design, the power supply of high-side switches usually requires a high-voltage domain on-chip power generation circuit. The existing technology mainly adopts charge pump boosting architecture or high-voltage LDO scheme. The charge pump technology realizes voltage conversion through a multi-stage capacitor switching network, but requires the integration of flying capacitor and oscillator logic, resulting in increased chip area and additional power consumption of high-frequency clock generator; the high-voltage LDO scheme has high output voltage precision, but relies on a complex error amplifier and a precise resistance division network, with more than 40 transistors, also resulting in a significant increase in layout area. Although these schemes can realize voltage conversion from high rail to low rail, they have obvious bottlenecks in circuit complexity and energy efficiency, and the self-starting function is strongly dependent on additional on-chip circuits, limiting their promotion in efficient and compact applications. SUMMARY

[0003] The purpose of the embodiments of the present application is to provide a high-voltage domain self-starting power generation system and method for high-side switches, which can realize high-voltage self-starting without auxiliary power supply, eliminate clamping power consumption through intelligent offset control, and lock stable voltage difference through resistance programmable architecture to simplify the circuit and solve the power supply problem of high-side switches.

[0004] In a first aspect, a high-voltage domain self-starting power generation system for high-side switches is provided, which can include a bias generation module, an offset control module, and an operational amplifier output module. The low-voltage enable signal end of the bias generation module is used to access the low-voltage enable signal; the reference voltage output end of the bias generation module is connected with the reference signal input end of the operational amplifier output module, the second bias voltage output end of the bias generation module is connected with the second bias voltage input end of the operational amplifier output module, and the first bias voltage output end of the bias generation module is connected with the first bias signal input end of the offset control module; The first voltage feedback input end of the offset control module and the second voltage feedback input end of the operational amplifier output module are respectively connected with the output voltage end of the operational amplifier output module, and the offset control voltage output end of the offset control module is connected with the control signal input end of the operational amplifier output module; The bias generation module is configured to output reference voltage, first bias voltage, and second bias voltage based on the input low-voltage enable signal and high-voltage power supply voltage; The offset control module is configured to output offset control voltage based on the input first bias voltage; The operational amplifier output module is configured to output an output voltage within a preset voltage range based on the input second bias voltage, the reference voltage, the offset control voltage and the high-voltage power supply voltage.

[0005] In a possible implementation, the bias generation module includes a first transistor, a clamping diode, a first resistor, a second resistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor. A gate of the first transistor is configured as the low-voltage enable signal terminal, a drain of the first transistor is connected to an anode of the clamping diode through the first resistor, a cathode of the clamping diode is connected to a high-voltage power supply, and the anode of the clamping diode is configured as the reference voltage output terminal; and a source of the first transistor is grounded. A source of the second transistor is connected to the high-voltage power supply through the second resistor, a gate of the second transistor is connected to the anode of the clamping diode, and a drain of the second transistor is connected to a drain of the third transistor. The third transistor and the fourth transistor constitute a first current mirror structure; a gate of the third transistor is short-circuited to a drain of the third transistor; a gate of the fourth transistor is connected to the gate of the third transistor, and the gate of the fourth transistor is configured as the first bias voltage output terminal; and sources of the third transistor and the fourth transistor are grounded. A source of the fifth transistor is connected to the high-voltage power supply, a gate of the fifth transistor is short-circuited to a drain of the fifth transistor and connected to a drain of the fourth transistor, and the gate of the fifth transistor is configured as the second bias voltage output terminal.

[0006] In a possible implementation, the offset control module includes a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor. The ninth transistor and the tenth transistor constitute a second current mirror structure; a source of the ninth transistor and a source of the tenth transistor are both connected to the high-voltage power supply; a gate of the ninth transistor is short-circuited to a drain of the ninth transistor and connected to a gate of the tenth transistor. A gate of the sixth transistor is connected to a gate of the seventh transistor, and the gate of the sixth transistor and the gate of the seventh transistor are both configured as the first bias signal input terminal; a source of the eighth transistor is connected to a drain of the sixth transistor, a drain of the eighth transistor is connected to a drain of the ninth transistor, and a gate of the eighth transistor is configured as the first voltage feedback input terminal. A drain of the tenth transistor is connected to a drain of the seventh transistor, and the drain of the tenth transistor and the drain of the seventh transistor are both configured as the offset control voltage output terminal; and sources of the sixth transistor and the seventh transistor are grounded.

[0007] In a possible implementation, the operational amplifier output module comprises an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a third resistor, and a clamping diode. The gates of the fourteenth transistor and the fifteenth transistor are connected and serve as the second bias voltage input terminal together, and the sources of the fourteenth transistor and the fifteenth transistor are both connected to a high-voltage power supply. The source of the sixteenth transistor is connected to the drain of the fourteenth transistor, the source of the eighteenth transistor, and the first end of the third resistor. The gate of the eighteenth transistor serves as the control signal input terminal. The gate of the sixteenth transistor serves as the second voltage feedback input terminal, and the drain of the sixteenth transistor is connected to the drain of the eleventh transistor. The eleventh transistor and the twelfth transistor constitute a third current mirror structure; the gate of the eleventh transistor is short-circuited with the drain of the eleventh transistor and connected to the gate of the twelfth transistor; and the sources of the eleventh transistor and the twelfth transistor are both grounded. The drain of the twelfth transistor is connected to the drain of the seventeenth transistor and the gate of the thirteenth transistor respectively. The gate of the seventeenth transistor serves as the reference signal input terminal, and the source of the seventeenth transistor is connected to the drain of the eighteenth transistor and the second end of the third resistor respectively. The drain of the fifteenth transistor is connected to the drain of the thirteenth transistor and the anode of the clamping diode, and serves as the output voltage terminal. The cathode of the clamping diode is connected to the high-voltage power supply, for clamping protection, to ensure that the output voltage is within a preset range.

[0008] In a possible implementation, in the mismatch control module, the mirror ratio of the ninth transistor and the tenth transistor constituting the second current mirror structure is set as N:1, where N is an integer greater than 1.

[0009] In a possible implementation, the pressure difference between the output voltage and the high-voltage power supply voltage is configured as a fixed value.

[0010] In a possible implementation, the fixed value is set by adjusting the bias current of the bias generation module and the resistance value of the third resistor.

[0011] In a second aspect, a high-voltage domain self-start power supply generation method for a high-side switch is provided. The method is applied to the system of the first aspect, and can comprise the following steps. The bias generation module outputs a reference voltage, a first bias voltage, and a second bias voltage based on the input low-voltage enable signal and high-voltage power supply voltage. The offset control module outputs an offset control voltage based on the input first bias voltage; The operational amplifier output module outputs an output voltage within a preset voltage range based on the input second bias voltage, the reference voltage, the offset control voltage, and the high-voltage power supply voltage.

[0012] Thirdly, an electronic device is provided, which includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; Memory, used to store computer programs; When a processor executes a program stored in memory, it implements any of the steps described in the second aspect above.

[0013] Fourthly, a computer-readable storage medium is provided, wherein a computer program is stored therein, and when executed by a processor, the computer program implements the steps of any of the methods described in the second aspect above.

[0014] This application provides a high-voltage domain self-starting power supply generation system and method for high-side switches. The system includes a bias generation module, an offset control module, and an operational amplifier output module. The low-voltage enable signal terminal of the bias generation module is used to input a low-voltage enable signal. The reference voltage output terminal of the bias generation module is connected to the reference signal input terminal of the operational amplifier output module, the second bias voltage output terminal of the bias generation module is connected to the second bias voltage input terminal of the operational amplifier output module, and the first bias voltage output terminal of the bias generation module is connected to the first bias signal input terminal of the offset control module. The first voltage feedback input of the offset control module and the second voltage feedback input of the op-amp output module are connected to the output voltage terminal of the op-amp output module, respectively. The offset control voltage output of the offset control module is connected to the control signal input of the op-amp output module. A bias generation module outputs a reference voltage, a first bias voltage, and a second bias voltage based on the input low-voltage enable signal and the high-voltage power supply voltage. The offset control module outputs an offset control voltage based on the input first bias voltage. The op-amp output module outputs an output voltage within a preset voltage range based on the input second bias voltage, reference voltage, offset control voltage, and high-voltage power supply voltage. This system uses the low-voltage enable signal to directly drive high-voltage startup through the bias generation module, eliminating dependence on auxiliary power supplies. The offset control module automatically adjusts the offset control voltage through output voltage feedback, dynamically controlling the connection of the third resistor. The op-amp output module, combined with a clamping protection mechanism, ultimately locks the output voltage difference. Its core advantages lie in its fully integrated, zero-dynamic-power clamping protection and adaptive stability over a wide voltage range, significantly simplifying the system structure and improving reliability. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 A schematic diagram of a high-voltage domain self-starting power supply generation system for a high-side switch provided in this application embodiment; Figure 2 A schematic flowchart illustrating a method for generating a high-voltage domain self-starting power supply for a high-side switch, provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0017] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0018] In the field of high-voltage integrated circuit design, powering high-side switches typically requires on-chip power generation circuitry in the high-voltage domain. Existing technologies mainly employ charge pump boost architectures or high-voltage LDO solutions. Charge pump technology achieves voltage conversion through a multi-stage capacitor switching network, but it requires the integration of flying capacitors and oscillator logic, leading to increased chip area and additional power consumption from the high-frequency clock generator. While high-voltage LDO solutions offer high output voltage accuracy, they rely on complex error amplifiers and precision resistor divider networks, with over 40 transistors, also resulting in a significant increase in layout area. Although these solutions can achieve high-side to low-side voltage conversion, their circuit complexity and energy efficiency are significant bottlenecks, and their bootstrap functionality heavily relies on on-chip additional circuitry, limiting their adoption in high-efficiency, compact applications.

[0019] Therefore, this application provides a high-voltage self-starting power supply generation system for high-side switches, which solves the above-mentioned problems existing in the prior art. It can realize high-voltage self-starting without auxiliary power supply, eliminate clamping power consumption through intelligent offset control, and lock stable voltage difference through a programmable resistor architecture, thereby simplifying the circuit to solve the power supply problem of high-side switches.

[0020] The preferred embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit this application. Furthermore, the embodiments and features in the embodiments of this application can be combined with each other without conflict.

[0021] Figure 1 This is a schematic diagram of a high-voltage domain self-starting power supply generation system for a high-side switch, provided as an embodiment of this application. Figure 1 As shown, the system may include: a bias generation module, an offset control module, and an operational amplifier output module.

[0022] Among them, A, the bias generation module includes: a low-voltage enable signal terminal, a reference voltage output terminal, a first bias voltage output terminal, and a second bias voltage output terminal; B. The offset control module includes: a first bias signal input terminal, a first voltage feedback input terminal, and an offset control voltage output terminal; C. The operational amplifier output module includes: a reference signal input terminal, a second bias voltage input terminal, an output voltage terminal, a second voltage feedback input terminal, and a control signal input terminal; The connection methods for the above ports are as follows: the low-voltage enable signal terminal is used to input the low-voltage enable signal; the reference voltage output terminal is connected to the reference signal input terminal, the second bias voltage output terminal is connected to the second bias voltage input terminal, and the first bias voltage output terminal is connected to the first bias signal input terminal. The first voltage feedback input terminal and the second voltage feedback input terminal are respectively connected to the output voltage terminal, and the offset control voltage output terminal is electrically connected to the control signal input terminal.

[0023] Furthermore, A, the bias generation module also includes a first transistor NM1, a clamping diode D1, a first resistor R1, a second resistor R2, a second transistor PM1, a third transistor NM2, a fourth transistor NM3, and a fifth transistor PM2; The gate of the first transistor NM1 serves as a low-voltage enable signal terminal. The drain of the first transistor NM1 is connected to the anode of the clamping diode D1 through the first resistor R1. The cathode of the clamping diode D1 is connected to the high-voltage power supply VBB. The anode of the clamping diode D1 serves as a reference voltage output terminal. The source of the first transistor NM1 is grounded. The source of the second transistor PM1 is connected to the high voltage power supply VBB through the second resistor R2, the gate of the second transistor PM1 is connected to the anode of the clamping diode D1, and the drain of the second transistor PM1 is connected to the drain of the third transistor NM2. The third transistor NM2 and the fourth transistor NM3 form the first current mirror structure; the gate and drain of the third transistor NM2 are shorted; the gate of the fourth transistor NM3 is connected to the gate of the third transistor NM2, and the gate of the fourth transistor NM3 serves as the first bias voltage output terminal VBN; the sources of the third transistor NM2 and the fourth transistor NM3 are both grounded. The source of the fifth transistor PM2 is connected to the high-voltage power supply VBB. The gate of the fifth transistor PM2 is shorted to the drain and connected to the drain of the fourth transistor NM3. The gate of the fifth transistor PM2 serves as the second bias voltage output terminal.

[0024] The bias generation module directly drives the high-voltage domain initialization using a low-voltage enable signal EN, eliminating the need for traditional charge pumps or level shifting circuits. Specifically, the low-voltage enable signal is transmitted to the second transistor PM1 via the first transistor NM1, the first resistor R1, and the clamping diode D1, generating the reference voltage VREF and the initial bias current IBIAS. This mechanism, activated by the low-voltage enable signal EN, directly utilizes the high-voltage supply voltage VBB and the diode breakdown characteristics to generate the required bias, eliminating the need for complex multi-stage startup circuits (such as oscillators and flying capacitors), significantly reducing chip area and power consumption.

[0025] B. The offset control module also includes the sixth transistor NM4, the seventh transistor NM5, the eighth transistor NM6, the ninth transistor PM5, and the tenth transistor PM6; The ninth transistor PM5 and the tenth transistor PM6 form a second current mirror structure; the source of the ninth transistor PM5 and the source of the tenth transistor PM6 are both connected to the high voltage power supply VBB, and the gate of the ninth transistor PM5 is shorted to the drain and connected to the gate of the tenth transistor PM6. The gate of the sixth transistor NM4 is connected to the gate of the seventh transistor NM5 and together serve as the first bias signal input terminal; the source of the eighth transistor NM6 is connected to the drain of the sixth transistor NM4, the drain of the eighth transistor NM6 is connected to the drain of the ninth transistor PM5, and the gate of the eighth transistor NM6 serves as the first voltage feedback input terminal. The drain of the tenth transistor PM6 is connected to the drain of the seventh transistor NM5, and together they serve as the offset control voltage output terminal; the sources of the sixth transistor NM4 and the seventh transistor NM5 are both grounded.

[0026] The mirror ratio of the ninth transistor and the tenth transistor constituting the second current mirror structure is set to N:1, where N is an integer greater than 1.

[0027] The voltage difference between the output voltage and the high-voltage power supply voltage is configured to a fixed value, which is set by adjusting the bias current of the bias generation module and the resistance value of the third resistor.

[0028] The offset control module establishes an automatic offset control mechanism based on output voltage OUT feedback. Using the eighth transistor NM6 as the control core, the operating state (off or on) of the eighth transistor is automatically adjusted according to changes in the output voltage, thereby controlling the level of the offset control voltage VREG. When the output voltage OUT is low, the offset control voltage VREG is low, causing the eighteenth transistor PM9 to conduct and short-circuit the third resistor R3. When the output voltage OUT rises to the threshold, the eighth transistor conducts, triggering the offset control voltage to flip to a high level, forcing the eighteenth transistor to turn off, thus connecting the third resistor to the feedback loop. This process achieves voltage differential lockout without capacitor involvement, ensuring the voltage difference between the output voltage and the reference voltage, and improving the system's response speed and reliability.

[0029] C. The op-amp output module also includes the eleventh transistor NM7, the twelfth transistor NM8, the thirteenth transistor NM9, the fourteenth transistor PM3, the fifteenth transistor PM4, the sixteenth transistor PM7, the seventeenth transistor PM8, the eighteenth transistor PM9, the third resistor R3, and the clamping diode D2; The gates of the fourteenth transistor PM3 and the fifteenth transistor PM4 are connected and together serve as the second bias voltage input terminal. The sources of the fourteenth transistor PM3 and the fifteenth transistor PM4 are both connected to the high voltage power supply VBB. The source of the sixteenth transistor PM7 is connected to the drain of the fourteenth transistor PM3, the source of the eighteenth transistor PM9, and the first terminal of the third resistor R3. The gate of the eighteenth transistor PM9 serves as the control signal input terminal; The gate of the sixteenth transistor PM7 serves as the second voltage feedback input, and the drain of the sixteenth transistor PM7 is connected to the drain of the eleventh transistor NM7. The eleventh transistor NM7 and the twelfth transistor NM8 form the third current mirror structure; the gate and drain of the eleventh transistor NM7 are shorted and connected to the gate of the twelfth transistor NM8; the sources of the eleventh transistor NM7 and the twelfth transistor NM8 are both grounded. The drain of the twelfth transistor NM8 is connected to the drain of the seventeenth transistor PM8 and the gate of the thirteenth transistor NM9, respectively. The gate of the seventeenth transistor PM8 is used as the reference signal input terminal, and the source of the seventeenth transistor PM8 is connected to the drain of the eighteenth transistor PM9 and the second terminal of the third resistor R3 respectively. The drain of the fifteenth transistor PM4 is connected to the drain of the thirteenth transistor NM9 and the anode of the clamping diode D2, and serves as the output voltage terminal; The cathode of clamping diode D2 is connected to the high-voltage power supply VBB for clamping protection, ensuring that the output voltage OUT is within the preset range.

[0030] In other words, the op-amp output module can feed back the output voltage it generates to the offset control module; and output the final output voltage based on the second bias voltage, the reference voltage, and the offset control voltage.

[0031] In the op-amp output module, the differential voltage is flexibly set via single-resistor programming. The value of the third resistor directly adjusts the voltage drop (IR3×R3) in the op-amp feedback loop. Combined with the reference voltage expression (VREF=VBB-VBF), the output voltage satisfies OUT=VBB-VBF+IR3×R3. By setting the bias current and the value of the third resistor, IR3×R3=0.5V, and in conjunction with the clamping diode breakdown voltage (VBF=6V), the differential voltage ΔV=5.5V is ultimately locked. Furthermore, through programmable control of the third resistor (such as layout adjustment or external configuration), it can adapt to the needs of different application scenarios, achieving adjustable differential voltage within the range of 4.5V to 6.5V (±10% adjustment), enhancing design flexibility and process adaptability.

[0032] This application provides a high-voltage domain self-starting power supply generation system for high-side switches. The system includes a bias generation module, an offset control module, and an operational amplifier output module. The low-voltage enable signal terminal of the bias generation module is used to input a low-voltage enable signal. The reference voltage output terminal of the bias generation module is connected to the reference signal input terminal of the operational amplifier output module, the second bias voltage output terminal of the bias generation module is connected to the second bias voltage input terminal of the operational amplifier output module, and the first bias voltage output terminal of the bias generation module is connected to the first bias signal input terminal of the offset control module. The first voltage feedback input of the offset control module and the second voltage feedback input of the op-amp output module are connected to the output voltage terminal of the op-amp output module, respectively. The offset control voltage output of the offset control module is connected to the control signal input of the op-amp output module. A bias generation module outputs a reference voltage, a first bias voltage, and a second bias voltage based on the input low-voltage enable signal and the high-voltage power supply voltage. The offset control module outputs an offset control voltage based on the input first bias voltage. The op-amp output module outputs an output voltage within a preset voltage range based on the input second bias voltage, reference voltage, offset control voltage, and high-voltage power supply voltage. This system uses the low-voltage enable signal to directly drive high-voltage startup through the bias generation module, eliminating dependence on auxiliary power supplies. The offset control module automatically adjusts the offset control voltage through output voltage feedback, dynamically controlling the connection of the third resistor. The op-amp output module, combined with a clamping protection mechanism, ultimately locks the output voltage difference. Its core advantages lie in its fully integrated, zero-dynamic-power clamping protection and adaptive stability over a wide voltage range, significantly simplifying the system structure and improving reliability.

[0033] Figure 2 This is a schematic flowchart illustrating a method for generating a high-voltage domain self-starting power supply for a high-side switch, provided in an embodiment of this application. Figure 2 As shown, this method can be applied to a high-voltage domain self-starting power supply generation system for high-side switches, and the method may include: Step S210: The bias generation module outputs a reference voltage, a first bias voltage, and a second bias voltage based on the input low-voltage enable signal and high-voltage power supply voltage. Step S220: The offset control module outputs an offset control voltage based on the input first bias voltage; Step S230: The operational amplifier output module outputs an output voltage within a preset voltage range based on the input second bias voltage, the reference voltage, the offset control voltage, and the high-voltage power supply voltage.

[0034] In summary, considering the modules of a high-voltage self-starting power supply generation system for high-side switches, the above method can be understood as follows: when the low-voltage enable signal is activated to a high level, the first transistor turns on because its gate receives the enable signal, forming a self-starting path. After turning on, the first transistor causes its drain current to flow through the first resistor, thereby pulling down the potential of the anode node of the clamping diode.

[0035] The cathode of the clamping diode is connected to the high-voltage power supply. When its anode potential is pulled down below the breakdown voltage, the diode enters reverse breakdown operation, clamping the anode potential at a stable level, which serves as the reference voltage VREF output. Under typical operating conditions, the breakdown voltage of the clamping diode is designed to be 6V, therefore the reference voltage value is equal to the high-voltage power supply voltage minus 6 volts.

[0036] Simultaneously, a reference voltage VREF is applied to the gate of the second transistor, turning it on. The source of the second transistor is connected to the high-voltage power supply voltage through a second resistor, and an initial bias current IBIAS is established from the drain of the second transistor to the drain of the third transistor, flowing into the first current mirror structure composed of the third and fourth transistors.

[0037] In the first current mirror structure, the gate and drain of the third transistor are shorted, and the gate of the third transistor is connected to the gate of the fourth transistor; the sources of both are grounded. The initial bias current flowing through the third transistor is mirrored to the fourth transistor, thereby generating a first bias voltage VBN. This first bias voltage is used to provide bias for the subsequent offset control module.

[0038] Furthermore, the mirrored current flowing through the fourth transistor drives the fifth transistor. The source of the fifth transistor is connected to a high-voltage power supply, and its gate and drain are shorted and connected to the drain of the fourth transistor, thereby generating a second bias voltage VBP at the gate of the fifth transistor. This second bias voltage is used to provide bias for the op-amp output module.

[0039] The above method directly controls the initialization process of the high-voltage circuit through the low-voltage enable signal, without the need for an additional auxiliary power supply or level shifting circuit, which significantly simplifies the system architecture and reduces chip area and power consumption.

[0040] Subsequently, the first bias voltage provides the operating bias for the offset control module. The first bias voltage is applied to the gates of the sixth and seventh transistors, causing them to conduct the same quiescent current I, forming a 1:1 current mirror relationship.

[0041] At this time, since the output voltage OUT is low, the gate voltage of the eighth transistor is insufficient to turn it on, and the eighth transistor operates in the off state. This state causes the current mirror formed by the ninth and tenth transistors to fail to form an effective current path, so that the offset control voltage VREG output node is maintained at approximately ground potential by the pull-down effect of the seventh transistor.

[0042] The low-level offset control voltage causes the eighteenth transistor to operate in the deep linear region, where its on-resistance is extremely small. This is equivalent to short-circuiting the third resistor, preventing it from participating in the circuit feedback.

[0043] As the second bias voltage drives the op-amp output module to start working, the output node begins to charge, and the output voltage gradually rises. When the output voltage rises to a certain threshold (satisfying the condition that it is greater than the sum of the gate-source turn-on voltage of the eighth transistor and the drain-source voltage of the sixth transistor, i.e., OUT>VGS(NM6)+VDS(NM4)), the eighth transistor enters the linear conduction region.

[0044] The conduction of the eighth transistor provides a current path for the sixth transistor, and the current flowing through the sixth transistor is transferred to the ninth transistor. Since the current mirror formed by the ninth and tenth transistors has a 1:2 mirror ratio, the tenth transistor generates an output current twice that of the original current (IPM6=2I).

[0045] The output current is greater than the on-state current of the seventh transistor (IPM6>INM5), thus pulling the offset control voltage output node high. The high-level offset control voltage turns off the eighteenth transistor, and the third resistor is connected to the operational amplifier feedback path.

[0046] At this point, a voltage difference is formed at the input of the op-amp. This voltage difference is equal to the product of the current flowing through the third resistor and the resistance value (OUT - VREF = IR3 * R3). Combining this with the expression for the reference voltage (the reference voltage is equal to the high-voltage power supply voltage minus the breakdown voltage of the clamping diode), we can obtain that the output voltage is equal to the high-voltage power supply voltage minus the breakdown voltage plus the voltage drop across the third resistor (OUT = VBB - VBF + IR3 * R3).

[0047] By appropriately setting the current value of the bias current source and the resistance value of the third resistor, the voltage drop across the resistor is made 0.5V (IR3•R3=0.5V). Combined with the 6V breakdown voltage design value, the voltage difference between the output voltage and the high-voltage power supply voltage is ultimately stabilized at 5.5V (ΔV=VBB-OUT=5.5V). This mechanism ensures that the system maintains stable output characteristics under different operating conditions. In the above method, as the high-voltage power supply voltage changes, the operational amplifier output module can automatically adjust the output voltage to keep the voltage difference between the high-voltage power supply voltage and the output voltage stable at 5.5V. This voltage difference can be finely adjusted by adjusting the ratio of the first resistor to the third resistor, and the layout has a built-in ±10% adjustment position, effectively suppressing the influence of process deviations and ensuring stability under all operating conditions.

[0048] This application also provides an electronic device, such as... Figure 3 As shown, it includes a processor 310, a communication interface 320, a memory 330, and a communication bus 340, wherein the processor 310, the communication interface 320, and the memory 330 communicate with each other through the communication bus 340.

[0049] Memory 330 is used to store computer programs; When the processor 310 executes the program stored in the memory 330, it performs the following steps: The bias generation module outputs a reference voltage, a first bias voltage, and a second bias voltage based on the input low-voltage enable signal and high-voltage power supply voltage. The offset control module outputs an offset control voltage based on the input first bias voltage; The operational amplifier output module outputs an output voltage within a preset voltage range based on the input second bias voltage, the reference voltage, the offset control voltage, and the high-voltage power supply voltage.

[0050] The communication bus mentioned above can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not mean that there is only one bus or one type of bus.

[0051] The communication interface is used for communication between the aforementioned electronic devices and other devices.

[0052] The memory may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0053] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0054] The implementation methods and beneficial effects of the various components of the electronic device in the above embodiments for solving the problem can be found in [reference needed]. Figure 2 The steps in the illustrated embodiments are used to implement the electronic device. Therefore, the specific working process and beneficial effects of the electronic device provided in this application will not be repeated here.

[0055] In another embodiment provided in this application, a computer-readable storage medium is also provided, which stores instructions that, when executed on a computer, cause the computer to perform a high-voltage domain self-starting power supply generation method for a high-side switch as described in any of the above embodiments.

[0056] In another embodiment provided in this application, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to execute a high-voltage domain self-starting power supply generation method for high-side switches as described in any of the above embodiments.

[0057] Those skilled in the art will understand that the embodiments in this application can be provided as methods, systems, or computer program products. Therefore, the embodiments in this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the embodiments in this application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0058] This application describes embodiments of methods, apparatus (systems), and computer program products according to embodiments of this application with reference to flowchart illustrations and / or block diagrams. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0059] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0060] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0061] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected," "coupled," or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0062] Although preferred embodiments have been described in this application, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the embodiments in this application are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments in this application.

[0063] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the embodiments of this application and their equivalents, then these modifications and variations are also intended to be included in the embodiments of this application.

Claims

1. A high-voltage self-starting power supply generation system for high-side switches, characterized in that, The system includes: a bias generation module, an offset control module, and an operational amplifier output module; The low-voltage enable signal terminal of the bias generation module is used to receive the low-voltage enable signal; the reference voltage output terminal of the bias generation module is connected to the reference signal input terminal of the operational amplifier output module; the second bias voltage output terminal of the bias generation module is connected to the second bias voltage input terminal of the operational amplifier output module; and the first bias voltage output terminal of the bias generation module is connected to the first bias signal input terminal of the offset control module. The first voltage feedback input terminal of the offset control module and the second voltage feedback input terminal of the operational amplifier output module are respectively connected to the output voltage terminal of the operational amplifier output module, and the offset control voltage output terminal of the offset control module is connected to the control signal input terminal of the operational amplifier output module. The bias generation module is used to output a reference voltage, a first bias voltage, and a second bias voltage based on the input low-voltage enable signal and high-voltage power supply voltage. The offset control module is used to output an offset control voltage based on the input first bias voltage; The operational amplifier output module is used to output an output voltage within a preset voltage range based on the input second bias voltage, the reference voltage, the offset control voltage, and the high-voltage power supply voltage.

2. The system as described in claim 1, characterized in that, The bias generation module includes a first transistor, a clamping diode, a first resistor, a second resistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor; The gate of the first transistor serves as the low-voltage enable signal terminal, the drain of the first transistor is connected to the anode of the clamping diode through the first resistor, the cathode of the clamping diode is connected to the high-voltage power supply, and the anode of the clamping diode serves as the reference voltage output terminal; the source of the first transistor is grounded. The source of the second transistor is connected to the high voltage power supply through the second resistor, the gate of the second transistor is connected to the anode of the clamping diode, and the drain of the second transistor is connected to the drain of the third transistor. The third transistor and the fourth transistor form a first current mirror structure; the gate and drain of the third transistor are shorted; the gate of the fourth transistor is connected to the gate of the third transistor, and the gate of the fourth transistor serves as the first bias voltage output terminal; the sources of both the third transistor and the fourth transistor are grounded. The source of the fifth transistor is connected to a high-voltage power supply, the gate of the fifth transistor is shorted to the drain and connected to the drain of the fourth transistor, and the gate of the fifth transistor serves as the output terminal of the second bias voltage.

3. The system as described in claim 1, characterized in that, The offset control module includes a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; The ninth transistor and the tenth transistor constitute a second current mirror structure; the source of the ninth transistor and the source of the tenth transistor are both connected to a high voltage power supply, and the gate of the ninth transistor is shorted to the drain and connected to the gate of the tenth transistor. The gate of the sixth transistor is connected to the gate of the seventh transistor and together serve as the first bias signal input terminal; the source of the eighth transistor is connected to the drain of the sixth transistor, the drain of the eighth transistor is connected to the drain of the ninth transistor, and the gate of the eighth transistor serves as the first voltage feedback input terminal. The drain of the tenth transistor is connected to the drain of the seventh transistor, and together they serve as the output terminal of the offset control voltage; the sources of the sixth and seventh transistors are both grounded.

4. The system as described in claim 1, characterized in that, The operational amplifier output module includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a third resistor, and a clamping diode; The gates of the fourteenth and fifteenth transistors are connected and together serve as the second bias voltage input terminal. The sources of the fourteenth and fifteenth transistors are both connected to a high-voltage power supply. The source of the sixteenth transistor is connected to the drain of the fourteenth transistor, the source of the eighteenth transistor, and the first terminal of the third resistor; The gate of the eighteenth transistor serves as the control signal input terminal; The gate of the sixteenth transistor serves as the second voltage feedback input terminal, and the drain of the sixteenth transistor is connected to the drain of the eleventh transistor. The eleventh and twelfth transistors constitute a third current mirror structure; the gate and drain of the eleventh transistor are shorted and connected to the gate of the twelfth transistor; the sources of the eleventh and twelfth transistors are both grounded. The drain of the twelfth transistor is connected to the drain of the seventeenth transistor and the gate of the thirteenth transistor, respectively. The gate of the seventeenth transistor serves as the reference signal input terminal, and the source of the seventeenth transistor is connected to the drain of the eighteenth transistor and the second terminal of the third resistor, respectively. The drain of the fifteenth transistor is connected to the drain of the thirteenth transistor and the anode of the clamping diode, and serves as the output voltage terminal; The cathode of the clamping diode is connected to a high-voltage power supply for clamping protection, ensuring that the output voltage is within a preset range.

5. The system as described in claim 3, characterized in that, In the offset control module, the mirror ratio of the ninth transistor and the tenth transistor constituting the second current mirror structure is set to N:1, where N is an integer greater than 1.

6. The system as described in claim 4, characterized in that, The voltage difference between the output voltage and the high-voltage power supply voltage is configured to a fixed value.

7. The system as described in claim 6, characterized in that, The fixed value is set by adjusting the bias current of the bias generation module and the resistance value of the third resistor.

8. A method for generating a high-voltage self-starting power supply for a high-side switch, characterized in that, Applied to the system according to any one of claims 1-7, the method comprises: The bias generation module outputs a reference voltage, a first bias voltage, and a second bias voltage based on the input low-voltage enable signal and high-voltage power supply voltage. The offset control module outputs an offset control voltage based on the input first bias voltage; The operational amplifier output module outputs an output voltage within a preset voltage range based on the input second bias voltage, the reference voltage, the offset control voltage, and the high-voltage power supply voltage.

9. An electronic device, characterized in that, The electronic device includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor, when executing a program stored in memory, implements the steps of the method of claim 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the method described in claim 8.

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