Gating circuit and multiplexer

Abstract

The invention provides a gating circuit and a multiplexer. The circuit comprises a first switch module, a second switch module, a voltage generation module, a first current generation module and a second current generation module, and the second switch module is electrically connected with the first switch module, the voltage generation module, the first current generation module and the second current generation module. The voltage generation module is electrically connected with the first current generation module and the second current generation module, the first switch module and the second switch module are both used for being electrically connected with the positive electrode of a battery, the first switch module is used for being electrically connected with a battery output bus, and the second switch module is used for being electrically connected with a switch common bus. According to the gating circuit provided by the embodiment of the invention, the speed bottleneck of a traditional scheme is effectively broken through, the overall switching frequency and the system response real-time performance of the multiplexer are greatly improved, and the requirements of a next generation battery management system for high-frequency and real-time voltage sampling can be met.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of multiplexers, and particularly relates to a gating circuit and a multiplexer. BACKGROUND

[0002] With the continuous improvement of the requirements for endurance and safety of electric vehicles, large-scale energy storage systems and high-end portable devices, multi-section series lithium battery packs have become the core energy supply solution, and the high-precision and high-real-time monitoring of the voltage of each battery monomer by the battery management chip is the key to guaranteeing the safe operation and prolonging the service life of the battery pack. In the voltage monitoring link, the high-voltage multiplexer undertakes the core task of "gating the voltage of a single battery and transmitting it to an analog-to-digital converter", and in order to realize functions such as rapid diagnosis of battery faults and real-time triggering of dynamic balancing, the multiplexer needs to have a high-speed channel switching capability of nanoseconds to microseconds.

[0003] Currently, the mainstream gating scheme of multiplexers in the industry usually adopts a topology structure of "back-to-back high-voltage PMOS tube and gate bias resistor", and the core design idea is to use the IR drop generated by the pull-down current on the bias resistor to drive the PMOS tube to turn on through the cooperation of the bias resistor and the global gate pull-down circuit, and then realize the gating transmission of the battery voltage. However, since the gate of the PMOS tube has inherent parasitic capacitance, and the value of the bias resistor needs to consider high-voltage isolation and bias current stability, the RC charging and discharging circuit formed by the two has a large time constant, and in the switch-off stage, the charge on the gate capacitor needs to be slowly charged through the bias resistor, and the gate potential cannot be quickly restored to the high-level state required for turning off. SUMMARY

[0004] The gating circuit and the multiplexer provided by the embodiments of the application can solve the problem that in the switch-off stage of the existing gating circuit, the charge on the gate capacitor needs to be slowly charged through the bias resistor, and the gate potential cannot be quickly restored to the high-level state required for turning off.

[0005] In a first aspect, the embodiments of the application provide a gating circuit, comprising a first switch module, a second switch module, a voltage generating module, a first current generating module and a second current generating module, the second switch module is electrically connected with the first switch module, the voltage generating module, the first current generating module and the second current generating module respectively, the voltage generating module is electrically connected with the first current generating module and the second current generating module respectively, the first switch module and the second switch module are both used for being electrically connected with the positive electrode of a battery, the first switch module is used for being electrically connected with a battery output bus, and the second switch module is used for being electrically connected with a switch common bus; The first current generation module is configured to receive a first clock signal, and the second current generation module is configured to receive a second clock signal; when the first clock signal is a first level signal and the second clock signal is a second level signal, the first current generation module is configured to generate a first current according to the first level signal, the voltage generation module is configured to generate a first voltage according to the first current, and transmit the first voltage to a common node, the common node being a connection point of the first switch module and the second switch module; the first switch module and the second switch module are both configured to turn on according to the voltage of the common node, so that the voltage output by the battery is transmitted to the battery output bus and the switch common bus. When the first clock signal is a third level signal and the second clock signal is a fourth level signal, the second current generation module is configured to generate a second current according to the second clock signal, so as to increase the rising slope of the voltage of the common node, and the first switch module and the second switch module are both configured to turn off according to the voltage of the common node.

[0006] In a possible implementation manner of the first aspect, the first switch module includes a first switch tube and a second switch tube, the gate of the first switch tube and the gate of the second switch tube are both electrically connected with the second switch module, the voltage generation module and the first current generation module respectively, the drain of the first switch tube is configured to be electrically connected with the positive electrode of the battery, the source of the first switch tube is electrically connected with the source of the second switch tube, and the drain of the second switch tube is configured to be electrically connected with the battery output bus. In a possible implementation manner of the first aspect, the second switch module includes a third switch tube and a fourth switch tube, the gate of the third switch tube and the gate of the fourth switch tube are both electrically connected with the first switch module, the voltage generation module and the first current generation module respectively, the drain of the third switch tube is configured to be electrically connected with the positive electrode of the battery, the source of the third switch tube is electrically connected with the source of the fourth switch tube and the voltage generation module respectively, and the drain of the fourth switch tube is configured to be electrically connected with the switch common bus. When the voltage of the selected battery cell is greater than the voltage of the non-selected battery cell, the voltage of the switch common bus in the gating circuit corresponding to the selected battery cell is transmitted to the source of the fourth switch tube and the common node through the body diode of the fourth switch tube in the gating circuit corresponding to the non-selected battery cell, the voltage of the common node is pulled up, and the first switch module in the gating circuit corresponding to the non-selected battery cell is turned off. In a possible implementation manner of the first aspect, the voltage generation module comprises a first transistor, a second transistor and a third transistor, a source of the first transistor is electrically connected with the second switch module, a gate of the first transistor is electrically connected with a drain of the first transistor and a source of the second transistor respectively, a source of the third transistor is electrically connected with a drain of the second transistor and a gate of the second transistor respectively, and a drain of the third transistor is electrically connected with the first current generation module and the second current generation module respectively. In a possible implementation manner of the first aspect, the voltage generation module further comprises a first resistor, a first end of the first resistor is electrically connected with the source of the first transistor, and a second end of the first resistor is electrically connected with the drain of the third transistor. In a possible implementation manner of the first aspect, the first current generation module comprises a fifth switch tube and a first current source, a gate of the fifth switch tube is used for receiving the first clock signal, a drain of the fifth switch tube is electrically connected with the voltage generation module, the first switch module and the second switch module respectively, a source of the fifth switch tube is electrically connected with a first end of the first current source, and a second end of the first current source is grounded. In a possible implementation manner of the first aspect, the second current generation module comprises a current generation unit and a current mirror unit, the current mirror unit is electrically connected with the current generation unit, the voltage generation module, the first switch module, the second switch module and the first current generation module respectively; The current generation unit is used for generating a reference current when the second clock signal is a fourth level signal, and the current mirror unit is used for generating the second current according to the reference current. In a possible implementation manner of the first aspect, the current generation unit comprises a sixth switch tube and a second current source, a gate of the sixth switch tube is used for receiving the second clock signal, a drain of the sixth switch tube is electrically connected with the current mirror unit, a source of the sixth switch tube is electrically connected with a first end of the second current source, and a second end of the second current source is grounded. In a possible implementation manner of the first aspect, the current mirror unit comprises a fourth transistor and a fifth transistor, a gate of the fourth transistor is electrically connected with a gate of the fifth transistor, a drain of the fourth transistor and the current generation unit respectively, a source of the fourth transistor and a source of the fifth transistor are electrically connected with the second switch module and the voltage generation module respectively, and a drain of the fifth transistor is electrically connected with the voltage generation module, the first switch module, the second switch module and the first current generation module respectively. In a second aspect, the embodiments of the present application provide a multiplexer, comprising a plurality of the gate-on-off circuit according to any one of the first aspect, the first switch module and the second switch module in each of the gate-on-off circuit are electrically connected with the positive electrode of the corresponding battery, and are respectively used as a plurality of input terminals of the multiplexer, each of the first switch module is electrically connected with the battery output bus, and is used as an output terminal of the multiplexer.

[0007] Compared with the prior art, the embodiments of the present application have the following beneficial effects: The gate-on-off circuit provided by the embodiments of the present application comprises a first switch module, a second switch module, a voltage generating module, a first current generating module and a second current generating module. When the first clock signal is a first level signal and the second clock signal is a second level signal, the first current generating module generates a first current according to the first level signal, the voltage generating module generates a first voltage according to the first current, and the first voltage is transmitted to a common node. The first switch module and the second switch module are both turned on according to the voltage of the common node, so that the voltage output by the battery can be stably transmitted to the battery output bus and simultaneously transmitted to the switch common bus. When the first clock signal is a third level signal and the second clock signal is a fourth level signal, the second current generating module generates a second current according to the second clock signal, the second current forms a rapid charging path from the common end of the first switch module and the voltage generating module to the common node, significantly increases the rising slope of the voltage of the common node, accelerates the charging process of the gate capacitance connected at the common node, and rapidly establishes the voltage of the common node. Under the action, the first switch module and the second switch module can be quickly turned off, and the connection between the positive electrode of the battery and the battery output bus and the switch common bus is cut off.

[0008] Therefore, the gate-on-off circuit provided by the embodiments of the present application provides a stable driving voltage for the turn-on of the switch module through the synergistic effect of the first current generating module and the voltage generating module, and guarantees the accuracy of voltage transmission. At the same time, in view of the slow turn-off problem caused by the passive charging and discharging of the resistor in the traditional scheme, the second current generating module is innovatively introduced, the voltage of the common node is rapidly lifted through the active injection of the second current, the turn-off speed of the first switch module and the second switch module is greatly improved, and the delay time of the turn-off process is significantly shortened. This design effectively breaks through the speed bottleneck of the traditional scheme, greatly improves the overall switching frequency of the multiplexer and the real-time response of the system, and can meet the demand of the next generation of battery management system for high-frequency and real-time voltage sampling. BRIEF DESCRIPTION OF DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0010] Figure 1 is a principle block diagram of a gating circuit provided by an embodiment of the present application; Figure 2 is a principle block diagram of a gating circuit provided by another embodiment of the present application; Figure 3 is a circuit connection schematic diagram of a gating circuit provided by an embodiment of the present application; Figure 4 is a circuit connection schematic diagram of two gating circuits provided by an embodiment of the present application; Figure 5 is a circuit connection schematic diagram of a gating circuit provided by another embodiment of the present application; Figure 6 is a waveform schematic diagram of a clock signal provided by an embodiment of the present application.

[0011] In the figure, 101, a first switch module; 102, a second switch module; 103, a voltage generating module; 104, a first current generating module; 105, a second current generating module; 1051, a current generating unit; 1052, a current mirror unit. DETAILED DESCRIPTION

[0012] In the following description, specific details are set forth in order to provide a thorough understanding of embodiments of the present application. However, persons of ordinary skill in the art will readily recognize that embodiments of the present application can be practiced without these specific details. In other instances, well-known structures, devices, circuits, and processes have not been described in detail so as not to unnecessarily obscure the description of the present application.

[0013] It should be understood that the term "comprising" as used in the specification and in the following claims indicates the presence of the recited features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0014] It should also be understood that the term "and / or" as used in the specification and in the following claims indicates any combination of one or more of the associated listed items and all possible combinations of those items.

[0015] As used in the specification and the appended claims, the term “if’ can be interpreted as meaning “when” or “upon” or “in response to determining” or “in response to detecting” depending on the context. Similarly, the phrase “if it is determined” or “if [the recited condition or event] is detected” can be interpreted as meaning “upon determining” or “in response to determining” or “upon detecting [the recited condition or event]” or “in response to detecting [the recited condition or event]” depending on the context.

[0016] In addition, in the description of the present application and the appended claims, the terms “first”, “second”, “third”, etc. are used only to distinguish descriptions, and cannot be understood as indicating or implying relative importance.

[0017] Reference in the specification to “one embodiment” or “some embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. The appearances of the phrases “in one embodiment”, “in some embodiments”, “in other embodiments”, “in additional embodiments”, and so on, in various places in the specification are not necessarily all referring to the same embodiment, unless otherwise specifically stated. The terms “comprise”, “include”, “have”, and their conjugates, mean “including but not limited to”, unless otherwise specifically stated.

[0018] Currently, the mainstream multiplexer gating scheme in the industry usually adopts the topology structure of “back-to-back high-voltage PMOS tube and gate bias resistor”, and the core design idea is to drive the PMOS tube to turn on by using the IR drop generated by the pull-down current on the bias resistor through the cooperation of the bias resistor and the global gate pull-down circuit, and then to realize the gating transmission of the battery voltage. However, since the gate of the PMOS tube has inherent parasitic capacitance, and the value of the bias resistor needs to consider high-voltage isolation and bias current stability, the RC charging and discharging circuit formed by the two has a large time constant. In the switch-off stage, the charge on the gate capacitor needs to be slowly charged through the bias resistor, and the gate potential cannot quickly recover to the high level state required for shutdown.

[0019] Based on the above problems, the gate circuit provided by the embodiment of the application includes a first switch module, a second switch module, a voltage generation module, a first current generation module and a second current generation module. When the first clock signal is a first level signal and the second clock signal is a second level signal, the first current generation module generates a first current according to the first level signal, the voltage generation module generates a first voltage according to the first current, and the first voltage is transmitted to a common node. The first switch module and the second switch module are both turned on according to the voltage of the common node, so that the voltage output by the battery can be stably transmitted to the battery output bus and simultaneously transmitted to the switch common bus. When the first clock signal is a third level signal and the second clock signal is a fourth level signal, the second current generation module generates a second current according to the second clock signal, and the second current forms a rapid charging path from the common end of the first switch module and the voltage generation module to the common node, significantly increases the rising slope of the voltage of the common node, accelerates the charging process of the gate capacitance connected at the common node, and rapidly establishes the voltage of the common node. Under the action, the first switch module and the second switch module can be quickly turned off, and the connection between the positive electrode of the battery and the battery output bus and the switch common bus is cut off.

[0020] Therefore, the gate circuit provided by the embodiment of the application provides a stable driving voltage for the switch module through the synergistic effect of the first current generation module and the voltage generation module, and guarantees the accuracy of voltage transmission. At the same time, in view of the slow turn-off problem caused by passive charging and discharging of the resistor in the traditional scheme, the second current generation module is innovatively introduced, the voltage of the common node is rapidly lifted through the active injection of the second current, the turn-off speed of the first switch module and the second switch module is greatly improved, and the delay time of the turn-off process is significantly shortened. This design effectively breaks through the speed bottleneck of the traditional scheme, greatly improves the overall switching frequency of the multiplexer and the real-time response of the system, and can meet the demand of the next generation of battery management system for high-frequency and real-time voltage sampling.

[0021] In order to illustrate the technical solutions described in the application, the following will be described through specific embodiments.

[0022] Figure 1 The principle block diagram of the gate circuit provided by the embodiment of the application is shown. Referring to Figure 1As shown, the gate circuit includes a first switch module 101, a second switch module 102, a voltage generating module 103, a first current generating module 104 and a second current generating module 105. The second switch module 102 is electrically connected with the first switch module 101, the voltage generating module 103, the first current generating module 104 and the second current generating module 105 respectively. The voltage generating module 103 is electrically connected with the first current generating module 104 and the second current generating module 105 respectively. The first switch module 101 and the second switch module 102 are both used for electrically connecting with the positive pole of the battery. The first switch module 101 is used for electrically connecting with the battery output bus. The second switch module 102 is used for electrically connecting with the switch common bus.

[0023] Specifically, the first current generating module 104 is used for receiving a first clock signal CLK1. The second current generating module 105 is used for receiving a second clock signal CLK2. When the first clock signal CLK1 is a first level signal (such as a high level signal) and the second clock signal CLK2 is a second level signal (such as a low level signal), the first current generating module 104 generates a first current according to the first level signal. The voltage generating module 103 generates a first voltage according to the first current and transmits the first voltage to a common node. The first switch module 101 and the second switch module 102 are both turned on according to the voltage of the common node, so that the voltage output by the battery can be stably transmitted to the battery output bus and simultaneously transmitted to the switch common bus. When the first clock signal CLK1 is a third level signal (such as a low level signal) and the second clock signal CLK2 is a fourth level signal (such as a high level signal), the second current generating module 105 generates a second current according to the second clock signal CLK2. The second current forms a rapid charging path from the common end of the first switch module 101 and the voltage generating module 103 to the common node, significantly increases the rising slope of the voltage of the common node, accelerates the charging process of the gate capacitance connected at the common node, and rapidly establishes the voltage of the common node. Under the action, the first switch module 101 and the second switch module 102 can be quickly turned off, cutting off the connection between the positive pole of the battery and the battery output bus and the switch common bus.

[0024] Therefore, the gating circuit provided by the embodiment of the present application can provide a stable driving voltage for the conduction of the switch module through the cooperation of the first current generating module 104 and the voltage generating module 103, and ensure the accuracy of voltage transmission. Meanwhile, the second current generating module 105 is introduced innovatively to solve the slow turn-off problem caused by passive charging and discharging of the resistor in the traditional scheme, and the turn-off speed of the first switch module 101 and the second switch module 102 is greatly improved through the way of actively injecting the second current to significantly shorten the delay time of the turn-off process. This design effectively breaks through the speed bottleneck of the traditional scheme, greatly improves the overall switching frequency of the multiplexer and the real-time response of the system, and can meet the demand of the next generation of battery management system for high-frequency and real-time voltage sampling.

[0025] It should be noted that the above gating circuit can be used as a core channel unit of the multiplexer, and a plurality of the above gating circuits form the multiplexer, wherein the first switch module 101 and the second switch module 102 in each gating circuit are electrically connected with the positive electrode of the corresponding single battery to form a plurality of independent battery voltage input ends VIN of the multiplexer, thereby realizing the separate gating and adaptation of each battery. The second switch module 102 in each gating circuit is electrically connected with the switch common bus VPUB to form a globally unified isolation potential reference bus. The first switch module 101 in each gating circuit is electrically connected with the battery output bus to form a unified voltage output end VOUT of the multiplexer, which is used to transmit the gated single battery voltage to the subsequent sampling units such as analog-to-digital converters.

[0026] In an embodiment of the present application, as shown in Figure 2 The second current generating module 105 includes a current generating unit 1051 and a current mirror unit 1052, and the current mirror unit 1052 is electrically connected with the current generating unit 1051, the voltage generating module 103, the first switch module 101, the second switch module 102 and the first current generating module 104 respectively.

[0027] Specifically, the current generating unit 1051 is configured to generate a stable reference current when the second clock signal CLK2 is a fourth level signal (high level signal), and the current mirror unit 1052 generates the second current by mirroring the reference current, so that the second current can be quickly injected into the common node to provide sufficient driving for the rapid lifting of the voltage of the common node, thereby realizing the rapid turn-off of the first switch module 101 and the second switch module 102.

[0028] The working principle of the gating circuit provided by the embodiment of the present application will be described in detail below in combination with the circuit schematic diagram and the waveform schematic diagram of the clock signal shown in Figures 3 to 6

[0029] In an embodiment of the present application, as shown in​Figure 3 As shown, the first switch module 101 includes a first switch tube DMP3 and a second switch tube DMP4, the gate of the first switch tube DMP3 and the gate of the second switch tube DMP4 are electrically connected with the second switch module 102, the voltage generation module 103 and the first current generation module 104 respectively, the drain of the first switch tube DMP3 is used for being electrically connected with the positive electrode of the battery, the source of the first switch tube DMP3 is electrically connected with the source of the second switch tube DMP4, and the drain of the second switch tube DMP4 is used for being electrically connected with the battery output bus.

[0030] Specifically, the first switch module 101 is composed of the first switch tube DMP3 and the second switch tube DMP4 which are coupled at the source, and the gates of the two tubes jointly receive a unified gate drive signal (the voltage of the common node). Among them, the drain of the first switch tube DMP3 is used for being connected with the positive electrode of the corresponding single battery, as the access end of the battery voltage, and the drain of the second switch tube DMP4 is connected with the battery output bus, as the output end of the voltage. When the first switch tube DMP3 and the second switch tube DMP4 are both turned on, the selected battery voltage can be stably transmitted from the positive electrode of the battery to the battery output bus, and at the same time, the anti-interference ability and reliability of the voltage transmission path are enhanced by the cooperative working characteristics of the double switch tubes, so as to provide accurate battery voltage signals for the subsequent sampling unit.

[0031] It should be noted that the first switch tube DMP3 and the second switch tube DMP4 are both built-in parasitic body diodes, and the conduction characteristics of the body diodes determine the unidirectionality of voltage transmission. Even if the first switch tube DMP3 is in the off state, the voltage output by the corresponding battery can still be conducted to the source of the first switch tube DMP3 through the body diode of the first switch tube DMP3, but at this time the voltage can only stop at the source node of the two-tube coupling; only when the second switch tube DMP4 is turned on under the action of the gate drive signal, the battery voltage at the source node can be transmitted to the battery output bus through the conduction channel of the second switch tube DMP4, so as to realize the effective selected output of the battery voltage, and further ensure the controllability of the voltage transmission, avoiding accidental leakage or signal crosstalk in the non-selected state.

[0032] For example, the designer can select the types of the first switch tube DMP3 and the second switch tube DMP4 according to the actual situation, that is, metal oxide field effect transistors or insulated gate bipolar transistors and other fully controlled power devices can be used. For example, the first switch tube DMP3 and the second switch tube DMP4 can be selected as PMOS tubes.

[0033] It should be noted that only one circuit structure of the first switch module 101 is shown in the embodiments provided in the present application, and it does not mean that only this circuit structure can realize the function of the first switch module 101. Other circuit structures that can realize the function can also be replaced, and are not limited to this.

[0034] In one embodiment of the present application, as shown in Figure 3 The second switch module 102 includes a third switch tube DMP1 and a fourth switch tube DMP2, the gate of the third switch tube DMP1 and the gate of the fourth switch tube DMP2 are respectively electrically connected with the first switch module 101, the voltage generation module 103 and the first current generation module 104, the drain of the third switch tube DMP1 is used for electrically connecting with the positive electrode of the battery, the source of the third switch tube DMP1 is respectively electrically connected with the source of the fourth switch tube DMP2 and the voltage generation module 103, and the drain of the fourth switch tube DMP2 is used for electrically connecting with the switch common bus.

[0035] Specifically, the second switch module 102 is composed of the third switch tube DMP1 and the fourth switch tube DMP2 which are coupled by the source, and the gates of the two tubes jointly receive a unified gate drive signal (the voltage of the common node); wherein the drain of the third switch tube DMP1 is used for connecting with the positive electrode of the corresponding single battery, as the access end of the battery voltage, and the drain of the fourth switch tube DMP2 is commonly connected with the switch common bus, as the transmission end of the potential reference. When the third switch tube DMP1 and the fourth switch tube DMP2 are both turned on, the selected battery voltage can be stably transmitted from the positive electrode of the battery to the switch common bus, providing a unified isolation potential reference for the global non-selected channel, and at the same time, the stability and anti-crosstalk ability of the potential transmission are enhanced by means of the cooperative working characteristics of the double switch tubes, and the dual functions of battery voltage selection and channel isolation are realized by cooperating with the first switch module 101, thereby guaranteeing the system reliability during multi-channel switching.

[0036] It should be noted that the third switch tube DMP1 and the fourth switch tube DMP2 are both built-in parasitic body diodes, and the conduction characteristics of the body diode determine the unidirectionality of voltage transmission. Even if the third switch tube DMP1 is in the off state, the voltage output by the corresponding battery can still be conducted to the source of the third switch tube DMP1 through the body diode of the third switch tube DMP1, but at this time the voltage can only stop at the source node coupled by the two tubes; only when the fourth switch tube DMP2 is turned on under the action of the gate drive signal, the battery voltage at the source node can be smoothly transmitted to the switch common bus through the conduction channel of the fourth switch tube DMP2, further ensuring the controllability of voltage transmission and avoiding accidental leakage or signal crosstalk in the non-selected state.

[0037] For example, the designer can select the types of the third switch tube DMP1 and the fourth switch tube DMP2 according to the actual situation, that is, metal oxide field effect transistors or insulated gate bipolar transistors and other fully controlled power devices can be used. For example, the third switch tube DMP1 and the fourth switch tube DMP2 can be both PMOS tubes.

[0038] It should be noted that only one circuit structure of the second switch module 102 is shown in the embodiments provided in the present application, and it does not mean that only this circuit structure can realize the function of the second switch module 102. Other circuit structures that can realize the function can also be replaced, and are not limited thereto.

[0039] Another defect of the prior art is that the voltage of a single cell in a series of cells can reach tens of volts, and there are dynamic fluctuations and line noise. The unselected channel needs to maintain a very high off-isolation to prevent safety hazards such as voltage sampling distortion, charge crosstalk between battery nodes, or even local short circuit caused by leakage current or false turn-on.

[0040] The gating circuit provided in the present application, due to the presence of the fourth switch tube DMP2, when the voltage of the selected battery unit is greater than the voltage of the unselected battery unit, the first switch tube DMP3, the second switch tube DMP4, the third switch tube DMP1 and the fourth switch tube DMP2 in the gating circuit corresponding to the selected battery unit are all turned on, and the voltage of the selected battery unit can be transmitted to the switch common bus. The voltage (high potential) of the switch common bus can be transmitted to the source and common node of the fourth switch tube DMP2 through the body diode of the fourth switch tube DMP2 in the gating circuit corresponding to the unselected battery unit, and then the common node voltage of the gating circuit corresponding to the unselected battery unit is pulled up to be close to the voltage level of the selected battery unit, resulting in that the gate-source voltage difference (VGS) of the two switch tubes cannot meet the turn-on threshold requirement, so they are reliably turned off, effectively isolating the accidental connection between the unselected battery unit and the selected battery unit and other battery nodes, and avoiding the risk of charge crosstalk or leakage between different potential batteries. In addition, since the drains of all second switch tubes DMP4 of the gating circuits are connected together, when the voltage of the battery output bus is the voltage of the selected battery unit, the source potential of the first switch tube DMP3 in the gating circuit corresponding to the unselected battery unit is the voltage of the unselected battery unit, and the source potential of the second switch tube DMP4 is close to the voltage level of the selected battery unit (due to the turn-on characteristic of the body diode), therefore, the gate potential (i.e. the voltage of the common node) must be increased to ensure that the first switch tube DMP3 will not be turned on, so that there will be no leakage.

[0041] It should be noted that when the voltage of the selected battery unit is less than the voltage of the unselected battery unit, since the voltage of the unselected battery unit is higher than the voltage of the selected battery unit, the voltage of the common node in the gating circuit corresponding to the unselected battery unit is greater than the voltage level of the selected battery unit, and the body diodes of the second switch tube DMP4 and the fourth switch tube DMP2 in the gating circuit corresponding to the unselected battery unit are all reverse biased, so there is no need to worry about the leakage problem.

[0042] As an example, Figure 4 As shown in FIG. 1, the voltage of VC4 is greater than the voltage of VC3, and if VC4 is turned on, VC3 needs to be turned off. When VC4 is turned on, the four corresponding switch tubes of VC4 are all turned on, at this time, VOUT is equal to the voltage of VC4, and VPUB is equal to the voltage of VC4. Since the drain of the fourth switch tube DMP2 corresponding to VC4 is connected to the drain of the fourth switch tube DMP2 corresponding to VC3, the voltage of VPUB can be transmitted to the source of the fourth switch tube DMP2 corresponding to VC3 and the common node (transmitted to the common node through the voltage generating module 103) through the body diode of the fourth switch tube DMP2 corresponding to VC3, so that the voltage of the source of the fourth switch tube DMP2 corresponding to VC3 and the voltage of the common node are both close to the voltage level of VC4, which makes the gate-source voltage difference (VGS) of the first switch tube DMP3 and the third switch tube DMP1 corresponding to VC3 be forced to maintain in a safe interval close to zero or even positive, which absolutely cannot be turned on, thereby eliminating any possibility of VGS reaching the opening threshold due to noise or crosstalk from the physical layer. This is an active and global isolation reinforcement, rather than a traditional passive resistance.

[0043] In an embodiment of the present application, as shown in FIG. 1, the voltage generating module 103 includes a first transistor PM1, a second transistor PM2 and a third transistor PM3, the source of the first transistor PM1 is electrically connected with the second switch module 102, the gate of the first transistor PM1 is electrically connected with the drain of the first transistor PM1 and the source of the second transistor PM2 respectively, the source of the third transistor PM3 is electrically connected with the drain of the second transistor PM2 and the gate of the second transistor PM2 respectively, and the drain of the third transistor PM3 is electrically connected with the first current generating module 104 and the second current generating module 105 respectively. Figure 3

[0044] Specifically, the voltage generating module 103 is composed of the first transistor PM1, the second transistor PM2 and the third transistor PM3 which are connected in series and in diode connection type. Through the diode connection topology of the three transistors in series, under the action of the first current provided by the first current generating module 104, the voltage drop (the total voltage drop is 3*VGS) is generated by using the gate-source voltage (VGS) superposition effect of the transistor when it is turned on, and the first voltage, i.e. VIN-3*VGS, is calculated and transmitted to the common node, which provides accurate and stable gate drive bias for the synchronous conduction of the first switch module 101 and the second switch module 102, and at the same time, the robustness of the bias voltage to process fluctuations and environmental changes is enhanced by the structural characteristics of the three transistors in series, so as to guarantee the stability and accuracy of the voltage transmission process.

[0045] ​For example, designers can select the types of the first transistor PM1, the second transistor PM2, and the third transistor PM3 according to the actual situation; that is, they can use fully controllable power devices such as metal-oxide-semiconductor field-effect transistors or insulated-gate bipolar transistors. For instance, the first transistor PM1, the second transistor PM2, and the third transistor PM3 can all be selected as PMOS transistors. It should be noted that VGS is determined by the first current I1 and the transistor's WL, that is, the absolute value of VGS is:

[0046] in, c is the hole mobility in the PMOS transistor. ox V is the capacitance per unit area of ​​the gate oxide layer, W / L is the width-to-length ratio of the PMOS transistor, and V is the capacitance per unit area of ​​the gate oxide layer. THP This is the threshold voltage of the PMOS transistor.

[0047] It should be noted that the embodiments provided in this application only show one circuit structure as the voltage generation module 103, and do not represent that only this one circuit structure can realize the function of the voltage generation module 103. Other circuit structures that can realize this function can also be substituted, and are not limited to this. In addition, other numbers of transistors can be used to form the voltage generation module 103, and Zener diodes can be used to replace the three transistors mentioned above. At the same time, the third transistor PM3 can be replaced with the output terminal of the cascode current mirror. With the high output impedance characteristics of the cascode current mirror, the bias branch current is stabilized, and the anti-interference capability of the reference voltage drop to process and temperature changes is improved. The specific implementation architecture of the voltage generation module 103 is not limited here.

[0048] In one embodiment of this application, such as Figure 5 As shown, the voltage generation module 103 also includes a first resistor R1, the first end of which is electrically connected to the source of the first transistor PM1, and the second end of which is electrically connected to the drain of the third transistor PM3.

[0049] Specifically, the first resistor R1 is used to establish a deterministic DC potential for the bias node, avoiding bias voltage drift caused by process fluctuations, temperature changes, and other factors. This significantly enhances the robustness of the output bias voltage of the voltage generation module 103 to process and environmental changes, ensuring a stable voltage drop output of three times VGS. Furthermore, the first resistor R1 provides an additional current path, accelerating the charging and discharging process during gate potential switching, effectively improving the establishment speed of the common node potential, further optimizing the switching response efficiency of the gating circuit, and simultaneously helping to suppress high-frequency noise interference to the bias node, ensuring the stability of the gate drive signal, and providing reliable support for the precise on / off control of the first switching module 101 and the second switching module 102.

[0050] In one embodiment of the present application, as shown in Figure 5 The first current generating module 104 includes a fifth switch tube DMN1 and a first current source. The gate of the fifth switch tube DMN1 is configured to receive a first clock signal CLK1. The drain of the fifth switch tube DMN1 is electrically connected with the voltage generating module 103, the first switch module 101 and the second switch module 102 respectively. The source of the fifth switch tube DMN1 is electrically connected with the first end of the first current source. The second end of the first current source is grounded.

[0051] Specifically, when the first clock signal CLK1 is a high level signal, the fifth switch tube DMN1 is turned on, and the constant current (first current) output by the first current source flows into the voltage generating module 103 through the turned-on fifth switch tube DMN1, thereby providing a stable bias current for the voltage generating module 103. When the first clock signal CLK1 is a low level, the fifth switch tube DMN1 is turned off, and the current path of the first current source is cut off, thereby terminating the bias current of the voltage generating module 103. In combination with the action of the subsequent second current generating module 105, the turn-off control of the switch module is realized. Through the clock-controlled characteristics of the fifth switch tube DMN1 and the constant current output characteristics of the first current source, the timing accurate control of the bias current is realized, and the current stability of the voltage generating module 103 is ensured, thereby ensuring the reliable generation of the voltage of the common node in the turn-on stage of the gating circuit.

[0052] For example, the designer can select the type of the fifth switch tube DMN1 according to the actual situation, that is, a full-controlled power device such as a metal oxide field effect transistor or an insulated gate bipolar transistor can be used. For example, the fifth switch tube DMN1 can be selected as an NMOS tube.

[0053] It should be noted that only one circuit structure of the first current generating module 104 is shown in the embodiments provided in the present application, and it does not mean that only this circuit structure can realize the function of the first current generating module 104. Other circuit structures that can realize the function can also be replaced, and are not limited thereto.

[0054] In one embodiment of the present application, as shown in Figure 5 The current generating unit 1051 includes a sixth switch tube DMN2 and a second current source. The gate of the sixth switch tube DMN2 is configured to receive a second clock signal CLK2. The drain of the sixth switch tube DMN2 is electrically connected with the current mirror unit 1052. The source of the sixth switch tube DMN2 is electrically connected with the first end of the second current source. The second end of the second current source is grounded.

[0055] Specifically, when the second clock signal CLK2 is a high level signal, the sixth switch tube DMN2 is turned on, and the constant reference current output by the second current source is transmitted to the current mirror unit 1052 through the turned-on sixth switch tube DMN2, so as to provide the current mirror unit 1052 with an accurate current replication reference; when the second clock signal CLK2 is a low level signal, the sixth switch tube DMN2 is turned off, the reference current transmission path is cut off, and the current generating unit 1051 stops working. Through the clock-controlled on-off of the sixth switch tube DMN2 and the constant current output characteristic of the second current source, the unit realizes the timing accurate control and stable output of the reference current, provides a reliable basis for the second current generated by the current mirror unit 1052, and further guarantees the high-speed turn-off function of the first switch module 101 and the second switch module 102.

[0056] For example, the designer can select the type of the sixth switch tube DMN2 according to the actual situation, that is, a full-controlled power device such as a metal oxide field effect transistor or an insulated gate bipolar transistor can be used. For example, the sixth switch tube DMN2 can be selected as an NMOS tube.

[0057] In an embodiment of the present application, as shown in Figure 5 The current mirror unit 1052 includes a fourth transistor PM4 and a fifth transistor PM5, the gate of the fourth transistor PM4 is electrically connected with the gate of the fifth transistor PM5, the drain of the fourth transistor PM4 and the current generating unit 1051, the source of the fourth transistor PM4 and the source of the fifth transistor PM5 are electrically connected with the second switch module 102 and the voltage generating module 103 respectively, and the drain of the fifth transistor PM5 is electrically connected with the voltage generating module 103, the first switch module 101, the second switch module 102 and the first current generating module 104 respectively.

[0058] Specifically, the current mirror unit 1052 is composed of the fourth transistor PM4 and the fifth transistor PM5 in a mirror-symmetrical structure, and the reference current output by the current generating unit 1051 is accurately copied through the transistor mirror principle to generate a second current in a fixed proportion with the reference current. The fourth transistor PM4 serves as a reference tube to receive and conduct the reference current, providing a stable reference for mirror replication, and the fifth transistor PM5 serves as an output tube to inject the copied second current into the common node, quickly charging the gate capacitance to raise the common node voltage, ensuring that the first switch module 101 and the second switch module 102 achieve high-speed turn-off. At the same time, the mirror structure ensures the stability and accuracy of the second current, and the cooperative work of the two transistors not only guarantees the reliability of the turn-off drive, but also enhances the adaptability of the circuit to process fluctuations and environmental changes, ensuring the high-speed switching of the gating circuit.

[0059] It should be noted that the rising speed of the voltage of the common node depends on the current and the size of the capacitance, and the gate capacitance includes all parasitic capacitances connected to the gate node. Without the fifth transistor PM5, the voltage of the common node can only be slowly raised by the first transistor PM1, the second transistor PM2 and the third transistor PM3 after the switch tubes (the first switch tube DMP3, the second switch tube DMP4, the third switch tube DMP1 and the fourth switch tube DMP2) are normally turned off, and the current is getting smaller and smaller, and the voltage rises very slowly. Because of the fifth transistor PM5, the voltage of the common node can be raised faster by setting the pulse width time of the second clock signal CLK2, so that the switch tube can be turned off in time.

[0060] It should be noted that, as shown in Figure 6 The first clock signal CLK1 and the second clock signal CLK2 are inverse signals. When the first clock signal CLK1 is high, the second clock signal CLK2 is low. When the first clock signal CLK1 is low, the second clock signal CLK2 is high.

[0061] For example, the designer can select the types of the fourth transistor PM4 and the fifth transistor PM5 according to the actual situation, that is, full-controlled power devices such as metal oxide field effect transistors or insulated gate bipolar transistors can be used. For example, the fourth transistor PM4 and the fifth transistor PM5 can be PMOS tubes.

[0062] For example, the designer can select the value of the reference current according to the actual situation. For example, the reference current can be 10 times the first current.

[0063] It should be noted that only one circuit structure of the second current generating module 105 is shown in the embodiments provided in the present application, and it does not mean that only this circuit structure can realize the function of the second current generating module 105. Other circuit structures that can realize the function can also be replaced, and are not limited to this.

[0064] Through the above circuit design and parameter selection, the application constructs a main active fast charging path from the source of the third switch tube DMP1 to the common node; the path can actively and quickly pull up the potential of the common node at the timing node when the switch tube needs to be turned off, thereby shortening the delay time of the switch-off process to less than one tenth of the traditional resistance downlink solution, successfully realizing the nanosecond-level high-speed switch-off effect, and greatly improving the overall channel switching frequency and system response real-time of the multiplexer. At the same time, for the adjacent battery channels with different potentials, the voltage of the common node is no longer passively followed by the current potential like the traditional solution, but is actively pulled up to the potential level close to the selected battery unit through the potential reference function of the switch common bus, effectively avoiding accidental connection between different potential battery nodes, and fundamentally eliminating the risk of leakage and misdirecting of non-selected channels.

[0065] The application also discloses a multiplexer comprising a plurality of the above-mentioned gating circuits. The multiplexer can realize independent gating and high-speed switching sampling of the voltage of each battery in a plurality of series-connected lithium battery groups by integrating a plurality of the above-mentioned gating circuits. With the active isolation mechanism of each gating circuit, the risk of leakage and misdirecting between non-selected battery channels is effectively eliminated, and the accuracy and reliability of voltage sampling are ensured. At the same time, the fast switch-off characteristic of each gating circuit can greatly improve the overall channel switching frequency of the multiplexer, meet the demand of the next generation of battery management systems for high-frequency and real-time voltage monitoring, and have the technical advantages of high isolation, high switching speed and high stability.

[0066] Since the processing and functions realized by the multiplexer in the embodiment are basically corresponding to the embodiments, principles and examples of the above-mentioned gating circuit, the description of the embodiment will not be described in detail, and the related description in the above-mentioned embodiments can be referred to.

[0067] The above-described embodiments are only used to illustrate the technical solutions of the application, rather than limit them; although the application has been described in detail with reference to the above-mentioned embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the above-mentioned embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the application, and should be included in the protection scope of the application.

Claims

1. A gating circuit, characterized in that, It includes a first switch module, a second switch module, a voltage generating module, a first current generating module, and a second current generating module. The second switch module is electrically connected to the first switch module, the voltage generating module, the first current generating module, and the second current generating module. The voltage generating module is electrically connected to the first current generating module and the second current generating module. Both the first switch module and the second switch module are used to be electrically connected to the positive terminal of the battery. The first switch module is used to be electrically connected to the battery output bus, and the second switch module is used to be electrically connected to the switch common bus. The first current generating module is used to receive a first clock signal, and the second current generating module is used to receive a second clock signal. When the first clock signal is a first level signal and the second clock signal is a second level signal, the first current generating module is used to generate a first current according to the first level signal, and the voltage generating module is used to generate a first voltage according to the first current, and transmit the first voltage to a common node, where the common node is the connection point between the first switching module and the second switching module. Both the first switching module and the second switching module are used to conduct voltage according to the common node, so that the voltage output by the battery is transmitted to the battery output bus and the switch common bus. When the first clock signal is a third-level signal and the second clock signal is a fourth-level signal, the second current generation module is used to generate a second current according to the second clock signal to increase the rising slope of the voltage of the common node. Both the first switch module and the second switch module are used to turn off according to the voltage of the common node.

2. The gating circuit according to claim 1, characterized in that, The first switching module includes a first switching transistor and a second switching transistor. The gates of the first switching transistor and the second switching transistor are electrically connected to the second switching module, the voltage generation module, and the first current generation module, respectively. The drain of the first switching transistor is electrically connected to the positive terminal of the battery, the source of the first switching transistor is electrically connected to the source of the second switching transistor, and the drain of the second switching transistor is electrically connected to the battery output bus.

3. The gating circuit according to claim 1, characterized in that, The second switching module includes a third switching transistor and a fourth switching transistor. The gates of the third switching transistor and the fourth switching transistor are electrically connected to the first switching module, the voltage generation module, and the first current generation module, respectively. The drain of the third switching transistor is electrically connected to the positive terminal of the battery. The source of the third switching transistor is electrically connected to the source of the fourth switching transistor and the voltage generation module, respectively. The drain of the fourth switching transistor is electrically connected to the switch common bus. When the voltage of the selected battery cell is greater than the voltage of the non-selected battery cell, the voltage of the common bus in the selection circuit corresponding to the selected battery cell is transmitted to the source of the fourth switch and the common node through the body diode of the fourth switch in the selection circuit corresponding to the non-selected battery cell, thereby pulling up the voltage of the common node and turning off the first switch module in the selection circuit corresponding to the non-selected battery cell.

4. The gating circuit according to claim 1, characterized in that, The voltage generating module includes a first transistor, a second transistor, and a third transistor. The source of the first transistor is electrically connected to the second switching module. The gate of the first transistor is electrically connected to the drain of the first transistor and the source of the second transistor. The source of the third transistor is electrically connected to the drain of the second transistor and the gate of the second transistor. The drain of the third transistor is electrically connected to the first current generating module and the second current generating module.

5. The gating circuit according to claim 4, characterized in that, The voltage generation module further includes a first resistor, a first end of which is electrically connected to the source of the first transistor, and a second end of which is electrically connected to the drain of the third transistor.

6. The gating circuit according to claim 1, characterized in that, The first current generating module includes a fifth switching transistor and a first current source. The gate of the fifth switching transistor is used to receive the first clock signal. The drain of the fifth switching transistor is electrically connected to the voltage generating module, the first switching module, and the second switching module, respectively. The source of the fifth switching transistor is electrically connected to the first terminal of the first current source, and the second terminal of the first current source is grounded.

7. The gating circuit according to claim 1, characterized in that, The second current generating module includes a current generating unit and a current mirror unit, wherein the current mirror unit is electrically connected to the current generating unit, the voltage generating module, the first switching module, the second switching module and the first current generating module respectively; The current generating unit is used to generate a reference current when the second clock signal is a fourth level signal, and the current mirror unit is used to generate the second current according to the reference current.

8. The gating circuit according to claim 7, characterized in that, The current generating unit includes a sixth switching transistor and a second current source. The gate of the sixth switching transistor is used to receive the second clock signal. The drain of the sixth switching transistor is electrically connected to the current mirror unit. The source of the sixth switching transistor is electrically connected to the first terminal of the second current source. The second terminal of the second current source is grounded.

9. The gating circuit according to claim 7, characterized in that, The current mirror unit includes a fourth transistor and a fifth transistor. The gate of the fourth transistor is electrically connected to the gate of the fifth transistor, the drain of the fourth transistor, and the current generating unit. The source of the fourth transistor and the source of the fifth transistor are both electrically connected to the second switching module and the voltage generating module, respectively. The drain of the fifth transistor is electrically connected to the voltage generating module, the first switching module, the second switching module, and the first current generating module, respectively.

10. A multiplexer, characterized in that, The system includes multiple gating circuits as described in any one of claims 1-9, wherein the first switch module and the second switch module in each gating circuit are electrically connected to the positive terminal of the corresponding battery and serve as multiple input terminals of the multiplexer, and each first switch module is electrically connected to the battery output bus and serves as the output terminal of the multiplexer.

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