Open-loop modulation transmitter with harmonic suppression switched capacitor power amplifier

Abstract

The invention relates to an open-loop modulation transmitter with a harmonic suppression switched capacitor power amplifier. The transmitter comprises a sixteen-phase delay locked loop, a binary frequency shift keying modulator and the harmonic suppression switched capacitor power amplifier. The sixteen-phase delay locked loop provides sixteen paths of clock signals with equal phase difference to the binary frequency shift keying modulator, and the sixteen paths of clock signals are used as input signals of the binary frequency shift keying modulator; the binary frequency shift keying modulator is connected with the harmonic suppression switched capacitor power amplifier and provides a modulation signal for the harmonic suppression switched capacitor power amplifier; and the harmonic suppression switched capacitor power amplifier is used for amplifying the modulation signal and suppressing a harmonic component so as to output the modulation signal after harmonic suppression. According to the invention, high data rate transmission can be supported, the higher harmonic suppression capability is provided, the design requirement of a matching network can be relaxed while the frequency spectrum purity is ensured, the chip area is reduced, and the system cost is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to an open-loop modulation transmitter with harmonic-rejection switched-capacitor power amplifier, and relates to the technical field of circuits. BACKGROUND

[0002] The Internet of Things industry has long focused on low-cost, low-power wireless communication solutions, while the demand for high data rate transmission has been largely overlooked. As the Internet of Things evolves towards more complex and diverse application scenarios, some systems have higher requirements for high-speed data transmission. For example, in many short-range wireless personal area networks (WPANs) and wireless sensor network applications, low-power transceivers that can provide relatively high communication data rates (more than 1 Mb / s) are needed. Transmitters for typical Internet of Things application scenarios usually use frequency shift keying (FSK) modulation, which has the advantages of low complexity and constant envelope output, allowing it to work with highly efficient digital power amplifiers.

[0003] However, in some high-speed applications, the data rate of traditional FSK systems (usually hundreds of kbps to several Mbps) can become a bottleneck restricting their performance expansion. Therefore, how to achieve higher data transmission rates under a low-power architecture has become an important issue in the design of Internet of Things transmitters.

[0004] In addition, to meet the demand for multi-band communication support in Internet of Things systems, the wideband modulation capability of the transmitter has also become a key design goal. Inverter-type Class-D power amplifiers are commonly used in low-power Internet of Things transmitters due to their high efficiency and simple structure. Under the condition of having sufficient driving capability, the inverter itself can support a relatively wide operating frequency range. However, in order to suppress the high-order harmonic spurious signals generated by the switching power amplifier, the overall bandwidth of the system is usually limited by the narrowband matching network at the output of the power amplifier. By suppressing the third and fifth harmonic components at the output of the power amplifier, the design requirements of the matching network can be relaxed while ensuring spectral purity, thereby reducing chip area and system cost.

[0005] In summary, it is of significant practical significance and application value to develop a transmitter that can achieve high data transmission rates and has high-order harmonic suppression capability. SUMMARY

[0006] In view of the deficiencies of the prior art, the technical problem to be solved by the present application is to provide an open-loop modulation transmitter with a harmonic-rejection switched-capacitor power amplifier, which can support high-speed data rate transmission and has high-order harmonic suppression capability, can relax the design requirements of the matching network while ensuring spectral purity, thereby reducing chip area and system cost.

[0007] In order to solve the above technical problems, the technical scheme of the present application is: an open-loop modulation transmitter with a harmonic suppression switched-capacitor power amplifier, the transmitter comprising a sixteen-phase delay-locked loop, a binary frequency-shift keying modulator, and a harmonic suppression switched-capacitor power amplifier; the sixteen-phase delay-locked loop provides sixteen clock signals with equal phase differences to the binary frequency-shift keying modulator as input signals of the binary frequency-shift keying modulator; the binary frequency-shift keying modulator is connected to the harmonic suppression switched-capacitor power amplifier and provides a modulated signal to the harmonic suppression switched-capacitor power amplifier; and the harmonic suppression switched-capacitor power amplifier is used to amplify the modulated signal and suppress harmonic components to output the modulated signal after harmonic suppression.

[0008] Preferably, the sixteen-phase delay-locked loop can generate sixteen clock signals with equal phase differences at the same frequency as a reference signal.

[0009] Preferably, the sixteen-phase delay-locked loop comprises a sixteen-phase voltage-controlled delay line, a phase-frequency detector, a charge pump, and a loop filter.

[0010] Preferably, the binary frequency-shift keying modulator comprises a reversible counter and a sixteen-to-one multiplexer, and the binary frequency-shift keying modulation can be realized by phase switching of the input sixteen-phase signals.

[0011] Preferably, the harmonic suppression switched-capacitor power amplifier comprises a phase signal generation circuit and a switched-capacitor power amplifier.

[0012] Preferably, the phase signal generation circuit comprises a four-phase voltage-controlled delay line, a phase-frequency detector, a charge pump, and a loop filter.

[0013] Preferably, the four-phase voltage-controlled delay line has four delay units connected in series, and the terminal delay unit is connected to the phase-frequency detector through an inverter to provide a detection signal for the phase-frequency detector.

[0014] Preferably, the phase-frequency detector is connected to the charge pump, and the phase-frequency detector generates a control signal according to the phase difference between a reference signal and the detection signal, and the control signal generates a control voltage through the charge pump to control the delay of the delay units, so that the phase difference between each delay unit is ultimately 45°.

[0015] Preferably, the switched-capacitor power amplifier comprises a plurality of identical switched-capacitor branches, and the output ends of each switched-capacitor branch are connected to serve as the output end of the transmitter.

[0016] Preferably, the switched-capacitor branch comprises a driving circuit, a switch, and a capacitor.

[0017] Preferably, the several capacitive branches are divided into three groups, which are connected to three-phase modulation signals respectively; the first group of capacitive branches is connected to 45° phase modulation signals, the second group of capacitive branches is connected to 90° phase modulation signals, and the third group of capacitive branches is connected to 135° phase modulation signals.

[0018] Preferably, the output voltage of the switched-capacitor power amplifier changes with the number of conducting capacitors, and the output voltage amplitude is several discrete levels in a period, which are determined by the number of conducting capacitors.

[0019] Compared with the prior art, the present application has the following beneficial effects:

[0020] The present application cascades a binary frequency shift keying modulator, a phase signal generation circuit and a switched-capacitor power amplifier in sequence, and provides a multi-phase carrier signal for the binary frequency shift keying modulator by a sixteen-phase delay locked loop, thereby realizing a transmitter supporting high data rate transmission and having harmonic suppression capability. The sixteen-phase delay locked loop converts the input carrier signal into sixteen-phase carrier signals uniformly distributed in phase, and a sixteen-to-one multiplexer in the binary frequency shift keying modulator selects the carrier signals of different phases in sequence, and realizes phase switching to output a modulation signal in combination with the control of a reversible counter. The modulation signal is input to the phase signal generation circuit to generate multiple modulation signals with a phase difference of 45°, and is combined into three driving signals to drive the switched-capacitor power amplifier. The switched-capacitor power amplifier realizes power amplification of the modulation signal by switching the capacitive branches of the multi-phase driving signal, and cancels the third and fifth harmonic components at the output end, and finally obtains the amplified modulation signal after harmonic suppression. The present application can support high data rate transmission while ensuring spectral purity, relax the design requirements of the power amplifier matching network, thereby reducing the chip area and system cost.

[0021] The present application will be further described in detail below in combination with the drawings and specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 It is an open-loop modulation transmitter total circuit schematic diagram with a harmonic suppression switched-capacitor power amplifier of the present application.

[0023] Figure 2 It is a phase signal generation circuit module schematic diagram of the present application.

[0024] Figure 3 It is a schematic diagram of the third and fifth harmonic suppression principle of the present application.

[0025] Figure 4 It is a schematic diagram of the switched-capacitor power amplifier of the present application. DETAILED DESCRIPTION

[0026] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0027] It should be noted that the following detailed descriptions are exemplary and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0028] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0029] like Figures 1-4 As shown, this embodiment provides an open-loop modulation transmitter with a harmonic suppression switched capacitor power amplifier. The transmitter includes a sixteen-phase delay-locked loop, a binary frequency shift keying modulator, and a harmonic suppression switched capacitor power amplifier.

[0030] The sixteen-phase delay-locked loop generates sixteen equal-phase-difference clock signals and provides these sixteen clock signals as input to the binary frequency-shift keying modulator. The binary frequency-shift keying modulator is connected to the harmonic suppression switched-capacitor power amplifier and provides a modulation signal to the harmonic suppression switched-capacitor power amplifier. The harmonic suppression switched-capacitor power amplifier amplifies the modulation signal and suppresses harmonic components, thereby outputting a harmonic-suppressed modulation signal.

[0031] The sixteen-phase delay-locked loop includes sixteen voltage-controlled delay lines, a frequency and phase detector, a charge pump, and a loop filter, and is capable of generating sixteen clock signals with an adjacent phase difference of 22.5°.

[0032] The binary frequency shift keying modulator includes a reversible counter and a 16-to-1 multiplexer. The 16-to-1 multiplexer is used to select one output from sixteen clock signals with an adjacent phase difference of 22.5° output from the delay-locked loop. The phase selection is determined by a four-bit binary control code output from the reversible counter.

[0033] When the reversible counter works in the counting mode, the control code increases from "0000" to "1111" and returns to "0000" in turn, completing a cycle. In this process, the output phase of the sixteen-to-one multiplexer gradually increases by 22.5° with the increase of the control code until the phase switching of 2π is completed. The linear phase increase corresponds to the decrease of the output signal frequency. When the reversible counter works in the counting-down mode, the control code decreases reversely, and the phase gradually decreases by 22.5°, and the output signal frequency increases accordingly.

[0034] In the embodiment of the present application, the control clock frequency of the reversible counter determines the switching rate of the control code, thereby determining the time required for the sixteen-to-one multiplexer to complete the phase switching of 2π, and finally determining the frequency offset of the output signal. In the present application, the control clock frequency is 160MHz (i.e. 16f, f=10MHz), and the time required for the output signal to complete the phase switching of 2π is 1 / f=100ns, and the corresponding frequency offset is 10MHz.

[0035] The harmonic suppression switched-capacitor power amplifier comprises a phase signal generation circuit and a switched-capacitor power amplifier.

[0036] The phase signal generation circuit comprises a four-phase voltage-controlled delay line, a frequency discriminator, a charge pump and a loop filter. As shown in Figure 2 The four-phase voltage-controlled delay line comprises four delay units connected in series. The end delay unit is connected with the frequency discriminator through a level inverter, and is used to provide a detection signal to the frequency discriminator.

[0037] The delay unit comprises two current-starved inverters (CSI). The current-starved inverters used in the present application can control the sizes of the pull-up and pull-down currents by changing the gate voltages of the MP2 and MN2 transistors, thereby reducing the duty cycle distortion caused by the different rising and falling times of the output voltage in the inverter.

[0038] In order to realize the control of the pull-up and pull-down currents, the control voltage output by the charge pump needs to be converted into control signals V P and V N through a single-ended to differential buffer, wherein the V P is inversely proportional to the charge pump control voltage and is connected to the MP2, and the V N is proportional to the charge pump control voltage and is connected to the MN2. When the charge pump control voltage rises, the V N rises and the V P falls, so that the current of the inverter increases when the level switches, thereby reducing the delay time of the inverter. When the charge pump control voltage falls, the delay time of the inverter increases.

[0039] The frequency and phase detector is connected to a charge pump and generates a control signal by comparing the phase difference between a reference signal and a detection signal. This control signal adjusts the charging and discharging currents of the charge pump to create a control voltage at the output of the loop filter, thereby adjusting the delay time of the delay units. Ultimately, the phase difference between each delay unit is 45°, with the outputs of the first three delay units connected to the switched-capacitor power amplifier.

[0040] The switched capacitor power amplifier includes ten identical switched capacitor branches, and the output terminals of each switched capacitor branch are connected to serve as the output terminals of the transmitter.

[0041] The switched capacitor branch includes a drive circuit, a switch, and a capacitor.

[0042] The output voltage of the switched capacitor power amplifier changes with the number of conducting capacitor branches, and the formula for the output voltage is as follows:

[0043]

[0044] Where C on For the total capacitance of the conducting capacitor branch, C total VDD is the sum of the capacitances of all capacitor branches, and VDD is the power supply voltage.

[0045] like Figure 3 As shown, the three modulation signals connected to the capacitor branch are 45° out of phase, the third harmonic of the three signals is 135° out of phase, and the fifth harmonic is 225° out of phase. When the sum of the capacitances of the three signal branches is... At that time, the ratio of the output voltages of the three signals is At this time, the third and fifth harmonics of the modulated signal will be canceled out.

[0046] like Figure 4 As shown, in order to approximate the ideal voltage ratio, the present invention uses a three-way voltage ratio of 3:4:3. The capacitor branch is divided into three groups, which are respectively connected to the three phase modulation signals Tap[0], Tap[1], and Tap[2]. The first group of capacitor branches includes three branches, which are connected to the 45° phase modulation signal; the second group of capacitor branches has four branches, which are connected to the 90° phase modulation signal; and the third group of capacitor branches has three branches, which are connected to the 135° phase modulation signal.

[0047] According to the output voltage formula derivation, the output voltage amplitude includes 0, 0.3VDD, 0.7VDD, VDD, in the initial state, all the capacitor branches are closed and regarded as ground, the output voltage is 0. When the 45° phase modulation signal becomes high potential, it enters state two, three branches in the first group of capacitor branches are turned on. The output voltage is 0.3VDD. When the 90° phase modulation signal becomes high potential, it enters state three, the capacitor branches of the first two groups are turned on, the output voltage is 0.7VDD. When the 135° phase modulation signal becomes high potential, it enters state four, three groups of capacitor branches are turned on, the output voltage is VDD. When the 45° phase modulation signal becomes zero potential after half a cycle, it enters state five, the input of the first group of capacitor branches is regarded as ground, the last two groups of capacitor branches are turned on, the output voltage is 0.7VDD. When the 90° phase modulation signal becomes zero potential, it enters state six, only the third group of branches is turned on, the output voltage is 0.3VDD. Finally, all the branches are closed and return to the initial state, the output voltage is 0.

[0048] The capacitor switch of the switch capacitor power amplifier is realized by a CMOS inverter, and the output impedance of the switch capacitor power amplifier is kept unchanged when the switch state changes by selecting appropriate sizes of PMOS and NMOS, so that the output voltage meets the preset value.

[0049] The above is only the preferred embodiment of the present application, and does not limit the other forms of the present application. Any skilled person in the art can use the disclosed technical content to make changes or modifications into equivalent embodiments. However, any simple modification, equivalent change and modification made according to the technical essence of the present application without departing from the technical solution content of the present application still belongs to the protection scope of the present application.

Claims

1. An open-loop modulation transmitter with a harmonic suppression switched-capacitor power amplifier, characterized in that: The transmitter includes a sixteen-phase delay-locked loop, a binary frequency shift keying modulator, and a harmonic suppression switched-capacitor power amplifier. The sixteen-phase delay-locked loop provides sixteen clock signals with equal phase differences to the binary frequency shift keying modulator as input signals. The binary frequency shift keying modulator is connected to the harmonic suppression switched-capacitor power amplifier and provides a modulation signal to it. The harmonic suppression switched-capacitor power amplifier amplifies the modulation signal and suppresses harmonic components to output a harmonic-suppressed modulation signal.

2. The open-loop modulation transmitter with harmonic suppression switched capacitor power amplifier according to claim 1, characterized in that: The sixteen-phase delay-locked loop can generate sixteen clock signals with equal phase differences to the reference signal frequency.

3. The open-loop modulation transmitter with harmonic suppression switched capacitor power amplifier according to claim 1, characterized in that: The sixteen-phase delay-locked loop includes a sixteen-phase voltage-controlled delay line, a frequency and phase detector, a charge pump, and a loop filter.

4. The open-loop modulation transmitter with harmonic suppression switched capacitor power amplifier according to claim 1, characterized in that: The binary frequency shift keying modulator includes a reversible counter and a 16-to-1 multiplexer, which can realize binary frequency shift keying modulation by switching the phase of the input 16-phase signal.

5. The open-loop modulation transmitter with harmonic suppression switched capacitor power amplifier according to claim 1, characterized in that: The harmonic suppression switched capacitor power amplifier includes a phase signal generation circuit and a switched capacitor power amplifier.

6. The open-loop modulation transmitter with harmonic suppression switched capacitor power amplifier according to claim 5, characterized in that: The phase signal generation circuit includes a four-phase voltage-controlled delay line, a frequency and phase detector, a charge pump, and a loop filter.

7. The open-loop modulation transmitter with harmonic suppression switched capacitor power amplifier according to claim 6, characterized in that: The four-phase voltage-controlled delay line has four delay units connected in series. The end delay unit is connected to the frequency and phase detector after passing through an inverter, providing a detection signal for the frequency and phase detector.

8. The open-loop modulation transmitter with harmonic suppression switched capacitor power amplifier according to claim 6, characterized in that: The frequency and phase detector is connected to the charge pump. The frequency and phase detector compares the phase difference between the reference signal and the detection signal to generate a control signal. The control signal generates a control voltage through the charge pump to control the delay of the delay unit, so that the phase difference between each delay unit is 45°.

9. The open-loop modulation transmitter with harmonic suppression switched capacitor power amplifier according to claim 5, characterized in that: The switched capacitor power amplifier includes several identical switched capacitor branches, and the output terminals of each switched capacitor branch are connected to serve as the output terminals of the transmitter.

10. The open-loop modulation transmitter with harmonic suppression switched capacitor power amplifier according to claim 9, characterized in that: The switched capacitor branch includes a drive circuit, a switch, and a capacitor.

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