Circuit, chip, electronic device and method for executing hash operation

Abstract

The invention relates to a circuit, a chip, an electronic device and a method for executing hash operation. According to an exemplary embodiment, the present disclosure discloses a circuit for performing a hash algorithm, which may include: first to eighth registers for storing data; wherein the data of the eighth register input in the first clock period, the data of the fifth register input in the second clock period and the data of the first register input in the third clock period are the same group of data; the first clock period, the second clock period and the third clock period are continuous clock periods. According to the technical scheme provided by the invention, the operation on the combinational logic path is advanced, and the serial steps of the key path are reduced, so that the operation speed of the circuit is remarkably improved on the premise of not changing the operation result.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit design, and more particularly, to a circuit, a chip, an electronic device and a method for performing a hash operation. BACKGROUND

[0002] SHA-256 (Secure Hash Algorithm 256-bit) is the core algorithm of the SHA-2 hash family and is widely used in the field of information security. It can convert data of any length into a fixed 256-bit hash digest, with core features such as one-way irreversibility, strong collision resistance, and avalanche effect, and is widely used in the field of data security.

[0003] SHA-256 plays a core role in blockchain technology and is a key technical support for ensuring the immutability and integrity of blockchain data. In the blockchain architecture, each block contains a block header and a block body. The block header stores the hash value of the previous block, the Merkle root hash of the transaction data in the current block, the timestamp, and other information. The hash calculation of these core data relies on the SHA-256 algorithm. Specifically, when a new block is generated, the system performs a hash operation on the block header information using SHA-256 to generate a unique 256-bit hash value. This hash value is both the "digital fingerprint" of the block and will be written into the header of the next block, forming a chain structure. Once someone tries to tamper with any data in the block, the hash value of the block will be completely changed, thereby causing the hash values of all subsequent blocks to be invalid and unable to be verified by all network nodes, ensuring the immutability of the data. In addition, SHA-256 is also used in the proof-of-work mechanism, which adjusts the nonce in the block header and performs SHA-256 hash operation on the block header until a hash value that meets certain rules is obtained, thereby proving that the calculation work is completed, ensuring the consensus reaching and safe operation of the blockchain network. SUMMARY

[0004] According to some aspects, the subject matter of the independent claims is provided. Some further aspects are defined in the dependent claims. Embodiments not falling under the claims for protection are to be interpreted as examples helpful for understanding the present disclosure.

[0005] According to a first aspect of the present disclosure, a circuit for performing a hash operation can include: first to eighth registers for storing data, a first adder, and a second adder; wherein the input data of the first adder includes the data stored in the seventh register, the data stored in an extension register outside the circuit, and a constant; and the input data of the second adder includes the output data of the first adder and the data stored in the second register.

[0006] According to a second aspect of the present disclosure, a chip can include the aforementioned multi-bit adder.

[0007] According to a third aspect of the present disclosure, an electronic device can include the aforementioned chip.

[0008] According to a fourth aspect of the present disclosure, a method for performing a hash operation can include receiving data stored in a seventh register using a first adder, extending the data stored in the register and a constant and performing a summation operation; receiving output data of the first adder and data stored in a second register using a second adder and performing a summation operation. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 A schematic diagram showing a hash algorithm processing procedure;

[0010] Figure 2 A schematic diagram showing a circuit for performing a hash operation;

[0011] Figure 3 A schematic diagram showing a circuit for performing a hash operation according to an exemplary embodiment of the present disclosure;

[0012] Figure 4A A schematic diagram showing a half adder;

[0013] Figure 4B A schematic diagram showing a full adder;

[0014] Figure 5 A schematic diagram showing a circuit for performing a hash operation according to another exemplary embodiment of the present disclosure;

[0015] Figure 6 A schematic diagram showing a chip according to an exemplary embodiment of the present disclosure;

[0016] Figure 7 A schematic diagram showing a method for performing a hash operation according to an exemplary embodiment of the present disclosure.

[0017] The same or substantially the same elements, operations, steps, etc. shown in the various figures can be denoted by the same reference numerals. Not every element, operation, step, etc. can be shown in each figure. DETAILED DESCRIPTION

[0018] Exemplary embodiments of the present application will be described more fully hereinafter with reference to the accompanying drawings. It is to be understood that the present disclosure should not be construed as limited to the exemplary embodiments described herein and that the present disclosure can be otherwise implemented by various other forms. These exemplary embodiments are provided herein only to more completely and fully convey the scope of the application to those skilled in the art. It should be understood that the drawings are given only by way of example and that they are not limiting of the present application.

[0019] The following examples are illustrative. While the specification comes with some places with reference to "an" or "one" or "some" embodiment, this does not necessarily mean that each

[0020] In this disclosure, the terms "at least one of A or B", "at least one of A and B", and "A and / or B" mean

A

B

A and B

A

B

C

A and B

A and C

B and C

A, B, and C

[0021] Figure 1 A schematic diagram showing the processing of data of arbitrary length using the SHA256 hashing algorithm. See Figure 1 After receiving data that needs to be processed using the SHA256 algorithm, a preprocessing operation needs to be performed on the data first, the preprocessing operation includes padding the input data, the padding method is to add a "1" bit first, and then add several "0" bits after the "1", the padding should ensure that the length of the data modulo 512 is equal to 448, that is, the length of the padded data should be an integer multiple of 512 plus 448. Finally, append the original data length of 64 bits at the end, so that the final data length is an integer multiple of 512.

[0022] The hash algorithm part includes pre-setting 8 initial hash values of 32 bits, which are derived from the decimal part of the square root of the first 8 prime numbers 2, 3, 5, 7, 11, 13, 17 and 19, and the first 32 bits of binary numbers are taken. 64 32-bit constants are predefined, which are derived from the decimal part of the cube root of the first 64 prime numbers, and the first 32 bits of binary numbers are taken; and a plurality of basic logic functions are defined, including CH (selection function), MAJ (majority function), F0, F1, etc., which are used for data transformation in the subsequent compression process.

[0023] Then the data block processing is performed, and the pre-processed data with an integer multiple of 512 in length is divided into blocks of 512 bits, obtaining a plurality of data blocks. The hash compression operation is performed on each data block in turn until all blocks are processed. For each data block, the current 512-bit data block is split into 16 32-bit words, and the subsequent 48 32-bit words are generated by loop calculation. The data block is subjected to 64 rounds of loop iteration operation, and the specific method and formula of loop iteration operation will be described in detail below.

[0024] After the single data block is processed by 64 rounds of loop iteration, the current 8 new 32-bit hash values are used as the initial hash values for the next message block processing, and the above operation is repeated. After all data blocks are processed, 8 new 32-bit hash values are obtained, forming a 256-bit (32-byte) binary number, which is the final hash result of SHA256. In the process of loop iteration, the 8 new 32-bit hash values obtained after each iteration are the same group of data.

[0025] Figure 2 A schematic diagram of a circuit 200 for performing hash operation is shown. The circuit 200 is used to implement the aforementioned loop operation on a single data block, which can be referred to as a hash operation, and the circuit used to perform the hash operation can be referred to as a hash compressor circuit. Referring to Figure 2The circuit 200 includes eight registers a, b, c, d, e, f, g, h, respectively used to store eight 32-bit initial hash values. In the process of each round of loop operation, the data stored in the eight registers are used, and the data stored in the registers are replaced by new data obtained by the current round of operation and are used in the next round of iteration operation. Therefore, each round of calculation can be regarded as a process of using and updating the data of the eight registers. In order to facilitate the description of the exemplary embodiments of the present disclosure, the name of the register may be directly used to refer to the data stored in the corresponding register in the following description. Those skilled in the art can understand that the register a can also be referred to as the first register, the register b can also be referred to as the second register, and so on. The register c can also be referred to as the third register, the register d can also be referred to as the fourth register, the register e can also be referred to as the fifth register, the register f can also be referred to as the sixth register, the register g can also be referred to as the seventh register, and the register h can also be referred to as the eighth register. Figure 2 The data stored in the eight registers in the N+1th round can be obtained according to the following operation mode:

[0026] t1 = h + F1(e) + CH(e, f, g) + K[i] + cur_w;

[0027] t2 = F0(a) + MAJ(a, b, c);

[0028] h = g;

[0029] g = f;

[0030] f = e;

[0031] e = d + t1;

[0032] d = c;

[0033] c = b;

[0034] b = a;

[0035] a = t1 + t2;

[0036] In the above operation mode, F0 and F1 are shift functions, and their calculation modes are respectively:

[0037] F0(x) = ROTR2(x) XOR ROTR13(x) XOR ROTR22(x),

[0038] F1(x) = ROTR6(x) XOR ROTR11(x) XOR ROTR25(x),

[0039] where ROTRn(x) represents a cyclic right shift of 32-bit variable x by n bits, and represents an exclusive-OR operation, whose logic is "0 for same, 1 for different", that is, judging the consistency of two binary bits and taking the judgment result (0 for same, 1 for different) as the output.

[0040] CH is a selection function, which is calculated as follows:

[0041] CH(x, y, z) = (x AND y) OR ((NOT x) AND z),

[0042] where AND is a 32-bit bitwise AND operation; NOT is a NOT operation. The logical meaning of CH is to select y or z as the output according to the value of x, that is, to make x become a selection switch, and select the value of y as the result when x is 1, and select the value of z as the result when x is 0, and the essence is to dynamically select the corresponding bit of y or z as the output according to the binary bit of x.

[0043] MAJ is a majority function, which is calculated as follows:

[0044] MAJ(x, y, z) = (x AND y) OR (x AND z) OR (y AND z),

[0045] The logical meaning of MAJ is to output the value that is in the majority among the three values x, y, and z, that is, to output 1 when the number of 1s in the three input bits is greater than the number of 0s, and to output 0 when the number of 0s is greater than the number of 1s.

[0046] K[i] is a 32-bit additional constant, and K is a pre-defined constant array, which is a fixed set of values at the time of algorithm design, and the values are derived from the decimal part of the cube root of the first 64 prime numbers, specifically, the first 32 binary numbers of the decimal part of the cube root of the 64 prime numbers are taken to form 64 32-bit constants, and one constant is used in each round of operation. cur_w is the current extended data, which is a 32-bit data.

[0047] As can be seen, in each round of loop operation, 6 of the 8 values, namely a, b, c, e, f, and g, are shifted by 1 position to b, c, d, f, g, and h, respectively. Variables a and e depend on all input values and are calculated in each round. cur_w is a 32-bit data calculated by a data expansion operation and fed to a compression operation, and K[i] is a specific 32-bit constant.

[0048] For the purpose of convenient description, the "receiving x data" or "input data is x" is used in the description of the operation of the circuit in the present disclosure, and those skilled in the art can understand that the meaning of "receiving x data" can be "input data is x". See Figure 2The values of the registers b, c, d, f, g and h of the right-hand side N+1 stage are respectively shifted from the values of the registers a, b, c, e, f and g of the left-hand side N stage (the shift operations are indicated by dashed lines).

[0049] The data in register a of level N+1 is obtained by performing operations on a subset of the data from registers in level N using logic units 202, 204, 206, 208, 210, 212, 216, 218, 220, and 224. Specifically, logic unit 202 receives the data from register a of level N and performs a shift operation F0(a) on it. Logic unit 204 receives the data from register a of level N, the data from register b of level N, and the data from register c of level N, and performs a multi-way multiplication operation (MAJ). Adder 206 receives the output data of logic unit 202, the output data of logic unit 204, and the sum bit data output by adder 220. After adding the three, the output sum bit data is passed to adder 208, while the carry data is passed to adder 208' of the next bit (data flow is shown in the dotted line, the same below). (The previous bit adder 208' indicates that the position of the adder is the same as that of adder 208, but it is used to perform the addition operation of the previous bit, the same below). Adder 208 receives the sum data output by adder 206, the carry data output by the previous bit adder 206' (not shown; the previous bit adder 206' indicates that its position is the same as adder 206, but it is used to perform the addition operation of the previous bit; the data flow is shown by the dotted line, the same below), and the sum data output by adder 220. After adding these three, the output sum data is passed to adder 210, while the carry data is passed to the next bit adder 210' (not shown in the figure). Adder 210 receives the sum data output by adder 208 and the carry data output by the previous bit adder 208' (not shown). After adding the two, the output data is shifted to register a in the (N+1)th stage for use in the next round of operation. Logic unit 212 receives the data in register e in the Nth stage and performs a shift operation F1(e) on it. Logic unit 216 receives data from Nth-level register e, Nth-level register f, and Nth-level register g, and performs CH selection operations. Adder 218 receives the sum data output from adder 224, the carry data output from the previous bit adder 224' (not shown), and the data output from logic unit 216. After adding these three, the output sum data is passed to adder 220, while the carry data is passed to the next bit adder 220' (not shown). Adder 220 receives the sum data output from adder 218, the carry data output from the previous bit adder 218' (not shown), and the data output from logic unit 212. After adding these three, the output sum data is passed to adder 222, while the carry data is passed to the next bit adder 222' (not shown).Adder 224 receives the data stored in the Nth-level register h, constant 226, and extended data 228. After adding the three, the output sum bit data is passed to adder 218, while the carry data is passed to adder 218' (not shown in the figure) for the next bit. Constant 226 is K[i] in the aforementioned formula, and its value is a pre-fixed value selected based on the number of iterations. Extended data 228 can be provided by an extended register outside the circuit. There are 16 extended registers, namely W[0] to W

[15] . In each iteration operation, 15 of the 16 data, namely W

[15] to W[1], are shifted by 1 position to W

[14] to W[0]. The data in the extended register W

[15] is input into the register W

[15] after performing combinational logic operations on the data stored in some other registers. Therefore, W

[15] , that is, the sixteenth extended register, always stores the current extended data. The extended data output to the compressor circuit is the data stored in the sixteenth extended register, that is, W

[15] , which is also the cur_w in the aforementioned formula.

[0050] like Figure 2 As shown, the data in register e of the (N+1)th stage is obtained by processing a portion of the data from registers in the Nth stage through logic unit 212, adder 214, logic unit 216, adder 218, adder 220, adder 222, and adder 224. Adder 222 receives the sum bit data output by adder 220, the carry data output by the previous bit adder 220' (not shown), and the data in register d. After adding these three, the sum bit data is passed to adder 214, while the carry data is passed to adder 214' (not shown) for the next bit. Adder 214 receives the sum bit data output by adder 222 and the carry data output by the previous bit adder 222' (not shown). After adding these two, the output data is shifted into register e for use in the next round of operation. The logic unit 212, logic unit 216, adder 218, adder 220 and adder 224 have been described in detail above, and will not be repeated here.

[0051] In traditional SHA circuits, the combinational logic paths for outputting 'a' and for outputting 'e' are quite long. For example, in Figure 2In the shown circuit, the combinational logic path of output a includes 4 logic operators and 6 adders, i.e. logic operator 202, logic operator 204, adder 206, adder 208, adder 210, logic operator 212, logic operator 216, adder 218, adder 220 and adder 224. The combinational logic path of output e includes 2 logic operators and 5 adders, i.e. logic operator 212, adder 214, logic operator 216, adder 218, adder 220, adder 222 and adder 224. The length of the combinational logic path determines the overall delay of the path, and further determines the frequency and operation speed of the circuit. Thus, the too long path greatly reduces the frequency and operation speed of the circuit. In order to solve the technical problem, the present disclosure proposes a circuit structure of SHA256 compressor, which advances the operation on the combinational logic path, reduces the serial steps of the critical path, and significantly improves the operation speed of the circuit without changing the operation result.

[0052] Figure 3 A schematic diagram of a circuit 300 for performing hash operation according to an exemplary embodiment of the present disclosure is shown. Compared with the circuit 200, the circuit 300 advances the addition of the four data of constant, extended data, data of register h and data of register d by one level, so that the algorithm is the same as the traditional scheme when performing operation at the present level. Referring to Figure 3 , the circuit 300 can include 8 registers a, b, c, d, e, f, g, h and an additional register h', which can be used together with the register h to store data related to the calculation of h. In some embodiments, the registers h and h' can be used to save the sum bit data and carry data output by the adder 326, respectively. The algorithm implemented by the circuit 300 can include three parts:

[0053] h = g + K[i] + cur_w + b;

[0054] e = CH(e, f, g) + h + F1(e);

[0055] a = F0(a) + MAJ(a, b, c) + e - d;

[0056] Corresponding to the above three parts, the combinational logic of the circuit 300 can have a three-segment structure to implement the above three algorithms, wherein the first segment is the calculation circuit of h, the second segment is the calculation circuit of e, and the third segment is the calculation circuit of a. The meanings of the symbols and functions in the above algorithms are the same as before, and will not be repeated. Those skilled in the art can understand that in the hardware implementation of SHA256, the clock cycle is the unit of scheduling the work of the circuit, and each clock cycle triggers the register read and write, the operation unit (such as adder, logic gate, etc.) to perform calculation, and completes a round of iteration. In the circuit 300 as shown inFigure 2 In the conventional SHA256 circuit shown, 8 data calculated and input to the corresponding registers in each clock cycle are the same group of data, while in the circuit 300 of the present disclosure Figure 3 In the exemplary embodiment disclosed, in order to improve the operation speed and make the corresponding calculation in advance, h, e and a calculated in three consecutive clock cycles can be the same group of data. For example, if the first clock cycle, the second clock cycle and the third clock cycle are consecutive clock cycles, the data calculated and input to the register h in the first clock cycle, the data calculated and input to the register e in the second clock cycle and the data calculated and input to the register a in the third clock cycle can be the same group of data.

[0057] Referring to Figure 3 The values of the registers b, c, f and g at the right side of the Nth stage are respectively obtained by shifting the values in the registers a, b, e and f at the left side of the (N-1)th stage (the shift operation is represented by a dashed line). In the combinational logic path of the first section of the circuit for calculating h, it can include the adder 324 and the adder 326; in the combinational logic path of the second section of the circuit for calculating e, it can include the logic operator 314, the logic operator 318, the adder 320, the adder 322 and the adder 316; in the combinational logic path of the third section of the circuit for calculating a, it can include the logic operator 302, the logic operator 304, the adder 312, the adder 306 and the adder 308. It can be seen that in the circuit 300 proposed in the present disclosure, only 3 adders are used in the combinational logic paths of the outputs a and e, compared with the circuit 200, 3 and 2 adders are respectively saved, in addition, compared with the shift path in the circuit 200 that directly shifts g to h, two adders are used in the combinational logic path of the output h of the circuit 300. Since the calculation circuits of a, e and h can run in parallel, compared with the circuit 200, the operation speed of the circuit 300 is greatly improved, in addition, the two adders in the combinational logic path of the output h can also increase the waiting time of the data stored in the register g shifted to the register h, avoiding the situation that the data locking error can be caused due to the too fast speed when directly performing the shift operation.

[0058] In another aspect, when a is calculated in the algorithm implemented by the circuit 300, the operation of "-d" needs to be performed. Since the circuit cannot directly implement the subtraction operation, in order to implement the "-d" operation in the aforementioned algorithm, the operation of inverting d and then adding 1 to the least significant bit needs to be performed. In order to implement this operation, the data output by the register d can be inverted and then 1 is added to the least significant bit. For example, an inverter can be added between the register d at the N-1 stage and the adder 312, and an additional adder can be added after the inverter. However, the output of d is on the output path, so the inverter and the adder are arranged after the register d, which makes the logic combination path of the output a additionally increase by one inverter and one adder, thereby reducing the operation speed of the output circuit of a. In order to not reduce the operation speed of the circuit for calculating a, in an embodiment, when the inversion operation is implemented, an inverter 310 can be arranged after the register c at the N-1 stage, so that the data to be shifted to the register d is inverted by the inverter first and then shifted to the register d. This design not only reduces the length of the combination logic path of a, but also increases the waiting time of the path of the data stored in the register c to be shifted to the register d, thereby avoiding the situation that the data locking error can be caused due to the too short shift path. In an embodiment, when the operation of adding 1 to the least significant bit is implemented, this operation can be arranged to be performed at the least significant bit of the adder 308. Since the adder 308 originally exists in the calculation circuit of a, this design does not increase the length of the combination logic path of the circuit for calculating a. The above is a general description of the design idea of the SHA256 compressor circuit 300 proposed in the present disclosure, and the operation devices used in the circuit will be specifically described below.

[0059] As Figure 3As shown, the logic operator 302 can receive the data stored in the register a of the N-1th stage, and take the data as input data to substitute into the shift function F0(x) to perform the shift logic operation of F0(a). In some embodiments, the single-bit logic operator 302 can be composed of 10 pairs of transistors. The logic operator 304 can receive the data stored in the registers a, b and c of the N-1th stage, and take the three data as input data to substitute into the MAJ(x, y, z) majority function to perform the majority logic operation of MAJ(a, b, c). In some embodiments, the single-bit logic operator 304 can be composed of 6 pairs of transistors. The adder 306 can receive the output data of the logic operator 302 (i.e. the operation result of F0(a)), the sum bit data output by the adder 312 and the carry-in data output by the adder 312' of the previous bit (not shown, the adder 312' of the previous bit means that the adder is located at the same position as the adder 312, but is used to perform the addition operation of the previous bit, and the same applies hereinafter), and perform the addition operation with the three data as input data to obtain and output the corresponding carry-in data and sum bit data. The "carry-in data" and "sum bit data" are two concepts involved in the addition operation of the digital circuit, and are the core of the digital circuit to convert the addition operation into the logic operation, and are one of the underlying principles of the computer to complete the arithmetic calculation, and are mainly used in the design of basic arithmetic units such as the half adder and the full adder. Figure 3 As shown in the dashed line in the middle, since the device outputting the data is not included in the current bit circuit, the dashed line only shows the end point of the data, not the start point, and the same applies hereinafter), the adder 306 can perform the addition operation with the three data as input data to obtain and output the corresponding carry-in data and sum bit data. The "carry-in data" and "sum bit data" are two concepts involved in the addition operation of the digital circuit, and are the core of the digital circuit to convert the addition operation into the logic operation, and are one of the underlying principles of the computer to complete the arithmetic calculation, and are mainly used in the design of basic arithmetic units such as the half adder and the full adder.

[0060] Figure 4A A schematic diagram of a half adder is shown. The half adder is a basic unit for implementing binary addition operation in a digital circuit, and the core function is to complete the independent summation and carry calculation of a single bit in the multi-bit addition operation, without involving the carry signal transmission from the low bit. As shown, Figure 4A The input port can only receive two current bit addend signals, denoted as current bit addend A and current bit addend B, both of which are binary logic signals (only taking values 0 or 1); and the corresponding output port generates two result signals: one is the sum bit signal S (Sum Bit) of the addition of the two addends, which is used to represent the addition result of the bit, and the other is the carry-out bit signal C (Carry-out Bit), which is used to represent the carry information generated by the addition of the bit.

[0061] Figure 4BA schematic diagram of a full adder is shown, which is related to... Figure 4A The core difference between a half-adder and a full adder lies in the fact that a full adder, based on the half-adder, adds the function of receiving the carry signal of the low-order bit (also known as the input carry signal). Therefore, it is suitable for bit operations in multi-bit addition, except for the least significant bit. For example... Figure 4B As shown, in addition to the local addend A and local addend B, which are the same as those in the half addend, the input signal of the full addend also includes an input carry signal Ci from the adjacent low-order bit. This signal is the carry result generated by the low-order bit addition operation and needs to participate in the local addition calculation. Similar to the half addend, the output signal of the full addend also includes the local sum bit signal S and the output carry signal Co passed to the adjacent high-order bit.

[0062] In the construction of practical multi-bit adders, such as 4-bit and 8-bit adders, half-adders and full adders can work together: since the least significant bit does not have a carry signal from a lower bit, a method can be used... Figure 4A The half-adder processes the sum of the least significant bits A0 and B0; however, all bits from the first bit to the most significant bit need to receive the carry signal transmitted from the lower bit, which can be achieved using... Figure 4B The full adder processes the data sequentially, ultimately achieving a complete multi-bit binary addition function. Those skilled in the art will understand that the "previous bit" in this disclosure can be an adjacent low bit, and the "next bit" can be an adjacent high bit.

[0063] Back Figure 3 Adder 306 can send the obtained sum data to adder 308 and send the obtained carry data to the next-stage adder 308' (not shown; the next-bit adder 308' means that the adder position is the same as adder 308, but it is used to perform the addition operation of the next bit. The direction of the output carry data is...) Figure 3The data input to the adder 306 is shown by a dashed line, which only shows the start of the data, not the end, since the data is not input to the devices included in the adder 306, and the same applies to the following. In some embodiments, the single-bit adder 306 can be composed of 14 pairs of transistors. The adder 308 can receive the sum bit data output by the adder 306 and the carry-in data output by the adder 306' (not shown) of the previous bit, add the two as input data bit by bit, and the adder 308 also receives the data "1" as input data to participate in the addition operation when performing the addition operation of the lowest bit, as described above, the operation of "adding 1 to the lowest bit" at the adder 308 is to implement the "-d" operation in the aforementioned algorithm, and the data "1" can be input into the adder 308 as carry-in data. In some embodiments, the single-bit adder 308 can be composed of 14 pairs of transistors. The inverter 310 can receive the data stored in the N-1 level register c as input data, perform an inversion operation on it to generate the complementary data of the data, and the output complementary data can be shifted to the N level register d, thereby combining the operation of "adding 1 to the lowest bit" performed by the adder 308 to jointly implement the "-d" operation in the aforementioned algorithm. The adder 312 can receive the data output by the N-1 level register d and the register e, and the data output by the logic operator 304 (i.e., the operation result of MAJ(a, b, c)), and perform an addition operation on the three data as input data, and the result of the operation can include sum bit data and carry-in data, wherein the sum bit data can be sent to the adder 306 as output data, and the carry-in data can be sent to the adder 306' (not shown) of the next bit as output data. In some embodiments, the single-bit adder 312 can be composed of 14 pairs of transistors. The logic operator 314 can be used to perform the shift logic operation of F1(x), which can receive the data stored in the N-1 level register e as input data and calculate F1(e) by substituting the data into the shift function F1(x). In some embodiments, the single-bit logic operator 314 can be composed of 10 pairs of transistors. The adder 316 can receive the output sum bit data generated by the adder 322 and the output carry-in data generated by the adder 322' (not shown) of the previous bit, perform an addition operation on the two data as its input data, and the result of the operation can be shifted to the N level register e as output data. In some embodiments, the single-bit adder 316 can be composed of 14 pairs of transistors. The logic operator 318 can receive the data stored in the N-1 level registers e, f, g, input e, f, g as input data into the selection function CH, perform a logic operation of CH(e, f, g), and can output the operation result as output data to the adder 320. In some embodiments, the single-bit logic operator 318 can be composed of 6 pairs of transistors.The adder 320 can receive the data stored in the N-1st register h, the data stored in the N-1st register h', and the output data generated by the logic operator 318 (i.e., the operation result of CH(e, f, g)) as input data to perform an addition operation, and the output sum data is sent to the adder 322, and the output carry data is sent to the adder 322' (not shown) of the next bit. In some embodiments, the single-bit adder 320 can be composed of 14 pairs of transistors.

[0064] The circuit 300 proposed by the present disclosure adds two adders in the shift path of the register h, and the last adder 326 in the path generates two data, i.e., the sum data and the carry data, after the addition operation, so in an embodiment, the two sum outputs h related data can be stored in the register h and the additional register h', as shown in Figure 3 The Nth register h can store the sum data therein, and the Nth additional register h' can store the output carry data. Those skilled in the art can understand that the register h' can also be referred to as the ninth register. In some embodiments, instead of adding the additional register h', an additional adder can be added after the adder 326 to perform a sum operation on the output carry data and the sum data, generate an output data, and shift the output data to the Nth register h. This embodiment will be described in detail in the exemplary embodiments of the present disclosure.

[0065] Next, adder 322 receives the sum bit data outputted by adder 320, the carry-in data outputted by adder 320' of the previous bit, and the output data generated by logic operator 314 (i.e., the operation result of F1(e)), and performs addition operation on the three data as input data, and outputs the obtained sum bit data to adder 316 and outputs the carry-in data to adder 316' (not shown) of the next bit. In some embodiments, adder 322 of a single bit can be composed of 14 pairs of transistors. Adder 324 receives the data stored in the N-1th register g, constant 328 and extension data 330. As previously described, constant 328 is a fixed constant preset by SHA256, and extension data 330 is the data stored in the extension register W

[15] , the specific meaning and calculation method of which are the same as previously described, and will not be described again here. Adder 324 performs addition operation on the data stored in the N-1th register g, constant 328 and extension data 330 as input data, and outputs the sum bit data in the operation result as output data to adder 326, and outputs the carry-in data as output data to adder 326' (not shown) of the next bit. Adder 326 receives the data stored in the N-1th register b, the sum bit data outputted by adder 324, and the carry-in data outputted by adder 324' (not shown) of the previous bit as input data, and performs addition operation on the three data, and then shifts the obtained sum bit data to the Nth register h for storage, and shifts the carry-in data to the Nth register h' for storage. In some embodiments, adder 324 of a single bit can be composed of 14 pairs of transistors.

[0066] Figure 5A schematic diagram of a circuit 500 for performing a hash operation according to another exemplary embodiment of the present disclosure is shown. The logic combination path for calculating a in the circuit 500 is the same as that in the circuit 300, except for the logic combination path for calculating h and the logic combination path for calculating e. As previously described, in the circuit 300, the output data of the adder 326 in the combination path for calculating h includes both carry data and sum data, and since a register can only store one 32-bit data, a register h' is added in the circuit 300, with the register h storing the sum data and the register h' storing the carry data. In the circuit 500, an alternative implementation is adopted for the logic combination path for calculating h, i.e. an adder 526 is added at the end of the logic combination path for outputting h, which adds the carry data and the sum data outputted by the previous adder and shifts the added data to the register h. Therefore, compared with the circuit 300, one adder is added in the h output path of the circuit 500, and thus the logic combination path for outputting h includes three adders in total. In addition, the circuit 500 does not need an extra register h'. Since there is only one register h and no extra register h', the addend inputted to the logic combination path for calculating e in the circuit 500 is reduced by one, and thus one adder can be omitted in the path. Therefore, compared with the circuit 300, the logic combination path for calculating e in the circuit 500 can include two logic processors and two adders. The main differences between the circuit 300 and the circuit 500 are described above, and the operation devices used in the circuit will be described in detail below.

[0067] As Figure 5As shown, the logic operator 502 can receive the data stored in the register a of the N-1 stage, and substitute the data as the input data into the shift function F0(x) to perform the shift logic operation of F0(a). In some embodiments, the single-bit logic operator 502 can be composed of 10 transistors. The logic operator 504 can receive the data stored in the registers a, b and c of the N-1 stage, and substitute the three data as the input data into the MAJ(x, y, z) majority function to perform the majority logic operation of MAJ(a, b, c). In some embodiments, the single-bit logic operator 504 can be composed of 6 pairs of transistors. The adder 506 can receive the output data of the logic operator 502 (i.e. the operation result of F0(a)), the sum bit data output by the adder 512, and the carry bit data output by the adder 512' (not shown) of the previous bit, and substitute the three data as the input data to perform the addition operation to obtain and output the corresponding carry bit data and sum bit data. The adder 506 can send the obtained sum bit data to the adder 508, and send the obtained carry bit data to the adder 508' (not shown) of the next bit. In some embodiments, the single-bit adder 506 can be composed of 14 pairs of transistors. The adder 508 can receive the sum bit data output by the adder 506 and the carry bit data output by the adder 506' (not shown) of the previous bit as the input data to perform the bit-by-bit addition, and when performing the addition operation of the lowest bit, the adder 508 can also receive the data "1" as the input data to participate in the addition operation together. As described before, the "add 1 to the lowest bit" operation at the adder 508 is to realize the "-d" operation in the aforementioned algorithm. In some embodiments, the single-bit adder 508 can be composed of 14 pairs of transistors. The inverter 510 can receive the data stored in the register c of the N-1 stage as the input data to perform the inversion operation to generate the complementary data of the data, and the output complementary data can be shifted to the register d of the N stage to realize the "-d" operation in the aforementioned algorithm together with the aforementioned "add 1 to the lowest bit" operation. The adder 512 can receive the data output by the registers d and e of the N-1 stage, and the data output by the logic operator 504 (i.e. the operation result of MAJ(a, b, c)), and substitute the three data as the input data to perform the addition operation to obtain and output the operation result, which can include the sum bit data and the carry bit data, wherein the sum bit data can be sent as the output data to the adder 506, and the carry bit data can be sent as the output data to the adder 506' (not shown) of the next bit. In some embodiments, the single-bit adder 512 can be composed of 14 pairs of transistors. The logic operator 514 can be used to perform the shift logic operation of F1(x), which can receive the data stored in the register e of the N-1 stage as the input data to calculate F1(e) by substituting the data into the shift function F1(x).In some embodiments, the single-bit logic operator 514 can be composed of 10 pairs of transistors. The adder 516 can receive the output from the adder 520 and the bit data, as well as the output carry-in data from the previous bit's adder 520' (not shown), perform an addition operation with the two data as input data, and output the operation result to the Nth-stage register e as output data. In some embodiments, the single-bit adder 516 can be composed of 14 pairs of transistors. The logic operator 518 can receive the data stored in the N-1st-stage registers e, f, and g, input the e, f, and g as input data to the selection function CH, perform a logic operation of CH(e, f, g), and output the operation result as output data to the adder 520. In some embodiments, the single-bit logic operator 518 can be composed of 6 pairs of transistors. The adder 520 can receive the data stored in the N-1st-stage register h, the output data from the logic operator 514 (i.e., the operation result of F1(e)) and the output data from the logic operator 518 (i.e., the operation result of CH(e, f, g)) as input data, perform an addition operation, and output the operation result's sum bit data to the adder 516 and the output carry-in data to the next bit's adder 516' (not shown). In some embodiments, the single-bit adder 520 can be composed of 14 pairs of transistors. The adder 522 can receive the data stored in the N-1st-stage register g, the constant 328, and the extension data 330, where the constant 328 is a fixed constant preset by the SHA256 and the extension data 330 is the data stored in the extension register W

[15] , as previously described. The adder 522 performs a summing addition operation with the data stored in the N-1st-stage register g, the constant 528, and the extension data 530 as input data, outputs the operation result's sum bit data to the adder 524 and the output carry-in data to the next bit's adder 524' (not shown). The adder 524 receives the data stored in the N-1st-stage register b, the adder 522's output sum bit data, and the carry-in data from the previous bit's adder 522' (not shown) as input data, performs an addition operation, and outputs the operation result's sum bit data to the adder 526 and the carry-in data to the next bit's adder 526' (not shown). In some embodiments, the single-bit adder 324 can be composed of 14 pairs of transistors. The adder 526 can receive the output sum bit data from the adder 524 and the output carry-in data from the previous bit's adder 524' (not shown), perform an addition operation with the two data as input data, and output the operation result to the Nth-stage register h as output data. In some embodiments, the single-bit adder 526 can be composed of 14 pairs of transistors.

[0068] In some embodiments, the adders used in this disclosure may be carry-save adders (CSAs) without carry chains or adders with carry chains. In some embodiments, adders 308, 316, 508, 516, and 526 may be adders with carry chains to generate 32-bit data shifted to the corresponding registers. In some embodiments, adders 306, 312, 314, 320, 322, 324, 326, 506, 512, 514, 520, 522, and 524 may be carry-save adders without carry chains.

[0069] Figure 6 A schematic diagram of a chip 600 according to an exemplary embodiment of the present disclosure is shown. Figure 6 As shown, chip 600 may include a data receiving unit 610, a data storage unit 620, a hash algorithm unit 630, a digest output unit 640, and a core control unit 650. The data receiving unit 610 serves as the entry point for the chip to interact with external data, continuously monitoring external interfaces. After capturing data to be processed, it can interact with the core control unit 650, receiving a data reception enable signal from the core control unit 650, and then transmitting the received external data to the data storage unit 620. The data storage unit 620 can store data in a specific location based on the data sent by the data receiving unit 610 and the control commands sent by the core control unit 650, and can provide feedback on its data storage status to the core control unit 650, such as remaining storage space and whether the data is completely stored. On the other hand, when the hash algorithm unit 630 needs data, the data storage unit 620, under the scheduling of the core control unit 650, can transmit the temporarily stored data to be hashed to the hash algorithm unit 630. The hash algorithm unit 630 may have a built-in specific hash algorithm such as SHA256. In some implementations, the hash algorithm unit 630 may include the SHA256 compressor circuit provided in the aforementioned exemplary embodiments of this disclosure, for example... Figure 3 The circuit 300 shown or Figure 5The circuit 500 is shown. The hash algorithm unit 630 can perform a specific hash operation according to instructions sent by the core control unit 650, such as hash calculation start, algorithm selection, etc. During the calculation process, the hash algorithm unit 630 can feed back the calculation progress to the core control unit 650, such as the current iteration round, whether there is a calculation exception, etc. After the calculation is completed, the generated fixed-length hash digest can be transmitted to the digest output unit 640. After receiving the hash digest from the hash algorithm unit 630, the digest output unit 640 can output the hash digest to the external system through a suitable external interface (such as a serial port, a bus interface, etc.) according to the output enable, output interface selection, etc. control instructions sent by the core control unit 650. The core control unit 650 can interact with other units and control the working state of other units.

[0070] According to an example embodiment of the present disclosure, the present disclosure also provides an electronic device, comprising: a circuit board and a chip. The chip can be as Figure 6 The chip 600 is shown, which can be arranged on the circuit board. The chip implementing the technical solutions of the present disclosure can be applied to various possible electronic devices, and the electronic device can be a computing device with computing power, or a terminal device or a server with data processing function, and the present disclosure does not limit the specific type of the electronic device.

[0071] Figure 7 A schematic diagram of a method 700 for performing hash operation according to an example embodiment of the present disclosure is shown. The example method 700 can be performed by the SHA256 compressor circuit as Figure 3 or Figure 5 shown, or by the chip as Figure 6 shown or the electronic device comprising the chip.

[0072] Referring to Figure 7 , the example method 700 can include: operation 710, calculating the data of the eighth register in the first clock cycle; operation 720, calculating the data of the fifth register in the second clock cycle; and operation 730, calculating the data of the first register in the third clock cycle; wherein the first clock cycle, the second clock cycle and the third clock cycle are consecutive clock cycles, and the data of the eighth register in the first clock cycle, the data of the fifth register in the second clock cycle and the data of the first register in the third clock cycle are the same group of data.

[0073] In some embodiments, the method can further include: using a first adder to receive the data stored in the seventh register, extend the data stored in the register and the constant, and perform a summation operation; using a second adder to receive the output data of the first adder and the data stored in the second register and perform a summation operation.

[0074] In some embodiments, the method can further comprise: receiving data stored in the third register using an inverter; receiving and storing data outputted by the inverter using a fourth register; receiving data stored in the first register, data stored in the second register and data stored in the third register using a first logic operator; receiving data stored in the first register using the second logic operator; receiving data stored in the fourth register, data stored in the fifth register and output data of the first logic operator using a third adder; receiving output data of the third adder and output data of the second logic operator using a fourth adder; receiving output data of the fourth adder using a fifth adder; wherein the fifth adder further receives a constant 1 to perform addition of the lowest bit, and receiving and storing output data of the fifth adder using the first register.

[0075] In some embodiments, the output data of the second adder can comprise a first part and a second part, and the method can further comprise: receiving and storing the first part of the output data of the second adder using an eighth register, and receiving and storing the second part of the output data of the second adder using a ninth register; receiving data stored in the fifth register, data stored in the sixth register and data stored in the seventh register using a third logic operator; receiving data stored in the fifth register using a fourth logic operator; receiving data stored in the eighth register, data stored in the ninth register and output data of the third logic operator using a sixth adder; receiving output data of the sixth adder and output data of the fourth logic operator using a seventh adder; receiving output data of the seventh adder using an eighth adder; and receiving and storing output data of the eighth adder using the fifth register.

[0076] In some embodiments, the method can further comprise: receiving input data of the second adder using a ninth adder; receiving and storing output data of the ninth adder using an eighth register; receiving data stored in the fifth register, data stored in the sixth register and data stored in the seventh register using a fifth logic operator; receiving data stored in the fifth register using a sixth logic operator; receiving data stored in the eighth register, output data of the fifth logic operator and output data of the sixth logic operator using a tenth adder; receiving output data of the tenth adder using an eleventh adder; and receiving and storing output data of the eleventh adder using the fifth register.

[0077] In some embodiments, the adder can comprise a carry-save adder.

[0078] In some embodiments, the fifth adder, the eighth adder, the ninth adder or the eleventh adder can further comprise a carry chain.

[0079] In some embodiments, the extension register can comprise a sixteenth extension register.

[0080] As mentioned above and reiterated below, the present disclosure includes, but is not limited to, the following exemplary embodiments.

[0081] One exemplary embodiment provides a circuit for performing a hash operation, which can comprise: first to eighth registers for storing data, a first adder and a second adder; wherein the input data of the first adder comprises: data stored in the seventh register, data stored in an extension register outside the circuit and a constant; the input data of the second adder comprises: output data of the first adder and data stored in the second register.

[0082] In some embodiments, the circuit can further comprise: an inverter, third to fifth adders, a first logic operator and a second logic operator; wherein the input data of the inverter comprises: data stored in the third register; the output data of the inverter is received and stored by the fourth register; the input data of the first logic operator comprises: data stored in the first register, data stored in the second register and data stored in the third register; the input data of the second logic operator comprises: data stored in the first register; the input data of the third adder comprises: data stored in the fourth register, data stored in the fifth register and output data of the first logic operator; the input data of the fourth adder comprises: output data of the third adder and output data of the second logic operator; the input data of the fifth adder comprises: output data of the fourth adder; wherein the input data of the lowest bit of the fifth adder further comprises a constant 1, and the output data of the fifth adder is received and stored by the first register.

[0083] In some embodiments, the circuit can further comprise a ninth register, a sixth to eighth adder, a third logic operator and a fourth logic operator; wherein the output data of the second adder comprises a first part and a second part, the first part of the output data of the second adder is received and stored by the eighth register, and the second part of the output data of the second adder is received and stored by the ninth register; the input data of the third logic operator comprises the data stored by the fifth register, the data stored by the sixth register and the data stored by the seventh register; the input data of the fourth logic operator comprises the data stored by the fifth register; the input data of the sixth adder comprises the data stored by the eighth register, the data stored by the ninth register and the output data of the third logic operator; the input data of the seventh adder comprises the output data of the sixth adder and the output data of the fourth logic operator; the input data of the eighth adder comprises the output data of the seventh adder; and the output data of the eighth adder is received and stored by the fifth register.

[0084] In some embodiments, the circuit can further comprise a ninth to eleventh adder, a fifth logic operator and a sixth logic operator; wherein the input data of the ninth adder comprises the input data of the second adder; the output data of the ninth adder is received and stored by the eighth register; the input data of the fifth logic operator comprises the data stored by the fifth register, the data stored by the sixth register and the data stored by the seventh register; the input data of the sixth logic operator comprises the data stored by the fifth register; the input data of the tenth adder comprises the data stored by the eighth register, the output data of the fifth logic operator and the output data of the sixth logic operator; the input data of the eleventh adder comprises the output data of the tenth adder; and the output data of the eleventh adder is received and stored by the fifth register.

[0085] In some embodiments, the adder can comprise a carry-save adder.

[0086] In some embodiments, the fifth adder, the eighth adder, the ninth adder or the eleventh adder can further comprise a carry chain.

[0087] In some embodiments, the extension register can comprise a sixteenth extension register.

[0088] In the present disclosure, the term "circuitry" can refer to one or more or all of: (a) hardware-only circuit implementations such as those comprised of only analog and / or digital hardware, (b) combinations of hardware circuits and software other than as just described in (a), if applicable, such as: (i) a combination of analog-only hardware circuits and software / hardware (ii) a combination of digital-only hardware circuits and software / hardware (iii) a combination of analog- and-digital hardware circuits and software / hardware, and (iv) portions of hardware circuits and software other than as just described in (a) and (b), if applicable, such as: (i) software / hardware combinations having other than just analog hardware (ii) software / hardware combinations having other than just digital hardware (iii) software / hardware combinations having other than just analog and digital hardware (iv) software / hardware combinations having other than just portions of hardware circuits and software, if applicable, such as: (i) any part of hardware processor circuits other than as just described in (a) through (iii) (ii) any part of software other than as just described in (a) through (iii) (c) to the extent that the foregoing (a), (b), and / or (c) includes hardware, such hardware can comprise a processor of a mobile device, other than the software / hardware combination of (a) through (c) above. As a further example, in the present disclosure, a "circuit" can also refer to, be part of, and / or operate as any of: a processor of a mobile device, a processor of a base station, a processor of a server, a processor of a cellular network device, or a similar integrated circuit in a server, cellular network device, or other computing or network device, if applicable to a particular claim feature.

[0089] The above describes the basic principles of the present disclosure in conjunction with the embodiments, but it should be noted that the advantages, benefits, effects and the like mentioned in the present disclosure are only examples and are not limiting, and these advantages, benefits, effects and the like cannot be considered as necessary for each embodiment of the present disclosure. In addition, the specific details of the above disclosure are only for the purpose of example and for the purpose of understanding, and are not limiting, and the above details do not limit the present disclosure to be necessarily implemented with the above specific details.

[0090] The words "comprise", "comprising", "include", "including", "have", "has", "contain", "containing", or similar words in the present disclosure are open-ended words that is "including but not limited to", and can be used interchangeably. The words "or" and "and" as used herein are the inclusive and not the exclusive or, and can be used interchangeably, unless the context clearly indicates otherwise. The word "such as" as used herein is the phrase "such as but not limited to", and can be used interchangeably.

[0091] In addition, in each of the example embodiments of the present disclosure, each component or each step can be decomposed and / or recombined. These decompositions and / or recombinations should be considered as equivalent solutions of the present disclosure.

[0092] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other aspects without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0093] The above description has been presented to enable any person skilled in the art to make or use the disclosure. The description is not intended to limit the embodiments of the disclosure to the forms disclosed herein. Although a number of example aspects and embodiments have been discussed, those of skill in the art will recognize certain modifications, alternatives, changes, additions, and sub-combinations thereof.

[0094] Although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter defined in the appended claims is not limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example implementations of the claims.

Claims

1. A circuit for performing a hash operation, comprising: Registers 1 through 8 are used to store data; among them... The data input into the eighth register in the first clock cycle, the data input into the fifth register in the second clock cycle, and the data input into the first register in the third clock cycle are the same set of data. The first clock cycle, the second clock cycle, and the third clock cycle are consecutive clock cycles.

2. The circuit as described in claim 1, further comprising: The first adder and the second adder; wherein... The input data of the first adder includes: the data stored in the seventh register, the data stored in the extended register outside the circuit, and constants; The input data of the second adder includes the output data of the first adder and the data stored in the second register.

3. The circuit as described in claim 2, further comprising: Inverter, third to fifth adders, first logic unit, and second logic unit; wherein... The input data of the inverter includes: the data stored in the third register; The output data of the inverter is received and stored in the fourth register; The input data of the first logic unit includes: data stored in the first register, data stored in the second register, and data stored in the third register; The input data of the second logic unit includes: the data stored in the first register; The input data of the third adder includes: the data stored in the fourth register, the data stored in the fifth register, and the output data of the first logic unit; The input data of the fourth adder includes: the output data of the third adder and the output data of the second logic unit; The input data for the fifth adder includes the output data of the fourth adder; The least significant bit of the input data for the fifth adder also includes the constant 1. The output data of the fifth adder is received and stored by the first register.

4. The circuit as described in claim 2, further comprising: The ninth register, the sixth to eighth adders, the third logic unit, and the fourth logic unit; among them, The output data of the second adder includes a first part and a second part. The first part of the output data of the second adder is received and stored by the eighth register, and the second part of the output data of the second adder is received and stored by the ninth register. The input data of the third logic unit includes: the data stored in the fifth register, the data stored in the sixth register, and the data stored in the seventh register; The input data of the fourth logic unit includes: the data stored in the fifth register; The input data of the sixth adder includes: the data stored in the eighth register, the data stored in the ninth register, and the output data of the third logic unit; The input data of the seventh adder includes: the output data of the sixth adder and the output data of the fourth logic unit; The input data for the eighth adder includes the output data for the seventh adder; The output data of the eighth adder is received and stored by the fifth register.

5. The circuit as described in claim 2, further comprising: Adders nine through eleven, the fifth logic unit, and the sixth logic unit; among them, The input data for the ninth adder includes: the input data for the second adder; The output data of the ninth adder is received and stored by the eighth register; The input data of the fifth logic unit includes: the data stored in the fifth register, the data stored in the sixth register, and the data stored in the seventh register; The input data of the sixth logic unit includes: the data stored in the fifth register; The input data of the tenth adder includes: the data stored in the eighth register, the output data of the fifth logic unit, and the output data of the sixth logic unit; The input data for the eleventh adder includes the output data of the tenth adder; The output data of the eleventh adder is received and stored by the fifth register.

6. The circuit as described in any one of claims 2 to 5, wherein: The adder includes a carry-store adder.

7. The circuit as described in any one of claims 2 to 5, wherein: The fifth, eighth, ninth, or eleventh adder also includes a carry chain.

8. The circuit as described in any one of claims 2 to 5, wherein: The extended registers include the sixteenth extended register.

9. A chip, comprising: The circuit as described in any one of claims 1-8.

10. An electronic device, comprising: The chip as described in claim 9.

11. A method for performing a hash operation, comprising: The data input to the eighth register is calculated during the first clock cycle; The data input to the fifth register is calculated during the second clock cycle; as well as, The data input to the first register is calculated in the third clock cycle; The first clock cycle, the second clock cycle, and the third clock cycle are consecutive clock cycles. The data input to the eighth register in the first clock cycle, the data input to the fifth register in the second clock cycle, and the data input to the first register in the third clock cycle are the same set of data.

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