Ethernet circuit, PoE device and PoE system

Abstract

The Ethernet circuit comprises a first rectifier bridge, a second rectifier bridge, a PD chip, a PSE chip, a relay, a first switching device and a network port. The first rectifier bridge is connected with the network port through the first cable pair and the second cable pair. The second rectifier bridge is connected with the network port through a third cable pair and a fourth cable pair; and the first rectifier bridge, the second rectifier bridge and the PD chip are connected in parallel to form a first parallel node and a second parallel node. A first terminal of the PD chip is electrically connected to the first parallel node. The relay is electrically connected with the first parallel connection node, the first rectifier bridge and the second rectifier bridge. The first port of the first switching device is connected with the second terminal of the PD chip, and the PSE chip is connected with the second port of the first switching device. And the network port is used for selectively connecting external power supply equipment or external PD equipment, so that the Ethernet circuit is switched between a PD mode and a PSE mode. And in the PD mode, a PD loop through which the power supply equipment supplies power to the PoE load is formed. In the PSE mode, a PSE loop through which the power supply module supplies power to the PD is formed.

Description

Technical Field

[0001] This application relates to the field of Ethernet technology, and more specifically, to an Ethernet circuit, a PoE device, and a PoE system. Background Technology

[0002] Power over Ethernet (PoE) is a technology that transmits data and power simultaneously over standard Ethernet cables. Network communication devices with PoE capabilities, whether single-port or multi-port, typically have only one port function: Power Sourcing Equipment (PSE) or Powered Device (PD), or neither. Users need to carefully distinguish between the different ports to avoid incorrect connection. Summary of the Invention

[0003] Based on the above technical problems, this application provides an Ethernet circuit, a PoE device, and a PoE system.

[0004] In a first aspect, this application provides an Ethernet circuit for a PoE device. The PoE device includes a power supply module and a PoE load. The Ethernet circuit includes a first rectifier bridge, a second rectifier bridge, a PD chip, a PSE chip, a mode switching unit, a first switching device, and a network port. The first rectifier bridge is connected to the network port via a first cable pair and a second cable pair. The second rectifier bridge is connected to the network port via a third cable pair and a fourth cable pair. The first rectifier bridge, the second rectifier bridge, and the PD chip are connected in parallel to form a first parallel node and a second parallel node. The first terminal of the PD chip is electrically connected to the first parallel node. The mode switching unit is electrically connected to the first parallel node, the first rectifier bridge, and the second rectifier bridge. The first port of the first switching device is connected to the second terminal of the PD chip, and the PSE chip is connected to the second port of the first switching device. The network port is used to selectively connect to an external power supply device or an external PD device, enabling the Ethernet circuit to switch between PD mode and PSE mode. In the PD mode, the PD chip is activated to enable the power supply device to supply power to the PoE load through the PD circuit. The PD circuit is formed by the positive terminal of the power supply device plugged into the PoE device, any one of the first cable pair to the fourth cable pair, an input rectifier bridge, the PD chip, an output rectifier bridge, any one of the remaining three components from the first cable pair to the fourth cable pair, and the negative terminal of the power supply device. The input rectifier bridge is either the first rectifier bridge or the second rectifier bridge directly connected to the positive terminal of the power supply device. The output rectifier bridge... The rectifier bridge is either the first rectifier bridge or the second rectifier bridge directly connected to the negative terminal of the power supply device. In the PSE mode, the PSE chip operates to enable the power supply module to supply power to the PD device through the PSE circuit. The positive terminal of the power supply module, the first parallel node, the mode switching unit, the second cable pair and the third cable pair, the PD device plugged into the network port, the first cable pair and the fourth cable pair, the first rectifier bridge and the second rectifier bridge, the second parallel node and the negative terminal of the power supply module together form the PSE circuit.

[0005] In some embodiments, the first rectifier bridge includes a first switching unit, a second switching unit, a third switching unit, and a fourth switching unit. The negative terminal of the first switching unit is connected to the positive terminal of the second switching unit to form a first node; the negative terminal of the second switching unit is connected to the negative terminal of the third switching unit to form a second node; the positive terminal of the third switching unit is connected to the negative terminal of the fourth switching unit to form a third node; and the positive terminal of the fourth switching unit is connected to the positive terminal of the first switching unit to form a fourth node. The first node is electrically connected to the first cable, and the third node is electrically connected to the second cable.

[0006] In some embodiments, the second rectifier bridge includes a first switching assembly, a second switching assembly, a third switching assembly, and a fourth switching assembly. The negative terminal of the first switching assembly is connected to the positive terminal of the second switching assembly to form a fifth node; the negative terminal of the second switching assembly is connected to the negative terminal of the third switching assembly to form a sixth node; the positive terminal of the third switching assembly is connected to the negative terminal of the fourth switching assembly to form a seventh node; and the positive terminal of the fourth switching assembly is connected to the positive terminal of the first switching assembly to form an eighth node. The fifth node is electrically connected to the third cable, the seventh node is electrically connected to the fourth cable, the second node and the sixth node are shared in the first parallel node, and the fourth node and the eighth node are shared in the second parallel node.

[0007] In some embodiments, the positive terminal of the power supply module is electrically connected to the first parallel node, and the negative terminal of the power supply module is electrically connected to the second parallel node; the first terminal of the PD chip is connected to both the positive terminal of the power supply module and the first parallel node, and the second terminal of the PD chip is connected to both the negative terminal of the power supply module and the second parallel node.

[0008] In some embodiments, the PSE chip includes a first interface, a second interface, a third interface, a fourth interface, and a fifth interface. The first interface and the second interface are electrically connected to the first switching unit and are respectively used to output a first control signal and a first drive signal to jointly control the on / off state of the first switching transistor in the first switching unit. The third interface and the fourth interface are respectively electrically connected to the fourth switching assembly and are respectively used to output a second control signal and a second drive signal to jointly control the on / off state of the second switching transistor in the fourth switching assembly. The PSE chip is electrically connected to the second parallel node through the first switching device. The fifth interface is electrically connected to the gate of the first switching device and the mode switching unit, respectively, and outputs a third control signal to control the on / off state of the first switching device and control the switching pin conduction path of the mode switching unit, so that the Ethernet circuit switches between the PD mode and the PSE mode.

[0009] In some embodiments, the mode switching unit includes a first pin, a second pin, a third pin, a fourth pin, a fifth pin, a sixth pin, a seventh pin, and an eighth pin. The first pin is electrically connected to the VCC power supply; the second pin is electrically connected to the third switching unit; the third pin is electrically connected to the first parallel node; the fourth pin is electrically connected to the third node; the fifth pin is electrically connected to the sixth node; the sixth pin is electrically connected to the first parallel node; the seventh pin is electrically connected to the second switching assembly; and the eighth pin is electrically connected to the fifth interface via a second switching device, grounded via the second switching device, and electrically connected to the VCC power supply via a diode. In the PD mode, the third control signal output by the fifth interface is at a first level, the second switching device is off, the third pin is electrically connected to the second pin, and the sixth pin is electrically connected to the seventh pin; in the PSE mode, the third control signal output by the fifth interface is at a second level, the second switching device is on, the third pin is electrically connected to the fourth pin, and the sixth pin is electrically connected to the eighth pin.

[0010] In some embodiments, the second switching device is an NPN transistor. The base of the second switching device is electrically connected to the fifth interface through a current-limiting resistor, the collector of the second switching device is electrically connected to the eighth pin of the mode switching unit, and the emitter of the second switching device is grounded. A bias resistor is connected in parallel between the base and emitter of the second switching device to stabilize the conduction state of the second switching device.

[0011] In some embodiments, the first switching device is an NMOS transistor. The gate of the first switching device is electrically connected to the fifth interface, the drain of the first switching device is electrically connected to the second parallel node, and the source of the first switching device is electrically connected to the current detection interface of the PSE chip. The current detection interface is also grounded through a detection resistor R20. The current detection interface is used to detect the current of the PSE circuit in real time during the PSE mode. When the detected current exceeds a preset current threshold, the PSE chip adjusts the output of the first drive signal and the second drive signal of the second interface and the fourth interface to cut off the conduction path of the first rectifier bridge and the second rectifier bridge.

[0012] In some embodiments, the PD chip further includes an I2C communication terminal and an interrupt terminal, and the PSE chip further includes an I2C communication interface and an interrupt interface. The I2C communication terminal communicates bidirectionally with the I2C communication interface for reporting information in the PD mode. The interrupt terminal is electrically connected to the interrupt interface for sending an interrupt signal to the PSE chip when overcurrent, overvoltage, or undervoltage is detected in the PSE mode, triggering the PSE chip to control the first switching device to turn off and disconnect the PSE circuit.

[0013] Secondly, this application provides a PoE device, which includes an Ethernet circuit, a PoE load, and a power supply module as described in any of the above embodiments. The PoE load is electrically connected to the Ethernet circuit, and the power supply device is used to supply power to the PoE load through the Ethernet circuit. The power supply module is electrically connected to the Ethernet circuit, and the power supply module is used to supply power to the PD device through the Ethernet circuit.

[0014] Thirdly, this application provides a PoE system, which includes the PoE device and external device described in the above embodiments. The external device is electrically connected to any one of the network ports of the PoE device. When the external device is a power supply device, the power supply device supplies power to the PoE load in the PoE device through the Ethernet circuit; when the external device is a PD device, the PD device obtains power from the power supply module in the PoE device.

[0015] The Ethernet circuit, PoE device, and PoE system of this application integrate a PD chip, a PSE chip, a mode switching unit, and two sets of rectifier bridges. By switching the mode switching unit, the same network port can switch between PD mode and PSE mode. In PD mode, a PD loop can be formed, and the power supply device plugged into the PoE device can supply power to the load in the PoE device through the PD loop. In PSE mode, a PSE loop can be formed, and the power supply module in the PoE device can supply power to the PD device plugged into the network port through the PSE loop. In this way, a physical network port is upgraded from a port with only a single function of power supply or power reception to an intelligent port with both power reception and power supply functions. When using it, users no longer need to remember or distinguish the function of a specific network port. They can plug in any network port to meet their required power supply or power reception functions.

[0016] Additional aspects and advantages of embodiments of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of embodiments of this application. Attached Figure Description

[0017] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, wherein: Figure 1 This is a simplified structural diagram of an Ethernet circuit according to certain embodiments of this application; Figure 2 This is a schematic diagram of the structure of a PoE device according to certain embodiments of this application; Figure 3 This is a partial structural schematic diagram of an Ethernet circuit according to certain embodiments of this application; Figure 4 for Figure 1 The diagram shows the equivalent circuit of the Ethernet circuit in PD mode. Figure 5 for Figure 4 The diagram shown illustrates the current flow direction of an Ethernet circuit in PD mode. Figure 6 for Figure 1 The diagram shows the equivalent circuit of the Ethernet circuit in PSE mode. Figure 7 for Figure 1 The diagram shown illustrates the current flow direction of the Ethernet circuit in PSE mode. Figure 8 This is a partial structural schematic diagram of an Ethernet circuit according to certain embodiments of this application; Figure 9 This is a schematic diagram of another part of the Ethernet circuit according to certain embodiments of this application; Figure 10 This is a schematic diagram of a portion of the Ethernet circuit according to certain embodiments of this application; Figure 11 This is a flowchart illustrating the workflow of a PoE device according to certain embodiments of this application; Figure 12 This is a schematic diagram of the structure of a POE system according to certain embodiments of this application.

[0018] Explanation of key component symbols: PoE System 1000; PoE device 100, external device 200; power supply device 201, PD device 202; Ethernet circuit 10, power supply module 20, PoE load 30; First cable pair PAIR-A, second cable pair PAIR-B, third cable pair PAIR-C, fourth cable pair PAIR-D; First parallel node N+, second parallel node N-; First rectifier bridge 11, second rectifier bridge 12, PD chip 13, PSE chip 14, mode switching unit SW1, network port 16, first switching device Q17; First switch unit 111, second switch unit 112, third switch unit 113, fourth switch unit 114; First switch assembly 121, second switch assembly 122, third switch assembly 123, fourth switch assembly 124; First node N1, second node N2, third node N3, fourth node N4, fifth node N5, sixth node N6, seventh node N7, eighth node N8; First terminal 131, second terminal 132; First interface 141, second interface 142, third interface 143, fourth interface 144, fifth interface 145; Pin 1, Pin 2, Pin 3, Pin 4, Pin 5, Pin 6, Pin 7, Pin 8; First port 171, second port 172; Second switching device Q18; First switch Q4, second switch Q16; Data terminal 133, clock terminal 134, interrupt terminal 135; Data interface 146, clock interface 147, interrupt interface 148, current detection interface 149; Sensing resistor R20, bias resistor R21, current limiting resistor R22; Input rectifier bridge B1, output rectifier bridge B2; Diode D9. Detailed Implementation

[0019] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the embodiments of this application, and should not be construed as limiting the embodiments of this application.

[0020] Power over Ethernet (PoE) is a technology that transmits data and power simultaneously over standard Ethernet cables. Network communication devices with PoE functionality, whether single-port or multi-port, typically have only one port function: Power Sourcing Equipment (PSE) or Powered Device (PD), or neither. Users must carefully distinguish between ports with different functions for correct connection, which can easily lead to incorrect port connections. To address this issue, this application provides an Ethernet circuit 10, a PoE device 100, and a PoE system 1000.

[0021] Please see Figure 1 , Figure 2 and Figure 12 In a first aspect, embodiments of this application provide an Ethernet circuit 10 applied to a PoE device 100. The PoE device 100 includes a power supply module 20 and a PoE load 30. The Ethernet circuit 10 includes a first rectifier bridge 11, a second rectifier bridge 12, a PD chip 13, a PSE chip 14, a mode switching unit SW1, a first switching device Q17, and a network port 16. The first rectifier bridge 11 is connected to the network port 16 via a first cable pair PAIR-A and a second cable pair PAIR-B. The second rectifier bridge 12 is connected to the network port 16 via a third cable pair PAIR-C and a fourth cable pair PAIR-D. The first rectifier bridge 11, the second rectifier bridge 12, and the PD chip 13 are connected in parallel to form the first parallel node N+ and the second parallel node N-. The first terminal 131 of the PD chip 13 is electrically connected to the first parallel node N+. The mode switching unit SW1 is electrically connected to the first parallel node N+, the first rectifier bridge 11, and the second rectifier bridge 12. The first port 171 (drain) of the first switching device Q17 is connected to the second terminal 132 of the PD chip 13. The PSE chip 14 is connected to the second port 172 (source) of the first switching device Q17. The network port 16 is used to selectively connect to the external power supply device 201 or the external PD device 202 so that the Ethernet circuit 10 can switch between PD mode and PSE mode.

[0022] In PD mode, PD chip 13 is activated so that power supply device 201 can supply power to PoE load 30 through PD circuit. The PD circuit is formed by the positive terminal of power supply device 201 plugged into PoE device 100, any one of the first cable pair PAIR-A to the fourth cable pair PAIR-D, input rectifier bridge B1, PD chip, output rectifier bridge B2, any one of the remaining three of the first cable pair PAIR-A to the fourth cable pair PAIR-D, and negative terminal of power supply device 201. The input rectifier bridge B1 is either the first rectifier bridge 11 or the second rectifier bridge 12 directly connected to the positive terminal of power supply device 201, and the output rectifier bridge B2 is either the first rectifier bridge 11 or the second rectifier bridge 12 directly connected to the negative terminal of power supply device 201.

[0023] In PSE mode, PSE chip 14 operates to enable power supply module 20 to supply power to PD device 202 through PSE circuit. The PSE circuit is formed by the positive terminal of power supply module 20, first parallel node N+, mode switching unit SW1, second cable pair PAIR-B and third cable pair PAIR-C, PD device 202 plugged into network port 16, first cable pair PAIR-A and fourth cable pair PAIR-D, first rectifier bridge 11 and second rectifier bridge 12, second parallel node N- and negative terminal of power supply module 20.

[0024] PoE device 100 is a network device that can simultaneously receive or provide data connectivity and DC power via a standard Ethernet cable. PoE device 100 is typically used as a critical node in network infrastructure, such as PoE-enabled switches / routers, wireless access points (APs), network cameras (IPCs), IP phones, IoT gateways, and industrial communication equipment, to simplify cabling, centralize power supply, and enhance deployment flexibility.

[0025] Ethernet circuit 10 is the core circuit module in PoE device 100 that realizes the functions of Ethernet data transmission and reception and bidirectional PoE power transmission (power receiving and supply). Power supply module 20 is a power supply integrated circuit structure in PoE device 100 that provides stable DC power to the device itself and external devices. Its input can come from an AC adapter or a built-in battery, and its output is connected to Ethernet circuit 10 to provide output power in PSE mode, and can serve as a supplement or backup to the system power in PD mode. PoE load 30 is a functional unit in PoE device 100 that relies on PoE power to operate, for example... Figure 3The PoE device 100 shown includes a main controller (CPU / MCU), switching chip, memory, sensors, and various peripheral circuits. The power for the PoE load 30 is supplied by the power supply module 20 and / or external PoE power received through the Ethernet circuit 10. Specifically, the Ethernet circuit 10 includes a first rectifier bridge 11, a second rectifier bridge 12, a PD chip 13, a PSE chip 14, a mode switching unit SW1, a first switching device Q17, and a network port 16.

[0026] The first rectifier bridge 11 is a bridge circuit in the Ethernet circuit 10 used to process the power-on signals of the first cable pair PAIR-A and the second cable pair PAIR-B. The first rectifier bridge 11 consists of four switching units (such as MOSFETs) forming a full-bridge topology. In PD mode, regardless of the polarity of the input voltage from these two cable pairs (PAIR-A, PAIR-B), rectification can be performed to provide the correct polarity DC power to subsequent circuits; in PSE mode, specific switching units inside the first rectifier bridge 11 can be controlled by the PSE chip 14 as controllable switches for the current return path.

[0027] The second rectifier bridge 12 is a bridge circuit in the Ethernet circuit 10 connected in parallel with the first rectifier bridge 11, used to process the power-on signals of the third cable pair PAIR-C and the fourth cable pair PAIR-D. The structure of the second rectifier bridge 12 is the same as that of the first rectifier bridge 11, and both are configured to extend the power supply capability of the PoE device 100 to all four Ethernet pairs. The output terminals of the first rectifier bridge 11 and the second rectifier bridge 12 are connected together, forming the first parallel node N+ (positive bus) and the second parallel node N- (negative bus) within the circuit.

[0028] The input rectifier bridge B1 and the output rectifier bridge B2 are the first rectifier bridge 11 and / or the second rectifier bridge 12 through which the PD circuit corresponding to any pair of the first cable pair PAIR-A, the second cable pair PAIR-B, the third cable pair PAIR-C, and the fourth cable pair PAIR-D passes (a total of 12 combinations based on their connection positions with the positive and negative terminals of the power supply device 201). For example, when the first cable pair PAIR-A is connected to the positive terminal of the power supply device 201 and the second cable pair PAIR-B is connected to the negative terminal of the power supply device 201, both the input rectifier bridge B1 and the output rectifier bridge B2 are the first rectifier bridge 11; as another example, when the second cable pair PAIR-B is connected to the positive terminal of the power supply device 201 and the third cable pair PAIR-C is connected to the negative terminal of the power supply device 201, the input rectifier bridge B1 is the first rectifier bridge 11, and the output rectifier bridge B2 is the second rectifier bridge 12.

[0029] The PD chip 13 is a controller connected between the first parallel node N+ and the second parallel node N- in the Ethernet circuit 10. In PD mode, the PD chip 13 performs protocol handshake, hierarchical classification, and implements input-side electrical protection with the external power supply device 201. In addition, the PD chip 13 has a communication interface (such as I2C) for exchanging status information with the main controller (CPU / MCU) or the PSE chip 14.

[0030] PSE chip 14 is a management chip in Ethernet circuit 10 used to control external power supply. The operating state of PSE chip 14 is controlled by the first switching device Q17. When enabled, PSE chip 14 outputs a signal to drive the mode switching unit SW1 to switch, and drives the transistors in the first rectifier bridge 11 and the second rectifier bridge 12, which serve as return path switches, through its control pins (such as GATE1, GATE2), thereby realizing PSE functions such as detection, classification, power supply, and overcurrent protection for the external PD device 202.

[0031] The mode switching unit SW1 is an electromagnetic switching device controlled by the PSE chip 14 in the Ethernet circuit 10, used to switch the current path between PD mode and PSE mode. It can be a relay. The coil drive circuit of the mode switching unit SW1 receives the (third) control signal. In the default state (PD mode), its contacts can guide PAIR-B and PAIR-C to the first rectifier bridge 11 and the second rectifier bridge 12 for rectification; in the operating state (PSE mode), its contacts directly connect PAIR-B and PAIR-C to the first parallel node N+ (positive bus) to form a power supply loop.

[0032] The first switching device Q17 is the enable switch for the PSE chip 14 in the Ethernet circuit 10. When the first switching device Q17 is turned on, the PSE chip 14 is activated and enters the working state; when the first switching device Q17 is turned off, the PSE chip 14 does not work, ensuring that no interference is generated in PD mode.

[0033] Network port 16 is a standard Ethernet physical interface (such as RJ-45) in Ethernet circuit 10, used to connect external network cables. The four pairs of twisted-pair cables (PAIR-A, PAIR-B, PAIR-C, PAIR-D) inside network port 16 are respectively connected to the corresponding contacts of the first rectifier bridge 11, the second rectifier bridge 12, and the mode switching unit SW1, forming the physical ports for data and power input and output.

[0034] Please see Figure 4 and Figure 5When the external power supply device 201 is connected to the network port 16, the external power supply device 201 will output a DC voltage with polarity detection through any combination of cable pairs. Regardless of which pair of lines the voltage is input from or what the polarity is, due to the parallel full-bridge structure of the first rectifier bridge 11 and the second rectifier bridge 12, the current can always find a path to flow out from the positive terminal of the power supply device 201, enter a rectifier bridge arm through a certain pair of cable pairs, power the PD chip 13 after flowing through the parallel node, and then return to the negative terminal of the power supply device 201 through another rectifier bridge arm and another pair of cable pairs, forming a complete current loop. During this process, the PD chip 13 is activated and works stably, supplying the acquired electrical energy to the PoE load 30 (such as CPU, MCU, etc.) inside the PoE device 100 through the first parallel node N+ and the second parallel node N-.

[0035] Please see Figures 6 to 9 When external power is needed through network port 16, the main controller or PSE chip 14 first outputs a high-level ON_PSE_PD signal. This signal turns on the first switching device Q17, activating the PSE chip 14; on the other hand, it drives the coil of the mode switching unit SW1, switching the contacts. After switching, the positive terminal of the power supply module 20 (such as a DC-DC power supply) inside the PoE device 100 is connected to the second and third cable pairs (such as PAIR-B and PAIR-C) of network port 16 through the contacts of the first parallel node N+ and the mode switching unit SW1, serving as the positive power output. After the PSE chip 14 is activated, it begins to control specific transistors (first switching transistor Q4 and second switching transistor Q16) in the first rectifier bridge 11 and the second rectifier bridge 12 through drive pins (such as GATE1 and GATE2), making the specific transistors act as controlled current return switches. When a legitimate PD device 202 is detected to be connected, the PSE chip 14 controls these specific transistors to turn on. Current flows out from the positive terminal of the power supply module 20, through the internal positive bus, mode switching unit SW1, and Pair B / C to the PD device 202, and then from the PD device 202 through Pair A / D, the controlled-on bridge arm, and the internal negative bus back to the negative terminal of the power supply module 20, thus forming a complete PSE power supply loop.

[0036] The Ethernet circuit 10 of this application integrates a PD chip 13, a PSE chip 14, a mode switching unit SW1, and two sets of rectifier bridges. By switching the mode switching unit SW1, the same network port 16 can switch between PD mode and PSE mode. In PD mode, a PD loop can be formed, and the power supply device 201 plugged into the network port 16 can supply power to the PoE load 30 in the PoE device 100 through the PD loop. In PSE mode, a PSE loop can be formed, and the power supply module 20 in the PoE device 100 can supply power to the PD device 202 plugged into the network port 16 through the PSE loop. In this way, a physical network port 16 is upgraded from a port with only a single function of power supply or power reception to an intelligent port with both power reception and power supply functions. When using it, the user no longer needs to remember or distinguish the function of a specific network port 16. Any network port 16 can be plugged in to meet the required power supply or power reception functions.

[0037] Please see Figure 1 , Figure 4 , Figure 5 and Figure 8 In some embodiments, the first rectifier bridge 11 includes a first switching unit 111, a second switching unit 112, a third switching unit 113, and a fourth switching unit 114. The negative terminal of the first switching unit 111 is connected to the positive terminal of the second switching unit 112 to form a first node N1; the negative terminal of the second switching unit 112 is connected to the negative terminal of the third switching unit 113 to form a second node N2; the positive terminal of the third switching unit 113 is connected to the negative terminal of the fourth switching unit 114 to form a third node N3; and the positive terminal of the fourth switching unit 114 is connected to the positive terminal of the first switching unit 111 to form a fourth node N4. The first node N1 is electrically connected to the first cable pair PAIR-A, and the third node N3 is electrically connected to the second cable pair PAIR-B.

[0038] The first to fourth switching units each include a controllable semiconductor switch, and the semiconductor switch is a metal-oxide-semiconductor field-effect transistor (MOSFET). The first switching unit 111, the second switching unit 112, the third switching unit 113, and the fourth switching unit 114 form a full-bridge topology. The second node N2 is the first parallel node N+, and the fourth node N4 is the second parallel node N-.

[0039] In this embodiment, the first rectifier bridge 11 is composed of four switching units connected in a bridge structure. The first node N1 is electrically connected to the first cable pair PAIR-A, and the third node N3 is electrically connected to the second cable pair PAIR-B. This ensures that in PD mode, regardless of the voltage polarity input from the external power supply device 201 through the first cable pair PAIR-A and the second cable pair PAIR-B, the body diodes or units operating as ideal diodes in the four switching units can form a complete rectifier bridge, automatically correcting the polarity and outputting correctly polarized DC power to the PD chip 13 between the second node N2 and the fourth node N4. This achieves a highly efficient and low-loss PD power receiving function.

[0040] Please see Figure 1 , Figure 4 , Figure 5 and Figure 8 In some embodiments, the second rectifier bridge 12 includes a first switching assembly 121, a second switching assembly 122, a third switching assembly 123, and a fourth switching assembly 124. The negative terminal of the first switching assembly 121 is connected to the positive terminal of the second switching assembly 122 to form a fifth node N5; the negative terminal of the second switching assembly 122 is connected to the negative terminal of the third switching assembly 123 to form a sixth node N6; the positive terminal of the third switching assembly 123 is connected to the negative terminal of the fourth switching assembly 124 to form a seventh node N7; and the positive terminal of the fourth switching assembly 124 is connected to the positive terminal of the first switching assembly 121 to form an eighth node N8. The fifth node N5 is electrically connected to the third cable pair PAIR-C, the seventh node N7 is electrically connected to the fourth cable pair PAIR-D, the second node N2 and the sixth node N6 are connected together to the first parallel node N+, and the fourth node N4 and the eighth node N8 are connected together to the second parallel node N-.

[0041] The first to fourth switching components each include a controllable semiconductor switch, and the semiconductor switch is a metal-oxide-semiconductor field-effect transistor (MOSFET). The first switching component 121, the second switching component 122, the third switching component 123, and the fourth switching component 124 are connected in a full-bridge topology. The sixth node N6 is the first parallel node N+, and the eighth node N8 is the second parallel node N-.

[0042] It can be understood that the second node N2, the sixth node N6, the first parallel node N+, and the first terminal 131 (PoE+) of the PD chip 13 are all the same node, directly connected to the internal PoE load 30 or one end of the internal power supply module 20; the fourth node N4, the eighth node N8, the second parallel node N-, and the second terminal 132 (PoE-) of the PD chip 13 are all the same node, directly connected to the internal PoE load 30 or the other end of the internal power supply module 20. The second rectifier bridge 12 is connected to the network port 16 through the third cable pair PAIR-C and the fourth cable pair PAIR-D, and maintains connection with other components in the Ethernet circuit 1010 through the sixth node N6 and the eighth node N8.

[0043] In this embodiment, the second rectifier bridge 12 is also composed of four switching components connected in a bridge structure, with the fifth node N5 electrically connected to the third cable pair PAIR-C and the seventh node N7 electrically connected to the fourth cable pair PAIR-D. Specifically, the second node N2 of the second rectifier bridge 12 and the sixth node N6 of the first rectifier bridge 11 are connected together to the first parallel node N+, and the fourth node N4 of the second rectifier bridge 12 and the eighth node N8 of the first rectifier bridge 11 are connected together to the second parallel node N-, thus forming a parallel connection between the two sets of rectifier bridges. In this way, the rectification capability in PD mode is extended to all four cable pairs, enabling compatible and efficient handling of high-power input; simultaneously, in PSE mode, this parallel structure allows the PSE chip 14 to independently and synchronously control the first cable pair PAIR-A (through the first rectifier bridge 11) and the fourth cable pair PAIR-D (through the second rectifier bridge 12) as controlled current return paths.

[0044] Please see Figure 1 , Figure 2 , Figure 8 and Figure 9 In some embodiments, the positive terminal of the power supply module 20 is electrically connected to the first parallel node N+, and the negative terminal of the power supply module 20 is electrically connected to the second parallel node N-; the first terminal 131 of the PD chip 13 is connected to both the positive terminal of the power supply module 20 and the first parallel node N+, and the second terminal 132 of the PD chip 13 is connected to both the negative terminal of the power supply module 20 and the second parallel node N-.

[0045] The power supply module 20 is typically one or more DC-DC power conversion units. Its input can be connected to an AC adapter, battery, or other DC power source, and its output provides a stable and controlled DC voltage. The positive and negative output terminals of the power supply module 20 are directly connected to the first parallel node N+ and the second parallel node N-, respectively.

[0046] The first terminal 131 (POE+) of the PD chip 13 is the positive power input pin, and the second terminal 132 (POE-) is the negative reference ground pin. The positive power input pin of the PD chip 13 is connected to the first parallel node N+ through a trace, and the negative reference ground pin is connected to the second parallel node N-, so that the output of the power supply module 20 and the power input of the PD chip 13 are connected in parallel to the same pair of bus nodes.

[0047] In this embodiment, the positive terminal of the power supply module 20 and the first terminal 131 of the PD chip 13 are both connected to the first parallel node N+, and the negative terminal of the power supply module 20 and the second terminal 132 of the PD chip 13 are both connected to the second parallel node N-. Thus, a DC power bus is constructed inside the PoE device 100. Whether the power comes from an external PoE input (processed by the rectifier bridge and PD chip 13 and output to this bus) or the internal power supply module 20, it all converges here. This design allows the power source of the PoE load 30 to be seamlessly switched or superimposed, enabling the PoE device 100 to be powered or received through any network port 16.

[0048] Please see Figure 8 and Figure 9 In some embodiments, the PSE chip 14 includes a first interface 141 (OUT1), a second interface 142 (GATE1), a third interface 143 (OUT2), a fourth interface 144 (GATE2), and a fifth interface 145 (ON_PSE_PD). ​​The first interface 141 and the second interface 142 are electrically connected to the first switching unit 111, respectively, and are used to output a first control signal and a first drive signal, respectively, to jointly control the on / off state of the first switching transistor Q4 in the first switching unit 111. The third interface 143 and the fourth interface 144 are respectively connected to the fourth switching unit 111. The switch component 124 is electrically connected and is used to output the second control signal and the second drive signal respectively, so as to jointly control the on and off of the second switch transistor Q16 in the fourth switch component 124. The PSE chip 14 is electrically connected to the second parallel node N- through the first switch device Q17. The fifth interface 145 is electrically connected to the gate of the first switch device Q17 and the mode switching unit SW1 respectively, and outputs the third control signal to control the on and off of the first switch device Q17 and control the switching pin conduction path of the mode switching unit SW1, so that the Ethernet circuit 10 switches between PD mode and PSE mode.

[0049] As the core component of power management, the PSE chip 14's interface enables mode control and power switch driving. Specifically, the first interface 141 (OUT1) and the second interface 142 (GATE1) form a pair of cooperative control channels to drive the first switch Q4 in the first rectifier bridge 11, which serves as a critical return path switch. The second interface 142 (GATE1) outputs a gate drive voltage, directly controlling the on and off states of the first switch Q4; the first interface 141 (OUT1) can be configured as a detection signal input or auxiliary control output, such as monitoring the drain voltage of the first switch Q4 to achieve state feedback of the switching node or provide additional enable logic. Similarly, the third interface 143 (OUT2) and the fourth interface 144 (GATE2) form another pair of cooperative control channels to drive the second switch Q16 in the second rectifier bridge 12, which serves as a critical return path switch. The fourth interface 144 (GATE2) outputs the gate drive voltage, which directly controls the on and off states of the second switch Q16; the third interface 143 (OUT2) can be configured as a detection signal input or auxiliary control output, such as monitoring the drain voltage of the second switch Q16 to realize the status feedback of the switching node or provide additional enable logic.

[0050] The fifth interface 145 (ON_PSE_PD) outputs a high / low level logic signal (the third control signal) as a mode switching command. This third control signal is simultaneously sent to two branches: one directly drives the gate of the first switching device Q17 (NMOS transistor), controlling its on / off state; the other is connected to the coil drive circuit of the mode switching unit SW1, which consists of the second switching device Q18 and external resistors. When the ON_PSE_PD signal goes high, it synchronously executes the following: turning on the first switching device Q17, thereby pulling the potential of the current detection pin (SENSE) of the PSE chip 14 low to near ground, thus enabling the PSE chip 14 itself; simultaneously, energizing the coil of the mode switching unit SW1 through the coil drive circuit, thereby switching the conduction state of its contacts.

[0051] In one specific implementation, after the ON_PSE_PD signal switches from a low level to a high level, the PSE chip 14 initializes and confirms that the first switching device Q17 is stably turned on, and then sends a drive signal through the second interface 142 (GATE1) and the fourth interface 144 (GATE2). During this period, the contacts of the mode switching unit SW1 switch.

[0052] In this embodiment, the PSE chip 14 coordinates with its first interface 141 (OUT1) and second interface 142 (GATE1) to control the first switching unit 111 (such as the first switching transistor Q4) of the first rectifier bridge 11, and coordinates with its third interface 143 (OUT2) and fourth interface 144 (GATE2) to control the fourth switching assembly 124 (such as the second switching transistor Q16) of the second rectifier bridge 12. Simultaneously, the PSE chip 14 outputs a third control signal through its fifth interface 145 (ON_PSE_PD). ​​This third control signal is used, on the one hand, to control the on / off state of the first switching device Q17 to enable the PSE chip 14 itself, and on the other hand, to control the switching of the mode switching unit SW1. In this way, by using a centralized control signal, the three actions of enabling the PSE chip 14, switching the main power supply positive path (through the mode switching unit SW1), and preparing the controlled return path (by driving the first switch Q4 and the second switch Q16) can be triggered and coordinated simultaneously. This achieves the integration and synchronization of the mode switching operation, with simple logic, high reliability, and ensures the accuracy of the conversion from PD mode to PSE mode.

[0053] Please see Figure 1 and Figure 8 In some embodiments, the mode switching unit SW1 includes a first pin 1, a second pin 2, a third pin 3, a fourth pin 4, a fifth pin 5, a sixth pin 6, a seventh pin 7, and an eighth pin 8. The first pin 1 is electrically connected to the VCC power supply, the second pin 2 is electrically connected to the third switching unit 113, the third pin 3 is electrically connected to the first parallel node N+, the fourth pin 4 is electrically connected to the third node N3, the fifth pin 5 is electrically connected to the sixth node N6, the sixth pin 6 is electrically connected to the first parallel node N+, the seventh pin 7 is electrically connected to the second switching assembly 122, and the eighth pin 8 is electrically connected to the fifth interface 145 through the second switching device Q18, grounded through the second switching device Q18, and electrically connected to the VCC power supply through the diode D9. In PD mode, the third control signal output by the fifth interface 145 is at the first level, the second switch Q18 is off, the third pin 3 and the second pin 2 are electrically connected, and the sixth pin 6 and the seventh pin 7 are electrically connected; in PSE mode, the third control signal output by the fifth interface 145 is at the second level, the second switch Q18 is on, the third pin 3 and the fourth pin 4 are electrically connected, and the sixth pin 6 and the eighth pin 8 are electrically connected.

[0054] Pin 1 of the mode switching unit SW1 is connected to a stable DC voltage source VCC, which must match the rated operating voltage of the SW1 coil. Pin 8 is connected to the drive control circuit through the second switching device Q18, and simultaneously connected to the VCC power supply through a parallel freewheeling diode D9. At the instant the second switching device Q18 is turned off, the freewheeling diode D9 provides a discharge path for the reverse induced electromotive force generated by the SW1 coil, preventing high-voltage spikes from damaging the second switching device Q18.

[0055] The connection of pins 2, 3, 4, 5, 6, and 7 constitutes the core of the signal path switching. Specifically, pin 2 is connected to the corresponding endpoint of the third switching unit 113 in the first rectifier bridge 11 (e.g., the drain of the MOSFET), and pin 7 is connected to the corresponding endpoint of the second switching assembly 122 in the second rectifier bridge 12 (e.g., the drain of the MOSFET). Pins 3 and 6 are internally connected in parallel and then connected to the first parallel node N+, i.e., the internal power supply positive bus. Pin 4 is connected to the third node N3 of the first rectifier bridge 11, which is directly connected to the second cable pair PAIR-B; pin 5 is connected to the sixth node N6 of the second rectifier bridge 12, which is directly connected to the third cable pair PAIR-C. This connection design makes the mode switching unit SW1 a controlled dual-channel bidirectional switch. When the coil is not energized (PD mode), internally, pins 2 and 3 are connected, and pins 6 and 7 are connected. At this time, PAIR-B and PAIR-C are introduced into the input sides of the first rectifier bridge 11 and the second rectifier bridge 12 respectively through pins 4 and 5, then through pins 2 and 7, to participate in the rectification process. When the coil is energized (PSE mode), the electromagnetic force drives the armature to switch the moving contact, that is, pins 3 and 4 are connected, and pins 6 and 5 are connected. In this way, the first parallel node N+ (the positive terminal of the power supply in the power supply module) is shorted with pins 4 and 5, thereby hard-wired the positive terminal of the power supply to PAIR-B and PAIR-C, establishing a low-impedance power supply output trunk, while disconnecting the connection between PAIR-B / C and the input side of the rectifier bridge.

[0056] In this embodiment, the first pin 1 of the mode switching unit SW1 is connected to the VCC power supply, the second pin 2 is connected to the third switching unit 113 of the first rectifier bridge 11, the third pin 3 is connected to the first parallel node N+ (power supply positive terminal), the fourth pin 4 is connected to the third node N3 of the first rectifier bridge 11 (connected to the second cable pair PAIR-B), the fifth pin 5 is connected to the sixth node N6 of the second rectifier bridge 12 (connected to the third cable pair PAIR-C), the sixth pin 6 is also connected to the first parallel node N+, the seventh pin 7 is connected to the second switching component 122 of the second rectifier bridge 12, and the eighth pin 8 is connected to the third control signal line of the PSE chip 14 through the second switching device Q18. This pin connection of the mode switching unit SW1 enables reliable physical path switching, ensuring that when the coil of the mode switching unit SW1 is controlled, its contacts can accurately connect or disconnect the internal power supply positive terminal or rectifier bridge with the specified network cable pair, thus ensuring smooth switching between PD mode and PSE mode.

[0057] Please see Figure 8 In some embodiments, the second switching device Q18 is an NPN transistor, and the base of the second switching device Q18 is connected to the fifth interface 145 (e.g., through a current-limiting resistor R22) via a current-limiting resistor R22. Figure 9 The second switching device Q18 is electrically connected to the ON_PSE_PD terminal, and the collector of the second switching device Q18 is electrically connected to the eighth pin 8 of the mode switching unit SW1. The emitter of the second switching device Q18 is grounded. A bias resistor R21 is connected in parallel between the base and emitter of the second switching device Q18 to stabilize the conduction state of the second switching device Q18.

[0058] The second switching device Q18 is an NPN bipolar junction transistor, forming a common-emitter switching circuit. The base of the second switching device Q18 is connected to the fifth interface 145 (ON_PSE_PD) of the PSE chip 14 through a current-limiting resistor R22. This current-limiting resistor R22 is used to set the base drive current and prevent overcurrent damage to the second switching device Q18 or the output stage of the PSE chip 14. The collector is directly connected to one end of the coil of the mode switching unit SW1 (pin 8), and the other end of the coil of the mode switching unit SW1 (pin 1) is connected to the drive voltage VCC. The emitter is directly grounded, forming a current loop.

[0059] A bias resistor R21 is connected in parallel between the base and emitter of the second switching device Q18. The bias resistor R21 provides a definite state bias for the second switching device Q18. When the ON_PSE_PD signal is low, the bias resistor R21 quickly pulls the base potential down to ground, ensuring that the second switching device Q18 is off, preventing malfunction of the mode switching unit SW1 due to false triggering, and enhancing the circuit's anti-interference capability.

[0060] When the ON_PSE_PD signal transitions to a high level, the base current flows into the base of the second switching device Q18 through the current-limiting resistor R22. By appropriately selecting the resistance ratio of the current-limiting resistor R22 to the bias resistor R21, it can be ensured that the base current is greater than the critical value required for the second switching device Q18 to enter the conduction state. At this time, a low impedance is presented between the collector and emitter of the second switching device Q18, providing a low-impedance path for the coil of the mode switching unit SW1 from VCC, through the coil, and then through the second switching device Q18 to ground. The current flowing in the coil generates a sufficient magnetic field to drive the contact switching.

[0061] In this embodiment, the second switching device Q18 is an NPN transistor. The base of Q18 is connected to the fifth interface 145 (ON_PSE_PD) of the PSE chip 14 via a current-limiting resistor R22, the collector is connected to the eighth pin 8 of the mode switching unit SW1, and the emitter is grounded. A bias resistor R21 is connected in parallel between the base and emitter. Thus, this circuit constitutes a stable and reliable coil drive module for the mode switching unit SW1. When the ON_PSE_PD signal is high, the second switching device Q18 is saturated and turned on, providing a defined grounding loop for the coil of the mode switching unit SW1, ensuring its reliable engagement. The bias resistor R21 ensures that when the control signal is low, the second switching device Q18 is reliably turned off, preventing malfunctions and guaranteeing the stability and anti-interference capability of the mode switching unit SW1's state switching operation.

[0062] Please see Figure 8 and Figure 9 In some embodiments, the first switching device Q17 is an NMOS transistor. The gate of the first switching device Q17 is electrically connected to the fifth interface 145 (ON_PSE_PD), the drain of the first switching device Q17 is electrically connected to the second parallel node N-, and the source of the first switching device Q17 is electrically connected to the current detection interface of the PSE chip 14. The current detection interface is also grounded through the detection resistor R20. The current detection interface is used to detect the current of the PSE circuit in real time in PSE mode. When the detected current exceeds the preset current threshold, the PSE chip 14 adjusts the second interface 142 (GATE1) and the fourth interface 144 (GATE2) to output the first drive signal and the second drive signal to cut off the conduction path of the first rectifier bridge 11 and the second rectifier bridge 12.

[0063] The gate (G) of the first switching device Q17 is directly connected to the fifth interface 145 (ON_PSE_PD) of the PSE chip 14 to receive the third control signal. The drain (D) is connected to the second parallel node N-, which is the negative bus of the internal power supply. The source (S) is connected to the dedicated current sensing interface (SENSE) on the PSE chip 14.

[0064] On one hand, the first switching device Q17 can act as an enable switch for the PSE chip 14, and its on / off state determines whether the PSE chip 14 is powered on. On the other hand, the source of the first switching device Q17 is the necessary path for the PSE power supply circuit current; all output current must flow through the channel of Q17 before flowing back to the N-node. Therefore, a sensing resistor R20 is connected between the source of the first switching device Q17 and the ground reference point. This sensing resistor R20 ensures the accuracy of current detection.

[0065] The current sensing mechanism inside the PSE chip 14 is based on differential measurement of the voltage drop across the sensing resistor R20. When the PSE circuit is turned on, current flows through the first switching device Q17 and the sensing resistor R20, generating a voltage drop proportional to the current across the sensing resistor R20. The sampling unit inside the PSE chip 14 continuously samples this voltage. This sampled value is compared with one or more current thresholds (such as overcurrent point, short-circuit point) set internally by the PSE chip 14 or through the I2C interface. Once the sampled voltage value exceeds the preset threshold voltage (corresponding to the preset current threshold), the drive signals output by the second interface 142 (GATE1) and the fourth interface 144 (GATE2) are immediately withdrawn, making them low level. This forcibly turns off the first switching transistor Q4 in the first rectifier bridge 11 and the second switching transistor Q16 in the second rectifier bridge 12, thereby physically cutting off the return path of the PSE current.

[0066] In this embodiment, the first switching device Q17 is an NMOS transistor, and its source is connected to the dedicated current detection interface of the PSE chip 14, which is grounded through a detection resistor R20. Thus, the PSE chip 14 can continuously measure the voltage drop across the detection resistor R20 to monitor the current in the PSE output circuit in real time with high precision. Once the current exceeds a preset safety threshold, the PSE chip 14 can immediately turn off the controlled switches (such as the first switch Q4 and the second switch Q16) in the first rectifier bridge 11 and the second rectifier bridge 12 through its control interface (such as GATE1 and GATE2), thereby quickly cutting off the power supply circuit. This achieves a fast-response overcurrent protection function, preventing equipment damage or safety accidents that may be caused by short circuits or faults in the downstream PD device 202.

[0067] Please see Figure 9 In some embodiments, the PD chip 13 also includes an I2C communication terminal (including a clock terminal 134 connected to the serial clock line SCL). Figure 9 The data terminal 133 (connected to I2C_SCL) and the serial data line SDA are connected in the middle. Figure 9 Connecting I2C_SDA and interrupt terminal 135 (in Figure 9The PSE chip 14 also includes an I2C communication interface (including a clock interface 147 connected to the serial clock line SCL). Figure 9 The data interface 146 (connected to I2C_SCL) and the serial data line SDA) are connected in the middle. Figure 9 The connection between I2C_SDA and interrupt interface 148 is in Figure 9 The I2C communication terminal is connected to the I2C communication interface for bidirectional communication and is used to report information in PD mode; the interrupt terminal 135 is electrically connected to the interrupt interface 148 and is used to send an interrupt signal to the PSE chip 14 when overcurrent, overvoltage or undervoltage is detected in PSE mode, triggering the PSE chip 14 to control the first switching device Q17 to turn off and cut off the PSE circuit.

[0068] The I2C communication terminal of PD chip 13 and the corresponding I2C communication interface of PSE chip 14 physically share the same set of signal lines. These two signal lines are connected to the I2C bus, which is usually connected to the master controller (CPU / MCU) to form a master-slave communication network. In this communication network, PD chip 13 and PSE chip 14 are slave devices, and the master controller can access them respectively through addressing.

[0069] In PD mode, PD chip 13 can periodically report its status information to the main controller via the I2C bus, including but not limited to: input voltage value, negotiated power class, input current, chip temperature, and various fault flags. In PSE mode, the main controller can also read the status information of PSE chip 14 via the I2C bus to obtain its output port voltage, real-time output current, port enable status, and any protective fault flags.

[0070] The interrupt terminal 135 provides an event-driven instant alarm mechanism. The interrupt terminal 135 of the PD chip 13 is directly connected to the interrupt interface 148 of the PSE chip 14. In PSE mode, even if the PD chip 13 does not perform the main power receiving function, its analog front end can still be configured to continuously sample the voltage between the wire pairs of the network port 16. When a preset abnormal condition is detected, such as the peer device exhibiting non-standard PD device 202 characteristics or the input voltage exceeding the safety threshold, the PD chip 13 will immediately pull the interrupt terminal 135 to a low level. This low-level interrupt signal is captured by the PSE chip 14, which immediately forces the shutdown of its GATE1 and GATE2 drive outputs, disconnecting the first switch Q4 and the second switch Q16; at the same time, it can also pull the ON_PSE_PD signal low, thereby turning off the first switching device Q17 and driving the switching contact of the mode switching unit SW1 to quickly cut off the entire PSE power supply circuit.

[0071] In this embodiment, the PD chip 13 and PSE chip 14 achieve bidirectional data interaction via an I2C communication terminal and are connected via an interrupt terminal 135. Thus, during system operation, the main controller can access and manage the PD chip 13 and PSE chip 14 via the I2C bus, obtaining real-time port status information (including input voltage, output current, operating mode, fault flags, etc.). Furthermore, in PSE mode, the PD chip 13 can be configured to continuously monitor the electrical parameters of the network port 16. If an abnormality is detected (e.g., a non-standard PD device 202 is connected to the other end, or voltage characteristics that may indicate a power supply risk), the PD chip 13 can send an immediate alarm to the PSE chip 14 or the main controller via an interrupt signal, triggering a protection process, such as shutting down the PSE output.

[0072] Secondly, this application provides a PoE device 100, which includes an Ethernet circuit 10, a PoE load 30, and a power supply module 20 according to any of the above embodiments. The PoE load 30 is electrically connected to the Ethernet circuit 10, and the power supply device 201 is used to supply power to the PoE load 30 through the Ethernet circuit 10. The power supply module 20 is electrically connected to the Ethernet circuit 10 and is used to supply power to a PD device 202 through the Ethernet circuit 10.

[0073] The PoE device 100 of this application integrates a PD chip 13, a PSE chip 14, a mode switching unit SW1, and two sets of rectifier bridges in its Ethernet circuit 10. By switching the mode switching unit SW1, the same network port 16 can switch between PD mode and PSE mode. In PD mode, a PD loop can be formed, and the power supply device 201 plugged into the network port 16 can supply power to the PoE load 30 in the PoE device 100 through the PD loop. In PSE mode, a PSE loop can be formed, and the power supply module 20 in the PoE device 100 can supply power to the PD device 202 plugged into the network port 16 through the PSE loop. In this way, a physical network port 16 is upgraded from a port with only a single function of power supply or power reception to an intelligent port with both power reception and power supply functions. When using it, the user no longer needs to remember or distinguish the function of a specific network port 16, and can plug into any network port 16 to meet their required power supply or power reception functions.

[0074] Thirdly, this application provides a PoE system 1000, which includes the PoE device 100 and an external device 200 as described in the above embodiments. The external device 200 is electrically connected to any one of the network ports 16 of the PoE device 100. When the external device 200 is a power supply device 201, the power supply device 201 supplies power to the PoE load 30 in the PoE device 100 through the Ethernet circuit 10; when the external device 200 is a PD device 202, the PD device 202 obtains power from the power supply module 20 in the PoE device 100.

[0075] Please combine Figure 11 Since the mode switching unit SW1 is initialized to PD mode and the first switching device Q17 is initialized to the off state during the production of PoE device 100, a PD loop can be formed when an external power supply device 201 is plugged into the network port 16 of PoE device 100. This causes the PD chip 13 to start and determine whether the external power supply device 201 conforms to the Power over Ethernet protocol, thus deciding whether to power the PoE device 100 with the external power supply device 201. The external power supply device 201 can be plugged into the network port 16 or a dedicated DC power jack to power on the PoE device 100. When plugged into the network port 16, it enters the PD mode of the Ethernet circuit 10. If the external power supply device 201 conforms to the Power over Ethernet protocol, the PoE device 100 is powered on.

[0076] Since the external power supply device 201 supplies power to the PoE load 30 of the PoE device 100, the PD chip 13 monitors whether the external PD device 202 is plugged into the network port 16. If the external PD device 202 is detected to be plugged into the network port 16, a power judgment is performed, and the power information required by the PD device 202 is uploaded to the main controller through the communication bus. The main controller then makes a comprehensive judgment on whether to output power based on the connection of the PD device 202 to other network ports 16. If the PSE chip 14 receives the third control signal through the fifth interface 145, it controls the first switching device Q17 to switch to the on state, and the mode switching unit SW1 also switches to the PSE mode connection state, forming a PSE loop to supply power to the PD device 202. If, through comprehensive judgment, the power input from the DC power supply or the power supplied by the external power supply device 201 through the PD mode cannot meet the power requirements of the external PD device 202, then the PSE mode of that network port 16 is not enabled, thus realizing centralized control and management of multiple ports.

[0077] In the PoE system 1000 of this application, the Ethernet circuit 10 integrates a PD chip 13, a PSE chip 14, a mode switching unit SW1, and two sets of rectifier bridges. By switching the mode switching unit SW1, the same network port 16 can switch between PD mode and PSE mode. In PD mode, a PD loop can be formed, and the power supply device 201 plugged into the network port 16 can supply power to the PoE load 30 in the PoE device 100 through the PD loop. In PSE mode, a PSE loop can be formed, and the power supply module 20 in the PoE device 100 can supply power to the PD device 202 plugged into the network port 16 through the PSE loop. In this way, a physical network port 16 is upgraded from a port with only a single function of power supply or power reception to an intelligent port with both power reception and power supply functions. When using it, the user no longer needs to remember or distinguish the function of a specific network port 16. Any network port 16 can be plugged in to meet the required power supply or power reception functions.

[0078] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0079] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the aforementioned method implementations, and will not be repeated here.

[0080] In the several embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0081] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0082] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0083] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer or a server) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0084] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An Ethernet circuit, characterized in that, This invention relates to a PoE device, which includes a power supply module and a PoE load. The Ethernet circuit includes a first rectifier bridge, a second rectifier bridge, a PD chip, a PSE chip, a mode switching unit, a first switching device, and a network port. The first rectifier bridge is connected to the network port via a first cable pair and a second cable pair. The second rectifier bridge is connected to the network port via a third cable pair and a fourth cable pair. The first rectifier bridge, the second rectifier bridge, and the PD chip are connected in parallel to form a first parallel node and a second parallel node. The first terminal of the PD chip is electrically connected to the first parallel node. The mode switching unit is electrically connected to the first parallel node, the first rectifier bridge, and the second rectifier bridge. The first port of the first switching device is connected to the second terminal of the PD chip. The PSE chip is connected to the second port of the first switching device. The network port is used to selectively connect to an external power supply device or an external PD device, so that the Ethernet circuit can switch between PD mode and PSE mode. In the PD mode, the PD chip is activated so that the power supply device can supply power to the PoE load through the PD circuit. The PD circuit is formed by the positive terminal of the power supply device plugged into the PoE device, any one of the first cable pair to the fourth cable pair, the input rectifier bridge, the PD chip, the output rectifier bridge, any one of the remaining three of the first cable pair to the fourth cable pair, and the negative terminal of the power supply device. The input rectifier bridge is either the first rectifier bridge or the second rectifier bridge directly connected to the positive terminal of the power supply device, and the output rectifier bridge is either the first rectifier bridge or the second rectifier bridge directly connected to the negative terminal of the power supply device. In the PSE mode, the PSE chip operates to enable the power supply module to supply power to the PD device through the PSE loop. The PSE loop is formed by the positive terminal of the power supply module, the first parallel node, the mode switching unit, the second cable pair and the third cable pair, the PD device plugged into the network port, the first cable pair and the fourth cable pair, the first rectifier bridge and the second rectifier bridge, the second parallel node and the negative terminal of the power supply module.

2. The Ethernet circuit according to claim 1, characterized in that, The first rectifier bridge includes a first switching unit, a second switching unit, a third switching unit, and a fourth switching unit. The negative terminal of the first switching unit is connected to the positive terminal of the second switching unit to form a first node; The negative terminal of the second switching unit is connected to the negative terminal of the third switching unit to form a second node; The positive terminal of the third switching unit is connected to the negative terminal of the fourth switching unit to form a third node; The positive terminal of the fourth switching unit is connected to the positive terminal of the first switching unit to form a fourth node; wherein: The first node is electrically connected to the first cable, and the third node is electrically connected to the second cable.

3. The Ethernet circuit according to claim 2, characterized in that, The second rectifier bridge includes a first switching assembly, a second switching assembly, a third switching assembly, and a fourth switching assembly. The negative terminal of the first switching component is connected to the positive terminal of the second switching component to form a fifth node; The negative terminal of the second switching component is connected to the negative terminal of the third switching component to form a sixth node; The positive terminal of the third switching component is connected to the negative terminal of the fourth switching component to form a seventh node; The positive terminal of the fourth switching component is connected to the positive terminal of the first switching component to form an eighth node; wherein: The fifth node is electrically connected to the third cable pair, the seventh node is electrically connected to the fourth cable pair, the second node and the sixth node are both connected to the first parallel node, and the fourth node and the eighth node are both connected to the second parallel node.

4. The Ethernet circuit according to claim 1, characterized in that, The positive terminal of the power supply module is electrically connected to the first parallel node, and the negative terminal of the power supply module is electrically connected to the second parallel node; the first terminal of the PD chip is connected to both the positive terminal of the power supply module and the first parallel node, and the second terminal of the PD chip is connected to both the negative terminal of the power supply module and the second parallel node.

5. The Ethernet circuit according to claim 3, characterized in that, The PSE chip includes a first interface, a second interface, a third interface, a fourth interface, and a fifth interface. The first and second interfaces are electrically connected to the first switching unit and are respectively used to output a first control signal and a first drive signal to jointly control the on / off state of the first switching transistor in the first switching unit. The third and fourth interfaces are respectively electrically connected to the fourth switching assembly and are respectively used to output a second control signal and a second drive signal to jointly control the on / off state of the second switching transistor in the fourth switching assembly. The PSE chip is electrically connected to the second parallel node through the first switching device. The fifth interface is electrically connected to the gate of the first switching device and the mode switching unit, respectively, and outputs a third control signal to control the on / off state of the first switching device and control the switching pin conduction path of the mode switching unit, so that the Ethernet circuit switches between the PD mode and the PSE mode.

6. The Ethernet circuit according to claim 5, characterized in that, The mode switching unit includes a first pin, a second pin, a third pin, a fourth pin, a fifth pin, a sixth pin, a seventh pin, and an eighth pin. The first pin is electrically connected to the VCC power supply; the second pin is electrically connected to the third switching unit; the third pin is electrically connected to the first parallel node; the fourth pin is electrically connected to the third node; the fifth pin is electrically connected to the sixth node; the sixth pin is electrically connected to the first parallel node; the seventh pin is electrically connected to the second switching assembly; and the eighth pin is electrically connected to the fifth interface through the second switching device, grounded through the second switching device, and electrically connected to the VCC power supply through a diode. In the PD mode, the third control signal output by the fifth interface is at the first level, the second switching device is turned off, the third pin is electrically connected to the second pin, and the sixth pin is electrically connected to the seventh pin; In the PSE mode, the third control signal output by the fifth interface is at the second level, the second switching device is turned on, the third pin is electrically connected to the fourth pin, and the sixth pin is electrically connected to the eighth pin.

7. The Ethernet circuit according to claim 6, characterized in that, The second switching device is an NPN transistor. The base of the second switching device is electrically connected to the fifth interface through a current-limiting resistor. The collector of the second switching device is electrically connected to the eighth pin of the mode switching unit. The emitter of the second switching device is grounded. A bias resistor is connected in parallel between the base and emitter of the second switching device to stabilize the conduction state of the second switching device.

8. The Ethernet circuit according to claim 5, characterized in that, The first switching device is an NMOS transistor. The gate of the first switching device is electrically connected to the fifth interface, the drain of the first switching device is electrically connected to the second parallel node, and the source of the first switching device is electrically connected to the current detection interface of the PSE chip. The current detection interface is also grounded through a detection resistor. The current detection interface is used to detect the current of the PSE circuit in real time in the PSE mode. When the detected current exceeds a preset current threshold, the PSE chip adjusts the output of the first drive signal and the second drive signal of the second interface and the fourth interface to cut off the conduction path of the first rectifier bridge and the second rectifier bridge.

9. The Ethernet circuit according to claim 5, characterized in that, The PD chip also includes an I2C communication terminal and an interrupt terminal, and the PSE chip also includes an I2C communication interface and an interrupt interface. The I2C communication terminal communicates bidirectionally with the I2C communication interface and is used to report information in the PD mode. The interrupt terminal is electrically connected to the interrupt interface and is used to send an interrupt signal to the PSE chip when overcurrent, overvoltage or undervoltage is detected in the PSE mode, triggering the PSE chip to control the first switching device to turn off and cut off the PSE circuit.

10. A PoE device, characterized in that, include: The Ethernet circuit according to any one of claims 1-9; A PoE load is electrically connected to the Ethernet circuit, and the power supply device is used to supply power to the PoE load through the Ethernet circuit; and A power supply module is electrically connected to the Ethernet circuit, and the power supply module is used to supply power to the PD device through the Ethernet circuit.

11. A PoE system, characterized in that, include: The PoE device as claimed in claim 10; and An external device can be plugged into and electrically connected to any one of the network ports of the PoE device. When the external device is a power supply device, the power supply device supplies power to the PoE load in the PoE device through the Ethernet circuit; In the case where the external device is a PD device, the PD device obtains power from the power supply module in the PoE device.

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