Semiconductor devices and their manufacturing methods
By irradiating the grooves during the semiconductor device manufacturing process, the carrier concentration distribution can be controlled, thus solving the problem of void defects in the metal filling process of high aspect ratio structures and improving the electrical parameters and stability of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NEXCHIP SEMICON CO LTD
- Filing Date
- 2026-01-22
- Publication Date
- 2026-05-26
AI Technical Summary
In semiconductor devices, high aspect ratio structures are prone to void defects during metal filling, which affect electrical parameters.
By irradiating the groove, charge carriers are generated in the first metal layer, and the charge carrier concentration is controlled to gradually decrease in the direction away from the bottom of the groove. The formation rate of the second metal layer is positively correlated with the charge carrier concentration, so as to reduce the probability of the second metal layer being sealed prematurely at the top corner of the groove.
It effectively reduces or even avoids the occurrence of void defects in the second metal layer, thereby improving the yield and stability of semiconductor devices.
Smart Images
Figure CN121586284B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology
[0002] As the feature size of semiconductor devices decreases, the isolation area between semiconductor devices also shrinks, and the probability of void defects in high aspect ratio structures of semiconductor devices increases accordingly. For example, for high aspect ratio structures of metallic materials, such as metal gate (MG) structures, voids (pits) often appear after filling, meaning there are gaps in the metal filler. This situation can easily lead to poor electrical parameters of semiconductor devices.
[0003] In the typical formation process of a metal gate structure, after the dummy poly is hollowed out, the interlayer dielectric (ILD) and spacers, under the effect of stress expansion, cause the sidewalls at the groove formed after the dummy poly is hollowed out to tilt. Because of this, coupled with the relatively fast filling rate at the top corner of the groove, the subsequently filled metal is prone to prematurely sealing at the top corner of the groove, resulting in voids and defects within the metal filling layer, which in turn affects the electrical parameters of the semiconductor device. Summary of the Invention
[0004] Therefore, it is necessary to provide a semiconductor device and a method for manufacturing the same, so as to reduce or even avoid the probability of void defects in the second metal layer.
[0005] This application provides a method for manufacturing a semiconductor device, comprising:
[0006] A substrate is provided, on which a dielectric layer and a first metal layer are formed, a groove is formed in the dielectric layer, and the first metal layer at least covers the sidewalls and bottom of the groove;
[0007] The groove is irradiated to generate charge carriers in the portion of the first metal layer located within the groove, and the concentration of the charge carriers gradually decreases in the direction away from the bottom of the groove.
[0008] A second metal layer is formed on the first metal layer to fill the groove, and the formation rate of the second metal layer is positively correlated with the concentration of the charge carriers.
[0009] In one embodiment, the process of irradiating the groove includes:
[0010] A first processing beam is directed toward the bottom of the groove, and a second processing beam is directed toward the sidewall of the groove, without either the first or the second processing beam penetrating the top corner of the groove.
[0011] In this process, the wavelength of the light incident on different positions of the sidewall in the second processing beam gradually increases in the direction away from the bottom of the groove, and the wavelength of the first processing beam is less than the minimum wavelength of the second processing beam.
[0012] In one embodiment, the wavelength range of the first processing beam includes 10 nm to 380 nm, and the wavelength range of the second processing beam includes 400 nm to 570 nm.
[0013] In one embodiment, during the irradiation process of the groove, the illumination intensity of the processing beam irradiating the surface of the first metal layer is positively correlated with the carrier concentration formed within the first metal layer.
[0014] In one embodiment, after forming the second metal layer, the method of manufacturing the semiconductor device further includes:
[0015] The first metal layer and the second metal layer are planarized so that the surfaces of the first metal layer and the second metal layer are flush with the surface of the dielectric layer to form a metal gate structure including the first metal layer and the second metal layer.
[0016] In one embodiment, the material of the first metal layer includes at least one of titanium nitride, tantalum nitride, and titanium-aluminum alloy, and the material of the second metal layer includes aluminum.
[0017] In one embodiment, the material of the dielectric layer includes at least one of silicon oxide and silicon nitride.
[0018] In one embodiment, the process of forming the dielectric layer and the first metal layer on the substrate includes:
[0019] A substrate is provided, and the dielectric layer is formed on the substrate;
[0020] The dielectric layer is etched to form the groove within the dielectric layer;
[0021] The first metal layer is formed on the dielectric layer, and the first metal layer at least covers the sidewalls and bottom of the groove.
[0022] In one embodiment, the aspect ratio of the groove ranges from 6 to 20.
[0023] Accordingly, this application also provides a semiconductor device manufactured using the semiconductor device manufacturing method described above.
[0024] An unexpected effect of this application is that by irradiating the groove, charge carriers are generated in the portion of the first metal layer located within the groove, and the concentration of charge carriers gradually decreases in the direction away from the bottom of the groove. By forming a second metal layer that fills the groove, and making the formation rate of the second metal layer positively correlated with the concentration of the charge carriers, the formation rate of the second metal layer gradually decreases in the direction away from the bottom of the groove, thus avoiding the probability of the second metal layer being prematurely sealed at the top corner of the groove, thereby reducing or even avoiding the probability of void defects appearing in the second metal layer. Attached Figure Description
[0025] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0026] Figure 1 This is a schematic diagram of the structure corresponding to the step of forming a groove in a manufacturing method of a metal grid structure in a related technology.
[0027] Figure 2 This is a schematic diagram of the structure corresponding to the step of forming a first metal filling layer on the interlayer dielectric layer in a manufacturing method of a metal grid structure in a related technology.
[0028] Figure 3 This is a schematic diagram of the structure corresponding to the step of forming a second metal filling layer in a trench in a semiconductor device manufacturing method in a related technology.
[0029] Figure 4 This is a schematic diagram of the structure corresponding to the planarization step in the manufacturing method of a semiconductor device in a related technology.
[0030] Figure 5 A flowchart illustrating a method for manufacturing a semiconductor device according to one embodiment of this application.
[0031] Figure 6 This is a schematic diagram of the structure corresponding to the step of providing a substrate and forming a dielectric layer with grooves on the substrate in a method for manufacturing a semiconductor device according to one embodiment of this application.
[0032] Figure 7 This is a schematic diagram of the structure corresponding to the step of forming a first metal layer on a dielectric layer in a method for manufacturing a semiconductor device according to one embodiment of this application.
[0033] Figure 8 This is a schematic diagram of the structure corresponding to the step of irradiating the groove in the manufacturing method of a semiconductor device provided in one embodiment of this application.
[0034] Figure 9 for Figure 8 The diagram shows the carrier distribution of the semiconductor device after irradiation.
[0035] Figure 10 This is a schematic diagram of the structure corresponding to the step of forming a second metal layer in the manufacturing method of a semiconductor device provided in one embodiment of this application.
[0036] Figure 11 This is a schematic diagram of the structure corresponding to the planarization step in the manufacturing method of a semiconductor device provided in one embodiment of this application.
[0037] The reference numerals in the figures include: 100-substrate; 110-interlayer dielectric layer; 111-trench; 120-first metal filler layer; 130-second metal filler layer; 131-hole defect; 200-substrate; 210-dielectric layer; 211-groove; 220-first metal layer; 230-second metal layer. Detailed Implementation
[0038] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.
[0040] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
[0041] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0042] When used herein, the singular forms of “a,” “an,” and “ / the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.
[0043] Figures 1 to 4 This is a structural diagram corresponding to some steps of a manufacturing method for a metal grid structure in a related technology. The following is combined with... Figures 1 to 4 Explain the specific manufacturing process of the metal grid structure.
[0044] First, refer to Figure 1 A substrate 100 is provided, on which an interlayer dielectric layer 110 is formed, and a trench 111 is formed within the interlayer dielectric layer 110. It should be noted that the trench 111 penetrates the interlayer dielectric layer 110 and exposes a portion of the surface of the substrate 100, thus forming a dummy poly structure within the remaining interlayer dielectric layer 110. Optionally, the aspect ratio of the trench 111 ranges from 6 to 20.
[0045] It should be noted that after the trench is formed, the interlayer medium layer will expand outward under stress, causing the sides of the trench to tilt, resulting in a trapezoidal shape with a narrow top and a wide bottom. This trench shape increases the difficulty of subsequently filling the trench with metal material.
[0046] Next, refer to Figure 2 A first metal filler layer 120 is formed on the interlayer dielectric layer 110, and the first metal filler layer 120 covers the sidewalls and bottom of the trench 111. Optionally, the first metal filler layer 120 is a metal stack structure composed of multiple layers of different metal materials, and the material of the first metal filler layer 120 includes at least one of titanium nitride (TiN), tantalum nitride (TaN), and titanium aluminum alloy (TiAl).
[0047] Then refer to Figure 3 and Figure 4 A second metal filler layer 130 is formed on the first metal filler layer 120, at least filling the trenches 111. The first metal filler layer 120 and the second metal filler layer 130 are planarized to make them flush with the interlayer dielectric layer 110, thereby forming a metal gate structure including the first metal filler layer 120 and the second metal filler layer 130. Optionally, the material of the second metal filler layer 130 includes aluminum (Al) or other commonly used metal materials and alloy materials. Optionally, a chemical mechanical polishing (CMP) process is used for planarization.
[0048] It should be noted that, due to the inclination of the trench sidewalls, the trench has a trapezoidal shape that is narrower at the top and wider at the bottom. Therefore, during the formation of the second metal filling layer, the filling speed at the top corner of the trench is relatively fast, while the filling speed at the bottom of the trench is relatively slow. This can easily cause the second metal filling layer to be sealed prematurely at the top corner of the trench, resulting in void defects in the second metal filling layer and affecting the electrical parameters of the semiconductor device.
[0049] To address the aforementioned problems, this application provides a semiconductor device and a method for manufacturing the same, thereby reducing or even avoiding the probability of void defects appearing in the second metal layer.
[0050] Figure 5 A flowchart illustrating a method for manufacturing a semiconductor device according to one embodiment of this application. See also... Figure 5 One embodiment of this application provides a method for manufacturing a semiconductor device, which includes the following steps S01 to S03.
[0051] Step S01: Provide a substrate on which a dielectric layer and a first metal layer are formed, wherein a groove is formed in the dielectric layer, and the first metal layer at least covers the sidewalls and bottom of the groove.
[0052] Step S02: Irradiate the groove to generate charge carriers in the portion of the first metal layer located within the groove, and the concentration of the charge carriers gradually decreases in the direction away from the bottom of the groove.
[0053] It should be noted that during the irradiation process, the thermoelectric effect generated by the interaction between free electrons in the first metal layer and the electromagnetic field of light waves is mainly utilized. When the photon energy is greater than the band gap energy (Eg=3.4eV), the free electrons jump to the conduction band and form charge carriers. The presence of charge carriers affects the formation rate of the second metal layer in subsequent processes.
[0054] Step S03: A second metal layer is formed on the first metal layer to fill the groove, and the formation rate of the second metal layer is positively correlated with the concentration of the charge carriers.
[0055] It should be noted that, since the formation rate of the second metal layer is positively correlated with the concentration of charge carriers, and the concentration of charge carriers in the first metal layer gradually decreases in the direction away from the bottom of the groove in step S02, the formation rate of the second metal layer at the bottom of the groove is relatively fast, the formation rate of the second metal layer at the sidewall of the groove is next, and the formation rate of the second metal layer at the top corner of the groove is relatively slow. This reduces or avoids the probability of the second metal layer being sealed prematurely at the top corner of the groove, thereby reducing or even avoiding the probability of forming void defects in the second metal layer.
[0056] The semiconductor device manufacturing method described above involves irradiating a groove to generate charge carriers in the portion of the first metal layer located within the groove, with the concentration of charge carriers gradually decreasing in the direction away from the bottom of the groove. By forming a second metal layer that fills the groove and making the formation rate of the second metal layer positively correlated with the concentration of the charge carriers, the formation rate of the second metal layer gradually decreases in the direction away from the bottom of the groove. This avoids the probability of the second metal layer prematurely sealing at the top corner of the groove, thereby reducing or even eliminating the probability of void defects appearing in the second metal layer.
[0057] Figures 6 to 11 This is a schematic diagram of the structure corresponding to some steps in the manufacturing method of a semiconductor device provided in one embodiment of this application. The following is in conjunction with... Figures 6 to 11 This application provides a detailed description of the manufacturing method for the semiconductor device.
[0058] First, refer to Figure 6 and Figure 7 A substrate 200 is provided, on which a dielectric layer 210 and a first metal layer 220 are formed. A groove 211 is formed within the dielectric layer 210, and the first metal layer 220 at least covers the sidewalls and bottom of the groove 211. In one embodiment, the aspect ratio of the groove 211 ranges from 6 to 20.
[0059] In one embodiment, the process of forming a dielectric layer and a first metal layer on a substrate includes: (Refer to...) Figure 6 A dielectric layer 210 is formed on the substrate 200; the dielectric layer 210 is etched to form a groove 211 within the dielectric layer 210; then, refer to... Figure 7 A first metal layer 220 is formed on the dielectric layer 210, and the first metal layer 220 at least covers the sidewalls and bottom of the groove 211. Optionally, the material of the dielectric layer 210 includes at least one of silicon oxide and silicon nitride.
[0060] It should be noted that after the groove is formed, the dielectric layer expands outward under stress, causing the sides of the groove to tilt. This results in a trapezoidal shape, narrower at the top and wider at the bottom, increasing the difficulty of filling the groove with metal material. Furthermore, with the groove's trapezoidal shape, the first metal layer formed on the inner wall of the groove will inherit this shape, increasing the risk of voids during the subsequent formation of the second metal layer.
[0061] In one embodiment, the material of the first metal layer includes at least one of titanium nitride (TiN), tantalum nitride (TaN), and titanium aluminum alloy (TiAl). In other embodiments of this application, the first metal layer can be prepared using other common metal materials or alloy materials. For example, the first metal layer can be a stacked structure composed of a tantalum nitride layer, a titanium nitride layer, and a titanium aluminum alloy layer. This application does not limit this.
[0062] Next, refer to Figure 8 and Figure 9 The groove 211 is irradiated to generate charge carriers in the portion of the first metal layer 220 located in the groove 211, and the concentration of charge carriers gradually decreases in the direction away from the bottom of the groove 211.
[0063] In one embodiment, the process of irradiating the groove includes: injecting a first processing beam into the bottom of the groove and injecting a second processing beam into the sidewall of the groove, wherein neither the first processing beam nor the second processing beam penetrates the top corner of the groove; wherein the wavelength of the light incident on different positions of the sidewall in the second processing beam gradually increases in the direction away from the bottom of the groove, and the wavelength of the first processing beam is less than the minimum wavelength of the second processing beam.
[0064] In one embodiment, the wavelength range of the first processing beam includes 10 nm to 380 nm, and the wavelength range of the second processing beam includes 400 nm to 570 nm. Optionally, the first processing beam is ultraviolet light, and the second processing beam includes violet light, blue light, and green light that sequentially irradiate the sidewall of the groove along a direction away from the bottom of the groove.
[0065] It should be noted that since the generation of charge carriers mainly utilizes the interaction between free electrons in the metal and the electromagnetic field of light waves, the shorter the wavelength of light, the easier it is for the first metal layer to absorb light, the stronger the corresponding thermoelectric effect, and the more charge carriers are formed. Therefore, the concentration distribution of charge carriers can be adjusted by adjusting the wavelength of the processing beam that irradiates different parts of the first metal layer.
[0066] Furthermore, during the irradiation process, the temperature of different parts of the first metal layer can be adjusted by controlling the intensity of the processing beam, thereby controlling the concentration distribution of charge carriers in the first metal layer. In one embodiment, during the irradiation of the groove, the intensity of the processing beam irradiating the surface of the first metal layer is positively correlated with the concentration of charge carriers formed within the first metal layer.
[0067] It is important to emphasize that since the carrier concentration distribution in the first metal layer is positively correlated with the formation rate of the subsequent second metal layer, in order to reduce the probability of void defects in the second metal layer, the carrier concentration distribution in the first metal layer needs to be adjusted as follows: the carrier concentration in the first metal layer at the bottom of the groove is relatively high, the carrier concentration in the first metal layer near the sidewall of the groove is next, and the carrier concentration in the first metal layer at the top corner of the groove is relatively low. This helps to reduce the probability of premature sealing during the subsequent formation of the second metal layer.
[0068] Next, refer to Figure 10 A second metal layer 230 is formed on the first metal layer 220, filling the grooves 211, and the formation rate of the second metal layer 230 is positively correlated with the carrier concentration. In one embodiment, the material of the second metal layer 230 includes aluminum (Al). In other embodiments of this application, the material of the second metal layer 230 may be adjusted to at least one of other metal materials or alloy materials as needed, and this application does not impose any restrictions on this.
[0069] It should be noted that, in the aforementioned steps, the carrier concentration distribution within the first metal layer is as follows: the carrier concentration in the first metal layer at the bottom of the groove is relatively high, the carrier concentration near the sidewall of the groove is next, and the carrier concentration at the top corner of the groove is relatively low. Therefore, during the formation of the second metal layer, the growth rate of the second metal layer at the bottom of the groove is relatively fast, the growth rate near the sidewall of the groove is next, and the growth rate at the top corner of the groove is relatively low. This avoids the probability of premature sealing of the second metal layer during its formation, thereby reducing or even eliminating the probability of void defects in the second metal layer, effectively improving the yield and stability of the semiconductor device.
[0070] See Figure 11 In one embodiment, after forming the second metal layer 230, the method of manufacturing the semiconductor device further includes: planarizing the first metal layer 220 and the second metal layer 230 so that the surfaces of the first metal layer 220 and the second metal layer 230 are flush with the surface of the dielectric layer 210 to form a metal gate (MG) structure including the first metal layer 220 and the second metal layer 230.
[0071] Accordingly, one embodiment of this application also provides a semiconductor device manufactured using the semiconductor device manufacturing method described above. (Comparison) Figure 4 and Figure 11It is known that in general metal gate structure fabrication methods, void defects 131 are easily generated in the second metal filling layer 130. However, this application forms charge carriers in the first metal layer 220 and controls the formation rate of the second metal layer 230, thereby reducing or even avoiding the probability of void defects forming in the second metal layer 230, and effectively improving the yield and stability of semiconductor devices.
[0072] An unexpected effect of this application is that by irradiating the groove, charge carriers are generated in the portion of the first metal layer located within the groove, and the concentration of charge carriers gradually decreases in the direction away from the bottom of the groove. By forming a second metal layer that fills the groove, and making the formation rate of the second metal layer positively correlated with the concentration of the charge carriers, the formation rate of the second metal layer gradually decreases in the direction away from the bottom of the groove, thus avoiding the probability of the second metal layer being prematurely sealed at the top corner of the groove, thereby reducing or even avoiding the probability of void defects appearing in the second metal layer.
[0073] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.
[0074] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0075] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method of manufacturing a semiconductor device, characterized by, include: A substrate is provided on which a dielectric layer and a first metal layer are formed, wherein a groove is formed in the dielectric layer, and the first metal layer at least covers the sidewalls and bottom of the groove; The groove is irradiated to generate charge carriers in the portion of the first metal layer located within the groove, and the concentration of the charge carriers gradually decreases in the direction away from the bottom of the groove. A second metal layer is formed on the first metal layer to fill the groove, and the formation rate of the second metal layer is positively correlated with the concentration of the charge carriers; The process of irradiating the groove includes: A first processing beam is directed toward the bottom of the groove, and a second processing beam is directed toward the sidewall of the groove, without either the first or the second processing beam penetrating the top corner of the groove. In this process, the wavelength of the light incident on different positions of the sidewall in the second processing beam gradually increases in the direction away from the bottom of the groove, and the wavelength of the first processing beam is less than the minimum wavelength of the second processing beam.
2. The method of manufacturing a semiconductor device according to claim 1, wherein The wavelength range of the first processing beam is 10nm to 380nm, and the wavelength range of the second processing beam is 400nm to 570nm.
3. The method of manufacturing a semiconductor device according to claim 1, wherein During the irradiation process of the groove, the light intensity of the processing beam irradiating the surface of the first metal layer is positively correlated with the carrier concentration formed in the first metal layer.
4. The method for manufacturing a semiconductor device according to claim 1, characterized in that, After forming the second metal layer, the method for manufacturing the semiconductor device further includes: The first metal layer and the second metal layer are planarized so that the surfaces of the first metal layer and the second metal layer are flush with the surface of the dielectric layer to form a metal gate structure including the first metal layer and the second metal layer.
5. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The material of the first metal layer includes at least one of titanium nitride, tantalum nitride, and titanium-aluminum alloy, and the material of the second metal layer includes aluminum.
6. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The material of the dielectric layer includes at least one of silicon oxide and silicon nitride.
7. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The process of forming the dielectric layer and the first metal layer on the substrate includes: A substrate is provided, and the dielectric layer is formed on the substrate; The dielectric layer is etched to form the groove within the dielectric layer; The first metal layer is formed on the dielectric layer, and the first metal layer at least covers the sidewalls and bottom of the groove.
8. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The aspect ratio of the groove ranges from 6 to 20.
9. A semiconductor device, characterized in that, It is manufactured using the manufacturing method of any one of claims 1 to 8.