Integrated circuit device and manufacturing method thereof

Abstract

The embodiment of the invention discloses an integrated circuit device and a manufacturing method thereof. The integrated circuit device includes a first cell including a first transistor; and a second cell adjoining the first cell at a first cell boundary and including at least a portion of the second circuit. The first cell includes one or more pin layers at a first cell boundary, the one or more pin layers including an uppermost pin layer, and the second circuit is connected to a gate of the first transistor through a first conductive path within the first cell, the first conductive path includes a first conductor forming a topmost conductive layer of the conductive layers of the first conductive path within the first cell, the topmost conductive layer being a higher layer than the topmost pin layer, and the second circuit includes a second conductor forming a lower layer than the topmost pin layer. The second conductor is electrically connected to the first conductive path at a first pin conductor of a first pin layer of the one or more pin layers.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to integrated circuit devices and methods of manufacturing the same. BACKGROUND

[0002] The continuing trend of miniaturization of integrated circuit devices has resulted in smaller and lower power devices that provide more functionality at higher speeds. The miniaturization process has also resulted in more stringent design and manufacturing specifications. SUMMARY

[0003] According to one aspect of embodiments of the present application, there is provided an integrated circuit device, comprising: a first unit comprising a first transistor in an active region on a substrate, the first transistor forming at least part of a first circuit; and a second unit adjoining the first unit at a first unit boundary, the second unit comprising at least part of a second circuit, wherein: the first unit comprises one or more pin layers at the first unit boundary, the one or more pin layers comprising a highest pin layer, the second circuit is electrically connected to a gate of the first transistor by a first conductive path within the first unit, the first conductive path comprises a first conductor in a topmost conductive layer of conductive layers of the first conductive path formed within the first unit, the topmost conductive layer being a higher layer than the highest pin layer, the second circuit comprises a second conductor, the second conductor being electrically connected to the first conductive path at a first pin conductor of a first pin layer of the one or more pin layers, and the first unit boundary corresponds to at least one of a break in the active region, an edge of one of the one or more pin layers, or a power rail in a conductive layer closest to the substrate.

[0004] According to another aspect of embodiments of the present application, there is provided a method of manufacturing an integrated circuit device, the method comprising: forming a first transistor in an active region on a substrate, the first transistor forming at least part of a first circuit in a first unit; forming at least part of a second circuit in a second unit adjoining the first unit at a first unit boundary; forming one or more pin conductors in the first unit at the first unit boundary, the one or more pin conductors comprising a highest pin conductor; forming a first conductive path within the first unit to electrically connect the second circuit to a gate of the first transistor, forming the first conductive path within the first unit comprising: forming a first conductor in a topmost conductive layer of conductive layers of the first conductive path formed within the first unit, the topmost conductive layer being a higher layer than the highest pin conductor; and forming a second conductor in the second unit, the second conductor being electrically connected to the first conductive path by a first pin conductor of the one or more pin conductors, wherein the first unit boundary corresponds to at least one of a break in the active region, an edge of one of the one or more pin layers, or a power rail in a conductive layer closest to the substrate.

[0005] According to yet another aspect of embodiments of the application, there is provided an integrated circuit device, comprising: a first transistor in a first active region on a substrate, the first transistor being in a first cell and having a gate coupled to a first conductive segment in a first conductive layer closest to the substrate; a second transistor in a second cell adjacent to the first cell at a cell boundary, the cell boundary corresponding to at least one of an isolation structure at an edge of the first active region or a power rail in the first conductive layer; one or more pin conductors in the first cell; a conductive path in the first cell, the conductive path coupling a first pin conductor of the one or more pin conductors to the gate of the first transistor; and wherein: the conductive path in the first cell comprises a second conductive segment in a highest conductive layer of conductive structures forming the conductive path in the first cell, and the second conductive segment is higher than a highest pin conductor of the one or more pin conductors in the first cell. BRIEF DESCRIPTION OF DRAWINGS

[0006] Various aspects of the disclosure can be best understood from the following detailed description when read with the accompanying drawings. It is emphasized that, according to common practice, the various drawings are not to scale. On the contrary, the dimensions of the various components are arbitrarily expanded or reduced for clarity. Like numerals may

[0007] Figure 1A is a block diagram of an integrated circuit (IC) according to some embodiments.

[0008] Figure 1B is a schematic diagram of an IC device according to some embodiments.

[0009] Figure 2 is a cross-sectional view of an IC device according to some embodiments.

[0010] Figure 3A is a schematic cross-sectional view of an intermediate fabrication structure of an IC device according to some embodiments.

[0011] Figure 3B is a schematic cross-sectional view of an intermediate fabrication structure of an IC device according to some embodiments.

[0012] Figure 4A is a schematic diagram of an IC device according to some embodiments.

[0013] Figure 4B is a partial layout diagram of an IC device according to some embodiments.

[0014] Figure 4C is a schematic diagram of an IC device according to some embodiments.

[0015] Figure 5A is a schematic diagram of an IC device according to some embodiments.

[0016] Figure 5B is a partial layout of an IC device according to some embodiments.

[0017] Figure 6A is a schematic of an IC device according to some embodiments.

[0018] Figure 6B is a partial layout of an IC device according to some embodiments.

[0019] Figure 7 is a flowchart of a placement and routing method according to some embodiments.

[0020] Figure 8 is a flowchart of a method of manufacturing an IC device according to some embodiments.

[0021] Figure 9 is a flowchart of a method of manufacturing an IC device according to some embodiments.

[0022] Figure 10 is a block diagram of an IC device design system according to some embodiments.

[0023] Figure 11 is a block diagram of an IC manufacturing system and its associated IC manufacturing flow according to some embodiments. DETAILED DESCRIPTION

[0024] The following disclosure provides many different embodiments, or examples, for implementing different features of the present disclosure. Specific examples of components, materials, values, steps, operations, arrangements, etc. are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to limit the present disclosure in any manner. Other components, materials, values, steps, operations, arrangements, etc. can be considered. For example, in the following description, forming a first component over or on a second component can include embodiments in which the first component and the second component are in direct contact, and can also include embodiments in which additional components can be formed between the first component and the second component, such that the first component and the second component can not be in direct contact. Furthermore, reference numerals and / or letters can be repeated in various examples in this disclosure. Such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0025] Furthermore, relative terms such as "below" or "above" or "upper" or "lower" or "under" or "over" or "top" or "bottom" could be used herein to describe an element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Such relative terms can be intended to encompass different orientations of the device in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the relative descriptive terms used herein can be interpreted accordingly.

[0026] One aspect of IC device design and fabrication includes preventing antenna effect damage to the device. Antenna effect is a term for the accumulation of electrical charge, for example during plasma operations in the IC device fabrication process, which can cause damage to device structures such as gate dielectric layers, such as gate oxide or high-k gate layers. Antenna effect damage occurs when electrical charge, often higher than the normal operating voltage of the IC device, is accumulated on one or more components of the IC structure during the fabrication process of the IC device, and the electrical charge causes damage to structures such as gate dielectric layers. This damage can cause yield and reliability problems in the fabrication of IC devices such as metal oxide semiconductor (MOS) IC devices, and is of particular concern in IC devices that include transistors isolated from the substrate, such as all around gate transistors, where the epitaxial structure is isolated by a bottom dielectric spacer, which can limit the ability to discharge electrical charge accumulated during the fabrication process. Accordingly, IC device design includes provisions to prevent antenna effect damage, such as through wiring design, process flow design, and / or circuit design. These provisions include antenna rules that are evaluated to determine whether antenna effect will cause damage to portions of the IC.

[0027] One approach to mitigate antenna effect damage is to reduce the area of charge-accumulating structures (e.g., metal wiring or other conductive wiring, vias, etc.) that are coupled to charge-sensitive structures such as gate dielectric. However, as device structure sizes are reduced, structures such as gate dielectric become very small, and thus the area of charge-accumulating structures attached thereto should also be reduced to avoid violating antenna rules (antenna rule violations can also be referred to as violating antenna design rule checks (DRCs)). This can limit wiring and / or wiring sizes, etc., and present challenges to placement and routing of cells in an IC. Another approach to mitigate antenna effect damage is to reduce or modify process operations that can cause charge accumulation, and / or reorder process operations that can accumulate charge so as to be performed when a charge-discharge structure is coupled to the network, such as a source / drain region of a transistor coupled to the network, a diode coupled to the network, etc. Another approach to mitigate antenna effects is to add a diode in the network to discharge accumulated charge (such a diode can be referred to as an antenna diode). Adding an antenna diode should take into account potential consequences such as timing challenges, wiring congestion, parasitic capacitance, and / or parasitic resistance of the diode. These approaches can be used individually, in various combinations, and / or in combination with other approaches.

[0028] In some embodiments, an integrated circuit design provides connecting a conductive structure in a second cell using a higher (and thus later formed) conductive layer in a first cell that would otherwise cause an antenna rule violation in the adjacent first cell. In some embodiments, the size and / or area of the conductive structure in the second cell is not limited by the antenna rule of the first cell. In some embodiments, an integrated circuit design provides connecting a conductive structure in a second cell without using an antenna diode that would otherwise cause an antenna rule violation in an adjacent first cell.

[0029] Figure 1A is a schematic diagram of an integrated circuit (IC) 100-1 in accordance with some embodiments.

[0030] In Figure 1AIn particular embodiments, IC 100-1 includes cell tiles 101A, 101B, 101C, and 101D (herein, one or more of cell tiles 101A, 101B, 101C, and 101D can be referred to simply as cell tile 101). Each cell tile 101 includes one or more networks 104 of source or drain regions 106 (which can be referred to as source / drain regions or S / D regions) and gates 108. In some embodiments, S / D regions 106 are regions of a semiconductor into which impurities are intentionally introduced, e.g., by diffusion, implantation, etc., to modulate properties of the semiconductor. In some embodiments, a source or drain is an element of a transistor, e.g., a MOS field effect transistor (MOSFET). A transistor generally includes a source terminal, a drain terminal, and a gate separated from a semiconductor channel region by a gate dielectric layer, e.g., a gate oxide layer. In operation, a voltage at gate 108 controls current between the source and drain.

[0031] Each network 104 includes some or all of a portion of one or more IC layout cells (not shown in FIG. 1) such as standard cells or IP cells. In some embodiments, network 104 spans two or more cells that are adjacent to each other in the layout, e.g., S / D regions 106 in one cell and gates 108 in another cell. Standard cells can correspond to logic functions such as NAND, NOR, latches, etc., used as building blocks for IC designs. In a cell placement and routing method, standard cells including multiple semiconductor devices are generated and stored in a standard cell library. An IC layout is then constructed by an automatic placement and routing (APR) tool that places selected standard cells next to each other in the IC layout. Figure 1A

[0032] In particular embodiments, to illustrate, network 104 includes conductive structure 109 that electrically connects S / D regions 106 with a single instance of gate 108 that corresponds to an access pin (also referred to as a pin or receiver) of the cell. In some embodiments, network 104 includes multiple pins corresponding to one or more cells. Figure 1A

[0033] Conductive structure 109 is one or more conductors arranged to provide electrical connections between elements of network 104, e.g., S / D regions 106 and gates 108. In some embodiments, conductive structure 109 includes conductors, e.g., conductive segments, conductive lines, etc., in conductive layers, e.g., metal layers, metal-containing layers, etc., and conductive interlayer via structures (which can be referred to simply as vias). In some embodiments, conductive regions of conductive structure 109 are arranged by an APR tool. In some embodiments, conductive structure 109 that electrically connects S / D regions 106 and gates 108 includes a via (e.g., a via 110) that extends through a dielectric layer 112 between S / D regions 106 and gates 108. Figure 1A ​​The via is an electrical connection between layers in IC 100-1 that pass through a plane of one or more adjacent layers. In some embodiments, the electrically conductive structures 109 include aluminum, copper, gold, silver, tungsten, etc.

[0034] In some embodiments, IC 100-1 is a set of electronic circuits on a substrate (e.g., a silicon wafer, etc. of a semiconductor material). Figure 1A One network 104 in IC 100-1 is shown, but it is understood that there are tens, hundreds, thousands, or even millions of networks within IC 100-1. In some embodiments, each cell tile 101 includes substantially more than a single instance of a network 104. In some embodiments, IC 100-1 has tens, hundreds, thousands, or even millions of cell tiles 101 on a single substrate. In some embodiments, each cell tile 101 integrates a large number of metal-oxide-semiconductor field-effect transistors (MOSFETs). In some embodiments, IC 100-1 is designed using an electronic design automation (EDA) system 1000 discussed below with respect to Figure 10 and / or fabricated using an IC fabrication system 1100 discussed below with respect to Figure 11 .

[0035] In some embodiments, cell tile 101 is an IC layout cell tile that is populated by an APR tool based on an algorithm (e.g., an algorithm that includes one or more iterative operations). In some embodiments, in the context of an EDA tool, a cell is a representation of a component within a schematic diagram or physical layout of an electronic circuit in software. A cell-based design approach enables a designer to analyze a chip design at different levels of abstraction.

[0036] In Figure 1A some embodiments, network 104 includes at least one driver (e.g., including S / D region 106) and at least one receiver (e.g., including gate 108). Gate 108 includes a thin gate dielectric layer. If a portion of network 104 connected to gate 108 obtains a voltage higher than a normal operating voltage of IC 100-1, the dielectric layer can break down or be damaged during IC device fabrication.

[0037] Violations of the antenna rule can be referred to as antenna violations. The antenna rule is often expressed as a permitted ratio of conductive structure area to gate area, such as gate dielectric area or gate oxide area. In some embodiments, the area counted in determining the conductive structure area is the total area of all conductive structures connected to the gate electrode and not connected to a charge discharge structure (e.g., source / drain regions). When an IC supports different transistor designs, gate dielectric thicknesses, gate oxides, etc. (e.g., thick gate dielectric layers for high voltage transistors and thin gate dielectric layers for high performance transistors), then each transistor design, gate dielectric thickness, etc. can have a different antenna rule. In addition, there are cumulative rules in which the sum of the ratios (or the sum of the parts) of all conductive structures determines the antenna effect limit or conductive area limit. In addition, there are rules that consider the perimeter of each structure.

[0038] One method of resolving an antenna violation is to add one or more diodes to the conductive structure contained in the area of the conductive structure that is evaluated by the antenna rule and violates the antenna rule, such as to the portion of the network 104. A diode is a two-terminal electronic component that primarily conducts current in one direction; it has a relatively low resistance in one direction and a higher resistance in the opposite direction. In some embodiments, the diode (which can be referred to as an antenna diode) has a first terminal coupled to the conductive structure 109 and a second terminal coupled to the device substrate, such as an n-type diffusion or implant in a p-type substrate, a p-type diffusion or implant in an n-type well, etc. For example, if the fabrication of the conductive structure 109 is expected to result in an antenna violation, then one or more antenna diodes (not shown in FIG. 1) can be connected to the conductive structure 109, such as at a location between the S / D regions 106 and the gate 108, to couple the conductive structure 109 to the substrate through the diode. The diode connected to the conductive structure 109 is used to protect the gate dielectric layer of the gate 108 from breakdown during fabrication of the IC device during operations in which the S / D regions 106 are not electrically connected to the gate 108. Adding one or more antenna diodes to the conductive structure 109 can prevent a violation of the antenna rule without changing the network 104. However, adding an antenna diode can introduce timing challenges, routing congestion, parasitic capacitance, and / or parasitic resistance of the antenna diode. Figure 1A

[0039] Figure 1B is a schematic plan view of an integrated circuit (IC) device 100-2 in accordance with some embodiments.

[0040] ​IC device 100-2 includes a core cell region 110 and an input / output (I / O) cell region 120 surrounding the edges of the core cell region 100. Core circuits in the core cell region 110 communicate with the I / O cell region 120 via interface signals 130. In some embodiments, such interface signals are routed through horizontal cell boundaries 120bh (parallel to the X-axis) at locations where cells in the core cell region 110 abut the I / O cell region 120 at horizontal edges (parallel to the X-axis) of the core cell region 110. In some embodiments, such interface signals are routed through vertical cell boundaries 120bv (parallel to the Y-axis) at locations where cells in the core cell region 110 abut the I / O cell region at vertical edges (parallel to the Y-axis) of the core cell region 110.

[0041] In some embodiments, the core cell region 110 and / or the I / O cell region include one or more standard cells. In some embodiments, the core cell region 110 and / or the I / O cell region 120 are located in one or more of the above-described cell blocks 101.

[0042] In IC device 100-2, the interface circuits between the core cell region 110 and the I / O cell region can have relatively long conductors, and thus are more likely to violate an antenna DRC than other cells of IC device 100-2.

[0043] As mentioned above, an antenna DRC is a check to avoid device damage, e.g., damage to a gate dielectric layer (or gate oxide) of a transistor, during fabrication of IC device 100-2. Operations performed during fabrication of IC device 100-2, e.g., operations involving plasma, can cause charge accumulation on device structures electrically connected to the gate, resulting in a voltage potential on the gate dielectric layer. Excessive charge accumulation can cause the gate dielectric layer to break down. This charge-induced breakdown can be referred to as plasma-induced damage (PID). Violations of the antenna DRC can occur when the area of a conductive material (e.g., a metal layer, a via, etc.) relative to the area of a gate dielectric layer exceeds a predetermined ratio. This ratio is specified as a design rule, which can vary depending on the particular layer of the IC, gate design, transistor design, process node, and similar factors. The antenna DRC is intended to identify and prevent the possibility of exceeding the metal-to-gate dielectric area ratio during fabrication. At the design stage, the problem of violating the antenna rule can be addressed or mitigated by coupling a diode to the charge-accumulating metal structure, the diode configured to discharge the accumulated charge at a voltage lower than the breakdown voltage of the gate dielectric layer connected to the metal structure. However, adding an antenna diode can impact the performance of the final IC, e.g., by imposing a greater capacitance on the corresponding circuit structure, which can slow down the operation of the circuit and / or increase the power consumption of the circuit.

[0044] The interface circuitry between the core cell region 110 and the I / O cell 120 may result in violations of antenna DRC (Discharge Ratio Control) because the signal wiring conductors coupled to the transistors may extend considerably beyond the cell edges. This extended signal wiring length beyond the cell edges increases the likelihood of charge accumulation. Furthermore, as process nodes advance and transistor structure sizes decrease, the corresponding gate dielectric area also decreases, which in turn reduces the area of ​​the conductors allowed for connections to meet design-required area ratios. Additionally, some process node-implemented transistor structures may be less capable of dissipating accumulated charge. For example, gate-all-around (GAA) transistors may include source / drain epitaxial structures isolated from the underlying substrate by bottom dielectric isolation, which in some cases may not provide an effective antenna discharge junction for the substrate or active region (OD region).

[0045] Figure 2 This is a schematic cross-sectional view of an IC device 200 according to some embodiments.

[0046] IC device 200 includes a substrate ( Figure 2 A first active circuit element 202 (e.g., a first transistor, a first pair of transistors, etc.) on a substrate and a second active circuit element 204 (e.g., a second transistor, a second pair of transistors, etc.) on a substrate. The first and second active circuit elements 202 and 204 are parts of the same network, such as network 104.

[0047] A first active circuit element 202 is located in a first unit 220A, and a second active circuit element 204 is located in a second unit 220B. The second unit 220B is adjacent to the first unit 220B at a unit boundary 206, which can also be referred to as an IP unit edge. In some embodiments, the second active circuit element 204 is part of the core circuit, and the first active circuit element 202 is part of the I / O circuit. In some embodiments, the second unit 220B is a core circuit unit, and the first unit 220A is an I / O unit. Figure 2 In the example, cell boundary 206 is located where the first cell 220A is adjacent to the second cell 220B relative to the X-axis direction, for example, relative to an adjacent position in the same horizontal row of the layout. In some embodiments, cell boundary 206 corresponds to a boundary extending parallel to the Y-axis direction, such as the aforementioned vertical cell boundary 120bv. However, the embodiments are not limited to this. Figure 2 The method shown applies to cells adjacent in the horizontal direction as well as cells adjacent in the vertical or Y-axis direction.

[0048] exist Figure 2In the following description, it will be assumed that the cell boundaries 206 extend parallel to the Y axis and correspond to functional or structural discontinuities in the active regions (extending parallel to the X axis) in the transistor layer that include the first and / or second active circuit elements 202, 204. One example of a functional discontinuity in an active region is a dummy gate structure configured to receive a voltage that inhibits conduction of a lower portion of the corresponding active region, e.g., inhibits an inversion layer in the lower portion of the corresponding active region. Examples of structural discontinuities in an active region include a physical edge of the active region or a gap, insulating structure, doped region, diffusion region, etc. in the active region that discontinues a first portion of the active region from a second portion of the active region. In some embodiments, the cell boundaries 206 correspond to a dummy gate structure (e.g., an isolated dummy gate formed of insulating material) that does not constitute a transistor functional component, a continuous oxide diffusion (CNOD) structure, a polysilicon on diffusion edge (PODE) structure, a continuous polysilicon on diffusion edge (CPODE) structure, a boundary isolation region, etc. In other embodiments, the cell boundaries 206 correspond to a feature or structure that extends parallel to the X axis. In some embodiments, the cell boundaries 206 correspond to a power rail in an M0 conductor layer (a first metal layer on a gate or polysilicon layer). In other embodiments, the cell boundaries correspond to another conductor in the M0 layer. In other embodiments, the cell boundaries correspond to a feature in one or more layers above the transistor layer or above the M0 layer. The boundaries of a cell or cell region can also be identified in other ways than described above.

[0049] In the following discussion, it will be assumed that the first active circuit element 202 includes at least one transistor having a gate dielectric layer that is to be evaluated according to the antenna DRC during IC device 200 design prior to fabrication of the IC device 200. By way of example only, Figure 2 The first active circuit element 202 and the second active circuit element 204 are shown in FIG. 1 to have a pair of transistors. However, it will be appreciated that the number of transistors can vary as appropriate, and in some embodiments one or both of the first active circuit element 202 and / or the second active circuit element 204 includes one transistor, or in other embodiments more than two transistors.

[0050] In Figure 2 In FIG. 1, the IC device 200 includes a conductive layer Mi having a first conductor 222. The first conductor 222 is connected to a gate of a first transistor in the first active circuit element 202. Both the first conductor 222 and the first transistor are in the first cell 220A. The first transistor in the first active circuit element 202 has a gate dielectric layer that is to be evaluated under the antenna rules, which can be referred to as a target gate dielectric layer.

[0051] In some embodiments, the conductive layer Mi is a first conductive layer M0 on a gate layer of the IC device 200. A via structure in a via layer (e.g., a via gate (VG) layer (not shown)) below the conductive layer Mi connects the gate of the first transistor to the conductive layer Mi.

[0052] In the completed IC device 200, the first conductor 222 and thus the first transistor having the target gate dielectric layer (whose gate is connected to the first conductor 222) is ultimately connected to the second active circuit element 204 in the second cell 220B. However, during the manufacturing process of the IC device 200, the first conductor 222 and the target gate dielectric layer are connected to a relatively small portion of the overall conductive structure that forms the connection between the first conductor 222 and the second active circuit element 204 in the second cell 220B.

[0053] In more detail, the first cell 220A includes a stack 224 of conductors and vias that couple the first conductor 222 to a second conductor 226. The second conductor 226 is coupled to a pin structure 228.

[0054] In Figure 2 In the completed IC device 200, the first conductor 222 and thus the first transistor having the target gate dielectric layer (whose gate is connected to the first conductor 222) is ultimately connected to the second active circuit element 204 in the second cell 220B. However, during the manufacturing process of the IC device 200, the first conductor 222 and the target gate dielectric layer are connected to a relatively small portion of the overall conductive structure that forms the connection between the first conductor 222 and the second active circuit element 204 in the second cell 220B.

[0055] The stack 224 includes conductors in the conductive layers Mi+1-Mn. Conductive vias in a via layer extend between adjacent conductors in the conductive layers Mi+1-Mn. In other embodiments, the stack 224 includes, for example, one or more deep vias that skip one or more of the conductive layers Mi+1-Mn. Although Figure 2 The conductive layers Mi, Mi+1, Mi+2, Mi+3,..., Mn, and Mn+1 are shown, in other embodiments, more or fewer conductive layers are provided.

[0056] The pin structure 228 includes pin conductors in pin layers 228i-k of the first cell 220A. The pin structure 228 also includes vias that connect the pin conductors. In some embodiments, the pin structure 228 includes one or more deep vias that skip one or more of the pin layers 228i-k. The pin layers 228i-k include pin layers 228i, 228i+1, 228i+2,..., 228k-1, and 228k, where the pin layer 228i is the lowest pin layer (closest to the substrate) and the pin layer 228k is the highest pin layer. Although Figure 2 Multiple pin layers are shown, in other embodiments, more or fewer pin layers can be provided.

[0057] In Figure 2In particular embodiments, the pin structure 228 includes a first pin conductor 228_1 in the pin layer 228i+1, a second pin conductor 228_2 in the pin layer 228k, and a pin conductor and via extending between the first pin conductor 223_1 and the second pin conductor 228_2.

[0058] The pin layers 228i~k correspond to the conductive layers Mi+2~Mn, i.e., the pin layer 288i corresponds to the conductive layer Mi+2. However, this is merely an example; the pin layer 288i can correspond to a conductive layer lower than Mi+2 (e.g., Mi+1) or higher than Mi+2 (e.g., Mi+3).

[0059] The pin conductors 228_1, 228_2 abut the cell boundary 206, and the second conductor 226 is coupled to the highest pin conductor 228_2 while being spaced apart from the cell boundary 206 by a distance D01. In addition to this, spacing the second conductor 226 apart from the cell boundary 206 allows the second conductor 224 to be made smaller. Making the second conductor 226 smaller reduces the area of the second conductor 224 that can accumulate electrical charge during the manufacture of the IC device 200.

[0060] In the second cell 220B, a third conductor 232 extends from the pin conductor 228_1. In some embodiments, the third conductor 232 and the pin conductor 228_1 are formed as a single piece of conductor, e.g., a single metal wire. The third conductor 232 extends in the second cell 220B by a length L01. Although in the example of FIG. 2B the third conductor 232 extends to the edge of the second cell 220B, in other embodiments the third conductor 232 can extend to a different location in the second cell 220B. Figure 2 Although in the example of FIG. 2B the third conductor 232 is located in the pin layer 228i+1 (corresponding to the conductive layer Mi+3), this is merely an example; the third conductor can be in any of the pin layers 228i~228k.

[0061] In some embodiments, the length L01 is large enough that the combined charge accumulation area of the third conductor 232, the pin structure 228, the second conductor 226, the stack 224, and the first conductor 222 exceeds the antenna DRC of the gate coupled to the first conductor 222. In some embodiments, the network including the second active circuit element 204, the third conductor 232, the pin structure 228, the second conductor 226, the stack 224, the first conductor 222, and the first active circuit element 202 has no antenna diode.

[0062] In the IC device 200, the second conductor 226 is in a higher layer (layer Mn+1) than the highest conductor in the pin structure 228, i.e., the second conductor 226 is in a higher conductive layer than the highest pin conductor 228_2 and the highest pin layer 228k corresponding to the conductive layer Mn. The conductive layers below the conductive layer Mn+1, i.e., the conductive layers Mn and below, are not used to couple the first conductor 222 to the pin layers 228i~k. In other words, the second conductor 226 is the highest conductor among the conductors coupling the target gate dielectric layer to the second active circuit element 204, and thus is the last formed conductor.

[0063] That is, the network including the second active circuit element 204, the third conductor 232, the pin structure 228, the second conductor 226, the stack 224, the first conductor 222, and the first active circuit element 202 uses the Mn+1 layer (or higher layer) as the last layer of the connection structure between the target gate dielectric layer (in the first active circuit element) and the pin conductors of the pin layers 228i~228k. By forming the second conductor 226 as the highest conductor among the conductors coupling the target gate dielectric layer to the second active circuit element 204, the design of the IC device 200 helps to avoid violating the antenna rule (i.e., DRC violation) by reducing the area of the conductive structure coupled to the target gate dielectric region during the fabrication of the IC device 200. Reducing the area of the conductive structure coupled to the target gate dielectric region during the fabrication process of the IC device 200 provides advantages such as increasing design flexibility (e.g., by increasing the number of available options for routing) and reducing antenna diodes, etc.

[0064] Figure 3A is a schematic cross-sectional view of an intermediate fabrication structure 200’ of the IC device 200 according to some embodiments.

[0065] In Figure 3A , the stack 224 of conductors and vias and Figure 2 the conductive structures of the pin layers 228i~k of the pin structure 228 have been partially formed. In detail, some conductors and vias in the stack 224 have been formed up to the conductive layer Mi+3. Further, some conductors and vias in the pin structure 228 have been formed up to the pin layer 228i+1, corresponding to the conductive layer Mi+3. In Figure 3A , the conductive layers and vias above the conductive layer Mi+3 have not been formed yet. Thus, Figure 2 the stack 224 of the IC device 200 is shown in Figure 3A as an intermediate stack 224’, Figure 2 the pin layers 228i~k of the pin structure 228 in Figure 3A are shown as an intermediate pin structure 228’. Figure 2 the third conductor 232 in Figure 3A is shown as an intermediate third conductor 232’ in the process of being formed.

[0066] In the IC device 200 in Figure 2 , the pin layers 228i-k are connected to the second active circuit element 204 through the third conductors 232 of length L01 in the conductive layers Mi+3 in the second cell 200B. In Figure 3A , the intermediate manufacturing structure 200', an intermediate third conductor 232' is being formed, but the intermediate third conductor 232' has not yet been connected to the first active circuit element 202. Thus, charges (e.g., shown as a series of plus signs ('+') on the intermediate third conductor 232' in Figure 3A ) that accumulate on the intermediate third conductor 232' during the manufacturing process due to plasma processing, etc., cannot affect the first active circuit element 202. In other words, Figure 3A , the antenna DRC for the gate dielectric in the first active circuit element 202 in the intermediate manufacturing structure 200' does not take into account the charges ('+') on the intermediate third conductor 232'. Thus, the length L01 of the third conductor 232 in the final IC device 200 is not limited by the concerns in Figure 3A that the intermediate third conductor 232' violates the antenna DRC for the first active circuit element 202. Thus, the third conductor 232 can be made long in the second cell 220B without violating the antenna DRC for the gate in the first active circuit element 202. This enables greater routing flexibility by expanding the available range of design lengths for the third conductor 232, and doing so does not require the addition of an antenna diode on the third conductor 232 to protect the first active circuit element 202.

[0067] Figure 3B is a schematic cross-sectional view of an intermediate manufacturing structure 200' of an IC device 200 according to some embodiments.

[0068] In Figure 3B , the manufacturing of the third conductor 232 has been completed. In some embodiments, a charge neutralization operation is performed after each conductor or conductive layer is completed to prevent the accumulation of continuous charges. In Figure 3B , the intermediate manufacturing structure 200' of Figure 3A , the accumulated charges ('+') on the intermediate third conductor 232' in the intermediate manufacturing structure 200' have been discharged. Discharging the accumulated charges on the third conductor 232 can prevent the accumulated charges from affecting the antenna rules for the target gate dielectric in the first active circuit element 202.

[0069] In Figure 3B , the stack 224 of conductors and vias and the conductive structure of the pin layers 228i-k of Figure 2 have been completed, and the second conductors 226 in the conductive layer Mn+1 are in the manufacturing process; this is shown in Figure 3B as the intermediate second conductors 226'.

[0070] In Figure 3B , the plasma manufacturing process, among others, causes charge ('+') to accumulate on the intermediate second conductor 226'. However, the design length of the second conductor 226 is controllable in IP, and can be made shorter (reducing the charge accumulation area) by the spacing distance D01 from the cell boundary 206. The shorter length of the second conductor 226 reduces the charge accumulation area and the amount of accumulated charge ('+') on the intermediate second conductor 226'. Furthermore, in Figure 3B , the intermediate second conductor 226' is coupled to the S / D regions of a transistor in the second active circuit element 204, which in some embodiments is operable to discharge the accumulated charge.

[0071] As described above, the IC device 200 is designed, constructed, and manufactured such that the intermediate manufacturing structures 200', 200" do not expose the first active circuit element 202 to the charge accumulation conductive area of the third conductor 232, and therefore, the antenna rule for the gates in the first active circuit element 202 does not constrain the length L01 of the third conductor 230 in the second cell 220B. This allows aspects of the features of the second cell 220B to be selected independently of the features of the first cell 220A, thereby allowing greater flexibility in the design or selection of the first and second cells 200A, 200B, for example, in the length L01 of the third conductor 232 in the second cell 220B. In some embodiments, the length L01 of the third conductor 232 in the conductive layer Mi+3 in the second cell 220B is greater than the length of any conductor in the conductive layer Mi+3 in the first cell 220A. In some embodiments, the length L01 of the third conductor 232 is greater than the length of any conductor in any conductive layer in the first cell 220A.

[0072] As the second conductor 226 is manufactured to couple the target gate dielectric layer of the first active circuit element 202 to the highest and last conductor in the conductors of the second active circuit element 204 (in the conductive layer Mn+1 or higher), the above-described design flexibility can extend to any conductive layer in the pin layers 228i~k, i.e., the conductive layers below the conductive layer Mn-1. Thus, the design of the IC device 200 helps to avoid violating the antenna rule, for example, in the intermediate manufacturing structures 200', 200" (or in another manufacturing stage), while providing greater design flexibility and / or reducing the number of antenna diodes included in the IC device 200.

[0073] Figure 4A is a schematic diagram of an IC device 400-1 according to some embodiments. Figure 4B is a partial layout diagram of an IC device 400-2 according to some embodiments.

[0074] Unless otherwise noted or apparent, elements of IC device 400-1, 400-2 having similar structure and function to elements of IC device 200 have the same reference number increased by 200.

[0075] Referring to Figure 4A IC device 400-1, in accordance with some embodiments, includes a first cell 420A and a second cell 420B abutting at a cell boundary 406 extending parallel to the Y axis. The first cell 420A includes a transistor 402 having a gate 402_1, e.g., a polysilicon gate, a high-k metal gate, etc., located over an active region 402_2, and a source 402_3 and a drain 402_4 in the active region 402_2. An active region break 402_5 breaks the active region 402_2 at the cell boundary 406. In some embodiments, the active region break 402_5 corresponds to a dummy gate structure, a doped region, an insulating material, etc. In some embodiments, the cell boundary 406 corresponds to a place and route boundary that defines an area in which to complete placement and constrain routing. The transistor 402 is shown as a planar structure, but in other embodiments the transistor 402 has other configurations, e.g., FinFet, gate-all-around (GAA), complementary FET (CFET), etc.

[0076] The gate 402_1 is coupled to a pin conductor 428 at the cell boundary 406. The pin conductor 428 is located in a conductive layer Mn. Although Figure 4A Not shown in FIG. 4A, but in some embodiments, in the second cell 420B, a conductor, e.g., having a length L01 and corresponding to the third conductor 232 of IC device 200, extends from the pin conductor 428 in the first cell 420A within the conductive layer Mn in the second cell 420B.

[0077] In comparison to IC device 200, the output pin of the transistor 402 is provided in the conductive layer Mn in IC device 400-1. That is, IC device 400-1 uses a higher output pin layer than IC device 200, which results in a simpler design for IC device 400-1 in comparison to IC device 200, which has multiple layers in the pin structure 228.

[0078] Pin conductor 428 is coupled to transistor 402 through a plurality of conductors and vias, the last formed of which is conductor 426 in conductive layer Mn+1, which is higher than the layer of pin conductor 428. Thus, conductor 426 is formed after pin conductor 428 and the conductors in conductive layer Mn in second cell 420B. By forming conductor 426 in a layer (layer Mn+1) that is higher than the pin layer (layer Mn), the conductors in the output pin layer in second cell 420B (i.e., layer Mn in second cell 4201B) can have a length (e.g., length L01) that is not limited by the antenna rule of transistor 402. Moreover, conductor 426 can be made shorter, e.g., by reducing the area of charge accumulation in first cell 420A through distance D01 between cell boundary 406 and conductor 426.

[0079] In Figure 4A , IC device 400-1 is shown as having conductors in conductive layers Mi through Mn+1, with vias in layers therebetween (e.g., in via layer VIAn between conductive layers Mn and Mn+1). However, a greater number of conductive layers are used in some embodiments, while a lesser number of conductive layers are used in other embodiments. Moreover, in some embodiments, the pin of transistor 402 is in a layer higher than conductive layer Mn (though below the last formed conductor 426, which can be in a layer higher than Mn+1), while in other embodiments it is in a layer lower than conductive layer Mn. Moreover, in Figure 4A , IC device 400-1 is shown as having four vias 445 extending vertically (parallel to the Z axis) between pin conductor 428 and overlying conductor 426. In some embodiments, fewer than four vias 445 are used, e.g., one via 445. In other embodiments, more than four vias 445 are used. Likewise, in Figure 4A , the number of vias 443 between conductors 442 in conductive layer Mn (at the end of conductor 426 opposite pin conductor 428) is four, but can be more or less in other embodiments. Moreover, the conductor lengths in conductive layers Mi ~ Mn can vary as desired. For example, IC device 200 includes relatively long conductors in conductive layer Mi, while IC device 400-1 includes relatively short conductors in conductive layer Mi, and longer conductors 441 in conductive layer Mi+1.

[0080] Referring to Figure 4BFor IC device 400-2, pin conductor 428 is under conductor 426, but the region of pin conductor 428 corresponding to distance D01 between cell boundary 406 and conductor 426 does not overlap with conductor 426. By extending pin conductor 428 from the cell boundary, conductor 426 can be shortened by distance D01. This has the advantage of reducing the charge accumulation area of conductor 426. Furthermore, since pin conductor 428 is not connected to transistor 402 when it is fabricated (since conductor 426 has not yet been formed), the length of pin conductor 428 when it is formed does not impact the antenna rule for transistor 402.

[0081] In Figure 4B , the legend identifies Mn, Mn(pin), VIAn, and Mn+1. Mn and Mn+1 are conductive layer n (e.g., metal layer n) and conductive layer n+1 (e.g., metal layer n+1), respectively. VIAn is via layer n.

[0082] The Mn, VIAn, and Mn+1 features define the shape that will become a physical structure (e.g., a metal structure) in the final fabricated device (e.g., a die or a chip) and help ensure that structures (e.g., metal connections) are correctly formed during fabrication.

[0083] The legend Mn(pin) identifies a pin layer, which is used to designate a connection point or pin on conductive layer Mn. Pins can be named as desired. In some embodiments, pins are used in layout versus schematic (LVS) and automatic place and route (APR) processes, in which pins help ensure that the layout matches the intended schematic by verifying the connections and functionality of the designed circuit.

[0084] Figure 4C is a schematic diagram of IC device 400-3, in accordance with some embodiments.

[0085] Elements of IC device 400-3 that have similar structure and functionality to elements of IC device 200 have the same reference number increased by 200, unless otherwise noted or otherwise apparent.

[0086] Referring to Figure 4C , IC device 400-3 includes a first cell 420A and a third cell 420C that are contiguous at a cell boundary 407 that extends parallel to the X axis, in accordance with some embodiments.

[0087] Cell boundary 407 is perpendicular to Figure 4A cell boundary 406. In Figure 4A , cell boundary 406 corresponds to active region break 402_5, which extends parallel to the Y axis, while in Figure 4CIn some embodiments, the cell boundary 407 corresponds to a midline of the power rail 404, such that half of the power rail 404 width is in the first cell 402A and the other half is in the third cell 420C. In some embodiments, the cell boundary 407 corresponds to a placement and routing boundary that defines an area where placement is complete and routing is restricted.

[0088] In the above Figure 4A In some embodiments, the first and second cells 420A and 420B abut each other in a same row of the layout (the row extends parallel to the X axis), the active region break 402_5 corresponds to a vertical cell boundary (parallel to the Y axis) in the layout (between the first and second cells 420A and 420B), and in the Figure 4C In some embodiments, the first and third cells 420A and 420C abut each other in respective rows of the layout (the rows each extend parallel to the X axis and are adjacent in the Y axis direction), the power rail 404 corresponds to a horizontal cell boundary (parallel to the X axis) in the layout (at which the first and third cells 420A and 420C abut).

[0089] The first cell 420A includes a transistor 403 having a gate 403_1, e.g., a polysilicon gate, a high-k metal gate, etc., over an active region 403_2, and a source 403_3 and a drain 403_4 in the active region 403_2. The transistor 403 is shown as a planar structure, but in other embodiments, the transistor 403 has other configurations, e.g., FinFet, gate-all-around (GAA), complementary FET (CFET), etc.

[0090] The gate 403_1 is coupled to a pin conductor 428 at the cell boundary 407. The pin conductor 428 is in a conductive layer Mn. Although Figure 4C In some embodiments, in the third cell 420C, a conductor (e.g., having a length L01 and corresponding to the third conductor 232 of the IC device 200) extends from the pin conductor 428 in the first cell 420A within the conductive layer Mn in the third cell 420C, although not shown in FIG. 4-2.

[0091] In comparison to the IC device 200, the output pin of the transistor 403 is provided in the conductive layer Mn in the IC device 400-3. That is, the IC device 400-3 uses a higher output pin layer than the IC device 200, which results in a simpler design for the IC device 400-3 in comparison to the IC device 200, which has multiple layers in the pin structure 228.

[0092] Pin conductor 428 is coupled to transistor 403 through a plurality of conductors and vias, with the last formed conductor being conductor 426 in conductive layer Mn+1, which is higher than the layer of pin conductor 428. Thus, conductor 426 is formed after pin conductor 428 and the conductors in conductive layer Mn in third cell 420C. By forming conductor 426 in a layer (layer Mn+1) that is higher than the output pin layer (layer Mn), the conductors in third cell 420C in the output pin layer (i.e., layer Mn in third cell 4201C) can have a length (e.g., length L01) that is not limited by the antenna rule of transistor 403. In addition, conductor 426 can be made shorter, e.g., reducing the charge accumulation area in first cell 420A by distance D02 between cell boundary 407 and conductor 426.

[0093] In Figure 4C , IC device 400-3 is shown as having conductors in conductive layers Mi through Mn+1, with vias in layers therebetween (e.g., in via layer VIAn between conductive layers Mn and Mn+1). However, a greater number of conductive layers are used in some embodiments, while a lesser number of conductive layers are used in other embodiments. In addition, in some embodiments, the output pin of transistor 403 is in a layer higher than conductive layer Mn (although below the last formed conductor 426, which can be in a layer higher than Mn+1), while in other embodiments it is in a layer lower than conductive layer Mn. In addition, in Figure 4C , IC device 400-3 is shown as having four vias 445 extending vertically (parallel to the Z axis) between pin conductor 428 and overlying conductor 426. In some embodiments, fewer than four vias 445 are used, e.g., one via 445. In other embodiments, more than four vias 445 are used. Likewise, in Figure 4C , the number of vias 443 between conductors 442 in conductive layer Mn (at the end of conductor 426 opposite pin conductor 428) is four, but can be more or less in other embodiments. In addition, the conductor lengths in conductive layers Mi ~ Mn can vary as desired. For example, IC device 200 includes relatively long conductors in conductive layer Mi, while IC device 400-3 includes relatively short conductors in conductive layer Mi, and longer conductors 441 in conductive layer Mi+1.

[0094] Reference is made to Figure 4CIC device 400-3, pin conductor 428 is under conductor 426, but the region of pin conductor 428 corresponding to distance D02 between cell boundary 407 and conductor 426 does not overlap with conductor 426. By extending pin conductor 428 from the cell boundary, conductor 426 can be shortened by distance D02. This has the advantage of reducing the charge accumulation area of conductor 426. Furthermore, since pin conductor 428 is not connected to transistor 403 when it is fabricated (since conductor 426 has not yet been formed), the length of pin conductor 428 does not impact the antenna rule for transistor 403 when pin conductor 428 is formed.

[0095] Figure 5A is a schematic diagram of IC device 500-1 according to some embodiments. Figure 5B is a partial layout diagram of IC device 500-2 according to some embodiments.

[0096] Elements of IC devices 500-1, 500-2 having structures and functions similar to elements of IC device 200 have the same reference number increased by 300, unless otherwise noted or otherwise apparent.

[0097] Referring to Figure 5A IC device 500-1 according to some embodiments includes a first cell 520A and a second cell 520B abutting at a cell boundary 506. First cell 520A includes a transistor 502 having a gate 502_1, e.g., a polysilicon gate, a high-k metal gate, etc., over an active region 502_2, and a source 502_3 and a drain 502_4 in active region 502_2. An active region break 502_5 breaks active region 502_2 at cell boundary 506. In some embodiments, active region break 502_5 corresponds to a dummy gate structure, a doped region, an insulating material, etc. In some embodiments, cell boundary 506 corresponds to a placement and routing boundary that defines an area where placement is complete and routing is constrained. Transistor 502 is shown as a planar structure, but in other embodiments transistor 502 has other configurations, e.g., FinFet, gate-all-around (GAA), complementary FET (CFET), etc.

[0098] Gate 502_1 is coupled to pin conductors 528_1-528_4 at cell boundary 506. Pin conductor 528_1 is in conductive layer Mn, pin conductor 528_2 is in conductive layer Mn-1, pin conductor 528_3 is in conductive layer Mx+1 (x+1 is less than n-1, i.e., a lower layer), and pin conductor is in conductive layer Mx. Although Figure 5ANot shown in FIG. 5, but in some embodiments, in the second unit 520B, one or more conductors (e.g., length L01, corresponding to the third conductor 232 of the IC device 200) extend from the pin conductors 528_1-528_4 in the first unit 520A into the respective conductive layers Mn, Mn-1, Mx+1, and / or Mx in the second unit 520B.

[0099] In various embodiments, the pins of the transistor 502 are provided in any of the conductive layers Mn, Mn-1, Mx+1, and / or Mx in the IC device 500-1. By forming multiple pin conductors, there is a variety of choices and flexibility for electrical connections in the IC device 500-1.

[0100] The pin conductors 528_1-528_4 are coupled to the transistor 502 through multiple conductors and vias, the last formed of which is the conductor 526 in the conductive layer Mn+1, which is higher than the highest output pin layer, i.e., higher than any of the pin conductors 528_1-528_4. Thus, the conductor 526 is formed after the pin conductors 528_1 and after any respective conductors in the conductive layers Mn, Mn-1, Mx+1, and / or Mx in the second unit 520B. By forming the conductor 526 in a layer (layer Mn+1) that is higher than the highest layer of the pin structure (layer Mn), the conductors in any of the output pin layers in the second unit 520B (i.e., any of the conductive layers Mn, Mn-1, Mx+1, and / or Mx in the second unit 520B) can have a length (e.g., length L01) that is not limited by the antenna rules of the transistor 502. Furthermore, the conductor 526 can be made shorter, e.g., by the distance D01 between the unit boundary 506 and the conductor 526 to reduce the charge accumulation area in the first unit 520A.

[0101] In Figure 5A The IC device 500-1 is shown in FIG. 5-1 with conductors in the conductive layers Mi through Mn+1, with vias in the layers in between (e.g., in the via layer VIA n between the conductive layers Mn and Mn+1, and in the via layer VIA x between the conductive layers Mx and Mx+1). However, a greater number of conductive layers are used in some embodiments, while a smaller number of conductive layers are used in other embodiments. Furthermore, in some embodiments, the pins of the transistor 502 are in a layer higher than the conductive layer Mn (although below the last formed conductor 526, which can be in a layer higher than Mn+1), while in other embodiments, the pins are in a layer lower than the conductive layer Mn. Furthermore, in some embodiments, the transistor 502 is in a layer higher than the conductive layer Mn (although below the last formed conductor 526, which can be in a layer higher than Mn+1), while in other embodiments, the transistor 502 is in a layer lower than the conductive layer Mn. Figure 5AIn particular, IC device 500-1 is shown with four vias 545 extending vertically (parallel to the Z-axis) between pin conductor 528_1 and overlying conductor 526. In some embodiments, fewer than four vias 545 are used, e.g., one via 545. In other embodiments, more than four vias 545 are used. Likewise, in Figure 5A In particular, the number of vias 543 between conductors 542 in conductive layer Mn (at the end of conductor 526 opposite pin conductor 528_1) is four, but can be more or less in other embodiments. Further, the length of the conductors in conductive layers Mi ~ Mn can vary as desired. For example, IC device 200 includes relatively long conductors in conductive layer Mi, while IC device 500-1 includes relatively short conductors in conductive layer Mi, and longer conductors 541 in conductive layer Mi+1.

[0102] Referring to Figure 5B IC device 500-2, pin conductor 528_1 is located below conductor 526, but the region of pin conductor 528_1 corresponding to distance D01 between cell boundary 506 and conductor 526 does not overlap conductor 526. By extending pin conductor 528_1 from the cell boundary, conductor 526 can be shortened by distance D01. This has the advantage of reducing the charge accumulation area of conductor 526. Further, because pin conductor 528_1 is not connected to transistor 502 when it is fabricated (as conductor 526 has not yet been formed), the length of pin conductor 528_1 when it is formed does not impact the antenna rules for transistor 502. This also applies to other pin conductors 528_2 through 528_4.

[0103] Figure 6A is a schematic diagram of IC device 600-1 in accordance with some embodiments. Figure 6B is a partial layout diagram of IC device 600-2 in accordance with some embodiments.

[0104] Elements of IC devices 600-1, 600-2 having structures and functions similar to elements of IC device 200 have the same reference numerals increased by 400, unless otherwise noted or otherwise apparent.

[0105] Referring to Figure 6AAccording to some embodiments, IC device 600-1 includes a first cell 620A and a second cell 620B abutting at a cell boundary 606. The first cell 620A includes a transistor 602 having a gate 602_1, e.g., a polysilicon gate, a high-k metal gate, etc., located over an active region 602_2, and a source 602_3 and a drain 602_4 in the active region 602_2. An active region break 602_5 breaks the active region 602_2 at the cell boundary 606. In some embodiments, the active region break 602_5 corresponds to a dummy gate structure, a doped region, an insulating material, etc. In some embodiments, the cell boundary 606 corresponds to a placement and routing boundary that defines an area where placement is complete and routing is constrained. The transistor 602 is shown as a planar structure, but in other embodiments the transistor 602 has other configurations, e.g., a FinFet, a gate-all-around (GAA), a complementary FET (CFET), etc.

[0106] The gate 602_1 is coupled to pin conductors 628_1-628_4 at the cell boundary 606. The pin conductors 628_1 are located in the conductive layer Mn, the pin conductors 628_2 are located in the conductive layer Mn-1, the pin conductors 628_3 are located in the conductive layer Mx+1 (x+1 is less than n-1, i.e., a lower layer), and the pin conductors are located in the conductive layer Mx. Although not shown in FIG. 6, in some embodiments, in the second cell 620B, one or more conductors, e.g., of length L01, corresponding to the third conductors 232 of the IC device 200, extend from the pin conductors 628_1-628_4 of the first cell 620A into the respective conductive layers Mn, Mn-1, Mx+1, and / or Mx in the second cell 620B. Figure 6A Although not shown in FIG. 6, in some embodiments, in the second cell 620B, one or more conductors, e.g., of length L01, corresponding to the third conductors 232 of the IC device 200, extend from the pin conductors 628_1-628_4 of the first cell 620A into the respective conductive layers Mn, Mn-1, Mx+1, and / or Mx in the second cell 620B.

[0107] In various embodiments, an output pin of the transistor 602 is provided in any of the conductive layers Mn, Mn-1, Mx+1, and / or Mx in the IC device 600-1. By forming multiple pin conductors, there are multiple choices and flexibility for electrical connections in the IC device 600-1.

[0108] Pin conductors 628_1-628_4 are coupled to transistor 602 through multiple conductors and vias, with the last formed conductor being conductor 626 in conductive layer Mn+1, which is higher than the highest output pin layer, i.e., higher than any of pin conductors 628_1-628_4. Thus, conductor 626 is formed after pin conductors 628_1 and after any corresponding conductors in conductive layers Mn, Mn-1, Mx+1, and / or Mx in second cell 620B. By forming conductor 626 in a layer (layer Mn+1) that is higher than the highest layer of the pin structure (layer Mn), the conductors in any output pin layer in second cell 620B (i.e., any conductive layer Mn, Mn-1, Mx+1, and / or Mx in second cell 620B) can have a length (e.g., length L01) that is not limited by the antenna rule of transistor 602. Moreover, conductor 626 can be made shorter, e.g., reducing the charge accumulation area in first cell 620A by distance D01 between cell boundary 606 and conductor 626.

[0109] In Figure 6A , IC device 600-1 is shown as having conductors in conductive layers Mi through Mn+1, with vias in layers therebetween (e.g., in via layer VIAn between conductive layers Mn and Mn+1, and in via layer VIAx between conductive layers Mx and Mx+1). However, a greater number of conductive layers are used in some embodiments, while a lesser number of conductive layers are used in other embodiments. Moreover, in some embodiments, the pins of transistor 602 are in a layer higher than conductive layer Mn (although below the last formed conductor 626, which can be in a layer higher than Mn+1), while in other embodiments, the pins are in a layer lower than conductive layer Mn. Moreover, in Figure 6A , IC device 600-1 is shown as having four vias 645 extending vertically (parallel to the Z axis) between pin conductor 628_1 and overlying conductor 626. In some embodiments, fewer than four vias 645 are used, e.g., one via 645. In other embodiments, more than four vias 645 are used. Likewise, in Figure 6A , the number of vias 643 between conductors 642 in conductive layer Mn (at the end of conductor 626 opposite pin conductor 628_1) is four, but can be more or less in other embodiments. Moreover, the conductor lengths in conductive layers Mi-Mn can vary as desired. For example, IC device 200 includes a relatively long conductor in conductive layer Mi, while IC device 600-1 includes a relatively short conductor in conductive layer Mi and a longer conductor 641 in conductive layer Mi+1.

[0110] Referring to Figure 6BThe pin conductor 628_1 is offset from the conductor 626 in the Y-axis direction for the IC device 600-2. The conductor 642 extends in the Y-axis direction to have a plate shape, which provides flexibility in layout, e.g., by placing some elements under the top metal layer (Mn+1). One end of the conductor 626 is spaced apart from the cell boundary by a distance D01. This has the advantage of reducing the charge accumulation area of the conductor 626. In addition, since the pin conductor 628_1 is not connected to the transistor 602 when it is fabricated (since the conductor 626 has not yet been formed), the length of the pin conductor 628_1 does not affect the antenna rule for the transistor 602 when the pin conductor 628_1 is formed. This applies to the other pin conductors 628_2-628_4 as well.

[0111] Figure 7 is a flowchart of a placement and routing method 700 according to some embodiments.

[0112] In the method 700, the method of placement and routing includes an operation 702 of evaluating a layout of an integrated circuit design to determine whether (Y) or not (N) an antenna rule violation exists in the cell placement, the routing placement, etc. of the layout.

[0113] If an antenna rule violation is found in operation 702, then operations 704 and / or 706 are performed in some embodiments. In operation 704, the antenna rule violation problem is wholly or partially solved by modifying a portion of the layout to add one or more antenna diodes. In operation 706, the antenna rule violation problem is wholly or partially solved by modifying a portion of the layout to connect the first and second cells using a conductor layer higher than the output pin layer. For a given antenna rule violation, operations 704 and 706 are used in alternative in some embodiments, and combined in other embodiments.

[0114] In some embodiments, operation 704 includes manually or using a software tool adding one or more antenna diodes to the IC design to provide a path for discharge of accumulated charge. In some embodiments, operation 704 includes using an auxiliary antenna repair engine to create an engineering change order to insert diodes to solve the antenna effect. The use of an auxiliary antenna repair engine is described in U.S. Patent Publication No. 2023 / 0053711 Al, which is incorporated herein in its entirety.

[0115] In some embodiments, operation 706 includes routing a first conductive layer, e.g., the top metal layer (Mn+1) as described above in connection with Figure 2The conductive layer Mi causes a first conductor (e.g., conductor 222) in a first cell (e.g., first cell 220A) to be coupled to a gate of a first transistor in the first cell. In some embodiments, operation 706 further includes routing a second conductive layer (e.g., conductive layer Mi+3) higher than the first conductive layer such that: a second conductor (e.g., conductor 232) is located in a second cell (e.g., second cell 220B) and is adjacent to the cell boundary; a pin conductor (e.g., pin conductor 228_1) is located in the first cell and is adjacent to the cell boundary; the second conductor extends in the second cell and is coupled between a source / drain region of a second transistor in the second cell and the pin conductor. In some embodiments, operation 706 further includes routing a third conductive layer, e.g., conductive layer Mn+1, higher than the second conductive layer such that: a third conductor (e.g., conductor 226) is located in the first cell and forms at least part of a conductive path in the first cell between the first conductor and the second conductor; and the third conductive layer is the highest conductive layer among the conductive layers forming the conductive path in the first cell. In some embodiments, the third conductor is spaced apart from the cell boundary.

[0116] In some embodiments, after operation 704 and / or 706, placement and routing continues (operation 708). In some embodiments, if no antenna rule violation is found in operation 702, placement and routing continues (operation 708) without performing operation 704 and / or 706.

[0117] Figure 8 is a flowchart of a method 800 of manufacturing an integrated circuit device according to some embodiments.

[0118] In method 800, operation 802 includes forming a first transistor in a first cell, the first transistor forming at least part of a first circuit. Operation 804 includes forming at least part of a second circuit in a second cell adjacent to the first cell at a first cell boundary. Operation 806 includes forming one or more pin layers in the first cell at the first cell boundary, the one or more pin layers including a highest pin layer. Operation 808 includes forming a first conductive path within the first cell to electrically connect the second circuit to a gate of the first transistor; operation 808 includes sub-operation 810 of forming a first conductor in a topmost one of the conductive layers forming the first conductive path within the first cell, the topmost one being a higher layer than the highest pin layer. Operation 812 includes forming a second conductor in the second cell and electrically connected to the first conductive path through a first one of the one or more pin layers. In some embodiments, method 800 is used to manufacture one or more of IC devices 200, 400_1, 400_2, 500_1, 500_2, 600_1, and / or 600_2 described above.

[0119] Figure 9This is a flowchart of a method 900 for manufacturing a semiconductor device according to some embodiments.

[0120] According to some embodiments, method 900 may, for example, use EDA system 1000 ( Figure 10 (Discussed below) and Integrated Circuit (IC) Manufacturing System 1100 ( Figure 11 (This will be discussed below) to achieve this. Examples of semiconductor devices that can be manufactured according to method 900 include one or more of the above-described IC devices 200, 400_1, 400_2, 500_1, 500_2, 600_1 and / or 600_2.

[0121] exist Figure 9 In this method 900, blocks 902-904 are included. In operation 902, a layout diagram is generated, including one or more layout diagrams disclosed herein. In some embodiments, operation 902 includes one or more of operations 702-708 described above in conjunction with method 700.

[0122] In some embodiments, the layout diagram generated in operation 902 includes: in a first conductive layer: a first conductor in a first cell, the first conductor being coupled to the gate of a first transistor in the first cell; in a second conductive layer above the first conductive layer: a second conductor in a second cell adjacent to the first cell at a cell boundary, and a pin conductor in the first cell adjacent to the cell boundary, the second conductor extending within the second cell and coupled between the source / drain region of the second transistor in the second cell and the pin conductor; and in a third conductive layer above the second conductive layer: a third conductor in the first cell, forming at least a portion of a conductive path in the first cell between the first conductor and the second conductor, the third conductor being spaced apart from the cell boundary, the third conductive layer being the highest conductive layer among the conductive layers forming the conductive path of the first cell.

[0123] According to some embodiments, operation 902 can, for example, be performed using EDA system 1000 ( Figure 10 (This will be discussed below) to achieve this. In some embodiments, operation 902 includes generating a shape corresponding to the structure to be represented in the semiconductor diagram.

[0124] In operation 904, based on the layout diagram, (A) one or more photolithographic exposures are performed, or (B) one or more semiconductor masks are fabricated, or (C) at least one of one or more components in an integrated circuit (IC) device (e.g., a semiconductor device) layer is fabricated. In some embodiments, operation 904 includes one or more of operations 802-812 described above in conjunction with method 800. See also the following description of... Figure 11 The discussion.

[0125] Figure 10is a block diagram of an electronic design automation (EDA) system 1000 according to some embodiments. The EDA system 1000 can be used to design one or more of the IC devices 200, 400_1, 400_2, 500_1, 500_2, 600_1, and / or 600_2 described above.

[0126] In some embodiments, the EDA system 1000 includes an APR system. In some embodiments, the EDA system 1000 is or includes a general purpose computing device that includes a hardware processor 1002 and a non-transitory computer- readable storage medium 1004 (also referred to as memory). The computer-readable storage medium 1004 is encoded (i.e., stored) with computer program code 1006 (i.e., a set of executable instructions). Execution of the instructions 1006 by the processor 1002 represents (at least in part) an EDA tool that implements some or all of the methods (hereinafter referred to as the processes and / or methods) described herein according to one or more embodiments.

[0127] In some embodiments, the methods described herein that represent a layout map of a wiring arrangement can be implemented using the EDA system 1000.

[0128] In some embodiments, the EDA system 1000 is configured to perform an APR operation to generate a layout of an IC, e.g., based on a schematic of the IC, the APR operation including a cell placement operation that places a first cell and a second cell in the layout map such that the first and second cells abut each other at a cell boundary, and a wiring operation that wires a network in the layout map that interconnects the first and second cells, the wiring operation including: wiring a first conductive layer such that: a first conductor in the first cell is coupled to a gate of a first transistor in the first cell; wiring a second conductive layer higher than the first conductive layer such that: a second conductor is located in the second cell and abuts the cell boundary, a pin conductor is located in the first cell and abuts a boundary thereof, the second conductor extends within the second cell and is coupled between a source / drain region of a second transistor in the second cell and the pin conductor; and wiring a third conductive layer higher than the second conductive layer such that: a third conductor is located in the first cell and forms at least part of a conductive path in the first cell between the first conductor and the second conductor, the third conductor is spaced apart from the cell boundary, and the third conductive layer is the highest conductive layer among the conductive layers that form the conductive path in the first cell.

[0129] In some embodiments, execution of the instructions 1006 by the hardware processor 1002 represents (at least in part) an IC device design system that implements some or all of one or more of the processes and / or methods.

[0130] In some embodiments, the computer program product includes a non-transitory computer-readable storage medium 1004 having stored therein instructions that, when executed by a processor 1002, cause the processor 1002 to perform a cell placement operation to place a first cell and a second cell in a layout such that the first and second cells abut each other at a cell boundary, and perform a first routing operation to route a network in the layout that interconnects the first and second cells, the first routing operation including: routing a first conductive layer such that: a first conductor in the first cell is coupled to a gate of a first transistor in the first cell; routing a second conductive layer higher than the first conductive layer such that: a second conductor is located in the second cell and abuts the cell boundary, a pin conductor is located in the first cell and abuts a boundary thereof, the second conductor extends within the second cell and is coupled between a source / drain region of a second transistor in the second cell and the pin conductor; and routing a third conductive layer higher than the second conductive layer such that: a third conductor is located in the first cell and forms at least part of a conductive path in the first cell between the first conductor and the second conductor, the third conductor is spaced apart from the cell boundary, and the third conductive layer is the highest conductive layer among the conductive layers that form the conductive path in the first cell. In some embodiments, the non-transitory computer-readable storage medium 1004 also has stored therein instructions that, when executed by the processor 1002, cause the processor 1002 to evaluate whether a second routing operation for the network would cause an antenna rule violation for the first transistor, and perform the first routing operation instead of the second routing operation when the evaluation determines that the second routing operation would cause the antenna rule violation for the first transistor.

[0131] The processor 1002 is electrically coupled to the computer-readable storage medium 1004 via a bus 1008. The processor 1002 is also electrically coupled to an I / O interface 1010 by the bus 1008. A network interface 1012 is also electrically connected to the processor 1002 via the bus 1008. The network interface 1012 is connected to a network 1014, enabling the processor 1002 and the computer-readable storage medium 1004 to connect to external elements via the network 1014. The processor 1002 is configured to execute the computer program code 1006 encoded in the computer-readable storage medium 1004, to cause the EDA system 1000 to be operable to perform part or all of the processes and / or methods described. In one or more embodiments, the processor 1002 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0132] In one or more embodiments, the computer-readable storage medium 1004 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). In some embodiments, the computer-readable storage medium 1004 includes a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid disk, and / or an optical disk. In one or more embodiments using an optical disk, the computer-readable storage medium 1004 includes a compact disk readonly memory (CD-ROM), a compact disk-read / write (CD-R / W), and / or a digital video disk (DVD).

[0133] In one or more embodiments, the computer-readable storage medium 1004 stores computer program code 1006 configured to cause the EDA system 1000 (where such execution represents (at least part of) an EDA tool) to be available for performing part or all of the described processes and / or methods. In one or more embodiments, the computer-readable storage medium 1004 also stores information that facilitates performing part or all of the described processes and / or methods. In one or more embodiments, the computer-readable storage medium 1004 stores a standard cell library 1007 including the standard cells disclosed herein. In one or more embodiments, the computer-readable storage medium 1004 stores one or more layout maps 1009 corresponding to one or more layouts disclosed herein.

[0134] The EDA system 1000 includes an I / O interface 1010. The I / O interface 1010 is coupled to external circuits. In one or more embodiments, the I / O interface 1010 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, a touch screen, and / or a cursor direction key for communicating information and commands to the processor 1002.

[0135] The EDA system 1000 also includes a network interface 1012 coupled to the processor 1002. The network interface 1012 allows the EDA system 1000 to communicate with a network 1014 to which one or more other computer systems are connected. The network interface 1012 includes a wireless network interface, such as Bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE- 1364. In one or more embodiments, part or all of the described processes and / or methods are implemented in two or more EDA systems 1000.

[0136] EDA system 1000 is configured to receive information through I / O interface 1010. The information received through I / O interface 1010 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 1002. The information is transferred to processor 1002 through bus 1008. EDA system 1000 is configured to receive information related to a user interface (UI) through I / O interface 1010. The information is stored in computer-readable storage medium 1004 as UI 1042.

[0137] In some embodiments, some or all of the processes and / or methods are embodied in a software application executed by a processor. In some embodiments, some or all of the processes and / or methods are embodied in a software application that is part of an additional software application. In some embodiments, some or all of the processes and / or methods are embodied in a plug-in to a software application. In some embodiments, at least one of the processes and / or methods is embodied in a software application that is part of an EDA tool. In some embodiments, some or all of the processes and / or methods are embodied in a software application used by EDA system 1000. In some embodiments, a tool such as Design Compiler® available from CADENCE DESIGN SYSTEMS, INC. or another suitable layout generation tool is used to generate a layout map including standard cells.

[0138] In some embodiments, the processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of the non-transitory computer-readable recording medium include, but are not limited to, one or more of external / removable and / or internal / built-in storage or storage units such as optical storage (e.g., DVD), magnetic storage (e.g., hard disk), semiconductor memory (e.g., ROM), RAM, storage cards, etc.

[0139] Figure 11 is a block diagram of an IC manufacturing system 1100 and its associated IC manufacturing flow according to some embodiments. In some embodiments, at least one of (A) one or more semiconductor masks or (B) at least one component in a semiconductor integrated circuit layer is manufactured using IC manufacturing system 1100 based on a layout map.

[0140] In Figure 11In particular embodiments, the IC fabrication system 1100 includes entities that interact in the design, development, and fabrication cycle and / or services related to fabricating IC devices 1160, such as a design house 1120, a mask house 1130, and an IC foundry / fabricator (“Fab”) 1150. The entities in the IC fabrication system 1100 are connected by a communication network. In some embodiments, the communication network is a single network. The communication network includes wired and / or wireless communication channels. Each entity interacts with and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design house 1120, the mask house 1130, and the IC foundry 1150 are owned by a single larger company. In some embodiments, two or more of the design house 1120, the mask house 1130, and the IC foundry 1150 coexist in a common facility and use common resources.

[0141] The design house (or design team) 1120 generates an IC design layout 1122 based on the above-described processes and / or methods. The IC design layout 1122 includes various geometric patterns corresponding to patterns of metal, oxide, or semiconductor layers that make up various components of the IC device 1160 to be fabricated. The layers combine to form various IC features. For example, portions of the IC design layout 1122 include various IC features, such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnections, and openings for pads, that are to be formed in a semiconductor substrate, such as a silicon wafer, and various material layers disposed on the semiconductor substrate. The design house 1120 implements appropriate design processes to form the IC design layout 1122. The design processes include one or more of logic design, physical design, or placement and routing. The IC design layout 1122 is presented in the form of one or more data files with geometric pattern information. For example, the IC design layout 1122 can be represented in a GDSII file format or a DFII file format.

[0142] The mask house 1130 includes mask data preparation 1132 and mask fabrication 1144. The mask house 1130 uses the IC design layout 1122 to fabricate one or more masks 1145 for use in fabricating various layers of the IC device 1160 according to the IC design layout 1122. The mask house 1130 performs mask data preparation 1132 in which the IC design layout 1122 is converted to a representative data file (RDF). The mask data preparation 1132 provides the RDF to the mask fabrication 1144. The mask fabrication 1144 includes a mask writer. The mask writer converts the RDF to an image on a substrate, such as a mask (reticle) 1145 or a substrate 1153, such as a semiconductor wafer. The IC design layout 1122 is manipulated by the mask data preparation 1132 to conform to the particular characteristics of the mask writer and / or requirements of the IC foundry 1150. In particular embodiments, the mask data preparation 1132 includes a mask data preparation system.Figure 11 In particular embodiments, mask data preparation 1132 and mask fabrication 1144 are shown as separate elements. In some embodiments, mask data preparation 1132 and mask fabrication 1144 can be collectively referred to as mask data preparation.

[0143] In some embodiments, mask data preparation 1132 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that can be caused by diffraction, interference, other process effects, etc. OPC adjusts IC design layout 1122. In some embodiments, mask data preparation 1132 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shift masks, other suitable techniques, etc., or combinations thereof. In some embodiments, inverse lithography techniques (ILT) are also used, which treat OPC as an inverse imaging problem.

[0144] In some embodiments, mask data preparation 1132 includes a mask rule checker (MRC), which uses a set of mask creation rules to check IC design layout 1122 after it has been processed by OPC. The set of mask creation rules contains certain geometric and / or connectivity restrictions to ensure that there is sufficient margin to account for variability in the semiconductor manufacturing process, etc. In some embodiments, MRC modifies IC design layout 1122 to compensate for limitations during mask fabrication 1144, which can undo some of the modifications performed by OPC to satisfy the mask creation rules.

[0145] In some embodiments, mask data preparation 1132 includes a lithography process check (LPC), which simulates the processing that will be performed by IC foundry 1150 to manufacture IC device 1160. LPC simulates the processing based on IC design layout 1122 to create a simulated manufactured device, such as IC device 1160. The processing parameters in the LPC simulation can include parameters related to various processes of the IC manufacturing cycle, parameters related to tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC takes into account various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, etc., or combinations thereof. In some embodiments, after the LPC creates a simulated manufactured device, if the shape of the simulated device is not close enough to satisfy design rules, then OPC and / or MRC are repeated to further refine IC design layout 1122.

[0146] It should be appreciated that the above description of mask data preparation 1132 has been simplified for clarity. In some embodiments, mask data preparation 1132 includes additional features, such as logic operations (LOPs) that modify IC design layout 1122 according to manufacturing rules. Furthermore, the processes applied to IC design layout 1122 during mask data preparation 1132 can be performed in a variety of different orders.

[0147] After mask data preparation 1132 and during mask manufacturing 1144, a mask 1145 or a set of masks 1145 is manufactured based on the modified IC design layout 1122. In some embodiments, mask manufacturing 1144 includes performing one or more photolithography exposures based on the IC design layout 1122. In some embodiments, based on the modified IC design layout 1122, a pattern is formed on a mask (photomask or reticle) 1145 using an e-beam or multiple e-beams mechanism. The mask 1145 can be formed using various techniques. In some embodiments, the mask 1145 is formed using binary technology. In some embodiments, the mask pattern includes opaque regions and transparent regions. A beam of radiation, such as an ultraviolet (UV) beam, used to expose a layer of image-sensitive material (e.g., photoresist) that has been coated on a wafer, is blocked by the opaque regions and transmitted through the transparent regions. In one example, a binary mask version of the mask 1145 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, the mask 1145 is formed using phase shift technology. In a phase shift mask (PSM) version of the mask 1145, various features in the pattern formed on the phase shift mask are configured to have appropriate phase differences to improve resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask generated by mask manufacturing 1144 is used for various processes. For example, in some embodiments, the mask is used for an ion implantation process to form various doped regions in a substrate 1153, for an etching process to form various etched regions in the substrate 1153, and / or for other suitable processes.

[0148] IC foundry 1150 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, the IC foundry 1150 is a semiconductor foundry. For example, there can be one manufacturing facility for front-end manufacturing (front-end-of-line (FEOL) manufacturing) of multiple IC products, while a second manufacturing facility can provide back-end manufacturing (back-end-of-line (BEOL) manufacturing) for interconnection and packaging of the IC products, and a third manufacturing facility can provide other services for the foundry business.

[0149] IC foundry 1150 includes wafer fabrication tools 1152 configured to perform various manufacturing operations on a substrate 1153 to manufacture an IC device 1160 according to a mask (e.g., mask 1145). In some embodiments, the wafer fabrication tools 1152 include one or more of a wafer stepper, an ion implanter, a photoresist coater, a process chamber (e.g., a CVD chamber or an LPCVD furnace), a CMP system, a plasma etching system, a wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes described herein.

[0150] IC foundry 1150 uses the mask 1145 manufactured by the mask room 1130 to manufacture an IC device 1160. Thus, the IC foundry 1150 uses the IC design layout 1122, at least indirectly, to manufacture the IC device 1160. In some embodiments, a substrate 1153 is manufactured by the IC foundry 1150 using the mask 1145 to form the IC device 1160. In some embodiments, the IC manufacturing includes performing one or more photolithography exposures based at least indirectly on the IC design layout 1122. In some embodiments, the substrate 1153 includes a silicon substrate or other suitable substrate having material layers formed thereon. In some embodiments, the substrate 1153 also includes one or more of various doped regions, dielectric features, multi-level interconnects, etc. (formed in subsequent manufacturing steps).

[0151] For detailed information about IC manufacturing systems (e.g., the IC manufacturing system 1100) and IC manufacturing processes related thereto, see, e.g., U.S. Patent No. 9,256,709, issued February 9, 2016, U.S. Pre-Grant Publication No. 2015 / 0278429 Al, published October 1, 2015, U.S. Pre-Grant Publication No. 2014 / 0040838 Al, published February 6, 2014, and U.S. Patent No. 7,260,442, issued August 21, 2007, the entireties of which are incorporated herein by reference. Figure 11

[0152] In some embodiments, an integrated circuit device includes a gate oxide containing device (GOX device); one or more first metal layer segments and one or more first vias coupled to the GOX device; one or more second metal layer segments and one or more second vias laterally spaced apart from the one or more first metal layer segments and the one or more first vias; and a conductive segment forming at least part of an electrical connection coupling at least one of the one or more second metal layer segments or one or more second vias to at least one of the one or more first metal layer segments or one or more first vias. In some embodiments, the conductive segment is in a conductive layer higher than a highest pin layer of the GOX device. In some embodiments, the highest pin layer is included in the one or more second metal layer segments. In some embodiments, a conductor coupled to a pin of the one or more second metal layer segments is free of an antenna diode.

[0153] ​For example, as disclosed in U.S. Patent No. 9256709: A method of transforming a first integrated circuit (IC) pattern, wherein the first IC pattern comprises a shape that is not one of a plurality of user-defined shapes, the method comprising: with a computer, deriving a second IC pattern that approximates the first IC pattern, wherein the second IC pattern comprises one of the plurality of user-defined shapes; calculating a pattern approximation error between the first and second IC patterns; when the pattern approximation error is greater than a user-defined threshold, performing the following operations: partitioning the first IC pattern into a plurality of sub-patterns; recursively transforming each of the plurality of sub-patterns. Wherein the first IC pattern comprises a plurality of sub-patterns, and a plurality of second IC sub-patterns are derived for the plurality of sub-patterns, respectively, the method further comprises: concatenating the plurality of second IC sub-patterns. The method further comprises, when the pattern approximation error is equal to or less than the user-defined threshold: outputting the second IC pattern in a computer-readable format. Receiving an integrated circuit (IC) design layout, the first pattern of the IC design layout is not rectangular; with a computer, determining a rectangle that approximates the first pattern; calculating a deviation between the first pattern and the rectangle; when the deviation is less than a user-defined threshold, replacing the first pattern in the IC design layout with the rectangle. Otherwise, performing the following operations: partitioning the first pattern into a plurality of sub-patterns; for each of the plurality of sub-patterns, recursively performing the steps of determining, calculating, conditionally replacing, and conditionally partitioning.

[0154] As disclosed in publication No. 2015 / 0278429A1: In one method, a design layout of an integrated circuit (IC) is received, the design layout having a primary feature; the primary feature is processed to correct, thereby generating a modified primary feature; using a computer, a simulated contour of the modified primary feature is generated, the simulated contour having a plurality of points; a plurality of auxiliary data is generated, wherein each auxiliary data includes at least one process performance factor associated with one of the points; and the simulated contour and the auxiliary data are stored in a tangible computer-readable medium for use by other IC processing stages. In one method, a device is received, the device having a primary feature of an integrated circuit (IC); a simulated contour of the primary feature and a plurality of auxiliary data are received, wherein the simulated contour includes a plurality of points and each auxiliary data represents at least one process performance factor at one of the points on the simulated contour; an image is exposed on a semiconductor substrate using the device and a lithography process; and the image on the semiconductor substrate is inspected using at least the plurality of auxiliary data.

[0155] As disclosed in publication number 2014 / 0040838 Al: In a method of manufacturing a mask, an integrated circuit (IC) design layout is received; a target feature surround (TFS) check operation is performed to identify target feature surround locations (TFSLs) in the IC design layout; a phase bar (PB) is inserted at the TFSLs; an optical proximity correction (OPC) is performed on the IC design layout with the PB to form a modified IC design layout; and the mask is fabricated according to the modified IC design layout. In a method of manufacturing a mask, a substrate is provided; an integrated circuit (IC) design layout having a phase bar (PB) is provided; an absorber layer is formed on the substrate, wherein the mask comprises the substrate and the absorber layer; the absorber layer is patterned to form an IC design layout pattern on the mask associated with the IC design layout, wherein the patterned absorber layer comprises opaque regions and regions where the absorber is absent; and the PB is formed in the regions where the absorber is absent according to the IC design layout. The PB is formed as a PB trench by removing a portion of the substrate in the regions where the absorber is absent. The depth of the PB trench is controlled to achieve a predetermined phase shift. The PB is formed by locally depositing PB material in the regions where the absorber is absent. The PB is formed with a predetermined phase shift by configuring the thickness, refractive index, and extinction coefficient of the PB material.

[0156] As disclosed in US patent number 7260442: In a method of manufacturing a mask, material and device data are provided; a first manufacturing model is determined from the material and device data; a first process run is performed on a first mask according to the first manufacturing model; first process data is collected during the first process run; backward modification data is determined from the material and device data and the first process data; the first manufacturing model is modified according to the backward modification data to obtain a second manufacturing model; a second process run is performed on a second mask according to the second manufacturing model. The backward modification data determining step further comprises performing a statistical process control analysis. The material data comprises resist type, characteristics, production date, post-coat decay, or lot relationship data. The device data comprises device type, mask layer, mask level, option correction type, pattern load, or device load data. The first process data comprises exposure tool, etch chamber, etch time, tool bias, lot relationship, or inspection result data. The manufacturing model defining step further comprises defining a manufacturing model that describes a mask write process. The manufacturing model defining step further comprises defining a manufacturing model that describes a mask bake process. The manufacturing model defining step further comprises defining a manufacturing model that describes a mask development process. The manufacturing model defining step further comprises defining a manufacturing model that describes a mask etch process. The method further comprises obtaining an inspection result from a previous process run, wherein the inspection result is a post-inspection result; determining forward modification data from the first process data and the inspection result; determining a re-etch manufacturing model from the forward modification data; and performing a re-etch process run on the first mask according to the re-etch manufacturing model.

[0157] For example, as disclosed in U.S. Patent Publication No. 2023 / 0053711 Al, in a method of designing an integrated circuit (IC) device, identifying, with a processor, a pin that fails a test to determine an antenna effect; identifying, with the processor, a network corresponding to the identified pin that fails the test to determine the antenna effect; and creating, using the processor, an engineering change order (ECO) script to insert a diode to resolve the antenna effect based on the identified network. The method can further include flagging, with the processor, the network of the pin that fails the test to determine the antenna effect; and identifying, with the processor, a suspect cell of the network based on the flagging using an automatic place and route (APR) tool. The method can further include flagging, with the processor, a gate that includes the pin that fails the test to determine the antenna effect; and identifying, with the processor, a cell that includes the gate based on the flagging using the APR tool. The method can further include determining, with the processor, whether the suspect cell of the network matches the cell that includes the pin that fails the test. The method can further include determining, with the processor, one or more diodes needed to resolve the antenna effect. The method can further include distributing, with the processor and in response to a plurality of pins electrically connected to the identified network, the one or more diodes among the plurality of pins based on an average. The method can further include implementing, with the processor, a layout change to include the one or more diodes electrically coupled to the pin that fails the test to determine the antenna effect. The method can further include implementing, with the processor, a layout change to include the one or more diodes electrically coupled to the pin that fails the test to determine the antenna effect in a metal layer below a metal layer in which the one or more diodes were initially placed. The method can further include determining, with the processor, one or more additional diodes to electrically connect to the pin that fails the test to determine the antenna effect based on allowed routing changes. The method can further include adding, with the processor and in response to a block antenna effect failure, the one or more diodes to a block that includes the network. The method can further include adding, with the processor and in response to a flat antenna effect failure, the one or more diodes to a block that includes at least a portion of the network. The method can further include creating, using the processor, an engineering change order (ECO) script and in response to the pin that fails the test to determine the antenna effect.

[0158] In some embodiments, a method of forming an integrated circuit device includes forming one or more first metal layers and one or more first vias; forming one or more second metal layers and one or more second vias, the second metal layers and second vias laterally spaced apart and separate from the one or more first metal layers and first vias; performing one or more of a plasma process or a charge neutralization process (such as chemical mechanical polishing (CMP)) on at least one of the one or more second metal layers or the one or more second vias; and, after performing the charge neutralization process, coupling at least one of the one or more second metal layers or the one or more second vias to at least one of the one or more first metal layers or the one or more first vias.

[0159] In some embodiments, a method for manufacturing a semiconductor structure includes forming a first metal layer; simultaneously forming a conductive layer and a second metal layer isolated from the conductive layer, the second metal layer electrically connected to the first metal layer through a first via; forming a top metal layer electrically connected to the conductive layer and the second metal layer through a second via. In some embodiments, the first metal layer is electrically connected to a pair of transistors, the conductive layer includes a signal routing trace and a first pin layer.

[0160] In some embodiments, a semiconductor structure includes a first metal layer electrically connected to a first pair of transistors; a second metal layer disposed on the first metal layer and electrically connected to the first metal layer through a first via; a conductive layer disposed in parallel to and isolated from the second metal layer; and a top metal layer disposed on the second metal layer and the conductive layer and electrically connected to the conductive layer and the second metal through a second via. In some embodiments, the conductive layer includes a signal routing trace and a first pin layer, and the signal routing trace is electrically connected to a second pair of transistors.

[0161] In some embodiments, an integrated circuit device includes a first cell including a first transistor in an active region on a substrate, the first transistor forming at least part of a first circuit; and a second cell abutting the first cell at a first cell boundary, the second cell including at least part of a second circuit. The first cell includes one or more pin layers at the first cell boundary, the one or more pin layers including a highest pin layer, the second circuit is electrically connected to a gate of the first transistor through a first conductive path within the first cell, the first conductive path including a first conductor of a topmost conductive layer of the conductive layers forming the first conductive path within the first cell, the topmost conductive layer being a higher layer than the highest pin layer, the second circuit includes a second conductor electrically connected to the first conductive path at a first pin conductor of a first pin layer of the one or more pin layers, the first cell boundary corresponding to at least one of a break in the active region, an edge of one of the one or more pin layers, or a power rail in the conductive layers closest to the substrate.

[0162] In some embodiments, the second conductor has a length L outside the first cell, and the length L is sufficient to cause a combined area of the first conductive path and the second conductor to exceed an antenna design rule check value of an antenna design rule of the gate of the first transistor. In some embodiments, the integrated circuit device further includes a second transistor located in the second cell and forming at least part of the second circuit. The second conductor is coupled to a source / drain region of the second transistor, and the second conductor is free of an antenna diode. In some embodiments, the first transistor and the first pin conductor are spaced apart in a first direction, the first conductor is spaced apart from the first transistor in a second direction perpendicular to the first direction, and the first conductor is spaced apart from the first pin conductor in the second direction. In some embodiments, the first transistor and the first pin conductor are spaced apart in a first direction, and the first conductor is spaced apart from the first cell boundary in the first direction. In some embodiments, the one or more pin layers include a plurality of pin layers, the first conductor at least partially overlaps a second pin conductor in a highest pin layer, and at least one via extends from the first conductor to the second pin conductor. In some embodiments, the integrated circuit device further includes a stack of conductors and vias located in the first cell and forming part of the first conductive path. An area of each conductor of the stack is less than an area of the first conductor. In some embodiments, the integrated circuit device further includes a stack of conductors and vias located in the first cell and forming part of the first conductive path. An area of each conductor of the stack is less than an area of the second conductor.

[0163] In some embodiments, a method of manufacturing an integrated circuit device includes forming a first transistor in an active region on a substrate, the first transistor forming at least part of a first circuit in a first cell; forming at least part of a second circuit in a second cell adjacent to the first cell at a first cell boundary; forming one or more pin conductors in the first cell at the first cell boundary, the one or more pin conductors including a highest pin conductor; forming a first conductive path within the first cell to electrically connect the second circuit to a gate of the first transistor, forming the first conductive path within the first cell includes forming a first conductor in a topmost conductive layer of conductive layers forming the first conductive path within the first cell, the topmost conductive layer being a higher layer than the highest pin conductor; and forming a second conductor in the second cell, the second conductor electrically connected to the first conductive path through a first pin conductor of the one or more pin conductors, wherein the first cell boundary corresponds to at least one of a break in the active region, an edge of one of the one or more pin layers, or a power rail in a conductive layer closest to the substrate.

[0164] In some embodiments, forming the one or more pin conductors includes forming the first pin conductor as a highest pin conductor. In some embodiments, the second conductor is formed outside the first cell to have a length L; and the length L is sufficient to cause a combined area of the first conductive path and the second conductor to exceed an antenna design rule check value of an antenna design rule of the gate of the first transistor. In some embodiments, the method further includes forming a second transistor in a second cell, the second transistor forming at least part of a second circuit. Forming the second conductor includes coupling the second conductor to a source / drain region of the second transistor, and the second conductor is free of an antenna diode. In some embodiments, the first transistor and the first pin conductor are formed to be spaced apart in a first direction, forming the first conductor includes spacing the first conductor from the first transistor in a second direction perpendicular to the first direction, the first conductor being spaced apart from the first pin conductor in the second direction. In some embodiments, the first transistor and the first pin conductor are formed to be spaced apart in a first direction, forming the first conductor includes spacing the first conductor from a first cell boundary in the first direction. In some embodiments, forming the one or more pin conductors includes forming a plurality of pin conductors, forming the first conductor includes forming the first conductor to at least partially overlap a second pin conductor in a highest pin layer, and forming at least one via extending from the first conductor to the second pin conductor. In some embodiments, forming the first conductive path within the first cell includes forming a stack of conductors and vias in the first cell, the conductors of the stack each having an area less than the second conductor.

[0165] In some embodiments, an integrated circuit device includes a first transistor in a first active region on a substrate, the first transistor being in a first cell and having a gate coupled to a first conductive segment in a first conductive layer closest to the substrate; a second transistor in a second cell adjacent to the first cell at a cell boundary, the cell boundary corresponding to at least one of an isolation structure at an edge of the first active region or a power rail in the first conductive layer; one or more pin conductors in the first cell; and a conductive path in the first cell, the conductive path coupling a first pin conductor of the one or more pin conductors to the gate of the first transistor. The conductive path in the first cell includes a second conductive segment in a highest conductive layer of conductive structures forming the conductive path in the first cell, and the second conductive segment is higher than a highest pin conductor of the one or more pin conductors in the first cell.

[0166] In some embodiments, the integrated circuit device further includes: a third conductive segment in the second cell, the third conductive segment coupling the second transistor to the first pin conductor. In some embodiments, the third conductive segment has a length L in the second cell; and the length L is sufficient to cause a combined area of the conductive path and the third conductive segment to exceed an antenna design rule check value of an antenna design rule of the first transistor. In some embodiments, the third conductive segment is coupled to a source / drain region of the second transistor, and the third conductive segment is free of an antenna diode.

[0167] In some embodiments, an integrated circuit device includes a first cell including a first transistor on a substrate, the first transistor forming at least part of a first circuit; and a second cell adjoining the first cell at a cell boundary, the second cell including a second transistor on the substrate and forming at least part of a second circuit. The second circuit includes a first conductor electrically connecting a source / drain region of the second transistor to a first pin layer of a plurality of pin layers, the first cell including a conductive path electrically connecting a gate of the first transistor to a second pin layer of the plurality of pin layers, the conductive path including a second conductor, the first pin layer being between the substrate and the second pin, the second pin being between the second conductor and the first pin.

[0168] In some embodiments, a non-transitory computer readable storage medium includes: a layout map of an integrated circuit, the layout map including: in a first conductive layer: a first conductor in a first cell, the first conductor coupled to a gate of a first transistor in the first cell; in a second conductive layer higher than the first conductive layer: a second conductor in a second cell adjoining the first cell at a cell boundary, and a pin conductor in the first cell adjoining the cell boundary, the second conductor extending within the second cell and coupled between a source / drain region of a second transistor in the second cell and the pin conductor; in a third conductive layer higher than the second conductive layer: a third conductor in the first cell forming at least part of a conductive path in the first cell between the first conductor and the second conductor, the third conductor being spaced apart from the cell boundary. The third conductive layer is a highest conductive layer of the conductive layers forming the conductive path in the first cell. In some embodiments, a combined area of the first conductor, the conductive path in the first cell, and the second conductor violates an antenna rule limit of the first transistor, and a combined area of the first conductor, the third conductor, and any conductive structures in the part of the conductive path in the first cell between the first conductor and the third conductor does not violate the antenna rule limit of the first transistor.

[0169] In some embodiments, a system includes a processor configured to perform an automatic placement and routing (APR) operation to generate a layout map of an integrated circuit (IC), where the APR operation includes a cell placement operation that places a first cell and a second cell in the layout map such that the first and second cells abut each other at a cell boundary, and a routing operation that routes a network interconnecting the first and second cells in the layout map, the routing operation including: routing a first conductive layer such that: a first conductor in the first cell is coupled to a gate of a first transistor in the first cell; routing a second conductive layer higher than the first conductive layer such that: a second conductor is located in the second cell and abuts the cell boundary, a pin conductor is located in the first cell and abuts a boundary thereof, the second conductor extends within the second cell and is coupled between a source / drain region of a second transistor in the second cell and the pin conductor; and routing a third conductive layer higher than the second conductive layer such that: a third conductor is located in the first cell and forms at least part of a conductive path in the first cell between the first conductor and the second conductor, the third conductor is spaced apart from the cell boundary, and the third conductive layer is a highest conductive layer among the conductive layers that form the conductive path in the first cell.

[0170] In some embodiments, a computer program product includes a non-transitory computer-readable storage medium having stored therein instructions that, when executed by a processor, cause the processor to: perform a cell placement operation that places a first cell and a second cell in a layout map such that the first and second cells abut each other at a cell boundary, and perform a first routing operation that routes a network interconnecting the first and second cells in the layout map, the first routing operation including: routing a first conductive layer such that: a first conductor in the first cell is coupled to a gate of a first transistor in the first cell; routing a second conductive layer higher than the first conductive layer such that: a second conductor is located in the second cell and abuts the cell boundary, a pin conductor is located in the first cell and abuts a boundary thereof, the second conductor extends within the second cell and is coupled between a source / drain region of a second transistor in the second cell and the pin conductor; and routing a third conductive layer higher than the second conductive layer such that: a third conductor is located in the first cell and forms at least part of a conductive path in the first cell between the first conductor and the second conductor, the third conductor is spaced apart from the cell boundary, and the third conductive layer is a highest conductive layer among the conductive layers that form the conductive path in the first cell. In some embodiments, the non-transitory computer-readable storage medium has further stored therein instructions that, when executed by the processor, cause the processor to: evaluate whether a second routing operation of the network would cause an antenna rule violation of the first transistor, and perform the first routing operation instead of the second routing operation when the evaluation determines that the second routing operation would cause the antenna rule violation of the first transistor.

[0171] As used herein, although terms such as "first", "second", and "third" describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another. Unless the context clearly indicates otherwise, the terms "first", "second", and "third" and the like used herein are not meant to indicate a sequential or chronological order, either.

[0172] While the numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in their respective testing measurements. Furthermore, as used herein, the terms "substantially", "about", or "approximately" generally mean values or ranges within 10% of a value or range given by a person of ordinary skill in the art. Alternatively, the terms "substantially", "about", or "approximately" mean within an acceptable standard error of the mean when considered by one of ordinary skill in the art. Other than in operational / working examples, or unless otherwise expressly specified, all numerical ranges, amounts, values and percentages disclosed herein are to be understood as "substantially", "about", or "approximately" the value or range reported. Accordingly, unless otherwise specified, the numerical parameters in the present disclosure and associated claims are approximations. At the very least, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges can be expressed here as from one endpoint to the other or between two endpoints. Unless otherwise stated, all ranges disclosed herein include the endpoints.

[0173] The above summary outlines features of several embodiments in order that the disclosure can be better understood by persons skilled in the art. Those skilled in the art will readily understand that they can readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein without departing from the spirit and scope of the disclosure. Those skilled in the art will also recognize or be able to ascertain, using no more than routine experimentation, many equivalents to the specific embodiments described herein. Such equivalents are considered to be within the scope of the disclosure and are covered by the following claims.

Claims

1. An integrated circuit device, comprising: The first unit includes a first transistor located in an active region on a substrate, the first transistor forming at least a portion of a first circuit; as well as The second unit is adjacent to the first unit at the boundary of the first unit, and the second unit includes at least a portion of the second circuit, wherein: The first unit includes one or more pin layers at its boundary, the one or more pin layers including the highest pin layer. The second circuit is electrically connected to the gate of the first transistor through a first conductive path within the first unit. The first conductive path includes a first conductor in the topmost conductive layer of the conductive layers formed within the first unit, wherein the topmost conductive layer is a layer higher than the highest pin layer. The second circuit includes a second conductor, which is electrically connected to the first conductive path at a first pin conductor of a first pin layer in one or more pin layers. The first cell boundary corresponds to at least one of the interruption in the active region, the edge of one or more pin layers, or the power rail in the conductive layer closest to the substrate.

2. The integrated circuit device according to claim 1, wherein, The second conductor has a length L outside the first unit, and The length L is sufficient to cause the combined area of ​​the first conductive path and the second conductor to exceed the antenna design rule check value of the antenna design rule for the gate of the first transistor.

3. The integrated circuit device according to claim 2, further comprising: The second transistor is located in the second cell and forms at least a portion of the second circuit. in: The second conductor is coupled to the source / drain region of the second transistor, and The second conductor does not have an antenna diode.

4. The integrated circuit device according to claim 1, wherein, The first transistor and the first pin conductor are spaced apart in a first direction. The first conductor is spaced apart from the first transistor in a second direction perpendicular to the first direction, and The first conductor is spaced apart from the first pin conductor in the second direction.

5. The integrated circuit device according to claim 1, wherein, The first transistor and the first pin conductor are spaced apart in a first direction, and The first conductor is spaced apart from the boundary of the first unit in the first direction.

6. The integrated circuit device according to claim 1, wherein, The one or more pin layers include multiple pin layers. The first conductor at least partially overlaps with the second pin conductor in the highest pin layer, and At least one through hole extends from the first conductor to the second pin conductor.

7. The integrated circuit device according to claim 6, further comprising: The stack of conductors and vias is located in the first cell and forms part of the first conductive path. The area of ​​each conductor in the stack is smaller than the area of ​​the first conductor.

8. The integrated circuit device according to claim 6, further comprising: The stack of conductors and vias is located in the first cell and forms part of the first conductive path. The area of ​​each conductor in the stack is smaller than the area of ​​the second conductor.

9. A method for manufacturing an integrated circuit device, the method comprising: A first transistor is formed in an active region on a substrate, the first transistor forming at least a portion of a first circuit in a first cell; At least a portion of a second circuit is formed in the second unit, the second unit being adjacent to the first unit at the boundary of the first unit; One or more pin conductors are formed in the first cell at the boundary of the first cell, the one or more pin conductors including the highest pin conductor; A first conductive path is formed within the first unit to electrically connect the second circuit to the gate of the first transistor. Forming the first conductive path within the first unit includes: A first conductor is formed in the topmost conductive layer of the conductive layer of the first conductive path formed within the first unit, the topmost conductive layer being a layer higher than the highest pin conductor; and A second conductor is formed in the second unit, and the second conductor is electrically connected to the first conductive path through a first pin conductor of one or more pin conductors. Wherein, the first cell boundary corresponds to at least one of the interruption in the active region, the edge of one or more pin layers, or the power rail in the conductive layer closest to the substrate.

10. An integrated circuit device, comprising: A first transistor is located in a first active region on a substrate, the first transistor is located in a first cell, and has a gate coupled to a first conductive segment in a first conductive layer closest to the substrate; The second transistor is located in the second cell and is adjacent to the first cell at the cell boundary, the cell boundary corresponding to at least one of the isolation structure at the edge of the first active region or the power rail in the first conductive layer. One or more lead conductors are located in the first unit; A conductive path, located in the first unit, couples a first pin conductor of the one or more pin conductors to the gate of the first transistor; and in: The conductive path in the first unit includes a second conductive segment in the highest conductive layer of the conductive structure forming the conductive path in the first unit, and The second conductive segment is higher than the highest pin conductor among the one or more pin conductors in the first unit.

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