Chip packaging structure and chip packaging method

Abstract

The invention provides a chip packaging structure and a chip packaging method, and relates to the technical field of semiconductors. The chip packaging structure comprises a first substrate, a second substrate, a chip and anti-reflection glass. The first substrate is provided with a first through hole and a first rewiring layer distributed on the periphery of the first through hole, and the first rewiring layer is connected with a first salient point and a second salient point; the first salient point is closer to the first through hole than the second salient point. The second substrate is provided with a second through hole and third salient points distributed on the periphery of the second through hole; and the third salient point and the second salient point are correspondingly arranged and are connected with each other. The chip is attached to the first substrate and is electrically connected with the first salient points. The anti-reflection glass is arranged on the side, away from the chip, of the first substrate and covers the first through hole. The structure is high in light transmission efficiency, compact in structure, small in packaging size and good in product performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a chip packaging structure and a chip packaging method. Background Technology

[0002] Existing image chip packaging is widely used in semiconductor devices such as image sensors and optical sensors, which have stringent requirements for spatial size and optical performance. The core functionality of these devices highly depends on the stable and efficient transmission of external light to the chip's photosensitive area; therefore, the light transmittance and imaging quality of the packaging structure directly determine the final performance of the product. Improving light transmittance and reducing the size of the packaging structure are pressing technical challenges that the industry needs to address. Summary of the Invention

[0003] The purpose of this invention is to provide a chip packaging structure and chip packaging method that can effectively improve light transmission efficiency, enhance imaging quality, and reduce the size of the packaging structure.

[0004] In a first aspect, the present invention provides a chip packaging structure, comprising: A first substrate; the first substrate has a first through hole and a first redistribution layer distributed around the outer periphery of the first through hole, the first redistribution layer is connected to a first bump and a second bump; the first bump is closer to the first through hole than the second bump. The second substrate; the second substrate is provided with a second through hole and a third protrusion distributed on the outer periphery of the second through hole; the third protrusion and the second protrusion are correspondingly arranged and connected to each other; A chip, which is attached to the first substrate and electrically connected to the first bump; Anti-reflective glass is disposed on the side of the first substrate away from the chip and covers the first through hole.

[0005] In an optional embodiment, the chip is provided with a fourth bump, which is welded to the first bump or connected by a hybrid bonding electrical connection. The second and third bumps are welded together or connected by hybrid bonding.

[0006] In an optional embodiment, the projection of the second through hole onto the first substrate completely covers the first through hole and the first bump.

[0007] In an optional embodiment, the first substrate and the second substrate are both glass substrates.

[0008] In an optional embodiment, the chip has a photosensitive area, which is disposed opposite to the first through hole.

[0009] In an optional embodiment, at least one side of the second substrate is provided with a second redistribution layer, and the side of the second substrate away from the first substrate is provided with a fifth bump, wherein the fifth bump or the third bump is electrically connected to the second redistribution layer.

[0010] In an optional embodiment, the surface of the anti-reflective glass is provided with microlenses and / or color transmission structures.

[0011] In an optional embodiment, a lens structure is also included, which is disposed on the side of the first substrate away from the second substrate and covers the anti-reflective glass.

[0012] Secondly, the present invention provides a chip packaging method, comprising: A second substrate is mounted to a first substrate, and a third bump on the second substrate is electrically connected to a second bump on the first substrate; wherein the first substrate has a first through hole, the second substrate has a second through hole, and the second through hole exposes the first through hole and exposes a first bump located on the outer periphery of the first through hole; An anti-reflective glass is attached to the side of the first substrate away from the second substrate; the anti-reflective glass covers the first through hole; The chip is mounted onto the first substrate; the chip is electrically connected to the first bump.

[0013] In an optional implementation, after the step of mounting the chip to the first substrate, the method further includes: A filler adhesive is formed between the chip and the first substrate.

[0014] The chip packaging structure and chip packaging method provided in this invention have the following advantages: The first substrate has a first through-hole, which effectively improves light transmission efficiency. The second substrate has a second through-hole to avoid obstructing the chip. The chip is mounted on the first substrate and located within the second through-hole, resulting in a compact structure that helps reduce the overall size of the package. In addition, an anti-reflective glass is provided on the other side of the first substrate, which effectively prevents light reflection, improves light transmittance, and thus helps improve image quality. Attached Figure Description

[0015] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0016] Figure 1This is a schematic diagram of a first type of chip packaging structure provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of the first substrate in the chip packaging structure provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the wafer-level structure of the first substrate; Figure 4 This is a partial structural schematic diagram of the first substrate; Figure 5 This is a schematic diagram of the wafer-level structure of the second substrate; Figure 6 This is a partial structural schematic diagram of the second substrate; Figure 7 This is a schematic diagram of the wafer-level bonding structure of the first substrate and the second substrate; Figure 8 This is a schematic diagram of a partial bonding structure between the first substrate and the second substrate; Figure 9 This is a schematic diagram of a second structure of the chip packaging structure provided in an embodiment of the present invention; Figure 10 This is a schematic diagram of a first process for a chip packaging structure provided in an embodiment of the present invention; Figure 11 This is a schematic diagram of a second process for a chip packaging structure provided in an embodiment of the present invention; Figure 12 This is a schematic diagram of a third type of chip packaging structure provided in an embodiment of the present invention.

[0017] Icons: 110-First substrate; 111-First through-hole; 112-First redistribution layer; 113-First bump; 114-Second bump; 120-Second substrate; 121-Second through-hole; 122-Third bump; 123-Fifth bump; 124-Conductive pillar; 126-Conductive adhesive; 130-Chip; 131-Photosensitive area; 132-Fourth bump; 135-Fill adhesive; 140-Anti-reflective glass; 141-First adhesive layer; 142-Microlens; 150-Lens structure; 151-Mounting part; 152-Lens part; 153-Second adhesive layer; 160-Circuit board; 161-Anisotropic conductive film. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0019] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0020] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0021] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this invention is in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention. In addition, the terms "first," "second," "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0022] Furthermore, terms such as "horizontal," "vertical," and "sag" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal relative to "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0023] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0024] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0025] Please combine Figure 1 and Figure 2This invention discloses a chip packaging structure comprising a first substrate 110, a second substrate 120, a chip 130, and an anti-reflective glass 140. The first substrate 110 has a first through-hole 111 and a first redistribution layer 112 distributed around the first through-hole 111. The first redistribution layer 112 connects a first bump 113 and a second bump 114; the first bump 113 is closer to the first through-hole 111 than the second bump 114. The second substrate 120 has a second through-hole 121 and a third bump 122 distributed around the second through-hole 121; the third bump 122 and the second bump 114 are correspondingly arranged and interconnected. The chip 130 is attached to the first substrate 110 and electrically connected to the first bump 113. The anti-reflective glass 140 is disposed on the side of the first substrate 110 away from the chip 130 and covers the first through-hole 111. In this chip packaging structure, the first substrate 110 has a first through-hole 111, which effectively improves light transmission efficiency. The second substrate 120 has a second through-hole 121, which avoids the chip 130. The chip 130 is mounted on the first substrate 110 and located within the second through-hole 121. The structure is compact and helps to reduce the overall size of the packaging structure. In addition, an anti-reflective glass 140 is provided on the other side of the first substrate 110, which can effectively prevent light reflection and improve light transmittance, thereby improving imaging quality.

[0026] Please combine Figures 3 to 8 The first bump 113 and the second bump 114 can be either bump-shaped or pad-shaped; no specific limitation is made here. The third bump 122 and the second bump 114 can be set one-to-one for easy bonding connection.

[0027] Optionally, chip 130 has a fourth bump 132, which is soldered to the first bump 113 or electrically connected using a hybrid bonding method. The second bump 114 and the third bump 122 are soldered to each other or electrically connected using a hybrid bonding method. It should be noted that as long as electrical connection between the second bump 114 and the third bump 122, and electrical connection between the fourth bump 132 and the first bump 113, can be achieved, it is acceptable.

[0028] In this embodiment, the fourth bump 132 and the first bump 113 are preferably bonded by hybrid bonding, ultrasonic welding, or laser welding to avoid contaminating the photosensitive area 131 on the chip 130 and affecting its photosensitivity due to the use of flux welding. Alternatively, in some embodiments, the fourth bump 132 and the first bump 113 can also be connected by bonding adhesive, or electrically connected by a mixture of bonding adhesive and organic acid. In this way, the bonding adhesive can be cured at the bonding high temperature to protect the solder joint.

[0029] Similarly, the third protrusion 122 and the second protrusion 114 can also be electrically connected by methods such as hot pressing, hybrid bonding, ultrasonic welding, laser welding, bonding adhesive, or a mixture of bonding adhesive and organic acid. It should be noted that the bonding adhesive here is conductive adhesive 126, such as NCP or NCF, or it can be anisotropic conductive film, etc., without specific limitations.

[0030] It is understandable that methods such as laser welding, hot pressing, conductive adhesive 126 bonding, or hybrid bonding are easy to operate, have mature processes, and provide reliable connections. Furthermore, these methods create shorter electrical connection paths, resulting in higher transmission efficiency and also helping to reduce packaging size.

[0031] Optionally, the projection of the second via 121 onto the first substrate 110 completely covers the first via 111 and the first bump 113. That is, the size of the second via 121 is larger than the size of the first via 111, and the second via 121 can completely expose the first via 111 and the first bump 113 on its outer periphery. This provides sufficient mounting space for the chip 130, facilitating chip mounting. The diameter of the second via 121 is approximately 2mm to 50mm.

[0032] Optionally, the chip 130 is provided with a photosensitive area 131, which is positioned opposite to the first through hole 111 to facilitate the reception of light.

[0033] Optionally, at least one side of the second substrate 120 is provided with a second redistribution layer (not shown), and the side of the second substrate 120 away from the first substrate 110 is provided with a fifth bump 123, which is electrically connected to the second redistribution layer. It can be understood that a second redistribution layer is provided on either side of the second substrate 120, or redistribution layers are provided on both sides of the second substrate 120. For example, a second redistribution layer is designed on the side of the second substrate 120 closest to the first substrate 110, and the second redistribution layer is electrically connected to the third bump 122. A second redistribution layer is designed on the side of the second substrate 120 away from the first substrate 110, and the second redistribution layer is electrically connected to the fifth bump 123. If a second redistribution layer is provided on both sides of the second substrate 120, the second substrate 120 is also provided with a conductive post 124 penetrating both sides, one end of which is electrically connected to the second redistribution layer on one side, and the other end is electrically connected to the redistribution layer on the other side. The conductive post 124 can be formed by TGV perforation, and the pore size of the TGV perforation is approximately 10um to 50um.

[0034] Optionally, the third bump 122, the fourth bump 132, and the fifth bump 123 can be in the form of bumps or pads; no specific limitation is made here. The first bump 113 can be in a single row or multiple rows, designed according to the connection requirements of the chip 130. Its distribution position, quantity, and shape can be flexibly set according to actual needs. Similarly, the quantity, position, and shape of the second bump 114, the third bump 122, the fourth bump 132, and the fifth bump 123 can also be flexibly set according to actual needs.

[0035] Optionally, the first substrate 110 and the second substrate 120 are both glass substrates. Using a glass substrate offers good light transmittance and high light transmission efficiency, and its coefficient of thermal expansion is better matched to that of the chip 130 and the filter. Furthermore, the relatively flat surface of the glass substrate facilitates the fabrication of the first and second super-wiring layers. In addition, the relatively thin glass substrate also helps to reduce the overall package size. It can be understood that the first super-wiring layer 112 can redistribute the number and position of the first bump 113 and the second bump 114, which is beneficial for achieving high-density connections of the chip 130, improving integration, and enhancing the product's functional versatility. Similarly, the second super-wiring layer can redistribute the number and position of the third bump 122 and the fifth bump 123, facilitating high-density and convenient connections.

[0036] Please combine Figure 9 Optionally, the surface of the anti-reflective glass 140 is provided with microlenses 142 and / or color transmission structures. It should be understood that the microlenses 142 and / or color transmission structures can be provided on any one side or both sides of the anti-reflective glass 140. Each side surface may only have microlenses 142, only have color transmission structures, or have both microlenses 142 and color transmission structures respectively. The anti-reflective glass 140 is bonded and fixed to the first substrate 110 by a first adhesive layer 141.

[0037] It should be noted that the microlens 142 is a microlens array covering the surface of the anti-reflective glass 140, and this microlens array corresponds to the photosensitive area 131 on the chip 130. Each microlens in the array corresponds to a pixel unit, and the microlenses are at the micro-nano scale. Normally, light incident from a camera lens is scattered; the microlenses can "converge" light that might otherwise fall between pixels or outside the photosensitive area 131 to the corresponding pixel photosensitive area 131, reducing light waste and improving light utilization. The microlens array also has a light-gathering effect, allowing each pixel to receive more light, especially in low-light environments, significantly improving the CMOS's light-sensing efficiency and sensitivity, reducing noise, and making the image clearer. Furthermore, the microlens array can more accurately guide light to each photosensitive pixel unit, preventing light from "overflowing" to adjacent pixels and causing crosstalk. The color transmission structure is beneficial for separating monochromatic light, providing a basis for color imaging, and precisely controlling color accuracy and color gamut, achieving color imaging and improving image quality.

[0038] In this embodiment, the method of attaching anti-reflective glass 140 has higher light transmission efficiency, higher light utilization rate, more mature process, controllable cost, and is conducive to improving the yield of the encapsulation structure compared with the structure of coating or pasting anti-reflective film.

[0039] Optionally, the chip packaging structure further includes a lens structure 150, which is disposed on the side of the first substrate 110 away from the second substrate 120 and is covered by an anti-reflective glass 140. In this embodiment, the anti-reflective glass 140 is located in the middle of the first substrate 110. The lens structure 150 includes a mounting portion 151 and a lens portion 152 connected together. The mounting portion 151 of the lens structure 150 is located at the edge of the first substrate 110 and is bonded to the first substrate 110 by a second adhesive layer 153. The mounting portion 151 of the lens structure 150 is arranged around the outer periphery of the anti-reflective glass 140. The lens portion 152 of the lens structure 150 covers the anti-reflective glass 140. Light enters from the lens portion 152, passes sequentially through the anti-reflective glass 140 and the first through-hole 111, and reaches the photosensitive area 131 of the chip 130.

[0040] Please combine Figure 10 This invention also provides a chip packaging method, which mainly includes the following steps: A second substrate 120 is mounted to a first substrate 110, and the third bump 122 of the second substrate 120 and the second bump 114 of the first substrate 110 are electrically connected. The first substrate 110 has a first through-hole 111, and the second substrate 120 has a second through-hole 121, which exposes the first through-hole 111 and the first bump 113 located on the outer periphery of the first through-hole 111. Optionally, the third bump 122 of the second substrate 120 and the second bump 114 of the first substrate 110 are electrically connected by laser welding, ultrasonic welding, hot pressing, or bonding with conductive adhesive 126.

[0041] An anti-reflective glass 140 is attached to the side of the first substrate 110 away from the second substrate 120; the anti-reflective glass 140 covers the first through hole 111. Optionally, the anti-reflective glass 140 is bonded and fixed to the first substrate 110 by a first adhesive layer 141. The first adhesive layer 141 must avoid the first through hole 111.

[0042] Chip 130 is mounted to the first substrate 110; chip 130 is electrically connected to the first bump 113. The fourth bump 132 and the first bump 113 of chip 130 can be electrically connected by laser welding, ultrasonic welding, hot pressing, or bonding with conductive adhesive 126. Figure 10 The electrical connection between chip 130 and the first substrate 110 is achieved using a hybrid bonding method. For example... Figure 11 The electrical connection between the chip 130 and the first substrate 110 is achieved by using hot-pressed conductive adhesive 126.

[0043] A filler adhesive 135 is formed between the chip 130 and the first substrate 110. The filler adhesive 135 protects the bonding structure between the chip 130 and the first substrate 110. It is worth noting that if there is a gap between the first substrate 110 and the second substrate 120, the filler adhesive 135 can also fill the gap between the first substrate 110 and the second substrate 120, thereby protecting the connection structure between the first substrate 110 and the second substrate 120.

[0044] Optionally, a second redistribution layer and a fifth bump 123 are formed on the side of the second substrate 120 away from the first substrate 110. A circuit board 160 is mounted on top of the second substrate 120, and the circuit board 160 and the fifth bump 123 are electrically connected. The electrical connection method includes, but is not limited to, soldering or connection using anisotropic conductive films 161. Figure 1 As shown, the circuit board 160 and the second substrate 120 are connected by bump soldering. Figure 12 As shown, the circuit board 160 and the second substrate 120 are connected by anisotropic conductive film 161.

[0045] In this embodiment, the first substrate 110, the second substrate 120, and the anti-reflective glass 140 are packaged at the wafer level or the panel level. The chip 130 and the lens structure 150 are mounted on the entire substrate, and then it is finally slit into individual products, which helps to improve production efficiency and reduce costs. It is easy to understand that in some embodiments, the chip 130 can be mounted first, then slit into individual chips, and then the lens structure 150 can be mounted. This is not specifically limited here.

[0046] In summary, the chip packaging structure and chip packaging method provided by the embodiments of the present invention have the following beneficial effects, including: The first substrate 110 has a first through-hole 111, which effectively improves light transmission efficiency. The second substrate 120 has a second through-hole 121, which avoids the chip 130. The chip 130 is mounted on the first substrate 110 and located within the second through-hole 121, resulting in a compact structure that helps reduce the overall size of the package. Furthermore, an anti-reflective glass 140 is provided on the other side of the first substrate 110, which effectively prevents light reflection and improves light transmittance, thereby enhancing image quality. The first substrate 110 and the second substrate 120 are made of glass substrates, which are thin, facilitating the design of the first and second super-wiring layers, and improving the connection density of the chip 130. The use of bump soldering effectively reduces the package height, eliminating the need for wire bonding and sealant, thus increasing the connection density of the chip 130 and avoiding the adverse effects of sealant stress. Ultrasonic soldering is also used to prevent contamination of the photosensitive area 131, improving photosensitivity and light transmission efficiency. In addition, the glass substrate has a coefficient of thermal expansion that matches that of silicon, the material of chip 130, which can reduce the stress on chip 130 during the packaging process and improve the overall reliability of the camera and the imaging quality under temperature changes.

[0047] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; any modifications, equivalent substitutions, improvements, etc., should be included within the protection scope of the present invention.

Claims

1. A chip packaging structure, characterized in that, include: A first substrate (110); the first substrate (110) is provided with a first through hole (111) and a first redistribution layer (112) distributed on the outer periphery of the first through hole (111), the first redistribution layer (112) is connected to a first bump (113) and a second bump (114); the first bump (113) is closer to the first through hole (111) than the second bump (114); The second substrate (120) is provided with a second through hole (121) and a third protrusion (122) distributed on the outer periphery of the second through hole (121); the third protrusion (122) and the second protrusion (114) are correspondingly arranged and connected to each other; Chip (130), the chip (130) is attached to the first substrate (110) and electrically connected to the first bump (113); Anti-reflective glass (140) is disposed on the side of the first substrate (110) away from the chip (130) and covers the first through hole (111).

2. The chip packaging structure according to claim 1, characterized in that, The chip (130) is provided with a fourth bump (132), and the fourth bump (132) and the first bump (113) are welded together or connected by hybrid bonding. The second protrusion (114) and the third protrusion (122) are welded or electrically connected by hybrid bonding.

3. The chip packaging structure according to claim 1, characterized in that, The projection of the second through hole (121) onto the first substrate (110) completely covers the first through hole (111) and the first bump (113).

4. The chip packaging structure according to claim 1, characterized in that, The first substrate (110) and the second substrate (120) are respectively made of glass substrates.

5. The chip packaging structure according to claim 1, characterized in that, The chip (130) is provided with a photosensitive area (131), which is disposed opposite to the first through hole (111).

6. The chip packaging structure according to claim 1, characterized in that, The second substrate (120) has a second redistribution layer on at least one side, and a fifth bump (123) is provided on the side of the second substrate (120) away from the first substrate (110). The fifth bump (123) or the third bump (122) is electrically connected to the second redistribution layer.

7. The chip packaging structure according to claim 1, characterized in that, The surface of the anti-reflective glass (140) is provided with microlenses (142) and / or color transmission structures.

8. The chip packaging structure according to any one of claims 1 to 7, characterized in that, It also includes a lens structure (150), which is disposed on the side of the first substrate (110) away from the second substrate (120) and covers the anti-reflective glass (140).

9. A chip packaging method, characterized in that, include: A second substrate (120) is bonded to a first substrate (110), and a third bump (122) of the second substrate (120) and a second bump (114) of the first substrate (110) are electrically connected; wherein the first substrate (110) has a first through hole (111), the second substrate (120) has a second through hole (121), the second through hole (121) exposes the first through hole (111) and exposes a first bump (113) located on the outer periphery of the first through hole (111). An anti-reflective glass (140) is attached to the side of the first substrate (110) away from the second substrate (120); the anti-reflective glass (140) covers the first through hole (111). A chip (130) is mounted to the first substrate (110); the chip (130) is electrically connected to the first bump (113).

10. The chip packaging method according to claim 9, characterized in that, After the step of mounting the chip (130) to the first substrate (110), the method further includes: A filler adhesive (135) is formed between the chip (130) and the first substrate (110).

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