Etching method and semiconductor process equipment

Abstract

The invention relates to the technical field of semiconductor processing, in particular to an etching method and semiconductor processing equipment. The etching method provided by the invention comprises the following steps: providing a substrate which comprises a silicon substrate and a metal column formed in the silicon substrate, introducing etching gas into a process chamber, and ionizing the etching gas to form plasma so as to etch the surface of the silicon substrate and enable the upper surface of the metal column to be higher than the upper surface of the silicon substrate; wherein in the process of etching the surface of the silicon substrate, an ion beam is injected into the process chamber for forming a charge shielding layer on the substrate. The etching method and the semiconductor process equipment provided by the invention can be used in advanced packaging, and especially can be used for relieving the problem of wafer pit abnormity caused by an electrochemical effect in an advanced packaging copper exposing process.

Description

Technical Field

[0001] This invention relates to the field of semiconductor processing technology, and more specifically, to an etching method and semiconductor process equipment. Background Technology

[0002] In the field of semiconductor device manufacturing, Moore's Law is gradually becoming ineffective due to the limitations of physical laws. Utilizing three-dimensional space to stack chips is an important strategy to extend Moore's Law (More than Moore). In 3D ICs, copper interconnects are a common method for realizing three-dimensional chip stacking.

[0003] The main process for realizing copper interconnects includes: first, etching vias on the wafer, filling them with silicon oxide to prevent leakage, then filling them with metallic copper, exposing the tops (protrusions) of the copper pillars, and then protecting the area outside the exposed copper with silicon oxide to prevent leakage. Therefore, exposing the tops (protrusions) of the copper pillars is a crucial step. However, in this step, because copper is already present on the wafer, the etching process will randomly create pits on the wafer surface due to electrochemical effects, such as... Figure 1 As shown, these pits will cause inconvenience to subsequent silicon oxide protection steps, thereby increasing the risk of device leakage. Furthermore, while suppressing electrochemical reactions and increasing physical bombardment can alleviate the aforementioned pitting anomaly, it also leads to the re-deposition of byproducts, making the oxide layer surface rougher, such as... Figure 2 As shown, this is also detrimental to subsequent processes. Summary of the Invention

[0004] The purpose of this invention is to provide an etching method and semiconductor process equipment that can be used to alleviate the problem of abnormal pitting on wafers caused by electrochemical effects in semiconductor fabrication processes.

[0005] In a first aspect, embodiments of the present invention provide an etching method, comprising: A substrate is provided, the substrate comprising a silicon substrate and metal pillars formed therein; Etching gas is introduced into the process chamber, and the etching gas is ionized to form plasma to etch the surface of the silicon substrate, so that the upper surface of the metal pillar is higher than the upper surface of the silicon substrate. During the etching process of the silicon substrate surface, an ion beam is injected into the process chamber to form a charge shielding layer on the substrate.

[0006] In some optional embodiments, the etching gas includes a first inert gas and a reactive gas, and the gas used to generate the ion beam includes a second inert gas; the first inert gas and the second inert gas each include at least one of nitrogen, helium, argon, neon or krypton; the reactive gas includes at least one of carbon fluorine gas or hydrocarbon fluorine gas, and nitrogen fluorine gas.

[0007] In some optional embodiments, the first inert gas and the second inert gas respectively comprise argon and / or helium; the reaction gas comprises fluorocarbon gas and fluoronitrogen gas, wherein the fluorocarbon gas comprises carbon tetrafluoride and the fluoronitrogen gas comprises nitrogen trifluoride.

[0008] In some optional embodiments, the ratio of the fluorocarbon gas to the fluoronitrogen gas is 2:1 to 10:1.

[0009] In some optional embodiments, the ratio of the fluorocarbon gas to the first inert gas is 1:1 to 3:1.

[0010] In some optional embodiments, the etching of the silicon substrate surface includes a pre-etching step and a main etching step. In the pre-etching step, the ratio of the first inert gas to the second inert gas is 1:5 to 1:15. In the main etching step, the ratio of the first inert gas to the second inert gas is 1:1 to 1:5.

[0011] In some optional embodiments, during the pre-etching step, the flow rate of the first inert gas is 10 sccm to 1000 sccm, the flow rate of the fluorocarbon gas and / or fluorocarbon gas is 10 sccm to 1000 sccm, the flow rate of the nitrogen fluoride gas is 0, and the flow rate of the second inert gas is 50 sccm to 5000 sccm.

[0012] In some optional embodiments, during the main etching step, the flow rate of the first inert gas is 100 sccm to 1000 sccm, the flow rate of the fluorocarbon gas and / or fluorocarbon gas is 10 sccm to 1000 sccm, the flow rate of the nitrogen fluoride gas is 10 sccm to 1000 sccm, and the flow rate of the second inert gas is 100 sccm to 5000 sccm.

[0013] In some optional embodiments, the process conditions for etching the silicon substrate surface include: a chamber pressure of 200 mTorr to 250 mTorr, an upper electrode power range of 500 W to 3000 W, and a lower electrode power range of 10 W to 1000 W.

[0014] In some alternative embodiments, etching gas is introduced into the process chamber through an inlet assembly, the inlet assembly including a central inlet group located in the middle of the process chamber and / or an edge inlet group located at the edge of the process chamber; an ion beam is injected into the process chamber through an ion beam device located between the upper surface of the substrate and the inlet assembly.

[0015] In a second aspect, embodiments of the present invention provide a semiconductor process apparatus, comprising: Process chambers; The lower electrode assembly, located within the process chamber, is used to support the substrate; An air intake assembly is used to introduce etching gas into the process chamber. An ion beam device is used to inject an ion beam into the process chamber, and the ion beam device is located between the gas inlet assembly and the lower electrode assembly.

[0016] In some optional embodiments, the ion beam device has at least two grid structures, including a first grid and a second grid. The first grid and the second grid are arranged sequentially along the direction of ion beam output. The first grid is located upstream of the second grid and is configured such that a periodic alternating voltage is applied to the first grid, and the voltage applied to the second grid is 5 V to 10 V higher than the voltage applied to the first grid.

[0017] In some alternative embodiments, the ion beam device is provided with a pitch angle adjustment mechanism, which is adjusted to make the angle of the emitted ion beam range from -30° to +30°.

[0018] In some alternative embodiments, the air intake assembly includes a central air intake group located in the middle of the process chamber and an edge air intake group located at the edge of the process chamber. The edge air intake group is arranged around the central air intake group, and the central air intake group and the edge air intake group are respectively connected to an air source outside the process chamber for selectively introducing etching gas into the process chamber.

[0019] In some alternative embodiments, the semiconductor process apparatus further includes at least one radio frequency (RF) coil disposed around the cavity sidewall of the process chamber, the RF coil being electrically connected to an RF source, and the ion beam device being disposed between the RF coil and the upper surface of the lower electrode assembly.

[0020] The above-described technical solutions adopted in the embodiments of this application can achieve the following beneficial effects: The etching method of this application, during the etching of a silicon substrate to make the upper surface of the metal pillar higher than the upper surface of the silicon substrate, injects an ion beam into the process chamber. This can be used to form a charge shielding layer on the substrate, which can minimize the bombardment effect of plasma on the silicon substrate, thereby reducing the metal ions generated by sputtering during physical etching. This solves the problem of electrochemical corrosion caused by metal ions during silicon etching, that is, it can solve the problem of abnormal pitting on the surface of the silicon substrate caused by electrochemical effects.

[0021] The semiconductor process equipment of this application is equipped with an ion beam device, which can inject an ion beam into the process chamber to form a charge shielding layer on the substrate, thereby solving the problem of abnormal pitting on the surface of the silicon substrate caused by electrochemical effects.

[0022] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0024] Figure 1 These are scanning electron microscope (SEM) images of pit anomalies at different magnifications in related technologies. Figure 2 A schematic diagram (SEM image) illustrating the roughness above the oxide layer caused by the redeposition of strong physical bombardment provided in related technologies. Figure 3 This is a schematic flowchart of an etching method provided in an embodiment of the present invention; Figure 4 A schematic flowchart of another etching method provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the process structure of another etching method provided in an embodiment of the present invention; Figure 6 SEM image of a silicon substrate etched by the etching method provided in this embodiment of the invention; Figure 7 A planar SEM image of a silicon substrate after etching using the etching method provided in this embodiment of the invention; Figure 8 A cross-sectional SEM image of a silicon substrate etched by the etching method provided in this embodiment of the invention; Figure 9This is a schematic diagram of the structure of a semiconductor process equipment provided in an embodiment of the present invention; Figure 10 This is a schematic diagram of the structure of an ion beam device in a semiconductor process equipment provided in an embodiment of the present invention.

[0025] Explanation of reference numerals in the attached figures: 1-Silicon substrate; 101-Silicon deep hole; 2-Silicon oxide (SiO2) layer; 3-Element; 4-Electrode; 5- Patterned photoresist layer; 6- Barrier layer; 7- Metal pillar (copper pillar); 10 - Process chamber; 20 - Intake assembly; 201 - Center intake assembly; 202 - Edge intake assembly; 30 - Radio frequency coil; 40 - Lower electrode assembly; 401 - Chuck; 402 - Lower electrode; 501 - Swing valve; 502 - Bypass valve; 503 - Molecular pump; 504 - Mechanical pump; 60 - Ion beam device; 601 - Ion source cavity; 602 - Two-layer grid structure; 603 - Pitch angle adjustment mechanism. Detailed Implementation

[0026] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings.

[0028] In related technologies, Figure 1 The image shows scanning electron microscope (SEM) images of the pit anomaly at different magnifications, such as... Figure 1 As shown, in advanced packaging exposed copper processes, the presence of copper on the wafer leads to random pits on the wafer surface during etching due to electrochemical effects. These pits complicate subsequent silicon oxide protection steps, increasing the risk of device leakage. Furthermore, Figure 2 This diagram illustrates the roughening of the oxide layer caused by redeposition due to intense physical bombardment. The central cylinder represents copper, surrounded by silicon oxide, and the bottom surface is a silicon substrate. Figure 2 As shown, if the electrochemical reaction is suppressed and physical bombardment is increased, the above-mentioned pitting anomaly can be alleviated, but the redeposition of by-products will occur, making the oxide layer rougher and unfavorable to subsequent processes.

[0029] While related technologies offer some silicon etching methods, they still cannot effectively solve the aforementioned technical problems. For example, related technologies disclose a method for forming structures on a substrate, which discloses the use of gases such as Ar, NF3, CF4, and SF6 for through-hole etching of silicon. However, this method only applies to silicon through-hole etching and does not disclose a silicon etching scheme after copper filling, thus failing to provide any inspiration for solving the aforementioned pitting problem. Similarly, related technologies also disclose a method for manufacturing trench-type silicon carbide MOSFET power devices. This method is used for trench gate formation and also discloses a silicon etching scheme after subsequent metal filling, but it does not provide any inspiration for solving the aforementioned pitting problem. Furthermore, related technologies also disclose a method for forming semiconductor devices. This method pre-connects different redistribution pattern portions of a redistribution pattern, achieving potential balance among the redistribution pattern portions with potential differences, thereby reducing the electrochemical cell effect. After forming a second passivation layer, the connection pattern is then etched. This eliminates the influence of the electrochemical cell effect without affecting the normal function of the semiconductor device, improving product yield and device reliability. However, the method to reduce the electrochemical cell effect by first achieving electrical equilibrium through metal connections before etching is cumbersome and costly. Another example is a deep silicon etching optimization method, which can reduce the complexity and cost of eliminating standing waves and optimize the trench structure of deep silicon etching, thus eliminating the scalloped structure after deep silicon etching, but it cannot prevent the appearance of pit defects. Yet another example is a copper electrode structure and its fabrication method, which uses chemical etching. While this method avoids pit defects, the chemical etching rate is relatively fast, making the process difficult to control. Furthermore, chemical etching is isotropic, making it difficult to achieve a perpendicular morphology.

[0030] In view of this, there is limited research on the aforementioned pitting anomaly in related technologies, and no effective technical means have been provided to solve the problem. The inventors of this application provide an etching method and semiconductor process equipment that can be used in advanced packaging exposed copper processes, and solve the technical problem of pitting anomalies on wafers (or substrates) caused by electrochemical effects. Specific technical solutions are described below.

[0031] refer to Figures 3 to 5 As shown, in some embodiments, an etching method is provided, the method comprising: A substrate is provided, the substrate comprising a silicon substrate and metal pillars formed in the silicon substrate; Etching gas is introduced into the process chamber, causing the etching gas to ionize and form plasma to etch the surface of the silicon substrate, so that the upper surface of the metal pillar is higher than the upper surface of the silicon substrate. In the process of etching the surface of the silicon substrate, an ion beam is injected into the process chamber to form a charge shielding layer on the substrate.

[0032] The inventors of this application have discovered that when metal pillars are present in a silicon substrate, and the surface of the silicon substrate is then etched, pits are easily formed on the surface of the silicon substrate. The principle behind the formation of these pits is as follows: According to Maxwell's equations: Δ E = ρ / ε , where Δ E This represents the electric field gradient, i.e., the electric potential. ρ Indicates charge density; ε Indicates the dielectric constant; The formula for the microscopic surface potential can be derived: V = σ / ε ,in, V Indicates surface potential; σ Represents surface charge density; ε This represents the dielectric constant.

[0033] Therefore, regarding the metal particles on the silicon (Si) surface: σ (Metal) > σ (Si), and, ε (Metal) ε Since the potential of the metal surface is greater than that of the Si surface, the etching rate near the metal particles is greater than the etching rate of the rest of the Si surface. Consequently, due to the electrochemical effect, etching the silicon substrate will randomly produce some pits on the surface of the silicon substrate.

[0034] Therefore, this application primarily aims to avoid or reduce the occurrence of the aforementioned pitting phenomenon, providing an effective solution. In particular, it provides an etching method and semiconductor process equipment to avoid or reduce the impact of pitting on product yield and device reliability during the etching process of etching a silicon substrate containing metal pillars to make the metal pillars protrude. Specifically: The etching method provided in this application first provides a substrate with metal pillars formed in a silicon substrate, and then etches the surface of the silicon substrate so that the upper surface of the metal pillars is higher than the upper surface of the silicon substrate, that is, the top of the metal pillars is exposed, making the metal pillars protrude from the silicon substrate. During the etching process of the silicon substrate surface, an etching gas is introduced into the process chamber, causing the etching gas to ionize and form plasma. The plasma is used to etch the silicon substrate surface. At the same time, an ion beam is injected into the process chamber, which can be used to form a charge shielding layer on the substrate. As can be seen from the above mechanism, the etching rate near the metal particles is greater than the etching rate of the rest of the Si surface, which easily leads to pitting. Based on this, the inventors of this application introduce an ion beam into the process chamber during the etching process, for example, by emitting an ion beam (such as Ar) towards the center of the process chamber using an ion beam device. +The plasma can form a positively charged charge shielding layer on the substrate, which can minimize the bombardment of the silicon substrate by the plasma, thereby reducing the metal ions (such as copper ions) sputtered by physical etching. This solves the problem of electrochemical corrosion caused by metal ions during silicon etching, and also solves the problem of pitting abnormalities on the surface of the silicon substrate caused by electrochemical effects.

[0035] In some specific embodiments, the provided etching method involves plasma etching of the silicon substrate surface using an etching gas, while simultaneously injecting an ion beam into the process chamber. The etching gas includes a first inert gas and a reactive gas, and the gas used to generate the ion beam includes a second inert gas. The first and second inert gases each include at least one of nitrogen, helium, argon, neon, or krypton; the reactive gas includes at least one of a fluorocarbon gas or a hydrocarbon gas, and a nitrogen-fluorine gas.

[0036] As an example, the first inert gas in the etching gas can be nitrogen (N2), helium (He), argon (Ar), neon (Ne), krypton (Kr), or any combination of two or more of these inert gases. Preferably, the first inert gas includes one or more of N2, He, or Ar. More preferably, the first inert gas is selected as He or Ar. In this way, physical etching can be achieved, and the structure to be etched can be protected or over-etching can be avoided. The etching method will be described below mainly using Ar as the first inert gas as an example.

[0037] In this embodiment, a second inert gas can be used to form an ion beam. The second inert gas can be of the same or different type as the first inert gas, but preferably the same.

[0038] As an example, the second inert gas can be nitrogen (N2), helium (He), argon (Ar), neon (Ne), krypton (Kr), or any combination of two or more of these inert gases. Preferably, the second inert gas includes one or more of N2, He, or Ar. More preferably, the second inert gas is selected as He or Ar. The etching method will be described below mainly using Ar as the second inert gas as an example.

[0039] In the aforementioned etching gases, the reactant gas includes at least one of a fluorocarbon gas or a fluorocarbon gas, and a fluorine-nitrogen gas. For example, the reactant gas includes a fluorocarbon gas and a fluorine-nitrogen gas, or a fluorocarbon gas and a fluorine-nitrogen gas, or a fluorocarbon gas, a fluorocarbon gas, and a fluorine-nitrogen gas. Optionally, the fluorocarbon gas includes one or more of carbon tetrafluoride (CF4), hexafluoroethane (C2F6), hexafluorobutadiene (C4F6), octafluorocyclobutane (C4F8), or octafluorocyclopentene (C5F8). Optionally, the fluorocarbon gas includes one or more of trifluoromethane (CHF3), difluoromethane (CH2F2), or monofluoromethane (CH3F). Optionally, the fluorine-nitrogen gas includes nitrogen trifluoride (NF3).

[0040] Preferably, in this embodiment, the reaction gas includes carbon fluoride gas and nitrogen fluoride gas, wherein the carbon fluoride gas includes carbon tetrafluoride and the nitrogen fluoride gas includes nitrogen trifluoride; that is, the reaction gas in this embodiment preferably uses CF4 and NF3.

[0041] Typically, etching gases CF4 and NF3 are used to etch silicon oxide; that is, CF4 and NF3 are primarily used for etching silicon oxide, such as in RPS cleaning systems for removing silicon oxide deposits from chamber sidewalls. However, the inventors of this application have creatively incorporated CF4 and NF3 into the etching gases used for etching silicon substrates. For example, using CF4 and NF3 as etching gases in exposed copper silicon etching processes helps alleviate the aforementioned pitting problem. This is because, as the pit formation mechanism described above indicates, pit formation mainly results from electrochemical reactions induced by metal particles. The combination of CF4, NF3, and a first inert gas such as Ar helps to change the potential and prevent electrochemical reactions, thereby reducing or avoiding the occurrence of pits.

[0042] It should be noted that the etching gas used in this application does not contain sulfur-containing gases such as sulfur hexafluoride (SF6) or gases such as oxygen (O2). This is because if SF6 is used in the etching gas, the sulfur will react with the metal (such as Cu), causing changes in the morphology of the metal pillars (such as Cu pillars), affecting the product yield or performance. Furthermore, if O2 is used in the inert gas, such as replacing Ar with O2, the electrochemical corrosion process will be aggravated, thus worsening the pitting problem and further exacerbating the adverse effects.

[0043] Specifically, as mentioned earlier, according to Maxwell's equations: Δ E = ρ / ε Furthermore, the formula for the microscopic surface potential can be derived: V = σ / ε ,in, V Indicates surface potential; σ Represents surface charge density; ε This represents the dielectric constant. For metal particles on the surface of silicon (Si): σ (Metal) > σ (Si), and, ε (Metal) ε (Si), meaning the potential of the metal surface is greater than the potential of the Si surface, therefore, the etching rate near the metal particles is greater than the etching rate of the rest of the Si surface. The mechanism by which replacing Ar with O2 exacerbates the electrochemical corrosion process and worsens the pitting problem is as follows: CF4→{CF2} n ↓+F-↑+F*↑ {CF2} n +O2→CO2↑ F- + F* + Si → SiF4↑ F- ions accumulate towards the metal particles, causing the etching rate near the metal particles to be higher than the etching rate of the rest of the Si surface. Meanwhile, O2 damages the protective film of CF, forming pits at the metal particles and exacerbating the pitting problem. Therefore, the etching gas in this application cannot contain gases such as O2 or SF6.

[0044] Therefore, in this embodiment, the etching gas uses a combination of CF4, NF3 and Ar to etch the silicon substrate, especially for silicon etching with exposed copper, which helps to reduce or avoid the occurrence of pits, thereby improving product yield and ensuring product performance.

[0045] In some embodiments, the ratio of fluorocarbon gas to fluoronitrogen gas is 2:1 to 10:1; as examples, the ratio of fluorocarbon gas to fluoronitrogen gas is 2:1, 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, 9:1, 10:1, etc. For example, the ratio of CF4 to NF3 is between 2:1 and 10:1.

[0046] This application controls the ratio of fluorocarbon gas and fluorine nitrogen gas within a suitable range, such as 2:1 to 10:1, to effectively utilize the respective functions of each gas and keep the content of fluorine nitrogen gas, such as NF3, within a suitable range, which helps to reduce or avoid the formation of pits. If the NF3 content is too low, chemical etching weakens, and the protective film of CF encapsulates the metal to form a micromask. The physical bombardment of Ar alone cannot remove this micromask, resulting in abnormalities such as protrusions. Therefore, it is also necessary to avoid the NF3 content being too low. If the NF3 content is too high, it will further aggravate the pit problem. The mechanism is similar to the above mechanism, that is, too much NF3 will destroy the protective film of CF, and NF3 will not form a protective film like CF4, thus making the etching rate near the metal higher than the etching rate of the rest of the Si surface, causing pit formation. The mechanism by which the pit problem is further aggravated by the excessive NF3 content is as follows: NF3→F-↑+F*↑ F- + F* + Si → SiF4↑ In some embodiments, the ratio of fluorocarbon gas to the first inert gas is 1:1 to 3:1; as examples, the ratio of fluorocarbon gas to the first inert gas is 1:1, 1:1, 3:1, etc. For example, the ratio of CF4 to Ar is between 1:1 and 3:1.

[0047] This application helps to reduce or avoid the occurrence of pits by controlling the ratio of fluorocarbon gas and the first inert gas within a suitable range, such as 1:1 to 3:1, and also helps to improve etching efficiency and ensure product yield.

[0048] In some embodiments, etching the silicon substrate surface includes a pre-etching step and a main etching step. In the pre-etching step, the ratio of the first inert gas to the second inert gas is 1:5 to 1:15; in the main etching step, the ratio of the first inert gas to the second inert gas is 1:1 to 1:5. As an example, in the pre-etching step, the ratio of the first inert gas to the second inert gas is 1:5, 1:6, 1:8, 1:10, 1:15, etc.; in the main etching step, the ratio of the first inert gas to the second inert gas is 1:1, 1:2, 1:3, 1:4, 1:5, etc.

[0049] It should be noted that the ratio of fluorocarbon gas to fluorine nitrogen gas is 2:1 to 10:1, and the ratio of fluorocarbon gas to the first inert gas is 1:1 to 3:1; these ratios refer to the main etching step. In the pre-etching step, a first inert gas such as Ar, a fluorocarbon gas such as CH4, and an ion beam (such as Ar) can be introduced. + (Ions); In the main etching step, a first inert gas such as Ar, a carbon-fluorine gas such as CH4, a nitrogen-fluorine gas such as NH3, and an ion beam (such as Ar) can be introduced. + ion).

[0050] By introducing an ion beam in the pre-etching step, an initial ion beam can be constructed, serving as a transition, before the ion beam (such as Ar) is formally introduced in the main etching step. + (Ions), and simultaneously input etching gases such as CF4, NF3 and Ar gas combinations, which can reduce or avoid the occurrence of pits, improve product yield and ensure product performance.

[0051] It should be understood that the aforementioned metal pillar can be a copper pillar, but is not limited to it. Other metals with the same or similar mechanisms of action can also be applied to this invention. This document mainly uses a copper pillar as an example for illustration, but this should not be considered a limitation of this application.

[0052] refer to Figures 4 to 5As shown, in some specific embodiments, the etching method of this application is applied in the exposed copper process of advanced packaging, and may specifically include the following steps: S10. Provide a substrate, i.e., provide the structure to be etched, the substrate including a silicon substrate 1 and metal pillars 7 formed in the silicon substrate. The metal pillars 7 can be, for example, copper pillars.

[0053] S20. Etch the surface of the silicon substrate 1 so that the upper surface of the metal pillar 7 is higher than the upper surface of the silicon substrate 1. This step, silicon etching arrangement, is the main improvement of this application. It involves etching the silicon substrate 1 in the presence of metal pillars 7, such as copper pillars, so that the metal pillars 7 protrude from the silicon substrate 1.

[0054] S30, post-processing, such as depositing a silicon oxide protective layer, etc.

[0055] In a specific example of the present invention, step S20, etching the surface of the silicon substrate, specifically includes the following steps: S201, Stabilization Step.

[0056] During the stabilization step S201, the chamber pressure is 1 mTorr to 100 mTorr, preferably 10 mTorr to 60 mTorr, and more preferably 50 mTorr; the upper electrode power is zero, the lower electrode power is zero, the flow rate of the first inert gas (such as Ar) is 1 sccm to 1000 sccm, preferably 10 sccm to 200 sccm, and more preferably 20 sccm; the flow rate of the reaction gas (such as fluorocarbon gas CF4) is 10 sccm to 1000 sccm, preferably 100 sccm to 300 sccm, and more preferably 200 sccm; the process duration is 1 s to 8 s, preferably 5 s to 6 s, and more preferably 5 s.

[0057] S202, Qihui Step.

[0058] In step S202, the ignition step, the chamber pressure is 1 mTorr to 100 mTorr, preferably 10 mTorr to 60 mTorr, and more preferably 50 mTorr; the power at the center of the upper electrode is 100 W to 10000 W, preferably 800 W to 1500 W, and more preferably 1000 W; the power at the edge of the upper electrode is 100 W to 10000 W, preferably 800 W to 1500 W, and more preferably 1000 W; the power of the lower electrode is zero; the flow rate of the first inert gas (e.g., Ar) is 1 sccm to 1000 sccm, preferably 10 sccm to 200 sccm, and more preferably 20 sccm; the flow rate of the reaction gas (e.g., fluorine-carbon gas CF4) is 10 sccm to 1000 sccm, preferably 100 sccm to 300 sccm, and more preferably 200 sccm; the process duration is 1 s to 8 s, preferably 5 s to 6 s. s, further preferably 5 s.

[0059] S203, Breakthrough Step.

[0060] In the process of step S203, the chamber pressure is 1 mTorr to 100 mTorr, preferably 10 mTorr to 60 mTorr, and more preferably 50 mTorr; the power at the center of the upper electrode is 100 W to 10000 W, preferably 1000 W to 2000 W, and more preferably 1500 W; the power at the edge of the upper electrode is 100 W to 10000 W, preferably 1000 W to 3000 W, and more preferably 2800 W; the power of the lower electrode is 10 W to 500 W, preferably 30 W to 100 W, and more preferably 50 W; the flow rate of the first inert gas (e.g., Ar) is 1 sccm to 1000 sccm, preferably 10 sccm to 200 sccm, and more preferably 20 sccm; the flow rate of the reaction gas (e.g., CF4) is 10 sccm to 1000 sccm, preferably 100 sccm to 300 sccm. The process time is 60 s to 240 s, preferably 100 s to 180 s, and even more preferably 120 s.

[0061] It should be understood that the above steps S201 stabilization step, S202 ignition step, and S203 breakthrough step can be selectively adjusted according to the specific circumstances, and no further restrictions are imposed on them.

[0062] S204, Pre-etching step.

[0063] During the pre-etching step S204, the chamber pressure is 1 mTorr to 100 mTorr, preferably 10 mTorr to 60 mTorr, and more preferably 50 mTorr; the power at the center of the upper electrode is 100 W to 10000 W, preferably 1000 W to 2000 W, and more preferably 1500 W; the power at the edge of the upper electrode is 100 W to 10000 W, preferably 1000 W to 3000 W, and more preferably 2800 W; and the power of the lower electrode is 10 W to 500 W, preferably 30 W to 100 W, and more preferably 50 W.

[0064] In the embodiments of this application, a pre-etching step is set before the main etching step, which can serve as a transition. For example, an ion beam can be introduced in the pre-etching step to initially construct the ion beam, and then the ion beam (such as Ar) can be formally introduced in the main etching step. + (Ions), and simultaneously input etching gases such as CF4, NF3 and Ar gas combinations, which can reduce or avoid the occurrence of pits, improve product yield and ensure product performance.

[0065] In some embodiments, in step S204, the flow rate of the first inert gas (e.g., Ar) is 10 sccm to 1000 sccm, preferably 10 sccm to 200 sccm, and more preferably 20 sccm; the flow rate of the second inert gas (e.g., Ar) used to generate the ion beam is 50 sccm to 5000 sccm, preferably 100 sccm to 1000 sccm, and more preferably 200 sccm; and the flow rate of the reactive gas (e.g., fluorocarbon gas CF4) is 10 sccm to 1000 sccm, preferably 100 sccm to 300 sccm, and more preferably 200 sccm.

[0066] In step S204, the pre-etching step, the process time is 2 s to 10 s, preferably 3 s to 8 s, and more preferably 5 s.

[0067] S205, Main etching step.

[0068] During the main etching step S205, the chamber pressure is 200 mTorr to 250 mTorr, preferably 220 mTorr to 240 mTorr, and more preferably 230 mTorr; the power at the center of the upper electrode is 500 W to 3000 W, preferably 600 W to 3000 W, and more preferably 1500 W; the power at the edge of the upper electrode is 500 W to 3000 W, preferably 1000 W to 3000 W, and more preferably 2800 W; and the power of the lower electrode is 10 W to 1000 W, preferably 100 W to 600 W, and more preferably 500 W.

[0069] In this embodiment, a higher chamber pressure is required in the main etching step, such as at least 160 mTorr, preferably above 200 mTorr. If the chamber pressure is lower than this, the pitting problem will be completely aggravated. That is, if the chamber pressure is too low, the pitting problem will be further aggravated.

[0070] Furthermore, within the aforementioned chamber pressure range, the use of the aforementioned upper electrode power and lower electrode power ensures etching efficiency and quality during the etching process.

[0071] In some embodiments, in the main etching step S205, the flow rate of the first inert gas (such as Ar) is 100 sccm to 1000 sccm, preferably 200 sccm to 500 sccm, and more preferably 200 sccm; the flow rate of the second inert gas (such as Ar) used to generate the ion beam is 100 sccm to 5000 sccm, preferably 100 sccm to 1000 sccm, and more preferably 200 sccm; the flow rate of the reactive gas (such as fluorine-carbon gas CF4) is 10 sccm to 1000 sccm, preferably 100 sccm to 500 sccm, and more preferably 350 sccm; the flow rate of the reactive gas (such as fluorine-nitrogen gas NF3) is 10 sccm to 1000 sccm, preferably 100 sccm to 300 sccm, and more preferably 100 sccm. Of course, the present invention is not limited to this. In practical applications, the gas flow rates of inert gas and reactant gas can be adjusted according to requirements, as long as the ratio of the two is within a suitable range.

[0072] It should be noted that the inlet flow rate of each etching gas in this application refers to the sum of the total inlet flow rates of all gases, that is, the sum of the center inlet flow rate and the edge inlet flow rate. As an example, the flow rate of the aforementioned reactive gas, CF4, is 350 sccm, which includes the sum of the center inlet flow rate and the edge inlet flow rate. This 350 sccm flow rate can be 200 sccm from the center and 150 sccm from the edge, or it can be 350 sccm entirely from the center with no inlet flow at the edge.

[0073] In this embodiment, the ratio of fluorocarbon gas to fluoronitrogen gas, such as CF4 and NF3, is controlled between 2:1 and 10:1. Within this range, adjusting the total airflow rate, such as reducing the total airflow rate of the main etching step to 80%, does not result in observed pitting problems. That is, adjusting the total airflow rate while ensuring that the CF4 and NF3 ratio is controlled between 2:1 and 10:1 can still reduce or avoid the occurrence of pits. However, if this range is exceeded, such as a CF4 and NF3 ratio less than 2:1 or greater than 10:1, the pitting problem will worsen. As mentioned earlier, if the NF3 content is too low, chemical etching weakens, and the protective film of CF encapsulates the metal to form a micromask. The physical bombardment of Ar alone cannot remove this micromask, leading to abnormalities such as protrusions. Therefore, it is necessary to avoid an excessively low NF3 content. If the NF3 content is too high, it will further aggravate the pitting problem. The mechanism is similar to the above mechanism, that is, too much NF3 will destroy the protective film of CF, and NF3 will not form a protective film like CF4, thus making the etching rate near the metal higher than the etching rate of the rest of the Si surface, resulting in the formation of pits.

[0074] In this embodiment, the ratio of fluorocarbon gas to the first inert gas, such as CF4 and Ar, is controlled between 1:1 and 3:1. This helps to reduce or avoid the occurrence of pits, improves etching efficiency, and ensures product yield.

[0075] Furthermore, in the main etching step S205, the substrate coolant temperature range is -15 ℃ to 40 ℃, such as 20 ℃, 30 ℃, or 40 ℃. Within this temperature range, a good etching effect can be ensured, and the occurrence of pits can be reduced or avoided. That is, through observation, it was found that no worsening of the pit problem was observed when cooling within this temperature range.

[0076] In the main etching step S205, the process time is 120 s to 500 s, preferably 240 s to 480 s, and more preferably 360 s.

[0077] S206, Desorption step.

[0078] In step S206, the desorption process, the chamber pressure is 1 mTorr to 100 mTorr, preferably 10 mTorr to 60 mTorr, and more preferably 50 mTorr; the power at the center of the upper electrode is 100 W to 1000 W, preferably 200 W to 600 W, and more preferably 500 W; the power at the edge of the upper electrode is 100 W to 1000 W, preferably 200 W to 600 W, and more preferably 500 W; the power of the lower electrode is zero; the flow rate of the first inert gas (e.g., Ar) is 1 sccm to 1000 sccm, preferably 50 sccm to 500 sccm, and more preferably 200 sccm; the flow rate of the reaction gas is zero; and the process time is 1 s to 10 s, preferably 2 s to 8 s, and more preferably 5 s.

[0079] In step S20 of this application, which involves etching the silicon substrate surface, the cavity hardware has a relatively small impact on the pitting problem of the present invention. For example, reducing the ceramic focusing ring from 6 mm to 1.5 mm has no effect on the effect of the present invention. If the ceramic focusing ring is replaced with a quartz focusing ring, although the pitting abnormality can be reduced, CF4 can etch quartz, making the focusing ring easy to be corroded, which will reduce the mass production capability of the cavity.

[0080] Furthermore, in this embodiment, either inductively coupled plasma (ICP) etching or capacitively coupled plasma (CCP) etching can be performed on the structure to be etched. In an ICP device, energy from a radio frequency (RF) power supply is introduced into the reaction chamber via an inductor coil in the form of magnetic field coupling, thereby generating plasma for etching. In a CCP device, RF or DC power applied to the electrodes is capacitively coupled to form plasma within the reaction chamber, achieving etching.

[0081] refer to Figure 5 As shown, optionally, in some specific examples, step S10 above, which provides a substrate, i.e., provides the structure to be etched, may specifically include the following steps: S110. Pre-treatment of silicon substrate 1. For example, in step S110, chemical mechanical polishing (CMP) is performed to treat the surface of silicon substrate 1. Optionally, it may include elements 3, silicon oxide (SiO2) layer 2, electrodes 4, etc.

[0082] S120. Photoresist coating and development are performed on the surface of silicon substrate 1. For example, in step S120, photoresist is coated on the silicon substrate, and then exposure and development are performed to form a patterned photoresist layer 5 on the surface of the silicon substrate.

[0083] S130. Perform Bosch etching on the silicon substrate 1, that is, perform silicon through-hole etching to etch a silicon deep hole 101 on the silicon substrate.

[0084] S140. A silicon oxide (SiO2) layer 2 is formed on the surface of the silicon substrate 1. For example, the SiO2 layer 2 is formed on the surface of the silicon substrate by plasma-enhanced chemical vapor deposition (PECVD), and the SiO2 layer 2 covers the inner wall of the silicon deep hole 101.

[0085] S150. Perform selective etching. For example, etch the bottom wall of the silicon deep hole 101 to remove the SiO2 layer 2 on the bottom wall of the silicon deep hole, thereby exposing the electrode 4 in the silicon substrate 1.

[0086] S160, Forming a barrier layer 6. For example, a titanium nitride (TiN) layer is formed on the surface of the silicon substrate 1 as a barrier layer 6. This barrier layer 6 covers the SiO2 layer, as well as the SiO2 layer 2 on the inner wall of the silicon deep hole 101 and the electrode 4 on the bottom wall of the silicon deep hole 101.

[0087] S170. Perform a metal filling process. For example, perform a copper filling (Cu) process to fill copper into the aforementioned silicon deep holes, forming copper pillars in the silicon deep holes.

[0088] S180. Perform chemical mechanical polishing (CMP) treatment. For example, remove the barrier layer 6 and SiO2 layer 2 on the upper surface of the silicon substrate 1 by CMP treatment, so that the upper surface of the metal pillar 7, such as the copper pillar, in the silicon deep hole 101 is flush with the upper surface of the silicon substrate 1.

[0089] It should be understood that the above steps S110 to S180 are merely exemplary and this application does not impose any limitations on them.

[0090] Continue to refer to Figure 5 As shown, optionally, in some specific examples, the post-processing of step S30 above may specifically include the following steps: S310, A silicon oxide (SiO2) layer 2 is formed on the surface of the silicon substrate 1. For example, the SiO2 layer 2 is formed on the surface of the silicon substrate by deposition, and the SiO2 layer 2 covers the surface of the silicon substrate and the surface of the metal pillar 7, such as the copper pillar.

[0091] S320, Perform photolithography. For example, form a patterned photoresist layer 5 on the SiO2 layer mentioned above.

[0092] S330, Etching the SiO2 layer. Using this patterned photoresist layer as a mask, etch the SiO2 layer.

[0093] It should be understood that steps S310 to S330 described above are merely exemplary and are not intended to limit the scope of this application.

[0094] like Figure 6 As shown in the SEM image, the silicon substrate etched using the etching method of this invention shows no pitting. Furthermore, as... Figure 7 and Figure 8 As shown in the SEM images of the plane and cross-section, no abnormal phenomenon of pitting was observed, indicating that the method of the present invention can effectively alleviate the pitting problem.

[0095] refer to Figures 9 to 10 As shown, correspondingly, in some embodiments, a semiconductor process apparatus is provided, comprising: Process chamber 10; The lower electrode assembly 40 is located inside the process chamber 10 and is used to support the substrate. The air intake assembly 20 is used to introduce etching gas into the process chamber 10; An ion beam device 60 is used to inject an ion beam into the process chamber 10. The ion beam device 60 is located between the inlet assembly 20 and the lower electrode assembly 40.

[0096] It should be understood that the semiconductor process equipment of this application can be used in the aforementioned etching method, and is based on the same inventive concept as the aforementioned etching method. Therefore, it has at least all the features and advantages of the aforementioned etching method, which will not be repeated here.

[0097] In this embodiment, the provided semiconductor process equipment includes a process chamber 10, which is a process chamber that can be evacuated, and a plasma for processing a substrate (or wafer) is formed inside the process chamber 10.

[0098] The semiconductor process apparatus of this embodiment may further include an inlet assembly 20, an upper electrode assembly, a lower electrode assembly 40, and a controller, etc.; wherein, the controller includes at least one processor and at least one memory, the memory storing a computer program, and when the computer program is executed by the processor, it implements the aforementioned etching method. As an example, in the semiconductor process apparatus, the controller is used to control the gas flow rate and chamber pressure of the process chamber 10, as well as the upper radio frequency power output by the upper radio frequency power supply and the lower radio frequency power output by the lower radio frequency power supply, etc., and the controller includes a processor and a memory, the memory storing a computer program, and when the computer program is executed by the processor, it implements the etching method disclosed in any of the above embodiments.

[0099] In this semiconductor process equipment, the air intake assembly 20 is used to introduce etching gas and the like into the process chamber 10. In some embodiments, the air intake assembly 20 includes a central air intake group 201 located in the middle of the process chamber 10 and an edge air intake group 202 located at the edge of the process chamber 10. The edge air intake group 202 is arranged around the central air intake group 201, and the central air intake group 201 and the edge air intake group 202 are respectively connected to an air source outside the process chamber 10 for selectively introducing etching gas into the process chamber 10.

[0100] In this embodiment, the air intake assembly 20 is provided with a central air intake group 201 and an edge air intake group 202. The central air intake group 201 and the edge air intake group 202 are respectively connected to an external air source, enabling multiple air intakes. For example, when introducing etching gas into the process chamber 10, the etching gas can be introduced into the process chamber 10 through the central air intake group 201, or through the edge air intake group 202, or simultaneously through both the central air intake group 201 and the edge air intake group 202. This allows for more air intake adjustment methods, facilitating the achievement of uniform etching and other plasma distribution requirements that meet specific semiconductor processes.

[0101] In this semiconductor process equipment, optionally, the lower electrode assembly 40 may include a chuck 401 for supporting a substrate or wafer, and may also include a lower electrode 402, an edge ring, and other structures. The lower electrode assembly 40 is located at the bottom of the process chamber 10, and is used to support the substrate or wafer to be processed while controlling factors affecting substrate or wafer processing, such as substrate or wafer temperature and electric field. The substrate or wafer to be processed can be placed on the chuck 401. The lower electrode assembly 40 has a lower electrode 402 and applies radio frequency power to it; for example, at least one radio frequency power supply can be applied to the lower electrode 402, thereby forming a radio frequency electric field within the process chamber 10, which generates plasma from the introduced process gas.

[0102] In this semiconductor process equipment, the upper electrode assembly and the lower electrode assembly 40 work together to excite the process gas, generate plasma, and complete the process processing. Optionally, the upper electrode assembly may include an RF coil 30, an upper RF power supply, and an upper matching unit, etc.

[0103] In some embodiments, the upper electrode assembly of the semiconductor process equipment includes at least one radio frequency coil 30. For example, in this embodiment, multiple radio frequency coils 30 are provided, and the multiple radio frequency coils 30 are arranged around the cavity sidewall of the process chamber 10. The radio frequency coils 30 are used to be electrically connected to a radio frequency source. The ion beam device 60 is disposed between the radio frequency coils 30 and the upper surface of the chuck 401 of the lower electrode assembly 40.

[0104] Optionally, an exhaust zone is provided at a suitable location within the semiconductor process equipment. This exhaust zone is connected to an external exhaust device (e.g., a vacuum pump) to extract used reaction gases and byproduct gases from the processing area during the process, establishing appropriate pressure within the processing area through gas flow. As an example, the exhaust device or vacuum device includes at least one valve, such as a swing valve 501 and a bypass valve 502; it may also include at least one vacuum pump, such as a molecular pump 503 and a mechanical pump 504, etc., without further limitation.

[0105] It should be noted that the specific structure and working principle of the air intake assembly 20, upper electrode assembly, lower electrode assembly 40, controller, exhaust device, etc. in the semiconductor process equipment can be referred to the relevant technology, and will not be elaborated here.

[0106] In this embodiment, an ion beam device 60 is introduced into the semiconductor process equipment. Optionally, the ion beam device 60 can be an ion gun device. The outlet of the ion beam device 60 is located between the radio frequency coil 30 and the lower electrode assembly 40. That is, the outlet of the ion beam device 60 is located between the substrate or wafer surface of the lower electrode assembly 40 and the radio frequency coil 30. This ensures the stability of the ion beam (such as Ar). + After the ion beam is incident, it can interact with the sheath layer on the etched surface.

[0107] Therefore, in this embodiment of the application, an ion beam device 60 is introduced around the process chamber 10, especially above the substrate or wafer (between the upper surface of the substrate or wafer and the RF coil 30), to emit an ion beam (such as Ar) toward the center of the process chamber 10. + The plasma can form a positively charged shielding layer on top of the wafer, minimizing the bombardment of the wafer by the plasma. This reduces the amount of metal ions such as copper ions generated by physical etching, thus solving the electrochemical corrosion problem caused by metal ions such as copper ions on silicon etching, and thus solving the pitting problem mentioned above.

[0108] refer to Figure 10 As shown, in some embodiments, the ion beam device 60 is provided with at least two layers of grid structure 602, which includes a first grid layer and a second grid layer. The first grid layer and the second grid layer are arranged sequentially along the direction of ion beam output. The first grid layer is located upstream of the second grid layer and is configured such that the first grid layer is supplied with a periodic alternating voltage, and the voltage supplied to the second grid layer is 5 V to 10 V higher than the voltage supplied to the first grid layer.

[0109] As an example, the ion beam device 60 can employ a double-layer grid structure for extracting the ion beam. Optionally, the ion beam device 60 may include an ion source cavity 601, an ionization component, a grid structure, etc., wherein the ion source cavity 601 may have a process gas inlet and an ionization outlet, and the ionization outlet may communicate with the interior of the process chamber 10; the ionization component is disposed within the ion source cavity 601 to generate ionization of the process gas. The aforementioned at least two-layer grid structure 602, such as the double-layer grid structure, may include a first grid and a second grid. Along the direction of ion beam output, the first grid and the second grid are spaced apart at the ionization outlet, and the first grid is located upstream of the second grid. It is configured such that a periodic alternating voltage is applied to the first grid, and the voltage applied to the second grid is 5 V to 10 V higher than the voltage applied to the first grid.

[0110] In this embodiment, by connecting the first grid layer to a periodic alternating voltage, the uniformity of the plasma can be improved. The second grid layer is designed with a complementary potential with a phase difference of 180°, which is 5 V to 10 V higher than the voltage of the first grid layer, thus improving the collimation of positive ions. Some electrons in the ion beam are blocked and separated by the grid, resulting in Ar in the emitted ion beam. + The proportion of ions increases.

[0111] In some embodiments, the ion beam device 60 is provided with a pitch angle adjustment mechanism 603, which adjusts the pitch angle adjustment mechanism 603 to make the angle of the emitted ion beam range from -30° to +30°.

[0112] As an example, the pitch angle adjustment mechanism 603 can adopt a telescopic structure, such as adjusting the pitch angle through a telescopic bracket, so that the angle of the emitted ion beam is adjustable from -30° to +30°. This can avoid the difference in plasma flow field during different processes, which could affect the injected Ar. + The ion beam is deflected and cannot reach the preset position. During the etching process, the incident angle of the symmetrically distributed ion beam is adjusted to ensure that the Ar... + The shielding layer formed is uniformly distributed radially on the wafer surface.

[0113] It should be noted that the specific implementation of the functions of the ion source cavity 601, ionization component, or other parts such as the driving component in the ion beam device 60 provided in this embodiment is not the core inventive point of this application, and those skilled in the art can implement it using existing technology, so it will not be described in detail here.

[0114] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An etching method, characterized by, Comprising: providing a substrate, the substrate comprising a silicon substrate and a metal pillar formed in the silicon substrate; introducing an etching gas into a process chamber, ionizing the etching gas to form a plasma to etch a surface of the silicon substrate such that an upper surface of the metal pillar is higher than an upper surface of the silicon substrate; wherein during the etching of the surface of the silicon substrate, an ion beam is injected into the process chamber for forming a charge shielding layer on the substrate.

2. The etching method according to claim 1, wherein the etching gas comprises a first inert gas and a reactive gas, and a gas used for generating the ion beam comprises a second inert gas; the first inert gas and the second inert gas each comprise at least one of nitrogen, helium, argon, neon or krypton; the reactive gas comprises at least one of a fluorocarbon gas or a hydrofluorocarbon gas, and a nitrogen fluorine gas.

3. The etching method according to claim 2, wherein the first inert gas and the second inert gas each comprise argon and / or helium; the reactive gas comprises a fluorocarbon gas and a nitrogen fluorine gas, wherein the fluorocarbon gas comprises carbon tetrafluoride and the nitrogen fluorine gas comprises nitrogen trifluoride; and / or, a ratio of the fluorocarbon gas and the nitrogen fluorine gas is 2:1 to 10:

1.

4. The etching method according to claim 2 or 3, wherein a ratio of the fluorocarbon gas and the first inert gas is 1:1 to 3:1; and / or, the etching of the surface of the silicon substrate comprises a pre-etching step and a main etching step, in the pre-etching step, a ratio of the first inert gas and the second inert gas is 1:5 to 1:15; in the main etching step, a ratio of the first inert gas and the second inert gas is 1:1 to 1:

5.

5. The etching method according to claim 4, wherein in the pre-etching step, a flow rate of the first inert gas is 10 sccm to 1000 sccm, a flow rate of the fluorocarbon gas and / or the hydrofluorocarbon gas is 10 sccm to 1000 sccm, a flow rate of the nitrogen fluorine gas is 0, and a flow rate of the second inert gas is 50 sccm to 5000 sccm; and / or, in the main etching step, a flow rate of the first inert gas is 100 sccm to 1000 sccm, a flow rate of the fluorocarbon gas and / or the hydrofluorocarbon gas is 10 sccm to 1000 sccm, a flow rate of the nitrogen fluorine gas is 10 sccm to 1000 sccm, and a flow rate of the second inert gas is 100 sccm to 5000 sccm.

6. The etching method of claim 1, wherein a process condition for the etching of the surface of the silicon substrate comprises a chamber pressure of 200 mTorr to 250 mTorr, an upper electrode power in a range of 500 W to 3000 W, and a lower electrode power in a range of 10 W to 1000 W.

7. The etching method according to any one of claims 1 to 3, 5 to 6, wherein the etching gas is introduced into the process chamber by a gas inlet assembly, the gas inlet assembly comprises a central gas inlet located in a middle of the process chamber and / or an edge gas inlet located at an edge of the process chamber; the ion beam is injected into the process chamber by an ion beam device, the ion beam device is located between an upper surface of the substrate and the gas inlet assembly.

8. A semiconductor process apparatus characterized by comprising: Comprising: a process chamber; a lower electrode assembly located in the process chamber for carrying a substrate; a gas inlet assembly for introducing an etching gas into the process chamber; An ion beam device is arranged to inject an ion beam into the process chamber, and is arranged between the gas inlet assembly and the lower electrode assembly.

9. The semiconductor process apparatus according to claim 8, wherein The ion beam device is provided with at least two layers of grid structures, including a first layer of grid and a second layer of grid, which are arranged in sequence along the direction of the ion beam output, and the first layer of grid is arranged upstream of the second layer of grid, and the first layer of grid is configured to be supplied with a periodic alternating voltage, and the second layer of grid is supplied with a voltage which is 5 V to 10 V higher than the voltage supplied to the first layer of grid. And / or, the ion beam device is provided with a pitch angle adjusting mechanism, and the pitch angle of the emitted ion beam is adjusted to be -30° to +30° by adjusting the pitch angle adjusting mechanism.

10. The semiconductor process apparatus according to claim 8 or 9, characterized by, The gas inlet assembly includes a central gas inlet assembly arranged in the middle of the process chamber, and an edge gas inlet assembly arranged around the central gas inlet assembly, and the central gas inlet assembly and the edge gas inlet assembly are respectively connected to a gas source outside the process chamber, and are used to selectively supply etching gas into the process chamber. And / or, the semiconductor process equipment further includes at least one radio frequency coil arranged around the side wall of the cavity of the process chamber, and the radio frequency coil is electrically connected to a radio frequency source, and the ion beam device is arranged between the radio frequency coil and the upper surface of the lower electrode assembly.

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