Chip stacking structure
By employing an interlaced distribution of rectangular ring sub-markers in the chip stacking structure and optimizing the design of metal line width and length, the problems of depressions and voids caused by alignment marks in the prior art are solved, achieving high-precision alignment and high-yield bonding effects.
Patent Information
- Application Number
- CN202511758488.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-26
- Publication Date
- 2026-02-27
AI Technical Summary
In existing chip stacking technologies, the design of alignment marks can impair key performance indicators or restrict design and process feasibility. In particular, after the CMP process, depressions and bonding voids are prone to occur, leading to decreased alignment accuracy and yield.
By setting multiple rectangular ring-shaped sub-markers on the first and second wafers, high-precision alignment is achieved through the staggered distribution of rectangular ring-shaped sub-markers on the bonding surface. Furthermore, by optimizing the width and length of the metal lines, the metal density is reduced, thus avoiding the problems of depressions and voids after the CMP process.
It improves the alignment accuracy and bonding yield of chip stacking, reduces the occurrence of depressions and voids after CMP process, and improves the quality and efficiency of wafer bonding.
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Figure CN121586478A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] Embodiments of the present disclosure relate to semiconductor device manufacturing technology, and particularly to a chip stack structure. BACKGROUND
[0002] In integrated circuit manufacturing, chip stack technology is widely used to improve integration and performance. Chip stack usually involves precise alignment and bonding of multiple layers of wafers, and the design and layout of alignment marks are one of the key factors to ensure the precision of the stack. To achieve high-precision stacking process, alignment marks for positioning are set on the wafer, and precise positioning is performed through these alignment marks.
[0003] However, in the current chip stack technology, the design of the alignment mark has inherent defects: these defects either directly damage the key performance indicators (such as alignment accuracy) of the mark, or severely restrict the feasibility of its design and process (such as structural integrity). SUMMARY
[0004] Therefore, embodiments of the present disclosure provide a chip stack structure.
[0005] To achieve the above-mentioned purpose, the technical solution of the present disclosure is implemented as follows: Embodiments of the present disclosure provide a chip stack structure, which comprises: a first wafer, the first wafer being provided with a first alignment mark; a second wafer bonded with the first wafer, the second wafer being provided with a second alignment mark; wherein the first alignment mark and the second alignment mark have a preset positional correspondence on the projection on the bonding surface; the first alignment mark and the second alignment mark comprise at least one sub-mark in the shape of a rectangular ring in a plane parallel to the bonding surface.
[0006] In some embodiments, the first alignment mark and the second alignment mark each comprise a plurality of sub-marks in the shape of a rectangular ring in a plane parallel to the bonding surface; the plurality of sub-marks comprise a first sub-mark extending in a first direction parallel to the bonding surface, and a second sub-mark extending in a second direction parallel to the bonding surface; wherein the first direction intersects the second direction.
[0007] In some embodiments, the sub-identifier is composed of bent metal wires parallel to the bonding surface; wherein the metal wires composing two opposite sides of the first sub-identifier in the second direction have a first width, the metal wires composing two opposite sides of the first sub-identifier in the first direction have a second width; the metal wires composing two opposite sides of the second sub-identifier in the first direction have the first width, the metal wires composing two opposite sides of the second sub-identifier in the second direction have the second width; the second width is less than or equal to the first width.
[0008] In some embodiments, the first width comprises 1 μm to 50 μm, and the second width comprises 1 μm to 50 μm.
[0009] In some embodiments, the first sub-identifier has a first length in the first direction, and a second length in the second direction; the second sub-identifier has a first length in the second direction, and a second length in the first direction; the first length comprises 5 μm to 100 μm, and the second length comprises 5 μm to 100 μm.
[0010] In some embodiments, the projected area of the sub-identifier on the bonding surface is less than or equal to fifty percent of a reference area; the reference area is the area of a rectangle defined by the outer edges of the projection of the sub-identifier on the bonding surface.
[0011] In some embodiments, the sub-identifier has a notch at its two opposite ends in the extension direction, which truncates the sub-identifier.
[0012] In some embodiments, the first alignment identifier is located in a first bonding layer in the first wafer which is in contact with the bonding surface; and the second alignment identifier is located in a second bonding layer in the second wafer which is in contact with the bonding surface.
[0013] In some embodiments, the first alignment identifier is located in a first redistribution layer in the first wafer which has metal interconnection structures; the second alignment identifier is located in a second redistribution layer in the second wafer which has metal interconnection structures; and there is a bonding layer between the first redistribution layer and the second redistribution layer.
[0014] In some embodiments, the preset positional correspondence is that the projection of the first alignment identifier on the bonding surface coincides with the projection of the second alignment identifier on the bonding surface; or, the projection of the first alignment identifier on the bonding surface and the projection of the second alignment identifier on the bonding surface are spatially staggered in the plane in which the bonding surface is located, and are separated from each other.
[0015] In the embodiments of the present disclosure, the first alignment mark and the second alignment mark for positioning are respectively arranged in the first wafer and the second wafer, and each mark contains at least one sub-mark in the form of a rectangular ring on the bonding surface, thereby improving the accuracy of image recognition, avoiding the problems of recesses and bonding cavities after CMP caused by the traditional large metal pattern alignment mark, and improving the bonding yield. BRIEF DESCRIPTION OF DRAWINGS
[0016] Figure 1 A structural schematic diagram of an alignment mark in an example; Figure 2 A structural schematic diagram of an alignment mark in another example; Figure 3 A structural schematic diagram of an alignment mark in still another example; Figure 4 A structural schematic diagram of a first alignment mark provided by the embodiments of the present disclosure; Figure 5 A structural schematic diagram of a second alignment mark provided by the embodiments of the present disclosure; Figure 6 A structural schematic diagram of another first alignment mark provided by the embodiments of the present disclosure; Figure 7 A schematic diagram of the projection position relationship of the first alignment mark and the second alignment mark on the bonding surface; Figure 8 A structural schematic diagram of a first sub-mark provided by the embodiments of the present disclosure; Figure 9 A structural schematic diagram of a second sub-mark provided by the embodiments of the present disclosure; Figure 10 A structural schematic diagram of another first sub-mark provided by the embodiments of the present disclosure; Figure 11 A structural schematic diagram of another second sub-mark provided by the embodiments of the present disclosure; Figure 12 A structural schematic diagram of still another first sub-mark provided by the embodiments of the present disclosure; Figure 13 A structural schematic diagram of still another second sub-mark provided by the embodiments of the present disclosure. DETAILED DESCRIPTION
[0017] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below in conjunction with the embodiments of the present disclosure and the drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the present disclosure.
[0018] In the following description, numerous specific details are given to provide a thorough understanding of the disclosure. However, it will be apparent that the disclosure can be practiced without one or more of the specific details. In other instances, well-known features are not described in order to avoid obscuring the disclosure. Unless otherwise specifically defined herein, all terms are to be given their broadest possible interpretation including modifi cations and variants thereof.
[0019] In the drawings, the size of layers, regions, elements, and the like, can be exaggerated relative to other layers, regions, elements, etc. for clarity. Like reference numbers in two or more drawings indicate like elements throughout.
[0020] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. The terminology used herein, such as "on", "over", "upper", "lower", "bottom", "top", and the like, is used for the purpose of brevity in describing the drawings only and is not intended to limit the scope of the present disclosure. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the drawings. For example, if a device described herein is turned over in use, a relative prefi x term such as "lower", "bottom", or "under" can be used to describe the same part or feature that would ordinarily be described as "upper" or "top" in the drawings. Thus, a device or structure can be oriented in use or operation in one direction and then flipped over to be oriented in a different direction, and the relative terms can be construed to encompass both orientations. The terms of degree such as "substantially", "about", and "approximately" as used herein mean to a degree of error expected by one of ordinary skill in the art to which the disclosure pertains. The terminology used herein, such as "on", "over", "upper", "lower", "bottom", "top", and the like, is used for the purpose of brevity in describing the drawings only and is not intended to limit the scope of the present disclosure. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the drawings. For example, if a device described herein is turned over in use, a relative prefi x term such as "lower", "bottom", or "under" can be used to describe the same part or feature that would ordinarily be described as "upper" or "top" in the drawings. Thus, a device or structure can be oriented in use or operation in one direction and then flipped over to be oriented in a different direction, and the relative terms can be construed to encompass both orientations. The terms of degree such as "substantially", "about", and "approximately" as used herein mean to a degree of error expected by one of ordinary skill in the art to which the disclosure pertains.
[0021] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device described herein is turned over in use, then a relative prefi x term such as "below" or "beneath" can be used to describe a relationship which is actually above or on top of the other element or feature. Accordingly, the exemplary terms "below" and "beneath" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0023] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.
[0024] In high-precision wafer alignment processes, alignment marks need to be placed on the upper and lower wafers to ensure that the alignment accuracy meets process requirements. Currently, the mainstream approach is to place the alignment marks on the redistribution layer (RDL). It's important to note that the alignment marks on the redistribution layer are typically made of metals such as aluminum. However, the large grain size of aluminum can lead to non-standard outlines of the alignment marks, resulting in decreased alignment accuracy. To address this issue, the industry has begun placing the alignment marks on the bonding interface (i.e., on the bonding layer). However, this approach requires controlling the roughness and dishing of the bonding interface, thus imposing more constraints on the design of alignment marks placed on the bonding interface.
[0025] In one example, alignment identifier 100 is set on the bonding interface, such as Figure 1 As shown, the alignment mark 100 includes four sub-markers 101 symmetrically distributed along the center of the alignment mark 100. Each sub-marker 101 consists of a metal line with a large area. Here, the alignment mark 100 located at the bonding interface can be formed by the following process: using a deposition process, a dielectric layer (such as silicon dioxide) is deposited on the surface of the wafer to form a bonding layer; using a photolithography process, the bonding layer is etched to form a groove on the surface of the bonding layer; a metal material is deposited on the surface of the bonding layer so that the metal material fills the groove; using a chemical mechanical polishing (CMP) process, the metal material located outside the groove is removed, leaving only the metal material located inside the groove, to form the alignment mark 100 within the groove.
[0026] However, in the above CMP process, due to the significant polishing selectivity of the polishing slurry to the metal material and the medium (such as silicon dioxide) around the metal material, and the greater local mechanical pressure on the wide metal pattern, the metal material is removed more, thereby forming a dished depression on the surface of the bonding layer, and further causing a larger cavity at the position of the alignment mark in the bonding process, resulting in wafer scrap.
[0027] Therefore, in another example, the metal alignment mark 200 (or the alignment mark 300) with a larger area is split into a plurality of sub-marks 201 (or sub-marks 301) arranged in an array under the premise of meeting the design rules, as shown in Figure 2 and Figure 3 However, this scheme still has certain defects, that is, this scheme will cause the boundary of the alignment mark 200 pattern to be unstable, that is, the spacing between the sub-marks 201 is difficult to accurately control. Specifically, when the spacing between the adjacent sub-mark A and the sub-mark B is too large, the image recognition algorithm will mistakenly think that the sub-mark A and the sub-mark B are two independent alignment marks, so that the contour of the entire alignment mark 200 cannot be obtained. When the spacing between the adjacent sub-mark A and the sub-mark B is too small, the surface of the bonding layer after the CMP process is prone to form a depression, thereby forming a cavity at the bonding interface, resulting in wafer scrap.
[0028] Therefore, the chip stacking structure provided by the embodiments of the present disclosure can effectively avoid bonding cavities and maintain clear and obvious pattern contours, thereby improving the bonding accuracy.
[0029] The chip stacking structure provided by the embodiments of the present disclosure includes: a first wafer provided with a first alignment mark 400; a second wafer bonded with the first wafer, the second wafer being provided with a second alignment mark 500; wherein the first alignment mark 400 and the second alignment mark 500 have a preset position corresponding relationship on the projection on the bonding surface; the first alignment mark 400 and the second alignment mark 500 include at least one sub-mark 401 in a rectangular ring shape on a plane parallel to the bonding surface, as shown in Figure 4 and Figure 5 .
[0030] Here, the first wafer refers to one of the base wafers constituting the chip stack structure, usually the top wafer or the bottom wafer. The first wafer can be integrated with multiple chip units, wiring layers, redistribution layers (RDL), etc. inside. A first alignment mark 400 for positioning is arranged in the first wafer, and the purpose is to achieve high-precision alignment operation in the subsequent bonding process. For example, one or more rectangular ring-shaped sub-marks 401 are designed at the edge area of the first wafer or the peripheral position of each chip unit in the first wafer, for the image recognition system to read and calculate the offset. Here, the rectangular ring shape should be understood as a kind of frame-like structure, that is, the projection of the sub-mark 401 on the bonding surface is a closed or non-closed rectangular frame surrounded by four sides, and the inside has a hollow area.
[0031] The second wafer is another wafer constituting the chip stack structure, which is bonded and connected with the first wafer. Similar to the first wafer, the second wafer is also provided with a second alignment mark 500 for positioning, so as to achieve accurate alignment in the bonding process. The second alignment mark 500 is also composed of at least one rectangular ring-shaped sub-mark 401, and the layout and size of the second alignment mark 500 match those of the first alignment mark 400.
[0032] The function of the second alignment mark 500 is similar to that of the first alignment mark 400, that is, to provide a reference point for the image recognition system before bonding, so that the image recognition system can measure the relative offset between the first wafer and the second wafer located on the first wafer. By comparing the image information of the first alignment mark 400 and the second alignment mark 500, the image recognition system can calculate the relative offset between the first alignment mark 400 and the second alignment mark 500, and adjust the relative position of the two wafers according to the offset, so as to achieve high-precision alignment effect.
[0033] In some embodiments, the first alignment mark 600 can only include one sub-mark 401, as shown in Figure 6 , and the second alignment mark can also only include one sub-mark. The shape of the first alignment mark 600 and the second alignment mark is exactly the same. At this time, the pre-set positional correspondence of the projection of the first alignment mark 600 and the second alignment mark on the bonding surface is that the projection of the first alignment mark 600 on the bonding surface coincides with the projection of the second alignment mark on the bonding surface.
[0034] In other embodiments, the first alignment mark 400 can include multiple sub-marks 401, as shown in Figure 4 , and the second alignment mark 500 can also include multiple sub-marks 401 equal in number to the sub-marks 401 in the first alignment mark 400, as shown in Figure 5As shown. At this time, the shapes of the first alignment mark 400 and the second alignment mark 500, as well as their layout positions on the corresponding wafers, are different. The preset positional correspondence between the projections of the first alignment mark 400 and the second alignment mark 500 onto the bonding surface is as follows: the projections of the first alignment mark 400 and the second alignment mark 500 onto the bonding surface are spatially staggered and separated from each other within the plane of the bonding surface, as shown. Figure 7 As shown, the dashed box contains the first alignment mark 400, and the dotted box contains the second alignment mark 500.
[0035] In some embodiments, the materials of the first alignment mark 400 and the second alignment mark 500 include copper (Cu), aluminum (Al), tungsten (W), etc.
[0036] In this embodiment, both the first alignment mark 400 and the second alignment mark 500 are graphical structures composed of at least one sub-marker 401. The sub-marker 401 is rectangular and arranged parallel to the bonding surface. Thus, the outer contour of the alignment mark can be used for image recognition, enabling the image recognition system to stably acquire positional information. Simultaneously, by eliminating the metal material at the center of the alignment mark, the density of metal material in the alignment mark graphic is reduced, thereby reducing potential depressions after CMP and decreasing the proportion of voids generated during bonding, thus improving alignment accuracy and yield.
[0037] In some embodiments, the first alignment mark 400 and the second alignment mark 500 both include a plurality of sub-markers 401 in a rectangular ring shape on a plane parallel to the bonding surface; the plurality of sub-markers 401 include: a first sub-marker 402 extending along a first direction parallel to the bonding surface, and a second sub-marker 403 extending along a second direction parallel to the bonding surface; wherein the first direction intersects the second direction.
[0038] like Figure 4 As shown, the first alignment mark 400 includes two first sub-markers 402 extending along a first direction and two second sub-markers 403 extending along a second direction. The first sub-markers 402 and the second sub-markers 403 in the first alignment mark 400 together form a complete "windmill-shaped" composite mark graphic.
[0039] like Figure 5 As shown, the second alignment mark 500 includes two first sub-markers 402 extending along a first direction and two second sub-markers 403 extending along a second direction. On a projection plane parallel to the bonding surface, the projections of the first alignment marks 400 and the second alignment marks 500 are staggered and nested. Specifically, the projection of each "windmill arm" of the first alignment mark 400 is embedded in the gap between the projections of two adjacent windmill arms of the second alignment mark 500, as shown...Figure 7 as shown.
[0040] The cooperation of the first alignment mark 400 and the second alignment mark 500 in the embodiments of the present disclosure can detect the relative rotation angle change of the first wafer and the second wafer with high precision, so as to improve the alignment accuracy from multiple dimensions including the rotation angle.
[0041] In some embodiments, the sub-mark 401 is composed of bent metal lines parallel to the bonding surface; wherein the metal lines composing the two opposite sides of the first sub-mark 402 in the second direction have a first width a, and the metal lines composing the two opposite sides of the first sub-mark 402 in the first direction have a second width b, as shown. Figure 8 Figure 9
[0042] Here, since the second width b is less than or equal to the first width a, in the first sub-mark 402, the width of the first metal line extending in the first direction is wider, and the width of the second metal line extending in the second direction is narrower, so that the profile of the first sub-mark 402 in the first direction is completely retained and used for image recognition. At the same time, the narrower second metal line can further reduce the metal density and reduce the risk of bonding voids.
[0043] In the second sub-mark 403, the width of the first metal line extending in the second direction is wider, and the width of the second metal line extending in the first direction is narrower, so that the profile of the second sub-mark 403 in the second direction is completely retained and used for image recognition. At the same time, the narrower second metal line can further reduce the metal density and reduce the risk of bonding voids.
[0044] Here, the settings of the first width a and the second width b need to consider factors such as the conductivity of the metal material, the limitation of the etching process, and the resolution of the pattern recognition system. For example, when the metal line is too narrow, it may cause recognition failure, and when the metal line is too wide, it is easy to cause local stress concentration, resulting in voids at the bonding interface, thereby affecting the yield of the wafer. Therefore, the designer needs to reduce the metal line density while ensuring the recognizability of the mark pattern.
[0045] In some embodiments, the first width a includes 1 μm to 50 μm, and the second width b includes 1 μm to 50 μm.
[0046] In the embodiments of the present disclosure, by limiting the first width a and the second width b within a reasonable range interval, the balance between the image recognition performance of the alignment mark and the stability of the bonding process can be achieved. Not only can it help to reduce the generation of bonding voids, but also can improve the alignment accuracy, thereby further improving the quality and yield of wafer bonding.
[0047] In some embodiments, the first sub-identification 402 has a first length d in the first direction and a second length c in the second direction; the second sub-identification 403 has the first length d in the second direction and the second length c in the first direction; the first length d includes 5 μm to 100 μm, and the second length c includes 5 μm to 100 μm.
[0048] Here, the first length d can be the overall length of the first sub-identification 402 in the first direction, for ensuring the integrity of the first sub-identification 402 profile in the first direction. The second length c can be the overall length of the first sub-identification 402 in the second direction, and the second length c can be smaller than the first length d, so as to reduce the copper density and avoid the recess problem after the CMP process caused by the large-area metal pattern.
[0049] Similarly, the first length d can also be the overall length of the second sub-identification 403 in the second direction, for ensuring the integrity of the second sub-identification 403 profile in the second direction. The second length c can be the overall length of the second sub-identification 403 in the first direction, and the second length c can be smaller than the first length, so as to reduce the copper density and avoid the recess problem after the CMP process caused by the large-area metal pattern.
[0050] In some embodiments, the projection area of the sub-identification 401 on the bonding surface is less than or equal to fifty percent of the reference area; the reference area is the area of the rectangle defined by the outer edges of the projection of the sub-identification on the bonding surface.
[0051] The projection area refers to the area of the bonding surface covered by the vertical projection of the sub-identification 401 on the bonding surface. The projection area reflects the size of the occupied space of the sub-identification 401 on the bonding surface, and affects the overall structural stability of the bonding interface. In order to prevent the generation of voids or cracks due to local stress concentration during the bonding process, the projection area needs to be strictly limited.
[0052] The reference area refers to the product of the overall length and the overall width of the sub-identification. Specifically, the reference area of the first sub-identification 402 is the product of the first length d and the second length c.
[0053] In the embodiments of the present disclosure, by limiting the projection area of the sub-identifiers 401 on the bonding surface within 50% of the reference area, the copper density of the bonding surface is effectively reduced, the recess problem caused by the large-area metal pattern after the CMP process is reduced, and the success rate and alignment accuracy of wafer bonding are improved.
[0054] In some embodiments, the sub-identifier 401 has a notch 404 at opposite ends thereof in the extension direction thereof.
[0055] The notch 404 refers to a cutout or interruption area provided at the two opposite ends of the sub-identifier 401 in the extension direction thereof, for locally cutting the originally continuous pattern structure. In this way, the distribution density of the metal pattern can be controlled, thereby avoiding the recess problem caused by the large-area copper pattern after the CMP process. The notch design of the sub-identifier 401 allows the main outline of the sub-identifier to be retained while reducing the overall copper density, thereby meeting the design requirements.
[0056] For example, for the first sub-identifier 402, the opposite ends thereof in the extension direction (the first direction) have notches 404. This allows the outline of the first sub-identifier 402 in the first direction to be completely retained and used for image recognition, while the outline of the first sub-identifier 402 in the second direction is broken. In this way, the metal line density can be reduced while ensuring the recognizability of the first sub-identifier pattern, as shown in Figure 10 .
[0057] For the second sub-identifier 403, the opposite ends thereof in the extension direction (the second direction) have notches 404. This allows the outline of the second alignment identifier 500 in the second direction to be completely retained and used for image recognition, while the outline of the second sub-identifier 403 in the first direction is broken. In this way, the metal line density can be reduced while ensuring the recognizability of the second sub-identifier 403 pattern.
[0058] In the embodiments of the present disclosure, the length of the metal line cut off at the notch 404 is not limited, and in the extreme case, the metal line extending along the second direction at the two ends of the first sub-identifier 402 in the first direction is completely removed, at this time, only two metal lines extending along the first direction and arranged in parallel are left in the first sub-identifier 402, as shown in Figure 12 . Similarly, in the extreme case, the metal line extending along the first direction at the two ends of the second sub-identifier 403 in the second direction is completely removed, at this time, only two metal lines extending along the second direction and arranged in parallel are left in the second sub-identifier 403, as shown in Figure 13 .
[0059] In some embodiments, the first alignment identifier 400 is located in a first bonding layer of the first wafer in contact with the bonding surface, and the second alignment identifier 500 is located in a second bonding layer of the second wafer in contact with the bonding surface.
[0060] Here, the first bonding layer is formed on the front surface of the first wafer, and is a medium layer directly involved in wafer bonding. The second bonding layer is formed on the front surface of the second wafer, and is also a medium layer directly involved in wafer bonding. The first bonding layer and the second bonding layer directly contact each other during bonding and form a firm chemical bond or a metal mixed bond, and together form a bonding surface.
[0061] In some embodiments, the material of the first bonding layer and the second bonding layer includes silicon dioxide (SiO2), silicon nitride (SiN), etc.
[0062] In the embodiments of the present disclosure, by arranging the first alignment mark 400 and the second alignment mark 500 in the first bonding layer of the first wafer and the second bonding layer of the second wafer respectively, high-precision alignment is achieved, and bonding defects caused by excessively large marks in the traditional way are avoided.
[0063] In some embodiments, the first alignment mark 400 is located in a first redistribution layer (RDL) having a metal interconnection structure in the first wafer; the second alignment mark 500 is located in a second redistribution layer having a metal interconnection structure in the second wafer; and the first redistribution layer and the second redistribution layer have a bonding layer therebetween.
[0064] The first redistribution layer contains a first metal interconnection structure composed of conductive materials such as copper, aluminum or tungsten, which is used to provide a flat and extended electrical connection and lead-out for active devices or lower interconnections on the first wafer. Similarly, the second redistribution layer contains a second metal interconnection structure composed of conductive materials such as copper, aluminum or tungsten, which is used to provide electrical connection and lead-out for active devices or lower interconnections on the second wafer.
[0065] In some embodiments, the first alignment mark 400 and the first metal interconnection structure can be formed in the first redistribution layer simultaneously by using the same deposition and etching process. That is, the material of the first alignment mark 400 can be the same as that of the first metal interconnection structure. Similarly, the second alignment mark 500 and the second metal interconnection structure can be formed in the second redistribution layer simultaneously by using the same deposition and etching process.
[0066] In the chip stack structure, the first redistribution layer and the second redistribution layer have a bonding layer therebetween. For example, the first redistribution layer and the second redistribution layer have a first bonding layer on the surface of the first wafer and a second bonding layer on the surface of the second wafer.
[0067] In the embodiments of the present disclosure, by optimizing the structural design of the alignment mark, the alignment mark can be applied not only to the redistribution layer but also to the bonding layer in contact with the bonding surface. Not only the accuracy of image recognition is improved, but also the problems such as bonding voids are effectively avoided, thereby significantly improving the quality and efficiency of wafer bonding process. In this way, the technical solution provided by the embodiments of the present disclosure can be applied to advanced packaging, such as wafer-level packaging (WLP) and three-dimensional stacking, and other application scenarios with high bonding precision requirements.
[0068] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present disclosure, the size of the sequence number of each process does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The sequence number of the above embodiments of the present disclosure is only for description, not representing the advantages and disadvantages of the embodiments.
[0069] The above only describes the preferred embodiments of the present disclosure, and does not limit the patent scope of the present disclosure. Any equivalent structural transformation made according to the content of the present disclosure specification and drawings, or direct / indirect application in other related technical fields is included in the patent protection scope of the present disclosure.
Claims
1. A chip stack structure, characterized by, The chip stack structure comprises: A first wafer provided with a first alignment mark; A second wafer bonded with the first wafer, the second wafer provided with a second alignment mark; wherein the first alignment mark and the second alignment mark have a preset positional correspondence on the projection on the bonding surface; the first alignment mark and the second alignment mark each comprise at least one sub-mark in a rectangular ring shape on a plane parallel to the bonding surface.
2. The chip stack structure of claim 1, wherein, The first alignment mark and the second alignment mark each comprise a plurality of sub-marks in a rectangular ring shape on a plane parallel to the bonding surface; the plurality of sub-marks comprise a first sub-mark extending along a first direction parallel to the bonding surface, and a second sub-mark extending along a second direction parallel to the bonding surface; wherein the first direction intersects the second direction.
3. The chip stack structure of claim 2, wherein, The sub-mark is composed of a bent metal line parallel to the bonding surface; wherein the metal lines composing two opposite sides of the first sub-mark in the second direction have a first width, and the metal lines composing two opposite sides of the first sub-mark in the first direction have a second width; the metal lines composing two opposite sides of the second sub-mark in the first direction have a first width, and the metal lines composing two opposite sides of the second sub-mark in the second direction have a second width; the second width is less than or equal to the first width.
4. The chip stack structure of claim 3, wherein, The first width comprises 1 μm to 50 μm, and the second width comprises 1 μm to 50 μm.
5. The chip stack structure of claim 2, wherein, The first sub-mark has a first length in the first direction, and a second length in the second direction; the second sub-mark has a first length in the second direction, and a second length in the first direction; the first length comprises 5 μm to 100 μm, and the second length comprises 5 μm to 100 μm.
6. The chip stack structure of claim 1, wherein, The projection area of the sub-mark on the bonding surface is less than or equal to fifty percent of a reference area; the reference area is the area of a rectangle defined by the outer edges of the projection of the sub-mark on the bonding surface.
7. The chip stack structure according to any one of claims 1 to 6, wherein The sub-mark has a notch at its two opposite ends in the extension direction, which truncates the sub-mark.
8. The chip stack structure according to any one of claims 1 to 6, wherein The first alignment mark is located in a first bonding layer in the first wafer in contact with the bonding surface; and the second alignment mark is located in a second bonding layer in the second wafer in contact with the bonding surface.
9. The chip stack structure according to any one of claims 1 to 6, wherein The first alignment mark is located in a first redistribution layer with a metal interconnection structure in the first wafer; the second alignment mark is located in a second redistribution layer with a metal interconnection structure in the second wafer; and the first redistribution layer and the second redistribution layer have a bonding layer therebetween.
10. The chip stack structure of claim 1, wherein, The preset positional correspondence is that the projection of the first alignment mark on the bonding surface coincides with the projection of the second alignment mark on the bonding surface; or The projection of the first alignment mark on the bonding surface and the projection of the second alignment mark on the bonding surface are spatially staggered and separated from each other in the plane in which the bonding surface is located.