Bonding sheet, semiconductor device, method for manufacturing semiconductor device, and apparatus for manufacturing semiconductor device

Abstract

The joining sheet (10) is one of a pair of sheets that join a first member and a second member, and is provided with a main surface (11) that joins the first member or the second member, and a main surface (12) that is located on the opposite side of the main surface (11), the main surface (12) being inclined with respect to the main surface (11), and the joining sheet (10) having electrical conductivity.

Description

Technical Field

[0001] This disclosure relates to bonding sheets, semiconductor devices, methods for manufacturing semiconductor devices, and apparatus for manufacturing semiconductor devices. Background Technology

[0002] Patent documents 1-3 disclose technologies related to a two-sided heat dissipation structure in which a semiconductor chip is sandwiched between two substrates. By transferring the heat generated on the semiconductor chip to the two substrates respectively, heat dissipation is improved.

[0003] Prior art literature

[0004] Patent documents

[0005] Patent Document 1: International Publication No. 2022 / 049641

[0006] Patent Document 2: Japanese Patent Application Publication No. 2021-2563

[0007] Patent Document 3: Japanese Patent Application Publication No. 2021-180290 Summary of the Invention

[0008] The problem that the invention aims to solve

[0009] When components such as semiconductor chips are sandwiched between two substrates, misalignment of the components may occur. Examples of misalignment include a single semiconductor chip being tilted, or multiple semiconductor chips having different heights. Misalignment may arise from factors such as the precision of the component placement process and differences in component dimensions. Misalignment can lead to, for example, poor connection between the component and the two substrates. Poor connection can result in mechanical, thermal, and / or electrical deterioration.

[0010] Therefore, this disclosure provides a bonding sheet capable of absorbing misalignment in the configuration of components, a semiconductor device, a method for manufacturing a semiconductor device, and an apparatus for manufacturing a semiconductor device.

[0011] Methods for solving problems

[0012] One aspect of this disclosure relates to a bonding sheet, which is one of a pair of sheets for bonding a first member and a second member, comprising: a first main surface for bonding with the first member or the second member; and a second main surface located on the opposite side of the first main surface, the second main surface being inclined relative to the first main surface, the bonding sheet being conductive.

[0013] A semiconductor device according to one aspect of this disclosure includes: a pair of sheets, comprising a first bonding sheet and a second bonding sheet, each being a bonding sheet according to the above-described aspect; the first member; and the second member, wherein the first member is a semiconductor element or a spacer, the first main surface of the first bonding sheet is bonded to the first member, the first main surface of the second bonding sheet is bonded to the second member, and the second main surfaces of the first bonding sheet and the second bonding sheet are bonded to each other.

[0014] A method for manufacturing a semiconductor device according to one aspect of this disclosure includes: a step of preparing a plurality of pairs of sheets, the pairs of sheets comprising a first bonding sheet and a second bonding sheet, each being a bonding sheet according to the above-described aspect; a step of preparing a first substrate, the first substrate being disposed on a plurality of the first members such that they do not overlap in plan view; a step of measuring at least one of the height of the upper surface of each of the plurality of the first members from the first substrate and the tilt relative to the first substrate; a step of disposing the plurality of the pairs of sheets on the upper surfaces of the corresponding first members; and a step of disposing a second substrate as the second member such that it covers the plurality of the pairs of sheets, wherein, in the disposing step, for at least one of the plurality of the pairs of sheets, the second main surfaces are staggered from each other based on at least one of the height of the upper surface of the corresponding first member and the tilt.

[0015] A method for manufacturing a semiconductor device according to one aspect of this disclosure includes: a step of preparing a pair of sheets, the pair of sheets comprising a first bonding sheet and a second bonding sheet, each being a bonding sheet according to the above-described aspect; a step of preparing a first substrate on which the first member is disposed; a step of measuring the tilt of the upper surface of the first member relative to the first substrate; a step of, based on the tilt, disposing the pair of sheets on the upper surface of the first member such that one of the first bonding sheet and the second bonding sheet is offset relative to the other in a rotational direction with a direction orthogonal to the second main surface as the axis of rotation; and a step of disposing a second substrate, which is the second member, such that it covers the pair of sheets.

[0016] A semiconductor device manufacturing apparatus according to one aspect of this disclosure includes: a first mounting section, which arranges a pair of sheets, each comprising a first bonding sheet and a second bonding sheet, which are bonding sheets according to the above-described aspect, on the upper surface of a corresponding first member, respectively, and a pair of first members disposed on a first substrate such that they do not overlap in plan view; a second mounting section, which arranges a second substrate, which serves as a second member, to cover the pair of sheets; and a measuring section, which measures at least one of the height of the upper surface of each of the pair of first members from the first substrate and its inclination relative to the first substrate, wherein the first mounting section, for at least one of the pair of sheets, arranges the second main surfaces offset from each other based on the height of the upper surface of the corresponding first member and the inclination at least one.

[0017] A semiconductor device manufacturing apparatus according to one aspect of this disclosure includes: a first mounting section, which arranges a pair of sheets, each comprising a first bonding sheet and a second bonding sheet, which are bonding sheets according to the above-described aspect, on the upper surface of a first member disposed on a first substrate; a second mounting section, which arranges a second substrate, which is the second member, such that it covers the pair of sheets; and a measuring section, which measures the tilt of the upper surface of the first member relative to the first substrate, wherein the first mounting section arranges the pair of sheets on the upper surface of the first member based on the tilt, such that one of the first bonding sheet and the second bonding sheet is offset relative to the other in a rotational direction with a direction orthogonal to the second main surface as the rotation axis.

[0018] Furthermore, one aspect of this disclosure can be implemented as a program that causes a computer to execute the above-described manufacturing method. Alternatively, one aspect of this disclosure can also be implemented as a computer-readable, non-transitory recording medium storing the program.

[0019] Invention Effects

[0020] According to this disclosure, deviations in the configuration of components can be absorbed. Attached Figure Description

[0021] Figure 1 This is a perspective view of the bonding sheet involved in Embodiment 1.

[0022] Figure 2 This is a side view of the bonding sheet involved in Embodiment 1.

[0023] Figure 3A This is a side view of the first joined state of the joined sheet pair according to Embodiment 1.

[0024] Figure 3B This is a side view of the second joined state of the joined sheet pair according to Embodiment 1.

[0025] Figure 3C This is a side view of the third joint state of the joint sheet pair according to Embodiment 1.

[0026] Figure 4A This is a top view of the semiconductor chip bonded to the bonding sheet according to Embodiment 1.

[0027] Figure 4B This is a top view used to illustrate the size relationship between the bonding sheet and the semiconductor chip involved in Embodiment 1.

[0028] Figure 5 This is a diagram showing the relationship between the tilt angle of the second main surface of the bonding sheet and the thickness of the bonding sheet according to Embodiment 1.

[0029] Figure 6 This is a cross-sectional view of the semiconductor device involved in Embodiment 2.

[0030] Figure 7 These are top, side, and bottom views showing the structure of the semiconductor chip in the semiconductor device according to Embodiment 2.

[0031] Figure 8 This is a top view showing the bonding state of multiple bonding sheet pairs of the semiconductor device according to Embodiment 2.

[0032] Figure 9 This is a cross-sectional view showing another example of the semiconductor device involved in Embodiment 2.

[0033] Figure 10 This is a top view showing the bonding state of multiple bonding sheet pairs of the semiconductor device according to Embodiment 2.

[0034] Figure 11A This is a cross-sectional view used to illustrate a step (the preparation step of the lower substrate) in the manufacturing method of the semiconductor device according to Embodiment 2.

[0035] Figure 11B This is a cross-sectional view used to illustrate a step (the bonding material formation step) of the semiconductor device manufacturing method according to Embodiment 2.

[0036] Figure 11C This is a cross-sectional view used to illustrate a step (chip mounting step) of the semiconductor device manufacturing method according to Embodiment 2.

[0037] Figure 11D This is a cross-sectional view used to illustrate a step (the arrangement step of bonding sheet pairs) in the manufacturing method of the semiconductor device according to Embodiment 2.

[0038] Figure 11E This is a cross-sectional view used to illustrate a step (the arrangement step of the upper substrate) in the manufacturing method of the semiconductor device according to Embodiment 2.

[0039] Figure 12 This is a cross-sectional view of the semiconductor device involved in Embodiment 3.

[0040] Figure 13 This is a cross-sectional view showing another example of the semiconductor device involved in Embodiment 3.

[0041] Figure 14A This is a cross-sectional view used to illustrate a step (the conductive paste preparation step) of the semiconductor device manufacturing method according to Embodiment 3.

[0042] Figure 14B This is a cross-sectional view used to illustrate a step (the arrangement step of the first bonding sheet) in the manufacturing method of the semiconductor device according to Embodiment 3.

[0043] Figure 14C This is a cross-sectional view used to illustrate a step (the conductive paste preparation step) of the semiconductor device manufacturing method according to Embodiment 3.

[0044] Figure 14D This is a cross-sectional view used to illustrate a step (the arrangement step of the second bonding sheet) in the manufacturing method of the semiconductor device according to Embodiment 3.

[0045] Figure 14E This is a cross-sectional view used to illustrate a step (the conductive paste preparation step) of the semiconductor device manufacturing method according to Embodiment 3.

[0046] Figure 14F This is a cross-sectional view used to explain a step (the arrangement step of the upper substrate) of the semiconductor device manufacturing method according to Embodiment 3.

[0047] Figure 15 This is a cross-sectional view of the semiconductor device according to Embodiment 4.

[0048] Figure 16 These are top, side, and bottom views showing the structure of the semiconductor chip in the semiconductor device according to Embodiment 4.

[0049] Figure 17 This is a cross-sectional view showing another example of the semiconductor device involved in Embodiment 4.

[0050] Figure 18A This is a cross-sectional view used to explain a step (the preparation step of the lower substrate) of the semiconductor device manufacturing method according to Embodiment 4.

[0051] Figure 18B This is a cross-sectional view used to illustrate a step (the bonding material formation step) of the semiconductor device manufacturing method according to Embodiment 4.

[0052] Figure 18C This is a cross-sectional view used to illustrate a step (chip mounting step) of the semiconductor device manufacturing method according to Embodiment 4.

[0053] Figure 18D This is a cross-sectional view used to illustrate a step (wire bonding step) of the semiconductor device manufacturing method according to Embodiment 4.

[0054] Figure 18E This is a cross-sectional view used to illustrate a step (the arrangement step of bonding sheet pairs) in the manufacturing method of the semiconductor device according to Embodiment 4.

[0055] Figure 18F This is a cross-sectional view used to illustrate a step (the arrangement step of the upper substrate) in the manufacturing method of the semiconductor device according to Embodiment 4.

[0056] Figure 19 This is a cross-sectional view of the semiconductor device according to Embodiment 5.

[0057] Figure 20 This is a cross-sectional view showing another example of the semiconductor device involved in Embodiment 5.

[0058] Figure 21 This is a block diagram of a semiconductor device manufacturing apparatus according to Embodiment 6.

[0059] Figure 22 This is a flowchart illustrating a method for manufacturing a semiconductor device according to Embodiment 6.

[0060] Figure 23A This is a cross-sectional view used to explain a step (the preparation step of the lower substrate) of the manufacturing apparatus for the semiconductor device according to Embodiment 6.

[0061] Figure 23B This is a cross-sectional view used to explain a step (chip holding step) of the operation of the semiconductor device manufacturing apparatus according to Embodiment 6.

[0062] Figure 23C This is a cross-sectional view used to explain a step (chip placement step) of the operation of the semiconductor device manufacturing apparatus according to Embodiment 6.

[0063] Figure 23D This is a cross-sectional view used to explain a step (bonding step) of the operation of the semiconductor device manufacturing apparatus according to Embodiment 6.

[0064] Figure 23E This is a cross-sectional view used to explain a step (measurement step) of the operation of the semiconductor device manufacturing apparatus according to Embodiment 6.

[0065] Figure 23F This is a cross-sectional view used to explain one step (holding step of the first bonding sheet) of the operation of the manufacturing apparatus of the semiconductor device according to Embodiment 6.

[0066] Figure 23G This is a cross-sectional view used to explain one step (the arrangement step of the first bonding sheet) of the operation of the manufacturing apparatus for the semiconductor device according to Embodiment 6.

[0067] Figure 23H This is a cross-sectional view used to explain one step (the holding step of the second bonding sheet) of the operation of the semiconductor device manufacturing apparatus according to Embodiment 6.

[0068] Figure 23I This is a cross-sectional view used to explain one step (the configuration step of the second bonding step) of the operation of the manufacturing apparatus for the semiconductor device according to Embodiment 6.

[0069] Figure 23J This is a cross-sectional view used to explain a step (the holding step of the upper substrate) of the manufacturing apparatus for the semiconductor device according to Embodiment 6.

[0070] Figure 23K This is a cross-sectional view used to explain a step (the placement step of the upper substrate) of the manufacturing apparatus for the semiconductor device according to Embodiment 6.

[0071] Figure 24 This is a perspective view showing a deformed example of a pair of joined sheets. Detailed Implementation

[0072] (Summary of this disclosure)

[0073] The first aspect of this disclosure relates to a bonding sheet, which is one of a pair of sheets that bond a first member and a second member, comprising: a first main surface that bonds to the first member or the second member; and a second main surface located on the opposite side of the first main surface, the second main surface being inclined relative to the first main surface, the bonding sheet being conductive.

[0074] Therefore, when used with other bonding sheets, the distance and inclination between the first main surfaces can be changed by adjusting the positional relationship between the second main surfaces. Thus, by configuring the bonding sheets with appropriate positional relationships according to the configuration state of the components to be bonded, deviations in the configuration of the components can be absorbed.

[0075] The bonding sheet according to the second aspect of this disclosure is the bonding sheet according to the first aspect, comprising: a metal layer having a third main surface and a fourth main surface located on the opposite side of the third main surface; a first coating layer covering at least a portion of the third main surface; and a second coating layer covering at least a portion of the fourth main surface, wherein the first main surface is a part of the surface of the first coating layer and the second main surface is a part of the surface of the second coating layer.

[0076] Therefore, the first and second coating layers can be used for bonding with other components or other bonding sheets. By pre-setting the bonding coating layers in the metal layer, the bonding process can be performed simply and with high precision.

[0077] The bonding sheet of the third aspect of this disclosure is the bonding sheet of the second aspect, wherein the first coating layer and the second coating layer each contain tin or a tin alloy as the main component.

[0078] Therefore, the desired film thickness can be easily and precisely achieved through processes such as plating. Furthermore, in the case of bonding, strong thermal bonding, mechanical bonding, and electrical bonding can be achieved by using reflow soldering processes such as formic acid reduction or hydrogen reduction.

[0079] The fourth aspect of this disclosure relates to a bonding sheet that is the same as the bonding sheet in the second or third aspect, wherein the third main surface is parallel to the first main surface, and the fourth main surface is parallel to the second main surface.

[0080] Therefore, the shape of the bonding sheet can be defined by the shape of the metal layer. By using a mold or the like to form the metal layer into a given shape, the dimensional accuracy of the bonding sheet can be improved.

[0081] The semiconductor device according to the fifth aspect of this disclosure includes: a pair of sheets, a first bonding sheet and a second bonding sheet, each being a bonding sheet as described in any one of the first to fourth aspects; the first member; and the second member, wherein the first member is a semiconductor element or a spacer, the first main surface of the first bonding sheet is bonded to the first member, the first main surface of the second bonding sheet is bonded to the second member, and the second main surfaces of the first bonding sheet and the second bonding sheet are bonded to each other.

[0082] Therefore, by adjusting the positional relationship between the second main surfaces of the first and second bonding sheets, the distance and inclination of the first main surfaces of the first and second bonding sheets can be changed. Thus, by arranging the first and second bonding sheets in an appropriate positional relationship according to the configuration state of the first member, deviations in the configuration of the first member can be absorbed.

[0083] The semiconductor device according to the sixth aspect of this disclosure is the semiconductor device according to the fifth aspect, wherein the second component is a substrate or a spacer.

[0084] The semiconductor device according to the seventh aspect of this disclosure is the semiconductor device according to the fifth or sixth aspect, wherein the first main surface of the first bonding sheet is larger than the first member when viewed from the top of the first main surface.

[0085] Therefore, by covering the entire upper surface of the first component with the bonding sheet, it is possible to achieve good thermal bonding, mechanical bonding, and electrical bonding of the first component.

[0086] The semiconductor device according to the eighth aspect of this disclosure is a semiconductor device according to any one of the fifth to seventh aspects, comprising: a first substrate; a second substrate disposed parallel to the first substrate, the second substrate being the second member; a plurality of the first members disposed between the first substrate and the second substrate, arranged in a top view of the first substrate such that they do not overlap; and a plurality of the pairs of sheets corresponding one-to-one with the plurality of the first members, wherein in each of the plurality of the pairs of sheets, the first main surface of the first bonding sheet is bonded to the corresponding first member, and the first main surface of the second bonding sheet is bonded to the second substrate.

[0087] Therefore, when multiple first components are configured, configuration deviations can easily occur due to differences in the dimensions of the first components and the precision of the configuration processing. By utilizing the pair of sheets disclosed herein, configuration deviations of the first components can be absorbed. The first and second substrates can be easily kept parallel, and device dimensions and heat dissipation can be easily set to target design values.

[0088] The semiconductor device according to the ninth aspect of this disclosure is the semiconductor device according to the eighth aspect, wherein in at least one of the plurality of said pairs of sheets, the second main surfaces are joined with one of them offset relative to the other.

[0089] Therefore, by adjusting the bonding state between the bonding sheets according to the configuration deviation of the first component, the configuration deviation of the first component can be absorbed.

[0090] The semiconductor device according to the 10th aspect of this disclosure is the semiconductor device according to the 9th aspect, wherein the direction in which the second main surfaces are offset from each other is the tilt direction of the second main surfaces.

[0091] Therefore, the thickness of a pair of sheets can be adjusted, thus absorbing the height deviation of multiple first components.

[0092] The semiconductor device according to the 11th aspect of this disclosure is the semiconductor device according to the 9th or 10th aspect, wherein the direction in which the second main surfaces are offset from each other is a rotational direction with an axis orthogonal to the second main surfaces.

[0093] Therefore, the tilt of the main surfaces of a pair of sheets can be adjusted, thus absorbing the tilt of the first component.

[0094] The semiconductor device according to the 12th aspect of this disclosure is the semiconductor device according to any one of the 9th to 11th aspects, wherein at least two of the plurality of the first components have different heights from the first substrate at their respective bonding surfaces with the corresponding first main surfaces.

[0095] Therefore, even if the joint surfaces of multiple first components have different heights, the height deviation can be absorbed by adjusting the joint state of a pair of sheets.

[0096] The semiconductor device according to the 13th aspect of this disclosure is the semiconductor device according to any one of the 9th to 12th aspects, wherein at least one of the plurality of the first components has a bonding surface with the corresponding first main surface that is inclined relative to the first substrate.

[0097] Therefore, even if the joint surface of the first component is tilted, the tilt can be absorbed by adjusting the joint state of the pair of sheets.

[0098] The 14th aspect of this disclosure relates to a method for manufacturing a semiconductor device, comprising: a step of preparing a plurality of pairs of sheets, the pairs of sheets including a first bonding sheet and a second bonding sheet, each being a bonding sheet according to any one of the first to fourth aspects; a step of preparing a first substrate, the first substrate being disposed on a plurality of the first members such that they do not overlap in plan view; a step of measuring at least one of the height of the upper surface of each of the plurality of the first members from the first substrate and the tilt relative to the first substrate; a step of disposing the plurality of the pairs of sheets on the upper surface of the corresponding first members; and a step of disposing a second substrate as the second member such that it covers the plurality of the pairs of sheets, wherein, in the disposing step, for at least one of the plurality of the pairs of sheets, the second main surfaces are staggered relative to each other based on at least one of the height of the upper surface of the corresponding first member and the tilt.

[0099] Therefore, by adjusting the positional relationship between the second main surfaces of the first and second bonding sheets, the distance and inclination of the first main surfaces of the first and second bonding sheets can be changed. Thus, by arranging the first and second bonding sheets in an appropriate positional relationship according to the configuration state of the first member, deviations in the configuration of the first member can be absorbed.

[0100] The semiconductor device manufacturing method according to the 15th aspect of this disclosure is the same as the semiconductor device manufacturing method according to the 14th aspect. In the process of performing the configuration, the offset direction and offset amount of the second main surfaces of the corresponding pair of sheets are determined based on the height and at least one of the upper surfaces of the plurality of first components, and the second main surfaces are configured to be offset from each other based on the determined offset direction and offset amount.

[0101] Therefore, since the offset is determined based on at least one of the measured height and the inclination, a pair of sheets can be configured in an appropriate engagement state according to the configuration of the first member.

[0102] The semiconductor device manufacturing method according to the 16th aspect of this disclosure is a semiconductor device manufacturing method according to the 14th or 15th aspect. In the step of performing the measurement, the height of the upper surface of each of the plurality of first components from the first substrate is measured. In the step of performing the configuration, for at least one of the plurality of pairs of sheets, based on the height of the upper surface of the corresponding first component, the pair of sheets are configured on the upper surface of the first component in a state where one of the first bonding sheet and the second bonding sheet is offset relative to the other in an inclined direction toward the second main surface.

[0103] Therefore, even if the joint surfaces of multiple first components have different heights, the height deviation can be absorbed by adjusting the joint state of a pair of sheets.

[0104] The semiconductor device manufacturing method according to the 17th aspect of this disclosure is a semiconductor device manufacturing method according to any one of the 14th to 16th aspects. In the step of performing the measurement, the tilt of the upper surface of each of the plurality of first members relative to the first substrate is measured. In the step of performing the arrangement, for at least one of the plurality of pairs of sheets, based on the tilt of the upper surface of the corresponding first member, the pair of sheets are arranged on the upper surface of the first member such that one of the first bonding sheet and the second bonding sheet is offset relative to the other in a rotation direction with the rotation axis set in a direction orthogonal to the second main surface.

[0105] Therefore, even if the joint surface of the first component is tilted, the tilt can be absorbed by adjusting the joint state of the pair of sheets.

[0106] The method for manufacturing a semiconductor device according to the 18th aspect of this disclosure includes: a step of preparing a pair of sheets, the pair of sheets comprising a first bonding sheet and a second bonding sheet, each being a bonding sheet according to any one of the first to fourth aspects; a step of preparing a first substrate on which the first member is disposed; a step of measuring the tilt of the upper surface of the first member relative to the first substrate; a step of, based on the tilt, displacing the pair of sheets on the upper surface of the first member such that one of the first bonding sheet and the second bonding sheet is offset relative to the other in a rotational direction with a direction orthogonal to the second main surface as the axis of rotation; and a step of displacing a second substrate, which is the second member, to cover the pair of sheets.

[0107] Therefore, by adjusting the positional relationship between the second main surfaces of the first and second bonding sheets, the inclination of the first main surface of the first bonding sheet and the first main surface of the second bonding sheet relative to each other can be changed. Thus, the inclination of the first member can be absorbed by arranging the first and second bonding sheets in an appropriate positional relationship according to the inclination of the bonding surface of the first member.

[0108] The semiconductor device manufacturing apparatus according to the 19th aspect of this disclosure includes: a first mounting section, which arranges a pair of sheets, each comprising a first bonding sheet and a second bonding sheet, which are bonding sheets according to any one of the first to fourth aspects, on the upper surface of a corresponding first member, respectively, and a pair of first members disposed on a first substrate such that they do not overlap in plan view; a second mounting section, which arranges a second substrate, which serves as a second member, such that it covers the pair of sheets; and a measuring section, which measures at least one of the height of the upper surface of each of the pair of first members from the first substrate and its inclination relative to the first substrate, wherein the first mounting section, for at least one of the pair of sheets, arranges the second main surfaces offset from each other based on the height of the upper surface of the corresponding first member and the inclination at least one.

[0109] Therefore, by adjusting the positional relationship between the second main surfaces of the first and second bonding sheets, the distance and inclination of the first main surfaces of the first and second bonding sheets can be changed. Thus, by arranging the first and second bonding sheets in an appropriate positional relationship according to the configuration state of the first member, deviations in the configuration of the first member can be absorbed.

[0110] The semiconductor device manufacturing apparatus according to the 20th aspect of this disclosure includes: a first mounting section, which arranges a pair of sheets, each comprising a first bonding sheet and a second bonding sheet, which are bonding sheets according to any one of the first to fourth aspects, on the upper surface of the first member disposed on the first substrate; a second mounting section, which arranges a second substrate, which is the second member, such that the pair of sheets are covered; and a measuring section, which measures the tilt of the upper surface of the first member relative to the first substrate, wherein the first mounting section arranges the pair of sheets on the upper surface of the first member based on the tilt, such that one of the first bonding sheet and the second bonding sheet is offset relative to the other in a rotational direction with a direction orthogonal to the second main surface as the rotation axis.

[0111] Therefore, by adjusting the positional relationship between the second main surfaces of the first and second bonding sheets, the inclination of the first main surface of the first bonding sheet and the first main surface of the second bonding sheet relative to each other can be changed. Thus, the inclination of the first member can be absorbed by arranging the first and second bonding sheets in an appropriate positional relationship according to the inclination of the bonding surface of the first member.

[0112] Hereinafter, the implementation methods will be described in detail with reference to the accompanying drawings.

[0113] Furthermore, the embodiments described below are all general or specific examples. The numerical values, shapes, materials, constituent elements, the arrangement and connection methods of the constituent elements, the steps, and the order of the steps shown in the following embodiments are examples and are not intended to limit this disclosure. In addition, constituent elements in the following embodiments that are not described in the independent claims are described as arbitrary constituent elements.

[0114] Furthermore, these figures are schematic diagrams and may not be strictly illustrative. Therefore, for example, the scales may not be consistent across different figures. Additionally, substantially identical structures are labeled with the same markings across different figures, and repetitive descriptions are omitted or simplified.

[0115] Furthermore, in this specification, terms such as parallel or perpendicular indicating the relationship between elements, terms such as square or rectangle indicating the shape of elements, and numerical ranges are not merely expressions with a strict meaning, but also imply expressions that include substantially equivalent ranges, such as differences of a certain percentage.

[0116] Furthermore, in this specification, the terms "above" and "below" do not refer to the absolute spatial orientation of upward (vertical above) and downward (vertical below), but are used as terms defined by relative positional relationships based on the stacking order in a stacked structure. Moreover, the terms "above" and "below" apply not only to cases where two constituent elements are arranged with a gap between them and another constituent element exists between them, but also to cases where two constituent elements are arranged closely together and are adjacent to each other.

[0117] Furthermore, in this specification and accompanying drawings, the x-axis, y-axis, and z-axis represent the three axes of a three-dimensional orthogonal coordinate system. In this specification, unless otherwise stated, the positive side of the z-axis is considered "above" and the negative side of the z-axis is considered "below".

[0118] Furthermore, unless otherwise stated, in this specification, ordinal numbers such as "first," "second," etc., do not imply the quantity or order of constituent elements, but are used for the purpose of avoiding confusion and distinguishing between similar constituent elements.

[0119] (Implementation Method 1)

[0120] [1-1. Structure]

[0121] First, regarding the overview of the bonding sheet involved in Embodiment 1, using Figure 1 as well as Figure 2 Please provide an explanation. Figure 1 This is a perspective view of the bonding sheet 10 involved in this embodiment. Figure 2 This is a side view of the bonding sheet 10 involved in this embodiment.

[0122] The bonding sheet 10 in this embodiment is one of a pair of sheets that bond the first component and the second component. Furthermore, the first component and the second component are, respectively, semiconductor elements, spacers, or substrates. A pair of sheets is a pair of bonding sheets comprising two bonding sheets 10.

[0123] The bonding sheet 10 is conductive. Thus, the bonding sheet 10 can be used as part of electrically connecting the first component and the second component.

[0124] The joining sheet 10 has a main surface 11, which is an example of a first main surface that joins with a first member or a second member, and a main surface 12, which is an example of a second main surface located on the opposite side of the first main surface. The main surface 12 is inclined relative to the main surface 11. Furthermore, the term "main surface" means the surface with the largest or second largest area among the plurality of surfaces of the member (here, the joining sheet 10). Specifically, the main surface 12 is the surface with the largest area among the plurality of surfaces of the joining sheet 10. The main surface 11 is the surface with the second largest area among the plurality of surfaces of the joining sheet 10.

[0125] The bonding sheet 10 of this embodiment has a flat cuboid shape (i.e., a cuboid whose height is shorter than the other sides) with one of its two base surfaces inclined. Specifically, the main surface 11 is a plane with a square shape when viewed from above. The main surface 12 is a plane inclined relative to the main surface 11. The inclination direction of the main surface 12 is a direction parallel to one side of the main surface 11 (x-axis direction).

[0126] like Figure 1 as well as Figure 2 As shown, the bonding sheet 10 includes a substrate 20 and coating layers 21 and 22.

[0127] Substrate 20 is an example of a metal layer comprising a metal as the main component. Furthermore, the term "main component" means that the material constituting the component (here, substrate 20) accounts for 50% or more by mass. Substrate 20 is, for example, a metal block material composed of silver (Ag).

[0128] like Figure 2 As shown, the substrate 20 has a main surface 13 as an example of a third main surface and a main surface 14 as an example of a fourth main surface located on the opposite side of the third main surface. Main surface 13 is a plane parallel to main surface 11. Main surface 14 is a plane parallel to main surface 12.

[0129] The substrate 20 is a component that defines the shape of the joining sheet 10. The substrate 20 has a sloping shape, with one of the two base surfaces of a flat cuboid. Specifically, the main surface 13 is a plane that is square in shape when viewed from above. The main surface 14 is a plane that is sloping relative to the main surface 13. The sloping direction of the main surface 14 is parallel to one side of the main surface 13 (x-axis direction).

[0130] The substrate 20 is formed, for example, using a forming technique that utilizes a mold. For example, by pressing a metal material, a substrate 20 with a shape in which the main surface 14 is inclined relative to the main surface 13 can be formed. In addition, the method of forming the substrate 20 is not particularly limited. For example, the substrate 20 can also be formed by grinding a rectangular block of metal material with its main surface inclined.

[0131] Alternatively, protrusions and depressions may be provided on the main surfaces 13 and 14, and they may not be planes parallel to the main surfaces 11 and 12 respectively. The covering layers 21 and 22 may also be configured to fill the protrusions and depressions provided on the main surfaces 13 and 14.

[0132] Coating layer 21 is an example of a first coating layer, covering at least a portion of the main surface 13. A portion of the surface of coating layer 21 is the main surface 11. In this embodiment, coating layer 21 covers the entire main surface 13 with a uniform film thickness.

[0133] Coating layer 22 is an example of a second coating layer, covering at least a portion of the main surface 14. A portion of the surface of coating layer 22 is the main surface 12. In this embodiment, coating layer 22 covers the entire main surface 14 with a uniform film thickness.

[0134] Coating layers 21 and 22 contain metal as the main component. Specifically, coating layers 21 and 22 each contain tin (Sn) or a tin alloy as the main component. A tin alloy is an alloy of tin and other metals besides tin. Other metals include, for example, silver (Ag), which is contained in the substrate 20, or copper (Cu), which is contained in the first or second component. For example, coating layers 21 and 22 are formed by plating onto the main surfaces 13 and 14, respectively.

[0135] Alternatively, a coating layer may also be provided on the side of the substrate 20. That is, the coating layers 21 and 22 may be integrated into the entire surface of the substrate 20. Alternatively, the bonding sheet 10 may not include the coating layers 21 and 22. In this case, the main surfaces 13 and 14 of the substrate 20 become the main surfaces 11 and 12 of the bonding sheet 10, respectively.

[0136] like Figure 2 As shown, the thickness T of the bonding sheet 10 represents the maximum thickness of the bonding sheet 10. That is, the thickness T is in the direction orthogonal to the main surface 11 ( Figure 2 The maximum distance between the main surfaces 11 and 12 in the z-axis direction is defined as follows: The thickness T is the sum of the thickness Tb of the base portion of the bonding sheet 10 and the thickness Ts of the inclined portion of the bonding sheet 10. The thickness Ts is the distance between the lower and upper ends of the main surface 12 in the z-axis direction, corresponding to the inclination height. Furthermore, the inclination angle of the main surface 12 relative to the main surface 11 is set as r (unit: °). r is, for example, greater than 0° and less than 45°.

[0137] Furthermore, the thicknesses of each of the coating layers 21 and 22 are sufficiently small compared to the thickness T of the bonding sheet 10, to a degree that is substantially negligible. Specifically, the thicknesses of each of the coating layers 21 and 22 are values ​​that are two or three digits smaller than the thickness T of the bonding sheet 10. For example, for cases where the thickness T is 1.0 mm or more and 10 mm or less, the thicknesses of each of the coating layers 21 and 22 are 0.1 μm or more and 10 μm or less, with 1 μm being an example.

[0138] [1-2. How to use the bonding sheet]

[0139] Next, the method of using the bonding sheet 10 will be explained.

[0140] The joining sheets 10 are used in pairs. That is, when joining the first member and the second member, a pair of sheets containing two joining sheets 10 (hereinafter, the joining sheet pair) is used. The two joining sheets 10 contained in the joining sheet pair have the same structure as each other, but are not limited thereto. It is also possible that at least one of the two joining sheets 10 is different in shape, material, and size.

[0141] Specifically, the main surfaces 12 of the two joining sheets 10 are joined to each other. In addition, the main surface 11 of one of the two joining sheets 10 is joined to the first member. The main surface 11 of the other of the two joining sheets 10 is joined to the second member.

[0142] The height of the joining sheet pair and the inclination of its two main surfaces 11 can be adjusted to desired values ​​within a certain range according to the joining state of the joining sheet pair, and then fixed in that state. This allows for the absorption of configuration deviations in the first and second members, which are respectively joined to the two main surfaces 11. The following describes several joining states that can be adopted by the joining sheet pair. Figures 3A-3C illustrate.

[0143] [1-2-1. First engagement state (normal state)]

[0144] Figure 3A This is a side view of the first joined state of the joining sheet pair 30 according to this embodiment. The joining sheet pair 30 is an example of a pair of sheets, including two joining sheets 10A and 10B. Joining sheet 10A is an example of the first joining sheet. Joining sheet 10B is an example of the second joining sheet.

[0145] The bonding sheets 10A and 10B respectively have the same as Figure 1 as well as Figure 2The bonding sheet 10 shown has the same structure. Main surfaces 11A and 11B correspond to main surface 11 as an example of a first main surface, and main surfaces 12A and 12B correspond to main surface 12 as an example of a second main surface. Furthermore, in Figure 3A In the accompanying drawings and thereafter, the illustrations of the substrate 20 and the coatings 21 and 22 are omitted.

[0146] like Figure 3A As shown, in the first engagement state, main surfaces 12A and 12B are configured to be completely identical to each other. Although in Figure 3A Not shown in the diagram, but on the main surface 11A of the bonding sheet 10A, for example, a semiconductor chip or spacer is bonded as a first component. On the main surface 11B of the bonding sheet 10B, for example, a substrate or spacer is bonded as a second component.

[0147] With the main surfaces 12A and 12B being completely identical, the thickness T1 of the bonding sheet pair 30 is the sum of the thickness T of the bonding sheet 10A and the thickness Tb of the base portion of the bonding sheet 10B. Furthermore, the main surface 11A, which is the bonding surface with the first member, and the main surface 11B, which is the bonding surface with the second member, are parallel.

[0148] [1-2-2. Second engagement state (misalignment state in the tilt direction)]

[0149] Figure 3B This is a side view of the second joined state of the joining sheet pair 30 according to this embodiment.

[0150] like Figure 3B As shown, in the second joining state, one of the main surfaces 12A and 12B is joined relative to the other in an inclined direction. Here, the main surface 12B of the joining sheet 10B slides relative to the main surface 12A of the joining sheet 10A in the sliding direction (the negative direction of the x-axis). In this case, the thickness T2 of the joining sheet pair 30 is represented by T1-Z1.

[0151] T1 is Figure 3A The thickness of the bonded sheet 30 in the shown state is represented by T + Tb (= Ta + 2Tb). Z1 is the offset of the bonded sheet 10B in the z-axis direction. (The remaining text appears to be incomplete and requires further context.) Figure 3A The sliding amount in the x-axis direction of the state shown is denoted as X1, and the tilt angle of the principal surfaces 12A and 12B is r (unit: °), which is represented by Z1 = X1 × tan(r).

[0152] In this way, it is possible to make the bonding sheet with a thickness T2 of 30 from Figure 3A The state change is shown. Specifically, it is possible to make the thickness T2 of the bonding sheet pair 30 smaller than the thickness T1.

[0153] Furthermore, the main surface 12B of the bonding sheet 10B can also slide relative to the main surface 12A of the bonding sheet 10A in the sliding direction (positive direction of the x-axis). In this case, the thickness T2 of the bonding sheet pair 30 can be greater than... Figure 3A The thickness T1 is shown.

[0154] If the bonding sheets 10A and 10B can be fixed when the main surfaces 12A and 12B are in slight contact, the thickness of the bonding sheet pair 30 can be adjusted within a range of 2Tb to 2T. If the main surfaces 12A and 12B need to be bonded with more than half of each other's area, the thickness of the bonding sheet pair 30 can be adjusted within a range of T-Ta / 2 to 2T-Ta / 2.

[0155] Furthermore, by sliding the main surfaces 12A and 12B in the tilting direction (without rotating them), the main surface 11A, which serves as the mating surface with the first member, and the main surface 11B, which serves as the mating surface with the second member, can be maintained in a parallel state. That is, while maintaining the tilt of the main surfaces 11A and 11B, the thickness T of the mating sheet pair 30 can be adjusted to the desired value.

[0156] [1-2-3. Third engagement state (misalignment state in the direction of rotation)]

[0157] Figure 3C This is a side view of the third joint state of the bonding sheet pair 30 according to this embodiment.

[0158] like Figure 3C As shown, in the third engagement state, one of the main surfaces 12A and 12B is engaged by rotating relative to the other. The rotation direction is the direction of rotation about an axis orthogonal to the main surfaces 12A and 12B. Figure 3C In the middle, it is shown that in the Figure 3A The state shown is considered as a 180° rotation when the rotation angle is 0°.

[0159] By rotating one of the bonding sheets 10A and 10B relative to the other, the tilt angle of the main surface 11A relative to the main surface 11B changes. Specifically, the tilt angle varies within a range of 0° to 2r°. Therefore, by adjusting the rotation angle of one of the bonding sheets 10A and 10B, the tilt angle of the main surface 11A relative to the main surface 11B can be set to a desired value and fixed.

[0160] [1-3. Determining the staggered amount]

[0161] Next, the method for determining the offset of the bonding sheets 10A and 10B will be explained.

[0162] The offset of the joining sheets 10A and 10B is determined based on the height and inclination of the upper surface of the first member that joins with the main surface 11A of the joining sheet 10A. Hereinafter, as the first member, an example is... Figure 4A The semiconductor chip 40 shown is an example.

[0163] Figure 4A This is a top view of the semiconductor chip 40 bonded to the bonding sheet 10 according to this embodiment. Here, the top view shape of the upper surface of the semiconductor chip 40 is set as a square with one side length D. The upper surface of the semiconductor chip 40 is the bonding surface to the bonding sheet 10.

[0164] The height and tilt of the upper surface of the semiconductor chip 40 are calculated by measuring its three-dimensional position at four locations P1 to P4 near the edge of the upper surface. The three-dimensional position measurement is performed, for example, using a laser-based ranging device. Based on the measurement results at the four locations, the height and tilt of the upper surface of the semiconductor chip 40 are calculated. Furthermore, the height and tilt are represented by the maximum height of the upper surface from a given reference plane and the tilt angle of the upper surface relative to that reference plane, respectively. The measurement locations can also be three locations.

[0165] Based on the measurement results, the tilt angle of the upper surface is set as A (unit: °), and the offset from the reference height is set as B (unit: mm). In addition, the reference height is, for example, the height of the upper surface of one of the other first components mounted on the same substrate, or the average height of the upper surfaces of multiple first components (including semiconductor chip 40) mounted on the same substrate.

[0166] First, calculate the rotation angle θ (in °) used to make the main surface 11A of the bonding sheet 10A inclined at the same angle A as the tilt angle. The rotation angle θ is equivalent to the offset in the direction of rotation. Here, although the axis orthogonal to the main surface 11A is set as the axis of rotation, it corresponds one-to-one with the case where the axis orthogonal to the main surface 12A is the axis of rotation.

[0167] like Figure 3C As shown, by rotating from 0° to 180°, the tilt angle of the principal face 11A changes from 0° to 2r°. The rotation angle and the tilt angle of the principal face 11A are directly proportional, so θ:A=180:2r holds. Therefore, the rotation angle θ is represented by the following equation (1).

[0168] (1) θ = 90° × A / r

[0169] Furthermore, the main surface 11A, when viewed from above, is larger than the upper surface of the semiconductor chip 40. Additionally, although not strictly necessary, it is desirable that the main surface 11A covers the entire upper surface of the semiconductor chip 40 when the bonding sheet 10A is rotated by an angle θ. The increased bonding area between the semiconductor chip 40 and the bonding sheet 10A improves heat dissipation and electrical conductivity.

[0170] Figure 4B This is a top view used to illustrate the size relationship between the bonding sheet 10A and the semiconductor chip 40 involved in this embodiment. Figure 4B The image shows the state in which the main surface 11A of the bonding sheet 10A is rotated by an angle θ (in °) with the axis passing through the center of the upper surface of the semiconductor chip 40 and orthogonal to the upper surface as the center.

[0171] If the length of one side of the main surface 11A, which is used to cover the entire upper surface of the semiconductor chip 40 during rotation, is set as S1, then S1 is represented by the following formula (2).

[0172] (2) S1=D×sin(θ)+D×cos(θ)

[0173] Therefore, S1 can be in the range of D or more and D×√2 or less. Therefore, if the length S1 of one side of the main surface 11A is more than √2 times the length D of one side of the upper surface of the semiconductor chip 40, the main surface 11A can be integrally joined to the upper surface of the semiconductor chip 40 regardless of the value of the rotation angle θ.

[0174] Next, the sliding amount X1 (in mm) of the bonding sheet 10B used to absorb height deviation in the tilting direction is calculated. The sliding amount X1 corresponds to the offset in the tilting direction. For example... Figure 3B As shown, the adjustment amount Z1 of the thickness of the bonding sheet for 30 is expressed by the following formula (3) for the sliding amount X1.

[0175] (3) X1 = Z1 ÷ tan(r)

[0176] As the thickness adjustment amount Z1, the offset amount B obtained by measurement from the reference height can be used to calculate the offset amount X1.

[0177] Furthermore, although not strictly necessary, it is desirable that, when the bonding sheet 10B slides relative to the bonding sheet 10A, the main surface 11B of the bonding sheet 10B covers the entire upper surface of the semiconductor chip 40 in a top view. That is, it is desirable that the bonding sheets 10A and 10B are configured such that no gap is formed in the space directly above the upper surface of the semiconductor chip 40. In this way, when sliding by a sliding amount X1, the length S of one side of the main surface 11B of the bonding sheet 10B covering the entire upper surface of the semiconductor chip 40 is D + X1 or more. This results in good heat dissipation and electrical conductivity.

[0178] In the case of rotation and sliding relative to the bonding sheet 30, the length S of one side of each of the main surfaces 11A and 11B is the sum of the length S1 of one side of the main surface 11A (expressed by equation (2) for covering the rotation) and the sliding amount X1. That is, the length S of one side satisfies equation (4).

[0179] (4) S≥S1+X1=D(sin(θ)+cos(θ))+B / tan(r)

[0180] Additionally, for example, if the top view shape of the main surfaces 11A and 11B is rectangular, the length of the shorter side can be considered as S. Furthermore, if the top view shape of the upper surface of the semiconductor chip 40 is rectangular, the length of the longer side can be considered as D.

[0181] Furthermore, depending on the bonding state of the bonding sheets 10A and 10B, one or both of the bonding sheets 10A and 10B may come into contact with components such as a substrate. Hereinafter, for thicknesses used to prevent the bonding sheets 10A and 10B from contacting other components (for example, the thickness T of the bonding sheet 10), the following are mainly used... Figure 2 Please provide an explanation.

[0182] Using the length S of one side of the main surface 11 and the tilt angle r of the main surface 12, the thickness Ts of the tilted portion of the joint sheet 10 is represented by the following formula (5).

[0183] (5) Ts = tan(r) × S

[0184] When the joining sheet 10 is configured by rotating it by a rotation angle θ, the following equation (6) is obtained according to equations (2) and (5).

[0185] (6) Ts=tan(r)×D(sin(θ)+cos(θ))

[0186] Furthermore, when rotated by a rotation angle θ, it is desirable that the lower end of the joining sheet 10B does not protrude downward beyond the main surface 11A of the joining sheet 10A. If the lower end of the joining sheet 10B protrudes downward, it may come into contact with other components. In order for the lower end of the joining sheet 10B not to protrude downward beyond the main surface 11A of the joining sheet 10A, the thickness Tb of the base portion of the joining sheet 10 should satisfy the following equation (7).

[0187] [Mathematical Expression 1]

[0188]

[0189] And, as Figure 3B As shown, when the joining sheet 10B slides relative to the joining sheet 10A in the sliding direction by a sliding amount X1, the thickness Tb of the base portion of the joining sheet 10 also requires an offset amount B from the reference height. Based on the above, the thickness T of the joining sheet 10 requires the sum of the minimum values ​​of Ts shown in equation (6), Tb shown in equation (7), and the offset amount B from the reference height. Therefore, the thickness T of the joining sheet 10 can be within the range shown in equation (8) below.

[0190] [Mathematical Expression 2]

[0191]

[0192] Furthermore, if the thickness T of the bonding sheet becomes too large, heat dissipation and conductivity deteriorate. In addition, increasing the thickness T also leads to the enlargement of the semiconductor device. In this embodiment, for example, the thickness T is 10 mm or less, or it may be 7 mm or less, but it is not limited to this. Furthermore, the thicknesses Tb and Ts may be equal, or one may be longer than the other.

[0193] Furthermore, the tilt angle r (unit: °) of the main surface 12 is greater than 0° and less than 45°. The tilt angle r can also be greater than 1° and less than 20°. In addition, it can be clearly seen from the above formula (8) that the minimum value of the thickness T of the bonding sheet 10 changes depending on the value of the tilt angle r.

[0194] Figure 5 This is a diagram showing the relationship between the tilt angle r of the main surface 12 of the bonding sheet 10 and the thickness T of the bonding sheet 10. Figure 5 In the diagram, the horizontal axis represents the tilt angle r (unit: °), and the vertical axis represents the thickness T (unit: mm). Figure 5 In the calculation, within the range of tilt angles of 1° and 17°, the value of T calculated based on Equation (8) is plotted for every 1°. In the calculation, the tilt of the semiconductor chip 40 is set to A = 1°, the offset from the reference height is set to B = 0.1 mm, and the length of one side of the upper surface of the semiconductor chip 40 is set to D = 5 mm.

[0195] like Figure 5 As shown, within a tilt angle r of 2° or more and 17° or less, the thickness T of the bonding sheet 10 can be approximately 3 mm or less. Furthermore, within a tilt angle r of 4° or more and 15° or less, the thickness T of the bonding sheet 10 can be approximately 2 mm or less. Further, within a tilt angle r of 7° or more and 8° or less, the thickness T of the bonding sheet 10 becomes a minimum. By reducing the thickness T of the bonding sheet 10, heat dissipation and conductivity can be further improved, and this contributes to the miniaturization of semiconductor devices.

[0196] (Implementation Method 2)

[0197] Next, implementation method 2 will be described.

[0198] In Embodiment 2, a semiconductor device having the bonding sheet pair described in Embodiment 1 will be described. Hereinafter, the description will focus on the differences from Embodiment 1, and the description of the commonalities will be omitted or simplified.

[0199] [2-1. Structure]

[0200] First, regarding the structure of the semiconductor device involved in Embodiment 2, using Figure 6 Please provide an explanation. Figure 6 This is a cross-sectional view of the semiconductor device 100 according to this embodiment.

[0201] like Figure 6 As shown, the semiconductor device 100 includes a lower substrate 110, an upper substrate 120, bonding members 131, 132 and 133, semiconductor chips 141, 142 and 143, bonding sheet pairs 151, 152 and 153, and a sealing member 160. In this embodiment, the semiconductor chips and bonding sheet pairs correspond one-to-one.

[0202] The lower substrate 110 is an example of the first substrate. The lower substrate 110 includes a heat sink 112, an insulating layer 114, and electrodes 116, 117, and 118.

[0203] The heat sink 112 is a flat plate containing a material with high thermal conductivity, such as metal, as its main component. For example, the heat sink 112 is a metal plate made of copper (Cu). The heat sink 112 is mainly provided to dissipate the heat generated in each of the semiconductor chips 141, 142, and 143 to the air or other components.

[0204] The insulating layer 114 is a layer containing an electrically insulating material as its main component. The insulating layer 114 is composed of silicon nitride, bauxite, aluminum nitride, etc. The insulating layer 114 is provided to electrically insulate the electrodes 116, 117, and 118 from the heat sink 112. The insulating layer 114 is larger than the heat sink 112 and covers the entire upper surface of the heat sink 112, but is not limited thereto. The insulating layer 114 may be the same size as the heat sink 112, or it may be smaller than the heat sink 112. Furthermore, the insulating layer 114 may be configured as an island only in the portions where the electrodes 116, 117, and 118 are located. That is, the insulating layer 114 only needs to ensure electrical insulation between the electrodes 116, 117, and 118 and the heat sink 112, or it may exist in the uncovered portions of the upper surface of the heat sink 112.

[0205] Electrodes 116, 117, and 118 correspond one-to-one with semiconductor chips 141, 142, and 143, respectively. Furthermore, electrodes 116, 117, and 118 can also be electrically connected to each other. Electrodes 116, 117, and 118 contain a conductive material as their main component. For example, electrodes 116, 117, and 118 are made of a metal such as copper (Cu).

[0206] The upper substrate 120 is an example of a second substrate arranged parallel to the first substrate. Furthermore, the phrase "the first substrate and the second substrate are arranged parallel" means that one main surface of the first substrate and one main surface of the second substrate are parallel. For example, the two facing main surfaces of each of the first and second substrates are parallel.

[0207] In this embodiment, the upper substrate 120 is also an example of a second component to which the bonding sheets 151, 152, and 153 are bonded. For example... Figure 6 As shown, the upper substrate 120 includes a heat sink 122, an insulating layer 124, and an electrode 126.

[0208] The heat sink 122 is a flat plate containing a material with high thermal conductivity, such as metal, as its main component. For example, the heat sink 122 is a metal plate made of copper (Cu). The heat sink 122 is mainly provided to dissipate the heat generated by the semiconductor chips 141, 142, and 143 to the air or other components.

[0209] The insulating layer 124 is a layer containing an electrically insulating material as its main component. The insulating layer 124 is composed of silicon nitride, bauxite, aluminum nitride, etc. The insulating layer 124 is provided to electrically insulate the electrode 126 from the heat sink 122. The insulating layer 124 is larger than the heat sink 122 and covers the entire lower surface of the heat sink 122, but is not limited thereto. The insulating layer 124 may be the same size as the heat sink 122 or smaller. The insulating layer 124 only needs to ensure electrical insulation between the electrode 126 and the heat sink 122, and may also exist in uncovered portions of the lower surface of the heat sink 122.

[0210] Electrode 126 is a single electrode shared by semiconductor chips 141, 142, and 143. Alternatively, electrodes corresponding one-to-one with semiconductor chips 141, 142, and 143, similar to electrodes 116, 117, and 118 on the lower substrate 110, can be provided instead of electrode 126. Electrode 126 contains a conductive material as its main component. For example, electrode 126 is made of a metal such as copper (Cu).

[0211] The lower substrate 110 and upper substrate 120 are, for example, DBC (Direct Bonded Copper) substrates. Copper films are formed on both sides of insulating layers 114 and 124, which are made of ceramic material, and patterned as needed, thereby forming the lower substrate 110 and upper substrate 120. Furthermore, the structure of the lower substrate 110 and upper substrate 120 is not particularly limited. For example, the heat sink 112 or 122, or the electrodes 116, 117, 118, or 126, may have a single-layer or multi-layer structure of metal monomers or metal alloys. Additionally, the insulating layers 114 or 124 may have a single-layer or multi-layer structure of insulating films. Furthermore, the lower substrate 110 and upper substrate 120 may only have metal heat sinks.

[0212] Bonding members 131, 132, and 133 are disposed in different regions on the upper surface of the lower substrate 110. Bonding members 131, 132, and 133 correspond one-to-one with semiconductor chips 141, 142, and 143, respectively. Specifically, bonding member 131 bonds the lower surface of semiconductor chip 141 to electrode 116. Bonding member 132 bonds the lower surface of semiconductor chip 142 to electrode 117. Bonding member 133 bonds the lower surface of semiconductor chip 143 to electrode 118.

[0213] The bonding components 131, 132, and 133 each comprise a conductive material as their main component. For example, bonding components 131, 132, and 133 are flat, cuboid components made of silver (Ag) with a surface coated (e.g., plated) with tin (Sn). Alternatively, bonding components 131, 132, and 133 may also be Ag sintering pastes. Ag sintering pastes are sintered materials containing nano- or micro-sized Ag particles.

[0214] Semiconductor chips 141, 142, and 143 are examples of first components serving as semiconductor elements. Semiconductor chips 141, 142, and 143 are positioned between the lower substrate 110 and the upper substrate 120 such that they do not overlap when viewed from above the lower substrate 110. In this embodiment, semiconductor chips 141, 142, and 143 are each elements having two electrodes.

[0215] Figure 7 These are (a) a top view, (b) a side view, and (c) a bottom view showing the structure of semiconductor chips 141, 142, and 143 of the semiconductor device 100 according to this embodiment. Semiconductor chips 141, 142, and 143 are specific examples of semiconductor chip 40 shown in Embodiment 1. Since they have the same structure as each other, semiconductor chip 141 will be used as an example in the following description.

[0216] Semiconductor chip 141 is, for example, a semiconductor device with two external electrodes, such as a Schottky barrier diode (SBD) or a freewheeling diode (FWD). Figure 7 As shown, the semiconductor chip 141 has a chip body 145, a lower surface electrode 146 and an upper surface electrode 147.

[0217] The chip body 145 is the main body of a device formed on a substrate containing silicon carbide (SiC), silicon (Si), gallium nitride (GaN), gallium oxide (GaO), or diamond as the main component. The chip body 145 has a flat cuboid shape. The size of the chip body 145 is not particularly limited, but the length of one side is in the range of 1 mm or more and 20 mm or less, and the thickness is 0.01 mm or more and 0.5 mm or less.

[0218] The lower surface electrode 146 is disposed on the lower surface of the chip body 145. The lower surface electrode 146 has a single-layer structure or a multi-layer structure of a metal monomer or metal alloy. For example, the lower surface electrode 146 has a stacked structure of titanium (Ti), nickel (Ni), and silver (Ag) arranged sequentially from the chip body 145 side, but is not limited thereto. For example, the outermost layer (lowest layer) of the lower surface electrode 146 may also be gold (Au).

[0219] The upper surface electrode 147 is disposed on the upper surface of the chip body 145. The upper surface electrode 147 has a single-layer structure or a multi-layer structure of a metal monomer or metal alloy. For example, the upper surface electrode 147 has a stacked structure of titanium (Ti), nickel (Ni), and silver (Ag) arranged sequentially from the chip body 145 side, but is not limited thereto. For example, the outermost surface (uppermost layer) of the upper surface electrode 147 may also be gold (Au).

[0220] When the semiconductor chip 141 is a diode, one of the lower surface electrode 146 and the upper surface electrode 147 is an anode electrode, and the other is a cathode electrode. The lower surface electrode 146 and the upper surface electrode 147 are configured to cover approximately the entire lower and upper surfaces of the chip body 145, respectively. The upper surface of the upper surface electrode 147 is the upper surface of the semiconductor chip 141 and is connected to the first main surface (main surface 11A) of the corresponding bonding sheet pair 30 (bonding sheet pair 151, 152, or 153).

[0221] The bonding sheet pairs 151, 152, and 153 are the bonding sheet pairs 30 shown in Embodiment 1. Figure 6 As shown, the bonding sheet pair 151 includes bonding sheets 151A and 151B. The bonding sheet pair 152 includes bonding sheets 152A and 152B. The bonding sheet pair 153 includes bonding sheets 153A and 153B. Bonding sheets 151A, 152A, and 153A are examples of the first bonding sheet. Figures 3A-3C The bonding sheet 10A is shown. Bonding sheets 151B, 152B, and 153B are examples of the second bonding sheet. Figures 3A-3C The bonding sheet 10B shown.

[0222] In this embodiment, bonding sheets 151, 152, and 153 correspond one-to-one with semiconductor chips 141, 142, and 143, respectively. The first main surface (main surface 11A) of bonding sheet 151A is bonded to semiconductor chip 141 (specifically, the upper surface electrode 147). The first main surface (main surface 11A) of bonding sheet 152A is bonded to semiconductor chip 142 (specifically, the upper surface electrode 147). The first main surface (main surface 11A) of bonding sheet 153A is bonded to semiconductor chip 143 (specifically, the upper surface electrode 147). The first main surface (main surface 11B) of each of bonding sheets 151B, 152B, and 153B is bonded to the upper substrate 120 (specifically, the electrode 126). The specific bonding states of each bonding sheet pair 151, 152, and 153 will be described later.

[0223] The sealing member 160 is a resin member used to seal semiconductor chips 141, 142, and 143. The sealing member 160 is formed using, for example, an insulating resin material such as epoxy. The sealing member 160 is provided to protect semiconductor chips 141, 142, and 143 from moisture and air.

[0224] [2-2. Example of absorption of height deviation]

[0225] In this embodiment, the upper surfaces of semiconductor chips 141, 142, and 143 are each at different heights. Furthermore, the height here refers to the distance from the upper surface of the lower substrate 110 (specifically, electrodes 116, 117, and 118). Figure 6 As shown, the upper surface of semiconductor chip 141 is lower than the upper surface of semiconductor chip 142 and higher than the upper surface of semiconductor chip 143.

[0226] In the semiconductor device 100, by adjusting the bonding states of the bonding sheets 151, 152, and 153, deviations in the height of the upper surfaces of the semiconductor chips 141, 142, and 143 can be absorbed. Specifically, the bonding states of the bonding sheets 151, 152, and 153 are determined based on the measurement results of the height of the upper surfaces of the semiconductor chips 141, 142, and 143, so that the first main surfaces (main surfaces 11B) of the bonding sheets 151B, 152B, and 153B are at the same height.

[0227] Figure 8 This is a top view showing the bonding state of the plurality of bonding sheet pairs 151, 152, and 153 of the semiconductor device 100 according to this embodiment. Figure 8 In the diagram, the dashed arrows indicate the tilting direction of the bonding sheets (lower bonding sheets 151A, 152A, 153A) that bond to the first components (semiconductor chips 141, 142, 143). The solid arrows indicate the tilting direction of the bonding sheets (upper bonding sheets 151B, 152B, 153B) that bond to the second component (upper substrate 120). The tilting direction is the direction in which the thickness of each bonding sheet decreases (in...). Figure 2 In the example shown, the negative direction of the x-axis is set as the positive direction.

[0228] In the bonding sheet pair 151, such as Figure 6 as well as Figure 8 As shown, the bonding sheets 151A and 151B are configured to be completely identical in top view. Figure 3A The shown engagement state.

[0229] In the bonding sheet pair 152, such as Figure 6 as well as Figure 8As shown, the bonding sheet 152B is configured to slide relative to the bonding sheet 152A in the sliding direction. Figure 3B (As shown in the bonding state). The upper surface of semiconductor chip 142 is located at a higher position than the upper surface of semiconductor chip 141, so the height difference is absorbed by making the thickness of bonding sheet pair 152 thinner than the thickness of bonding sheet pair 151.

[0230] In the joining sheet pair 153, such as Figure 6 as well as Figure 8 As shown, bonding sheet 153B is configured to slide relative to bonding sheet 153A in the sliding direction. The upper surface of semiconductor chip 143 is located at a lower position than the upper surface of semiconductor chip 141, so the height difference is absorbed by making the thickness of bonding sheet pair 153 greater than the thickness of bonding sheet pair 151.

[0231] Furthermore, in the bonding sheet pair 151, the main surface 11A of the lower bonding sheet 151A and the semiconductor chip 141 are arranged so that their centers are aligned. In contrast, in each of the bonding sheet pairs 152 and 153, the main surfaces 11A of the lower bonding sheets 152A and 153A and the semiconductor chip 141 are arranged so that their centers are not aligned. In other words, the bonding positions of the lower bonding sheets 151A, 152A, and 153A with their corresponding semiconductor chips 141, 142, and 143 are different. By making the bonding positions different, gaps between the bonding sheet pairs can be eliminated in the space directly above each of the semiconductor chips 141, 142, and 143. As a result, the heat generated in each of the semiconductor chips 141, 142, and 143 can be efficiently transferred to the upper substrate 120, improving heat dissipation. In addition, the mechanical strength and conductivity of the bonding can also be improved.

[0232] As described above, in the semiconductor device 100 according to this embodiment, the bonding states of the bonding sheets 151, 152, and 153 are adjusted based on the height of the upper surfaces of the corresponding semiconductor chips 141, 142, and 143. Therefore, deviations in the height of the upper surfaces of the semiconductor chips 141, 142, and 143 are absorbed. Furthermore, at this time, there are no gaps between the bonding sheets directly above the semiconductor chips 141, 142, and 143, thus enhancing the thermal bonding, electrical bonding, and mechanical bonding between each semiconductor chip and the upper substrate 120. Consequently, heat dissipation, conductivity, and mechanical bonding strength are improved.

[0233] [2-3. Examples of tilted absorption]

[0234] Next, for the absorption example based on the tilt of the bonding sheets to 151, 152, and 153, the following is used: Figure 9 as well as Figure 10 Please provide an explanation.

[0235] Figure 9 This is a cross-sectional view showing another example of a semiconductor device involved in this embodiment. Figure 9 The semiconductor device 101 shown has a similar Figure 6 The semiconductor device 100 shown has the same constituent elements. The orientation and position of the semiconductor chips 142 and 143, and the bonding state of the bonding sheets 152 and 153, are different. Hereinafter, the description will focus on the differences from the semiconductor device 100, and the description of the commonalities will be omitted or simplified.

[0236] exist Figure 9 In this process, the upper surfaces of semiconductor chips 142 and 143 are inclined relative to the upper surface of semiconductor chip 141. The inclination angle of the upper surface of semiconductor chip 143 is greater than the inclination angle of the upper surface of semiconductor chip 142.

[0237] Figure 10 This is a top view showing the bonding state of the plurality of bonding sheet pairs 151, 152, and 153 of the semiconductor device 101 according to this embodiment. Figure 10 In the diagram, the dashed arrows indicate the tilting direction of the bonding sheets (lower bonding sheets 151A, 152A, 153A) that bond to the first components (semiconductor chips 141, 142, 143). The solid arrows indicate the tilting direction of the bonding sheets (upper bonding sheets 151B, 152B, 153B) that bond to the second component (upper substrate 120). The tilting direction is the direction in which the thickness of each bonding sheet decreases (in...). Figure 2 In the example shown, the negative direction of the x-axis is set as the positive direction.

[0238] In the bonding sheet pair 152, such as Figure 9 as well as Figure 10 As shown, bonding sheets 152A and 152B are configured such that one is rotated relative to the other by a rotation angle θ. The rotation angle θ is determined based on the tilt angle of the upper surface of the semiconductor chip 142. Therefore, the first main surface (main surface 11A) of bonding sheet 152A is tilted relative to the first main surface (main surface 11B) of bonding sheet 152B, thus absorbing the tilt of the upper surface of the semiconductor chip 142. That is, the first main surface (main surface 11B) of bonding sheet 152B can be made flush with the first main surface (main surface 11B) of bonding sheet 151B.

[0239] In the joining sheet pair 153, such as Figure 9 as well as Figure 10 As shown, the joint sheets 153A and 153B are configured such that one of them has been rotated 180° relative to the other. Figure 3C(The shown is a bonding state). Here, an example with a rotation angle of 180° is shown, but it can also be less than 180°. Thus, the first main surface (main surface 11B) of the bonding sheet 153A is tilted relative to the first main surface (main surface 11B) of the bonding sheet 153B, thereby absorbing the tilt of the upper surface of the semiconductor chip 143. That is, the first main surface (main surface 11B) of the bonding sheet 153B can be made flush with the first main surface (main surface 11B) of the bonding sheet 151B.

[0240] Even when rotated, gaps between the bonding sheet pairs are not formed in the space directly above semiconductor chips 142 and 143. Specifically, the bonding positions of the main surfaces 11A of bonding sheets 152A and 153A with semiconductor chips 142 and 143 are adjusted. This allows for efficient heat transfer from semiconductor chips 141, 142, and 143 to the upper substrate 120, improving heat dissipation. Furthermore, it also improves the mechanical strength and conductivity of the bond.

[0241] As described above, in the semiconductor device 101 according to this embodiment, the bonding states of the bonding sheets 151, 152, and 153 are adjusted based on the tilt of the upper surfaces of the corresponding semiconductor chips 141, 142, and 143. This absorbs the tilt of the upper surfaces of the semiconductor chips 141, 142, and 143. Furthermore, there are no gaps between the bonding sheets directly above the semiconductor chips 141, 142, and 143, thus enhancing the thermal, electrical, and mechanical bonding between each semiconductor chip and the upper substrate 120. Consequently, heat dissipation, conductivity, and mechanical bonding strength are improved.

[0242] [2-4. Manufacturing Method]

[0243] Next, regarding the manufacturing method of the semiconductor device 100, using Figures 11A to 11E Please provide an explanation.

[0244] Figures 11A to 11E This is a cross-sectional view showing each step of the manufacturing method of the semiconductor device 100 according to this embodiment.

[0245] First, such as Figure 11A As shown, a lower substrate 110 is prepared. For example, after forming a metal film such as copper on both the upper and lower surfaces of the insulating layer 114, the metal film is patterned as needed to fabricate the lower substrate 110. However, the method for fabricating the lower substrate 110 is not limited to this. Alternatively, a pre-fabricated lower substrate 110 may be used.

[0246] Next, as Figure 11BAs shown, bonding members 131, 132, and 133 are disposed on the upper surfaces of electrodes 116, 117, and 118 of the lower substrate 110. The bonding members 131, 132, and 133 are, for example, block-shaped members of silver (Ag) with tin (Sn) coated on the surface (Sn-coated bonding material) or Ag sintering paste.

[0247] Next, as Figure 11C As shown, semiconductor chips 141, 142, and 143 are disposed on the upper surfaces of bonding members 131, 132, and 133, respectively. After the semiconductor chips 141, 142, and 143 are disposed, bonding members 131, 132, and 133 are bonded by heat treatment. The heat treatment is a treatment corresponding to the material of bonding members 131, 132, and 133. For example, when bonding members 131, 132, and 133 are Sn-coated bonding materials, a reflow soldering process using formic acid reduction or hydrogen reduction is performed as the heat treatment. Furthermore, when bonding members 131, 132, and 133 are Ag sintered paste, a reflow soldering or annealing process in a nitrogen environment is performed as the heat treatment. Thus, the lower surfaces of bonding members 131, 132, and 133 are bonded to electrodes 116, 117, and 118, respectively, and the upper surfaces of bonding members 131, 132, and 133 are bonded to semiconductor chips 141, 142, and 143, respectively.

[0248] Next, as Figure 11D As shown, bonding sheet pairs 151, 152, and 153 are disposed on the upper surfaces of semiconductor chips 141, 142, and 143, respectively. Although not shown in the figure, before the placement process of the bonding sheet pairs, at least one of the height and tilt of the upper surfaces of semiconductor chips 141, 142, and 143 is measured. Furthermore, based on the measurement results, the offset direction and offset amount of the second main surfaces (main surfaces 12A and 12B) of the bonding sheet pairs corresponding to each semiconductor chip are determined. In addition, in determining the offset direction and offset amount of the second main surfaces, specifically, the three-dimensional position (x-coordinate, y-coordinate, z-coordinate) and rotation angle (θ) of the placement of each of the two bonding sheets are calculated. Alternatively, the offset direction and offset amount of the second main surfaces can be calculated themselves. Based on the calculated three-dimensional position and rotation angle, the lower bonding sheets 151A, 152A, and 153A and the upper bonding sheets 151B, 152B, and 153B are disposed. Therefore, based on the height and tilt of the upper surface of each semiconductor chip, the second main surfaces of the corresponding bonding sheet pairs are staggered from each other. For example... Figure 11D As shown by the dashed lines, the upper surfaces (main surfaces 11B) of the joining sheets 151, 152 and 153 become flush.

[0249] Next, as Figure 11E As shown, the upper substrate 120 is configured to cover the upper surfaces of each of the bonding sheet pairs 151, 152, and 153. After the upper substrate 120 is configured, the bonding sheet pairs 151, 152, and 153 are bonded by heat treatment. For example, if the bonding sheet of each of the bonding sheet pairs 151, 152, and 153 is a Sn-coated bonding material, a reflow soldering process using formic acid reduction or hydrogen reduction is performed as the heat treatment. This results in the bonding of the first main surface (main surface 11A) of the lower side of each bonding sheet pair to the corresponding semiconductor chip, the bonding of the second main surface (main surface 11B) of the upper side of each bonding sheet pair to the upper substrate 120, and the bonding of the second main surfaces (main surfaces 12A and 12B) of each bonding sheet pair to each other. The positional relationship between the first and second bonding sheets after bonding is fixed, maintaining a stable state. In each joint, an alloy of copper (Cu) and tin (Sn) or an alloy of silver (Ag) and tin (Sn) is formed to achieve a good thermal, mechanical and electrical bond.

[0250] Next, by Figure 11E The structure shown is manufactured by sealing it with a resin or other sealing component 160. Figure 6 or Figure 9 The semiconductor device 100 or 101 shown.

[0251] As described above, by utilizing a coating layer such as Sn provided on the surface of the bonding sheets, the bonding between the bonding sheets and between the bonding sheets and other components can be thermally, electrically, and mechanically strengthened. Therefore, the heat dissipation, conductivity, and mechanical bonding strength of the semiconductor device 100 or 101 can be improved. For example, from the viewpoint of heat dissipation, a heat resistance of 250°C can be achieved.

[0252] (Implementation Method 3)

[0253] Next, implementation method 3 will be described.

[0254] In Embodiment 3, the main difference compared to Embodiment 2 is the structure of the bonding sheet. The following description focuses on the differences from Embodiment 2, omitting or simplifying the description of the commonalities.

[0255] [3-1. Structure]

[0256] First, regarding the structure of the semiconductor device involved in Embodiment 3, using Figure 12 Please provide an explanation.

[0257] Figure 12 This is a cross-sectional view of the semiconductor device 200 according to this embodiment. Figure 12 As shown, semiconductor device 200 and Figure 6 Compared to the semiconductor device 100 shown, the semiconductor device 200 has bonding sheets 251, 252, and 253 instead of bonding sheets 151, 152, and 153. In addition, the semiconductor device 200 has bonding layers 271, 272, 273, 274, 275, 276, 277, 278, and 279.

[0258] like Figure 12 As shown, the bonding sheet pair 251 includes bonding sheets 251A and 251B. The bonding sheet pair 252 includes bonding sheets 252A and 252B. The bonding sheet pair 253 includes bonding sheets 253A and 253B. Bonding sheets 251A, 252A, and 253A are examples of the first bonding sheet, having... Figure 2 The bonding sheet 10 shown has the structures of the coating layers 21 and 22 removed. Bonding sheets 251B, 252B, and 253B are examples of the second bonding sheet, having... Figure 2 The bonding sheet 10 shown has the structures of the coating layers 21 and 22 removed. For example, bonding sheets 251A, 251B, 252A, 252B, 253A and 253B are metal block components made of silver (Ag).

[0259] Bonding layers 271, 272, 273, 274, 275, 276, 277, 278, and 279 are components that join two adjacent components together. Bonding layers 271, 272, 273, 274, 275, 276, 277, 278, and 279 are electrically conductive. For example, bonding layers 271, 272, 273, 274, 275, 276, 277, 278, and 279 are sintered silver (Ag) materials.

[0260] Bonding layer 271 bonds the upper surface of semiconductor chip 141 to the first main surface (main surface 11A) of bonding sheet 251A of bonding sheet pair 251. Bonding layer 272 bonds the upper surface of semiconductor chip 142 to the first main surface (main surface 11A) of bonding sheet 252A of bonding sheet pair 252. Bonding layer 273 bonds the upper surface of semiconductor chip 143 to the first main surface (main surface 11A) of bonding sheet 253A of bonding sheet pair 253.

[0261] Bonding layer 274 bonds the second main surface (main surface 12A) of bonding sheet 251A and the second main surface (main surface 12B) of bonding sheet 251B of bonding sheet pair 251. Bonding layer 275 bonds the second main surface (main surface 12A) of bonding sheet 252A and the second main surface (main surface 12B) of bonding sheet 252B of bonding sheet pair 252. Bonding layer 276 bonds the second main surface (main surface 12A) of bonding sheet 253A and the second main surface (main surface 12B) of bonding sheet 253B of bonding sheet pair 253.

[0262] Bonding layer 277 bonds the first main surface (main surface 11B) of bonding sheet 251 of bonding sheet pair 251 to the electrode 126 of upper substrate 120. Bonding layer 278 bonds the first main surface (main surface 11B) of bonding sheet 252 of bonding sheet pair 252 to the electrode 126 of upper substrate 120. Bonding layer 279 bonds the first main surface (main surface 11B) of bonding sheet 253 of bonding sheet pair 253 to the electrode 126 of upper substrate 120.

[0263] exist Figure 12 In the semiconductor device 200 shown, with Figure 6 Similarly, the semiconductor device 100 shown also configures the bonding sheets 251, 252, and 253 to have different bonding states, thereby absorbing height variations on the upper surfaces of the semiconductor chips 141, 142, and 143. The bonding states of the bonding sheets 251, 252, and 253 are similar to those of the bonding layers 274, 275, or 276 disposed in the middle. Figure 6 as well as Figure 8 The bonding states of the bonding sheets 151, 152 and 153 shown are the same.

[0264] In addition, Figure 13 The image shows an example of the tilting of the upper surfaces of the absorbing semiconductor chips 141, 142, and 143. Figure 13 This is a cross-sectional view showing another example of a semiconductor device involved in this embodiment. Figure 13 The semiconductor device 201 shown has a similar Figure 12 The semiconductor device 200 shown has the same constituent elements.

[0265] exist Figure 13 In the semiconductor device 201 shown, with Figure 9 Similarly, the semiconductor device 101 shown is configured such that the bonding sheets 251, 252, and 253 are arranged in different bonding states, thereby tilting the upper surfaces of the absorbing semiconductor chips 141, 142, and 143. The bonding states of the bonding sheets 251, 252, and 253 are similar to those of the bonding layers 274, 275, or 276 disposed in the middle. Figure 9as well as Figure 10 The bonding states of the bonding sheets 151, 152 and 153 shown are the same.

[0266] [3-2. Manufacturing Method]

[0267] Next, regarding the manufacturing method of the semiconductor device 200, using Figures 14A to 14F Please provide an explanation.

[0268] Figures 14A to 14F This is a cross-sectional view showing each step of the manufacturing method of the semiconductor device 200 according to this embodiment. In the manufacturing method of the semiconductor device 200, the processes from the preparation of the lower substrate 110 to the placement of semiconductor chips 141, 142, and 143 and their bonding with bonding members 131, 132, and 133 are the same as in Embodiment 2, as follows: Figures 11A to 11C As shown.

[0269] After the semiconductor chips 141, 142, and 143 are bonded to the bonding members 131, 132, and 133, as Figure 14A As shown, bonding layers 271, 272, and 273 are respectively disposed on the upper surfaces of semiconductor chips 141, 142, and 143. Bonding layers 271, 272, and 273 are, for example, Ag sintering paste. For example, Ag sintering paste is applied to cover the entire upper surface of each of semiconductor chips 141, 142, and 143.

[0270] Next, as Figure 14B As shown, bonding sheets 251A, 252A, and 253A are disposed on the upper surfaces of bonding layers 271, 272, and 273, respectively. Additionally, although not shown in the figure, before the bonding sheet disposal process, at least one of the height and tilt of the upper surfaces of semiconductor chips 141, 142, and 143 is measured. Furthermore, based on the measurement results, the offset direction and offset amount of the second main surfaces (main surfaces 12A and 12B) of the bonding sheet pair corresponding to each semiconductor chip are determined. Specifically, in determining the offset direction and offset amount of the second main surfaces, the three-dimensional position (x-coordinate, y-coordinate, z-coordinate) and rotation angle (θ) of each of the two bonding sheets are calculated. Alternatively, the offset direction and offset amount of the second main surfaces themselves can also be calculated. Based on the calculated three-dimensional position and rotation angle, the lower bonding sheets 251A, 252A, and 253A are disposed sequentially.

[0271] Next, as Figure 14CAs shown, bonding layers 274, 275, and 276 are respectively disposed on the second main surface (main surface 12A) of each of the bonding sheets 251A, 252A, and 253A. Bonding layers 274, 275, and 276 are, for example, Ag sintering paste. For example, Ag sintering paste is applied such that it covers the entire second main surface (main surface 12A) of each of the bonding sheets 251A, 252A, and 253A.

[0272] Next, as Figure 14D As shown, bonding sheets 251B, 252B, and 253B are disposed on the upper surfaces of bonding layers 274, 275, and 276, respectively. The placement (three-dimensional position and rotation angle) of bonding sheets 251B, 252B, and 253B is determined based on measurements of at least one of the height and tilt of the upper surfaces of semiconductor chips 141, 142, and 143. Based on the height and tilt of the upper surfaces of each semiconductor chip, the second main surfaces of the corresponding bonding sheet pairs are staggered, thus making the upper surfaces (main surfaces 11B) of bonding sheet pairs 251, 252, and 253 flush.

[0273] Next, as Figure 14E As shown, bonding layers 277, 278, and 279 are respectively disposed on the first main surface (main surface 11B) of each of the bonding sheets 251B, 252B, and 253B. Bonding layers 277, 278, and 279 are, for example, Ag sintering paste. For example, Ag sintering paste is applied such that it covers the entire first main surface (main surface 11B) of each of the bonding sheets 251B, 252B, and 253B.

[0274] Next, as Figure 14F As shown, an upper substrate 120 is configured to cover the upper surfaces of each of the bonding sheet pairs 251, 252, and 253. After the upper substrate 120 is configured, the bonding sheets 251, 252, and 253 are bonded by heat treatment. In this embodiment, reflow soldering or annealing in a nitrogen environment is performed as the heat treatment. Thus, the bonding of the first main surface (main surface 11A) of the lower first bonding sheet to the corresponding semiconductor chip, the bonding of the second main surface (main surface 11B) of the upper second bonding sheet of each bonding sheet pair to the upper substrate 120, and the bonding of the second main surfaces (main surfaces 12A and 12B) of each bonding sheet pair to each other are performed via bonding layers 271, 272, 273, 274, 275, 276, 277, 278, and 279, respectively. The positional relationship between the first and second bonding sheets after bonding is fixed, maintaining a stable state. In each joint, a sintered layer of silver (Ag) is formed, achieving good thermal, mechanical, and electrical bonding.

[0275] Next, by Figure 14FThe structure shown is manufactured by sealing it with a resin or other sealing component 160. Figure 12 or Figure 13 The semiconductor device 200 or 201 shown.

[0276] As described above, even without tin (Sn) coating on the surface of the bonding sheets, the thermal, electrical, and mechanical properties of the bonding between the bonding sheets and between the bonding sheets and other components can be enhanced by using bonding layers such as Ag sintering paste. Therefore, heat dissipation, electrical conductivity, and mechanical bond strength can be improved.

[0277] (Implementation Method 4)

[0278] Next, implementation method 4 will be described.

[0279] In Embodiment 4, the main difference compared to Embodiment 2 is the structure of the semiconductor chip. The following description focuses on the differences from Embodiment 2, omitting or simplifying the description of the commonalities.

[0280] [4-1. Structure]

[0281] First, regarding the structure of the semiconductor device involved in Embodiment 4, using Figure 15 Please provide an explanation.

[0282] Figure 15 This is a cross-sectional view of the semiconductor device 300 according to Embodiment 4. Figure 15 As shown, semiconductor device 300 and Figure 6 Compared to the semiconductor device 100 shown, semiconductor chips 341, 342, and 343 are provided instead of semiconductor chips 141, 142, and 143. Furthermore, on the lower substrate 110, besides… Figure 6 In addition to the structure shown, electrodes 381, 382, ​​and 383 are also provided. Furthermore, the semiconductor device 300 also includes leads 391, 392, and 393.

[0283] Semiconductor chips 341, 342, and 343 are examples of first components serving as semiconductor elements. Semiconductor chips 341, 342, and 343 are positioned between the lower substrate 110 and the upper substrate 120 such that they do not overlap when viewed from above the lower substrate 110. In this embodiment, semiconductor chips 341, 342, and 343 are each elements having three electrodes.

[0284] Figure 16These are (a) a top view, (b) a side view, and (c) a bottom view showing the structure of semiconductor chips 341, 342, and 343 of the semiconductor device 300 according to this embodiment. Semiconductor chips 341, 342, and 343 are specific examples of semiconductor chip 40 shown in Embodiment 1. Since they have the same structure as each other, semiconductor chip 341 will be used as an example in the following description.

[0285] Semiconductor chip 341 is, for example, a semiconductor device with three external electrodes, such as a field-effect transistor (FET) or an insulated-gate bipolar transistor (IGBT). Figure 16 As shown, the semiconductor chip 341 has a chip body 345, a lower surface electrode 346, and upper surface electrodes 347 and 348.

[0286] The chip body 345 is the main body of a device formed on a substrate containing silicon carbide (SiC), silicon (Si), gallium nitride (GaN), gallium oxide (GaO), or diamond as the main component. The chip body 345 has a flat cuboid shape. The size of the chip body 345 is not particularly limited, but the length of one side is in the range of 1 mm or more and 20 mm or less, and the thickness is 0.01 mm or more and 0.5 mm or less.

[0287] The lower surface electrode 346 is disposed on the lower surface of the chip body 345. The lower surface electrode 346 has a single-layer structure or a multi-layer structure of a metal monomer or metal alloy. For example, the lower surface electrode 346 has a stacked structure of titanium (Ti), nickel (Ni), and silver (Ag) arranged sequentially from the chip body 345 side, but is not limited thereto. For example, the outermost layer (bottom layer) of the lower surface electrode 346 may also be gold (Au).

[0288] Upper surface electrodes 347 and 348 are disposed on the upper surface of the chip body 345. Upper surface electrodes 347 and 348 each have a single-layer or multi-layer structure of a metal monomer or metal alloy. For example, upper surface electrodes 347 and 348 may have a stacked structure of titanium (Ti), nickel (Ni), and silver (Ag) arranged sequentially from the chip body 345 side, but are not limited to this. For example, the outermost surface (uppermost layer) of each of the upper surface electrodes 347 and 348 may also be gold (Au).

[0289] When the semiconductor chip 341 is a transistor, the lower surface electrode 346, upper surface electrode 347, and 348 correspond to the gate electrode, source electrode, and drain electrode, or the base electrode, emitter electrode, or collector electrode, respectively. For example, the lower surface electrode 346 is the drain electrode, the upper surface electrode 347 is the source electrode, and the upper surface electrode 348 is the gate electrode. The lower surface electrode 346 is configured to cover approximately the entire lower surface of the chip body 345. The upper surface electrodes 347 and 348 are configured to cover approximately the entire chip body 345 such that they do not contact each other. The upper surface of the upper surface electrode 347 is the upper surface of the semiconductor chip 341 and is connected to the first main surface (main surface 11A) of the corresponding bonding sheet pair 30 (bonding sheet pair 151, 152, or 153). The upper surface electrode 348 is connected to the electrodes 381, 382, ​​or 383 of the lower substrate 110 via leads 391, 392, or 393.

[0290] Electrodes 381, 382, ​​and 383 correspond one-to-one with semiconductor chips 341, 342, and 343, respectively. Furthermore, electrodes 381, 382, ​​and 383 can be electrically connected to each other, or to at least one of electrodes 116, 117, and 118. Electrodes 381, 382, ​​and 383 contain a conductive material as their main component. For example, electrodes 381, 382, ​​and 383 are made of a metal such as copper (Cu).

[0291] Leads 391, 392, and 393 are conductive wires. Leads 391, 392, and 393 are formed, for example, using metals such as gold (Au), copper (Cu), or aluminum (Al).

[0292] like Figure 15 As shown, lead 391 connects the upper surface electrode 348 of semiconductor chip 341 (in... Figure 15 (Not shown in the diagram) and the electrode 381 of the lower substrate 110 are electrically connected. Lead 392 connects the upper surface electrode 348 of the semiconductor chip 342 (in...) Figure 15 (Not shown in the diagram) and the electrode 382 of the lower substrate 110 are electrically connected. Lead 393 connects the upper surface electrode 348 of the semiconductor chip 343 (in...) Figure 15 (Not shown in the figure) and the electrode 383 of the lower substrate 110 are electrically connected.

[0293] exist Figure 15 In the semiconductor device 300 shown, with Figure 6Similarly, in the semiconductor device 100 shown, the bonding sheets 151, 152, and 153 are configured with different bonding states to absorb height variations on the upper surfaces of the semiconductor chips 341, 342, and 343. At this time, to ensure the connection portions of the leads 391, 392, and 393, the bonding sheets 151, 152, and 153 are configured not to cover the upper surface electrodes 348 of the semiconductor chips 341, 342, and 343.

[0294] In addition, Figure 17 The image shows an example of the tilting of the upper surfaces of the absorbing semiconductor chips 341, 342, and 343. Figure 17 This is a cross-sectional view showing another example of a semiconductor device involved in this embodiment. Figure 17 The semiconductor device 301 shown has a similar Figure 15 The semiconductor device 300 shown has the same constituent elements.

[0295] exist Figure 17 In the semiconductor device 301 shown, with Figure 9 Similarly, in the semiconductor device 101 shown, the bonding sheets 151, 152, and 153 are configured with different bonding states, such that the upper surfaces of the absorbing semiconductor chips 341, 342, and 343 are tilted. At this time, to ensure the connection portions of the leads 391, 392, and 393, the bonding sheets 151, 152, and 153 are configured not to cover the upper surface electrodes 348 of the semiconductor chips 341, 342, and 343 respectively.

[0296] As described above, in the semiconductor device 300 or 301 according to this embodiment, a portion of the upper surface of each semiconductor chip is not covered by the bonding sheet. This allows it to be applied even when multiple electrodes are provided on the upper surface of the semiconductor chip. Furthermore, this embodiment shows an example where the multiple semiconductor chips in the semiconductor device 300 or 301 are of the same type of semiconductor element, but it is not limited to this. The semiconductor device 300 or 301 may also include multiple semiconductor elements of different types. For example, the semiconductor device 300 or 301 may also include semiconductor chip 141 and semiconductor chip 341. Different types of semiconductor chips sometimes have different heights. By adjusting the arrangement of the bonding sheet according to the type of semiconductor chip, height deviations and tilts can be absorbed even when different types of semiconductor chips are provided.

[0297] [4-2. Manufacturing Method]

[0298] Next, regarding the manufacturing method of the semiconductor device 300, using... Figures 18A to 18F Please provide an explanation.

[0299] Figures 18A to 18F This is a cross-sectional view showing each step of the manufacturing method of the semiconductor device 300 according to this embodiment.

[0300] First, such as Figure 18A As shown, a lower substrate 110 is prepared. For example, after forming a metal film such as copper on the upper and lower surfaces of the insulating layer 114, the metal film is patterned as needed to fabricate the lower substrate 110. However, the method for fabricating the lower substrate 110 is not limited to this. Alternatively, a pre-fabricated lower substrate 110 may be used. In this embodiment, electrodes 116, 117, and 118 are provided not only on the upper surface of the insulating layer 114, but also electrodes 381, 382, ​​and 383.

[0301] Next, as Figure 18B As shown, bonding members 131, 132, and 133 are disposed on the upper surfaces of electrodes 116, 117, and 118 of the lower substrate 110. The bonding members 131, 132, and 133 are, for example, block members of silver (Ag) with tin (Sn) coated on the surface (Sn-coated bonding material) or Ag sintering paste.

[0302] Next, as Figure 18C As shown, semiconductor chips 341, 342, and 343 are disposed on the upper surfaces of bonding members 131, 132, and 133, respectively. After the semiconductor chips 341, 342, and 343 are disposed, bonding members 131, 132, and 133 are bonded by heat treatment. Thus, the lower surfaces of bonding members 131, 132, and 133 are bonded to electrodes 116, 117, and 118, respectively, and the upper surfaces of bonding members 131, 132, and 133 are bonded to semiconductor chips 341, 342, and 343, respectively.

[0303] Next, as Figure 18D As shown, the upper surface electrodes 348 (not shown) on the upper surfaces of semiconductor chips 341, 342, and 343 are respectively bonded to the electrodes 381, 382, ​​and 383 of the lower substrate 110 using leads 391, 392, and 393. The bonding of leads 391, 392, and 393 is performed using known wire bonding techniques.

[0304] Next, as Figure 18EAs shown, bonding sheet pairs 151, 152, and 153 are disposed on the upper surfaces of semiconductor chips 341, 342, and 343, respectively. Although not shown in the figure, before the placement of the bonding sheet pairs, at least one of the height and tilt of the upper surfaces of semiconductor chips 341, 342, and 343 is measured. Furthermore, based on the measurement results, the offset direction and offset amount of the second main surfaces (main surfaces 12A and 12B) of the bonding sheet pairs corresponding to each semiconductor chip are determined. In addition, in determining the offset direction and offset amount of the second main surfaces, specifically, the three-dimensional position (x-coordinate, y-coordinate, z-coordinate) and rotation angle (θ) of the placement of each of the two bonding sheets are calculated. Alternatively, the offset direction and offset amount of the second main surfaces can be calculated themselves. Based on the calculated three-dimensional position and rotation angle, the lower bonding sheets 151A, 152A, and 153A and the upper bonding sheets 151B, 152B, and 153B are disposed sequentially. Therefore, based on the height and tilt of the upper surface of each semiconductor chip, the second main surfaces of the corresponding bonding sheet pairs are staggered from each other. For example... Figure 18E As shown by the dashed lines, the upper surfaces (main surfaces 11B) of the joining sheets 151, 152 and 153 become flush.

[0305] Next, as Figure 18F As shown, the upper substrate 120 is configured to cover the upper surfaces of each of the bonding sheet pairs 151, 152, and 153. After the upper substrate 120 is configured, the bonding sheet pairs 151, 152, and 153 are bonded by heat treatment. For example, if the bonding sheet of each of the bonding sheet pairs 151, 152, and 153 is a Sn-coated bonding material, a reflow soldering process using formic acid reduction or hydrogen reduction is performed as the heat treatment. This results in the bonding of the first main surface (main surface 11A) of the lower side of each bonding sheet pair to the corresponding semiconductor chip, the bonding of the second main surface (main surface 11B) of the upper side of each bonding sheet pair to the upper substrate 120, and the bonding of the second main surfaces (main surfaces 12A and 12B) of each bonding sheet pair to each other. The positional relationship between the first and second bonding sheets after bonding is fixed, maintaining a stable state. In each joint, an alloy of copper (Cu) and tin (Sn) or an alloy of silver (Ag) and tin (Sn) is formed, achieving a good thermal, mechanical, and electrical bond.

[0306] Next, by Figure 18F The structure shown is manufactured by sealing it with a resin or other sealing component 160. Figure 15 or Figure 17 The semiconductor device 300 or 301 shown.

[0307] Alternatively, in the same manner as in Embodiment 3, bonding sheets 251, 252, and 253, and bonding layers 271, 272, 273, 274, 275, 276, 277, 278, and 279 may be provided instead of bonding sheets 151, 152, and 153.

[0308] (Implementation Method 5)

[0309] Next, implementation method 5 will be described.

[0310] In Embodiment 5, the main difference compared to Embodiment 4 is that the bonding sheets are used to bond the spacer and the upper substrate. The following description focuses on the differences from Embodiment 4, omitting or simplifying the description of commonalities.

[0311] First, regarding the structure of the semiconductor device involved in Embodiment 5, using Figure 19 Please provide an explanation.

[0312] Figure 19 This is a cross-sectional view of the semiconductor device 400 according to Embodiment 5. (As shown) Figure 19 As shown, the semiconductor device 400, in addition to Figure 15 In addition to the structure of the semiconductor device 300 shown, it also includes spacers 441, 442 and 443, and bonding layers 471, 472 and 473.

[0313] Spacers 441, 442, and 443 are examples of the first components that are bonded to the bonding sheet. Spacers 441, 442, and 443 are provided for height adjustment or to ensure space for bonding leads. To ensure the connection portions of leads 391, 392, and 393, spacers 441, 442, and 443 do not cover the upper surface electrodes 348 of each of the semiconductor chips 341, 342, and 343.

[0314] Spacers 441, 442, and 443 are formed using a conductive material. Specifically, spacers 441, 442, and 443 contain a metal as the main component. For example, spacers 441, 442, and 443 are made of metal monomers or alloys such as copper (Cu), molybdenum (Mo), aluminum (Al), or silicon (Si). As alloys, for example, Cu-Mo alloys or Al-Si alloys are used. Alternatively, spacers 441, 442, and 443 may also be made of graphite. Furthermore, a coating layer (plating layer) of tin (Sn), silver (Ag), or gold (Au) may be formed on the surface of spacers 441, 442, and 443.

[0315] Bonding layers 471, 472, and 473 are components that mechanically, thermally, and electrically bond two adjacent components together. Bonding layers 471, 472, and 473 are electrically conductive. For example, bonding layers 471, 472, and 473 are sintered silver (Ag) materials.

[0316] Bonding layer 471 bonds the upper surface (upper surface electrode 347) of semiconductor chip 341 to the lower surface of spacer 441. Bonding layer 472 bonds the upper surface (upper surface electrode 347) of semiconductor chip 342 to the lower surface of spacer 442. Bonding layer 473 bonds the upper surface (upper surface electrode 347) of semiconductor chip 343 to the lower surface of spacer 443.

[0317] By adjusting the shape and thickness of spacers 441, 442, and 443, deviations in the arrangement of semiconductor chips 341, 342, and 343 (deviations in the height and tilt of each upper surface) can be absorbed. However, some deviations in the arrangement of semiconductor chips 341, 342, and 343 are due to issues with mounting accuracy, making it difficult to prepare spacers of appropriate shape and thickness in advance. Therefore, in this embodiment, bonding sheets 151, 152, and 153 are also disposed between the corresponding spacers and the upper substrate 120. This absorbs deviations in the arrangement of the spacers (semiconductor chips), improving heat dissipation and conductivity.

[0318] Specifically, in Figure 19 In the semiconductor device 400 shown, with Figure 6 Similarly, the semiconductor device 100 shown also configures the bonding sheets 151, 152, and 153 with different bonding states to absorb height variations on the upper surfaces of the semiconductor chips 341, 342, and 343. The bonding states of the bonding sheets 151, 152, and 153 are different except that the bonding objects are spacers 441, 442, and 443 instead of semiconductor chips. Figure 6 as well as Figure 8 The bonding states of the bonding sheets 151, 152 and 153 shown are the same.

[0319] In addition, Figure 20 The image shows an example of the tilting of the upper surfaces of the absorbing semiconductor chips 341, 342, and 343. Figure 20 This is a cross-sectional view showing another example of a semiconductor device involved in this embodiment. Figure 20 The semiconductor device 401 shown has a similar Figure 19 The semiconductor device 400 shown has the same constituent elements.

[0320] exist Figure 20 In the semiconductor device 401 shown, and Figure 9 Similarly, the semiconductor device 101 shown also configures the bonding sheets 151, 152, and 153 to have different bonding states, thereby tilting the upper surfaces of the semiconductor chips 341, 342, and 343. The bonding states of the bonding sheets 151, 152, and 153 are different except that the bonding objects are spacers 441, 442, and 443 instead of semiconductor chips. Figure 9 as well as Figure 10 The bonding states of the bonding sheets 151, 152 and 153 shown are the same.

[0321] The manufacturing method of the semiconductor device 400 or 401 involved in this embodiment is the same as the manufacturing method shown in Embodiments 2 to 4, so the description is omitted.

[0322] Alternatively, similar to Embodiment 3, bonding sheets 251, 252, and 253, and bonding layers 271, 272, 273, 274, 275, 276, 277, 278, and 279 may be provided instead of bonding sheets 151, 152, and 153. Furthermore, semiconductor chips 141, 142, or 143 may be provided instead of at least one of semiconductor chips 341, 342, and 343.

[0323] (Implementation Method 6)

[0324] Next, implementation method 6 will be described.

[0325] In Embodiment 6, the manufacturing apparatus for the semiconductor device according to Embodiments 2 to 5 will be described. Hereinafter, the description will focus on the differences from Embodiments 1 to 5, and the description of the commonalities will be omitted or simplified.

[0326] Figure 21 This is a block diagram of a semiconductor device manufacturing apparatus 500 according to this embodiment. Figure 21 As shown, the manufacturing apparatus 500 includes a first mounting section 510, a second mounting section 520, and a measuring section 530.

[0327] The first mounting section 510 and the second mounting section 520 are each implemented by a component mounting device. Furthermore, the first mounting section 510 and the second mounting section 520 can be implemented by one component mounting device, or by multiple component mounting devices. The component mounting device may also be equipped with a reflow oven or a high-temperature oven for heat treatment.

[0328] The measuring unit 530 measures at least one of the height and tilt of the upper surface of the first component. The measuring unit 530 is, for example, an optical ranging device that measures the distance to the measuring position on the upper surface of the first component by illuminating light at that position and detecting the reflected light. Alternatively, the measuring unit 530 can also be a camera that captures images of the upper surface of the first component. The structure of the measuring unit 530 is not particularly limited as long as it can measure at least one of the height and tilt of the upper surface of the first component.

[0329] The specific processing and use of the first mounting section 510, the second mounting section 520, and the measuring section 530 Figure 22 as well as Figures 23A to 23K Please provide an explanation.

[0330] Figure 22 This is a flowchart illustrating a method for manufacturing a semiconductor device according to this embodiment. Figures 23A to 23K These are cross-sectional views used to explain each step of the operation of the semiconductor device manufacturing apparatus according to this embodiment.

[0331] like Figure 22 As shown, firstly, one or more bonding sheet pairs 30 are prepared (S10). For example, the manufacturing apparatus 500 may also include a manufacturing section for manufacturing the bonding sheet 10. The manufacturing section forms the substrate 20 by forming it using a mold, and forms the coating layers 21 and 22 by plating on its surface. Alternatively, plating may not be performed.

[0332] Next, a first substrate (S12) is prepared with one or more first components (semiconductor chips or spacers). The first component is a semiconductor chip or a spacer. For example, such as Figure 23A As shown, the manufacturing apparatus 500 prepares the lower substrate 110 and assembles the bonding members 131 and 132. The assembly of the bonding members 131 and 132 is performed through printing, coating using a dispenser, or mounting of sheet components, etc. Next, as... Figure 23B As shown, semiconductor chips 141 and 142 are held by suction nozzles 601 and 602. Semiconductor chips 141 and 142 are positioned in a given storage location such as a tray. Suction nozzles 601 and 602 pick up the semiconductor chips one by one from the tray and hold them, moving them to the mounting position. Then, as... Figure 23C As shown, semiconductor chips 141 and 142 are disposed on the upper surfaces of bonding members 131 and 132 respectively (de-adhesion). Subsequently, semiconductor chips 141 and 142 are bonded to bonding members 131 and 132 by heat treatment. Additionally, suction nozzles 601 and 602 are included in the first mounting portion 510 or the second mounting portion 520. The placement of the components and the heat treatment are performed, for example, through the first mounting portion 510 or the second mounting portion 520.

[0333] exist Figure 23D The image shows an example where the height and tilt of the upper surfaces of semiconductor chips 141 and 142 deviate. This deviation may be caused by the configuration of bonding members 131 and 132, the mounting of semiconductor chips 141 and 142, and heat treatment, etc.

[0334] Next, the measuring unit 530 measures the height of the upper surface of the first member and at least one of its inclination (S14). For example, as... Figure 23E As shown, laser displacement gauges 611 and 612 are respectively as follows: Figure 4A The three-dimensional positions (x-coordinate, y-coordinate, z-coordinate) of four points on the upper surfaces of semiconductor chips 141 and 142 are measured as shown, and the height and tilt of the upper surfaces are calculated based on the measurement results. Laser displacement gauges 611 and 612 are examples of the measuring unit 530. Furthermore, based on the calculation results, the manufacturing apparatus 500 determines the offset direction and offset amount of the second main surfaces of the corresponding bonding sheet pair 30. Specifically, the manufacturing apparatus 500 determines the arrangement position and orientation (rotation angle) of the first and second bonding sheets. For example, the manufacturing apparatus 500 includes a non-volatile memory storing the program for calculation and determination, a volatile memory serving as a transient storage area for executing the program, input / output ports, a processor for executing the program, etc. Alternatively, in the calculation and determination, the program may not be executed by a processor, but by electronic circuits implemented with integrated circuits or the like in hardware.

[0335] Next, the first mounting portion 510 arranges a pair of sheets, namely the bonding sheet pair including the first bonding sheet and the second bonding sheet, on the upper surface of the first member in a state offset in an inclined direction and / or rotational direction (S16). When multiple first members (semiconductor chips or spacers) are provided on the first substrate, the first mounting portion 510 aligns the multiple bonding sheet pairs with each of the multiple first members and arranges them on the upper surface of the corresponding first member. For example, the first mounting portion 510 arranges the bonding sheet pairs on the upper surface of the corresponding semiconductor chip. At this time, the first mounting portion 510 arranges the second main surfaces of the first bonding sheet and the second bonding sheet offset from each other based on the height of the upper surface of the first member measured by the measuring portion 530 and at least one of the inclination.

[0336] Specifically, such as Figure 23F As shown, suction nozzles 621 and 622 hold the bonding sheets 151A and 152A. The bonding sheets 151A and 152A are positioned in a given storage location such as a tray. Suction nozzles 621 and 622 pick up the bonding sheets one by one from the tray and hold them, moving them to the installation position. Then, as... Figure 23GAs shown, bonding sheets 151A and 152A are disposed on the upper surfaces of semiconductor chips 141 and 142 respectively (de-adhesion). At this time, bonding sheets 151A and 152A are disposed at a position and orientation (rotation angle) determined based on measurement results. Similarly, as... Figure 23H As shown, suction nozzles 621 and 622 hold the bonding sheets 151B and 152B. The bonding sheets 151B and 152B are positioned in a given storage location such as a tray. Suction nozzles 621 and 622 pick up the bonding sheets one by one from the tray and hold them, moving them to the installation position. Then, as... Figure 23I As shown, bonding sheets 151B and 152B are disposed on the upper surfaces of semiconductor chips 141 and 142 respectively (de-adhesion). At this time, bonding sheets 151B and 152B are disposed at a position and orientation (rotation angle) determined based on measurement results.

[0337] Next, the second mounting portion 520 is configured with a second substrate as a second member, such that one or more pairs of bonding sheets are covered (S18). For example, the second mounting portion 520 is configured with an upper substrate 120, such that multiple pairs of bonding sheets are covered. Specifically, as... Figure 23J As shown, the upper substrate 120 is held by a suction nozzle 630. The upper substrate 120 is positioned in a given storage location such as a tray. The suction nozzle 630 picks up the upper substrate 120 from the tray and holds it, moving it to the mounting position. Then, as... Figure 23K As shown, the upper substrate 120 is disposed on the upper surfaces of the bonding sheets 151B and 152B respectively (de-adhesion). Then, through heat treatment, the semiconductor chip 141, bonding sheets 151A and 151B, and the semiconductor chip 142, bonding sheets 152A and 152B are respectively bonded, and the bonding sheets 151B and 152B are bonded to the upper substrate 120. If necessary, the lower substrate 110 and the upper substrate 120 can be molded together using resin or the like, thereby manufacturing a semiconductor device.

[0338] As described above, the distance and inclination of the first main surface of the first bonding sheet and the first main surface of the second bonding sheet can be changed by adjusting the positional relationship between the second main surfaces of the first bonding sheet and the second bonding sheet. Therefore, by arranging the first bonding sheet and the second bonding sheet in an appropriate positional relationship according to the configuration state of the first member, deviations in the configuration of the first member can be absorbed.

[0339] (Other implementation methods)

[0340] The foregoing has described, based on embodiments, bonding sheets, semiconductor devices, methods for manufacturing semiconductor devices, and apparatus for manufacturing semiconductor devices, involving one or more methods, but this disclosure is not limited to these embodiments. Various modifications to these embodiments that would be conceived by those skilled in the art, as well as combinations of constituent elements from different embodiments, are also included within the scope of this disclosure, provided they do not depart from its spirit.

[0341] For example, in the embodiments described above, a cuboid-shaped joining sheet with one main surface inclined relative to another main surface is used as an example, but the shape of the joining sheet is not limited to this. For example, the joining sheet can also be as follows: Figure 24 As shown in the joining sheets 50A and 50B, they have a shape in which one main surface (upper surface) of a flat cylinder is inclined relative to the other main surface (lower surface). Additionally, Figure 24 This is a perspective view showing a modified example of the joint sheet 50.

[0342] Alternatively, the joining sheets can also have a shape in which one main face (upper surface) of a flattened elliptical cylinder is inclined relative to another main face (lower surface). Furthermore, the joining sheets can also have a shape in which one main face (upper surface) of a flattened polygonal prism, such as a pentagonal prism, hexagonal prism, or octagonal prism, is inclined relative to another main face (lower surface). Additionally, the joining sheets can also have a shape in which one main face (upper surface) of a flattened frustum of a polygon is inclined relative to another main face (lower surface). A pair of joining sheets can also comprise two joining sheets of different shapes and sizes.

[0343] For example, in the embodiments described above, the case where the main surface 11 is a first main surface that joins with the first member or the second member has been described, but it is not limited thereto. The main surface 12 may also be an example of a first main surface that joins with the first member or the second member. In this case, the main surface 11 becomes an example of a second main surface. That is, in the two joining sheets 10, the main surfaces 11 are joined to each other.

[0344] Furthermore, while an example of a one-to-one correspondence between a semiconductor chip and a bonding sheet has been described, this is not a limitation. For example, multiple bonding sheet pairs may be provided on the upper surface of the semiconductor chip. Alternatively, if the upper surfaces of multiple semiconductor chips have the same height and inclination, one bonding sheet pair may be provided to each upper surface of the multiple semiconductor chips.

[0345] Furthermore, for example, the number of semiconductor chips (first components) included in the semiconductor device may be only one. If the upper surface of the single semiconductor chip is tilted, the tilt can be absorbed by using a pair of bonding sheets. That is, the lower substrate (first substrate) and the upper substrate (second substrate) can be arranged in parallel.

[0346] Furthermore, the above-described embodiments can be modified, substituted, added, omitted, etc., within the scope of the claims or their equivalents.

[0347] Industrial availability

[0348] This disclosure can be used as a bonding sheet, a semiconductor device, a method for manufacturing a semiconductor device, and an apparatus for manufacturing a semiconductor device, for example, in semiconductor devices such as power modules.

[0349] Explanation of reference numerals in the attached figures

[0350] 10, 10A, 10B, 50A, 50B, 151A, 151B, 152A, 152B, 153A, 153B, 251A, 251B, 252A, 252B, 253A, 253B Jointed Sheets

[0351] 11, 11A, 11B, 12, 12A, 12B, 13, 14 Main face

[0352] 20 Substrate

[0353] 21, 22 Covering layers

[0354] 30, 50, 151, 152, 153, 251, 252, 253 joint sheet pairs

[0355] Semiconductor chips 40, 141, 142, 143, 341, 342, 343

[0356] 100, 101, 200, 201, 300, 301, 400, 401 Semiconductor Devices

[0357] 110 lower base plate

[0358] 112, 122 heat sink

[0359] 114, 124 Insulation Layer

[0360] Electrodes 116, 117, 118, 126, 381, 382, ​​383

[0361] 120 upper base plate

[0362] 131, 132, 133 Joint components

[0363] 145 and 345 chip main body

[0364] 146, 346 Lower surface electrodes

[0365] 147, 347, 348 Upper surface electrodes

[0366] 160 Sealing Components

[0367] Bonding layers 271, 272, 273, 274, 275, 276, 277, 278, 279, 471, 472, 473

[0368] Lead wires 391, 392, and 393

[0369] Spacers 441, 442, and 443

[0370] 500 manufacturing unit

[0371] 510 First Installation Department

[0372] 520 Second Installation Department

[0373] 530 Measurement Department

[0374] 601, 602, 621, 622, 630 suction nozzles

[0375] 611, 612 Laser displacement gauges.

Claims

1. A joining sheet, which is one of a pair of sheets joining a first member and a second member, comprising: a first main surface joining the first member or the second member; and a second main surface located on the opposite side of the first main surface, the second main surface being inclined with respect to the first main surface, the joining sheet having electrical conductivity.

2. The joining sheet according to claim 1, wherein: a metal layer having a third main surface and a fourth main surface located on the opposite side of the third main surface; a first coating layer coating at least a portion of the third main surface; and a second coating layer coating at least a portion of the fourth main surface, the first main surface being a portion of a surface of the first coating layer, the second main surface being a portion of a surface of the second coating layer.

3. The joining sheet according to claim 2, wherein: the first coating layer and the second coating layer each contain tin or a tin alloy as a main component.

4. The joining sheet according to claim 2, wherein: the third main surface is parallel to the first main surface, the fourth main surface is parallel to the second main surface.

5. A semiconductor device comprising: a pair of sheets including a first joining sheet and a second joining sheet each being the joining sheet according to any one of claims 1 to 4; the first member; and the second member, the first member being a semiconductor element or a spacer, the first main surface of the first joining sheet joining the first member, the first main surface of the second joining sheet joining the second member, the second main surface of each of the first joining sheet and the second joining sheet joining each other.

6. The semiconductor device according to claim 5, wherein: the second member is a substrate or a spacer.

7. The semiconductor device according to claim 5, wherein: the first main surface of the first joining sheet is larger than the first member in plan view of the first main surface.

8. The semiconductor device according to claim 5, comprising: a first substrate; a second substrate disposed in parallel to the first substrate, the second substrate being the second member; a plurality of the first members disposed between the first substrate and the second substrate so as not to overlap each other in plan view of the first substrate; and a plurality of the pair of sheets corresponding one-to-one to the plurality of the first members, in each of the plurality of the pair of sheets, the first main surface of the first joining sheet joining the corresponding first member, the first main surface of the second joining sheet joining the second substrate.

9. The semiconductor device according to claim 8, wherein: in at least one of the plurality of the pair of sheets, the second main surfaces are joined with one being offset with respect to the other.

10. The semiconductor device according to claim 9, wherein: a direction in which the second main surfaces are offset with respect to each other is an inclined direction of the second main surface.

11. The semiconductor device according to claim 9, wherein: a direction in which the second main surfaces are offset with respect to each other is a rotation direction about a direction orthogonal to the second main surface.

12. The semiconductor device according to claim 9, wherein: ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ At least two of the first members each have a different height from the first substrate at a joint surface with the corresponding first main surface.

13. The semiconductor device according to claim 9, wherein At least one of the first members each has an inclination with respect to the first substrate at a joint surface with the corresponding first main surface.

14. A method for manufacturing a semiconductor device, comprising: a step of preparing a plurality of pairs of sheets each including a first bonding sheet and a second bonding sheet each being the bonding sheet according to any one of claims 1 to 4; a step of preparing a first substrate provided with a plurality of the first members so as not to overlap each other in plan view; a step of measuring at least one of a height from the first substrate and an inclination with respect to the first substrate of an upper surface of each of the first members; a step of disposing the plurality of pairs of sheets on the upper surface of the corresponding first member; and a step of disposing a second substrate as the second member so as to cover the plurality of pairs of sheets, in the step of disposing, for at least one of the plurality of pairs of sheets, the second main surfaces are disposed apart from each other based on at least one of the height and the inclination of the upper surface of the corresponding first member.

15. The method for manufacturing a semiconductor device according to claim 14, wherein in the step of disposing, based on at least one of the height and the inclination of the upper surface of each of the first members, a direction and an amount of the second main surfaces of the corresponding pair of sheets are determined apart from each other, and the second main surfaces are disposed apart from each other based on the determined direction and amount.

16. The method for manufacturing a semiconductor device according to claim 14, wherein in the step of measuring, the height from the first substrate of the upper surface of each of the first members is measured, in the step of disposing, for at least one of the plurality of pairs of sheets, based on the height of the upper surface of the corresponding first member, one of the first bonding sheet and the second bonding sheet is disposed apart from the other in a direction of inclination of the second main surface.

17. The method for manufacturing a semiconductor device according to claim 14, wherein in the step of measuring, the inclination with respect to the first substrate of the upper surface of each of the first members is measured, in the step of disposing, for at least one of the plurality of pairs of sheets, based on the inclination of the upper surface of the corresponding first member, one of the first bonding sheet and the second bonding sheet is disposed apart from the other in a direction of rotation with a direction orthogonal to the second main surface as an axis of rotation.

18. A method for manufacturing a semiconductor device, comprising: a process of preparing a pair of sheets including a first bonding sheet and a second bonding sheet each being the bonding sheet according to any one of claims 1 to 4; a process of preparing a first substrate provided with the first member; a process of measuring inclination of an upper surface of the first member with respect to the first substrate; a process of arranging the pair of sheets on the upper surface of the first member in a state in which one of the first bonding sheet and the second bonding sheet is offset with respect to the other in a rotation direction with a direction orthogonal to the second main surface set as a rotation axis, based on the inclination; a process of arranging a second substrate as the second member so as to cover the pair of sheets.

19. A manufacturing apparatus of a semiconductor device, comprising: a first mounting portion that arranges a pair of sheets including a first bonding sheet and a second bonding sheet each being the bonding sheet according to any one of claims 1 to 4 on an upper surface of a corresponding first member in each correspondence with a plurality of the first members arranged on a first substrate so as not to overlap each other in plan view; a second mounting portion that arranges a second substrate as the second member so as to cover a plurality of the pair of sheets; and a measurement portion that measures at least one of a height from the first substrate and an inclination with respect to the first substrate of the upper surface of each of the plurality of the first members, the first mounting portion arranges the second main surface in a state in which one of the first bonding sheet and the second bonding sheet is offset with respect to the other in a rotation direction with a direction orthogonal to the second main surface set as a rotation axis, based on at least one of the height and the inclination of the upper surface of the corresponding first member, for at least one of the plurality of the pair of sheets.

20. A manufacturing apparatus of a semiconductor device, comprising: a first mounting portion that arranges a pair of sheets including a first bonding sheet and a second bonding sheet each being the bonding sheet according to any one of claims 1 to 4 on an upper surface of the first member arranged on a first substrate; a second mounting portion that arranges a second substrate as the second member so as to cover the pair of sheets; and a measurement portion that measures an inclination of the upper surface of the first member with respect to the first substrate, the first mounting portion arranges the pair of sheets on the upper surface of the first member in a state in which one of the first bonding sheet and the second bonding sheet is offset with respect to the other in a rotation direction with a direction orthogonal to the second main surface set as a rotation axis, based on the inclination. ​ ​

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