Clock detection method, clock detection circuit and image sensor

Abstract

The invention provides a clock detection method, a clock detection circuit and an image sensor, an enable signal is accessed through a first input end of an AND gate, a first clock signal is accessed through a second input end of the AND gate, and an output end of the AND gate is connected with a control end of a first switching element; the first end of the first capacitor is connected with the first end of the first switch piece, and the second capacitor is connected between the second end of the first switch piece and the ground; the first end of the second switch piece is connected with a preset voltage, and the second switch piece is connected with the second end of the first switch piece; the positive input end of the comparator is connected with the second end of the second switch piece, the negative input end of the comparator is connected with preset voltage, and the output end of the comparator is connected with the input end of the trigger; the trigger end of the trigger is connected with the second input end of the AND gate, and the reset end of the trigger is connected with the first input end of the AND gate to output a clock detection result signal. The input system clock detection circuit is adopted to judge the input system clock frequency, and the user experience is improved.

Description

Technical Field

[0001] This application relates to the field of image sensor technology, specifically to a clock detection method, a clock detection circuit, and an image sensor. Background Technology

[0002] Image sensors are widely used in imaging fields such as video, surveillance, industrial manufacturing, automobiles, and home appliances. The clock circuit in an image sensor is a crucial component of its analog-to-digital circuitry. Driven accurately by the clock circuit, the image sensor transmits the sampled signal to the digital processing module for processing. The chip's input system clock is often provided by a crystal oscillator, serving as the input reference clock for the entire chip. Its frequency determines the normal operation of various clocks within the chip, and detecting whether the system clock frequency is within the design value is critical for monitoring the chip's proper functioning.

[0003] In conceiving and developing this application, the applicant discovered that commonly used clock frequency detection circuits are often quite complex, requiring counters, operational amplifiers, etc., which consumes a lot of hardware resources and power consumption, and also has circuit stability issues. Therefore, how to complete the frequency detection of the input clock with a stable clock frequency detection circuit with a smaller layout area and lower power consumption is an urgent problem to be solved. Summary of the Invention

[0004] To alleviate the above problems, this application provides a clock detection circuit, including a first AND gate, a first switch, a second switch, a first capacitor, a second capacitor, a comparator, and a flip-flop; An enable signal is connected to the first input terminal of the first AND gate, a first clock signal is connected to the second input terminal of the first AND gate, and the output terminal of the first AND gate is connected to the control terminal of the first switch. The first terminal of the first capacitor is connected to the first terminal of the first switch, the second terminal of the first capacitor is grounded, the second capacitor is connected between the second terminal of the first switch and ground, and the third terminal of the first switch is grounded. The first end of the second switch is connected to a first preset voltage, and the second end of the second switch is connected to the second end of the first switch. The positive input terminal of the comparator is connected to the second terminal of the second switching element, the negative input terminal of the comparator is connected to the second preset voltage, and the output terminal of the comparator is connected to the input terminal of the trigger. The trigger terminal of the flip-flop is connected to the second input terminal of the first AND gate, the reset terminal of the flip-flop is connected to the first input terminal of the first AND gate, and the output terminal of the flip-flop outputs a clock detection result signal.

[0005] Optionally, the clock detection circuit further includes a frequency upsampling circuit. The input terminal of the frequency upsampling circuit is connected to the second input terminal of the first AND gate, and the output terminal of the frequency upsampling circuit is connected to the trigger terminal of the flip-flop. The frequency upsampling circuit is used to increase the trigger frequency of the trigger terminal to avoid delay in the flip-flop clock detection result signal output by the trigger terminal.

[0006] Optionally, the first switching element includes a first transmission gate and a second transmission gate; The first control terminal of the first transmission gate is connected to the first control signal output from the output terminal of the first AND gate, the second control terminal of the first transmission gate is connected to the second control signal, the input terminal of the first transmission gate serves as the first terminal of the first switching device, and the output terminal of the first transmission gate is grounded. The first control terminal of the second transmission gate is connected to the second control signal, the second control terminal of the second transmission gate is connected to the first control signal output by the output terminal of the first AND gate, the output terminal of the second transmission gate is connected to the output terminal of the second switch, and the input terminal of the second transmission gate is connected to the input terminal of the first transmission gate. The first control signal and the second control signal are complementary control signals.

[0007] Optionally, the second switching element is a field-effect transistor.

[0008] Optionally, the clock detection circuit further includes a signal stabilization unit connected to the output of the flip-flop.

[0009] Optionally, the signal stabilization unit includes a first NOT gate and a second NOT gate. The input of the first NOT gate is connected to the output of the flip-flop, the output of the first NOT gate is connected to the input of the second NOT gate, and the output of the second NOT gate outputs the clock detection result signal.

[0010] Optionally, the first preset voltage is greater than the second preset voltage.

[0011] Optionally, the capacitance of the first capacitor is less than the capacitance of the second capacitor.

[0012] This application also provides a clock detection method applied to the clock detection circuit described above, the clock detection method comprising: By disabling the enable signal, the first switch is controlled to ground the two ends of the first capacitor, and the second switch is controlled to turn on to charge the second capacitor to the first preset voltage, wherein the first preset voltage is greater than the second preset voltage. The second switch is turned off, causing the enable signal to flip to active. Based on the first clock signal, the first switch is alternately turned on. The first terminal of the first capacitor is alternately switched between grounding and connecting to the second capacitor, so that the input voltage at the positive input terminal of the comparator conforms to the first preset function expression, wherein the capacitance value of the first capacitor is less than the capacitance value of the second capacitor. When the voltage of the second capacitor drops below the second preset voltage, the output voltage of the comparator flips, and based on the Taylor expansion of the first preset function expression, the pulse width of the clock detection signal is detected as the frequency detection result of the first clock signal.

[0013] Optionally, the first preset function expression is:

[0014] The Taylor expansion of the first preset function expression is:

[0015] Where Vin is the input voltage at the positive input terminal of the comparator, C1 is the capacitance of the first capacitor, C2 is the capacitance of the second capacitor, V1 is the voltage value of the first preset voltage, and n is the number of cycles.

[0016] Optionally, the second preset voltage is greater than a predetermined voltage value, and the predetermined voltage value is positively correlated with the accuracy of the frequency detection result of the first clock signal.

[0017] Optionally, the process of using the pulse width of the clock detection signal as the frequency detection result of the first clock signal based on the Taylor expansion of the first preset function expression includes: fixing the number of cycles of the comparator output flip, so that the frequency of the first clock signal is linearly related to the pulse width of the clock detection signal.

[0018] Optionally, the process of using the pulse width of the clock detection signal as the frequency detection result of the first clock signal based on the Taylor expansion of the first preset function expression includes: determining the detection result of the first clock signal by using the pulse width of the clock detection signal, since the clock frequency of the first clock signal is proportional to the pulse width of the clock detection signal.

[0019] This application also provides an image sensor, including the clock detection circuit described above.

[0020] This application also provides an image sensor, which includes a memory and a processor, wherein the memory stores a computer program, which, when executed by the processor, implements the steps of the clock detection method described above.

[0021] The clock detection method, clock detection circuit, and image sensor provided in this application utilize an input system clock detection circuit. An enable signal is input to the first input terminal of a first AND gate, a first clock signal is input to the second input terminal of the first AND gate, and the output terminal of the first AND gate is connected to the control terminal of a first switch. A first terminal of a first capacitor is connected to the first terminal of the first switch, and the second terminal of the first capacitor is grounded. A second capacitor is connected between the second terminal of the first switch and ground, and the third terminal of the first switch is grounded. A first preset voltage is input to the first terminal of the second switch, and the second terminal of the second switch is connected to the second terminal of the first switch. The positive input terminal of a comparator is connected to the second terminal of the second switch, the negative input terminal of the comparator is connected to a second preset voltage, and the output terminal of the comparator is connected to the input terminal of a flip-flop. The trigger terminal of the flip-flop is connected to the second input terminal of the first AND gate, the reset terminal of the flip-flop is connected to the first input terminal of the first AND gate, and the output terminal of the flip-flop outputs a clock detection result signal. This application employs an input system clock detection circuit, which can determine whether the input system clock frequency meets design requirements, thus improving the user experience. Attached Figure Description

[0022] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0023] Figure 1 This is a schematic diagram of a clock detection circuit according to an embodiment of this application.

[0024] Figure 2 This is a schematic diagram of the connection structure between the first switch S1 and the second switch S2 according to an embodiment of this application.

[0025] Figure 3 This is a flowchart of a clock detection method according to an embodiment of this application.

[0026] Figure 4 This is a timing diagram of a key node for clock detection in an embodiment of this application.

[0027] The realization of the objectives, functional features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. The accompanying drawings have illustrated specific embodiments of this application, which will be described in more detail below. These drawings and textual descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this application to those skilled in the art through reference to specific embodiments. Detailed Implementation

[0028] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0029] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0030] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0031] First Embodiment This application provides a clock detection circuit. Figure 1 This is a schematic diagram of a clock detection circuit according to an embodiment of this application.

[0032] like Figure 1 As shown, in one embodiment, the clock detection circuit includes a first AND gate, a first switch S1, a second switch S2, a first capacitor C1, a second capacitor C2, a comparator CMP, and a flip-flop DFF.

[0033] For example, a clock circuit is an electronic circuit used to generate and distribute clock signals. Clock signals play a role in synchronizing and coordinating the operation of various components in a digital system. They provide a unified time reference, enabling data transmission and processing within the system to proceed in the correct order and timing.

[0034] The first input of the first AND gate is connected to an enable signal, the second input of the first AND gate is connected to a first clock signal, and the output of the first AND gate is connected to the control terminal of the first switch S1.

[0035] For example, an AND gate is a circuit that implements the logical "multiplication" operation. It has two or more inputs and one output (general circuits have only one output, while ECL circuits have two outputs). The circuit outputs a high level (logic "1") only when all inputs are high (logic "1"); otherwise, the output is low (logic "0").

[0036] The first terminal of the first capacitor C1 is connected to the first terminal of the first switch S1, the second terminal of the first capacitor C1 is grounded, the second capacitor C2 is connected between the second terminal of the first switch S1 and ground, and the third terminal of the first switch S1 is grounded.

[0037] The first end of the second switch S2 is connected to the first preset voltage, and the second end of the second switch S2 is connected to the second end of the first switch S1.

[0038] The positive input terminal of comparator CMP is connected to the second terminal of the second switch S2, the negative input terminal of comparator CMP is connected to the second preset voltage, and the output terminal of comparator CMP is connected to the input terminal of flip-flop DFF.

[0039] For example, a comparator is a circuit or device that performs a comparison function. A comparator is a circuit that compares an analog voltage signal with a reference voltage. The two inputs of a comparator are analog signals, and the output is a binary signal 0 or 1. When the difference between the input voltages increases or decreases and the sign remains unchanged, its output remains constant.

[0040] The trigger terminal of the flip-flop DFF is connected to the second input terminal of the first AND gate, the reset terminal of the flip-flop DFF is connected to the first input terminal of the first AND gate, and the output terminal of the flip-flop DFF outputs the clock detection result signal.

[0041] For example, a flip-flop is an information storage device with memory function and two stable states. It is the most basic logic unit for constructing various sequential circuits and an important unit circuit in digital logic circuits. Therefore, flip-flops have wide applications in digital systems and computers. For example, a D flip-flop has two stable states, 0 and 1, and can flip from one stable state to the other under the action of a certain external signal.

[0042] In this embodiment, an enable signal is received at the first input terminal of a first AND gate, a first clock signal is received at the second input terminal of the first AND gate, and the output terminal of the first AND gate is connected to the control terminal of a first switch. The first terminal of a first capacitor is connected to the first terminal of the first switch, the second terminal of the first capacitor is grounded, a second capacitor is connected between the second terminal of the first switch and ground, and the third terminal of the first switch is grounded. A first preset voltage is received at the first terminal of the second switch, and the second terminal of the second switch is connected to the second terminal of the first switch. The positive input terminal of a comparator is connected to the second terminal of the second switch, the negative input terminal of the comparator is connected to the second preset voltage, and the output terminal of the comparator is connected to the input terminal of a flip-flop. The trigger terminal of the flip-flop is connected to the second input terminal of the first AND gate, the reset terminal of the flip-flop is connected to the first input terminal of the first AND gate, and the output terminal of the flip-flop outputs a clock detection result signal. By employing an input system clock detection circuit, it is possible to determine whether the input system clock frequency meets the design requirements, thus improving the user experience.

[0043] Optionally, the clock detection circuit further includes a frequency upsampling circuit. The input of the frequency upsampling circuit is connected to the second input of the first AND gate, and the output of the frequency upsampling circuit is connected to the trigger terminal of the flip-flop. The frequency upsampling circuit is used to increase the trigger frequency of the trigger terminal to avoid delay in the clock detection result signal output by the flip-flop.

[0044] For example, the first clock signal is converted into a second clock signal with a higher frequency by the up-conversion circuit and output to the enable terminal of the flip-flop. This can increase the frequency of the enable signal at the flip-flop enable terminal, and the flip-flop can avoid delayed flipping when the comparator flips, thereby avoiding clock frequency errors.

[0045] Figure 2 This is a schematic diagram of the connection structure between the first switch S1 and the second switch S2 according to an embodiment of this application.

[0046] like Figure 2 As shown, optionally, the first switching element S1 includes a first transmission gate A1 and a second transmission gate B1.

[0047] The first control terminal of the first transmission gate A1 is connected to the first control signal Vs1 output from the output terminal of the first AND gate, the second control terminal of the first transmission gate A1 is connected to the second control signal Vs1b, the input terminal of the first transmission gate A1 serves as the first terminal of the first switching element S1, and the output terminal of the first transmission gate A1 is grounded.

[0048] The first control terminal of the second transmission gate B1 is connected to the second control signal Vs1b, the second control terminal of the second transmission gate B1 is connected to the first control signal Vs1 output from the output terminal of the first AND gate, the output terminal of the second transmission gate B1 is connected to the output terminal of the second switch S2, and the input terminal of the second transmission gate B1 is connected to the input terminal of the first transmission gate A1; Among them, the first control signal Vs1 and the second control signal Vs1b are complementary control signals.

[0049] Optionally, a clock differential output circuit is connected to the output of the first AND gate to generate two control signals that are inversely related to each other. The clock differential output circuit includes, but is not limited to, any of the following structures: direct differential amplifier structure, transformer-coupled differential output, logic gate generating differential signal, differential signal buffer structure, etc.

[0050] For example, a transmission gate (TG gate) is an electronic component primarily used as an analog switch to transmit analog signals. It consists of a P-channel and an N-channel enhancement-mode MOSFET connected in parallel, enabling signal transmission in digital circuits. The main function of a TG gate is to allow or block current flow under specific conditions, thereby achieving signal transmission or blocking. In digital circuit logic design, the TG gate (CMOS transmission gate) functions similarly to an open-collector (OC) gate. When the control signal is high, both the P-channel and N-channel MOSFETs are turned on, allowing the signal to pass to the output; when the control signal is low, both are turned off, and the output presents a high-impedance state (Z). This characteristic allows the TG gate to function in level transitions, similar to an OC gate. Using multiple transmission gates with appropriate control voltages can achieve the effect of a single-pole multi-throw (SNP) switch.

[0051] Optionally, the second switching device is a field-effect transistor.

[0052] For example, a field-effect transistor (FET) is simply called a field-effect transistor. A field-effect transistor (FET) is a semiconductor device that uses the electric field effect of the input circuit to control the current in the output circuit. There are two main types: junction field-effect transistors (JFETs) and metal-oxide-semiconductor field-effect transistors (MOS-FETs). Since conduction is carried out by majority carriers, it is also called a unipolar transistor. It belongs to the voltage-controlled semiconductor device category. It has advantages such as high input resistance (10⁷–10¹⁵ Ω), low noise, low power consumption, large dynamic range, easy integration, no secondary breakdown phenomenon, and a wide safe operating area.

[0053] Optionally, the clock detection circuit also includes a signal stabilization unit, which is connected to the output of the flip-flop.

[0054] For example, the signal output by the trigger may have limited power and load capacity. Therefore, a signal stabilization unit can be used to stabilize the signal output by the trigger, thereby enhancing the load capacity of the trigger.

[0055] Optionally, the signal stabilization unit includes a first NOT gate and a second NOT gate. The input of the first NOT gate is connected to the output of the flip-flop, the output of the first NOT gate is connected to the input of the second NOT gate, and the output of the second NOT gate outputs the clock detection result signal.

[0056] For example, by performing two NOT operations on the signal output by the first flip-flop, the carrying capacity of the data output signal of the first flip-flop can be effectively improved, data errors can be avoided during data transmission, and the accuracy of data transmission can be effectively improved.

[0057] Optionally, the first preset voltage is greater than the second preset voltage.

[0058] For example, after the first preset voltage charges the second capacitor, the voltage across the second capacitor is equal to the first preset voltage. As the first switching element alternately turns on, the voltage across the second capacitor gradually decreases. When the voltage across the second capacitor drops below the second preset voltage, the comparator's output signal flips.

[0059] Optionally, the capacitance of the first capacitor is smaller than the capacitance of the second capacitor.

[0060] For example, when the first switching device is alternately turned on, the first terminal of the first capacitor switches between ground and connected to the first terminal of the second capacitor. When the capacitance of the first capacitor is much smaller than that of the second capacitor, the node voltage at the positive input terminal of the comparator will decrease slightly in each alternation cycle, causing the voltage across the second capacitor to gradually decrease.

[0061] Second Embodiment This application also provides a clock detection method, applied to the clock detection circuit described above. Figure 3 This is a flowchart of a clock detection method according to an embodiment of this application.

[0062] like Figure 3 As shown, in one embodiment, the clock detection method includes: S10: By invalidating the enable signal, control the first switch to ground the two ends of the first capacitor, and control the second switch to turn on to charge the second capacitor to a first preset voltage, wherein the first preset voltage is greater than the second preset voltage.

[0063] S20: Control the second switch to turn off, flip the enable signal to active, and control the first switch to turn on alternately based on the first clock signal. Control the first terminal of the first capacitor to switch alternately between grounding and connecting to the second capacitor so that the input voltage at the positive input terminal of the comparator conforms to the first preset function expression, wherein the capacitance value of the first capacitor is less than the capacitance value of the second capacitor.

[0064] S30: When the voltage of the second capacitor drops to less than the second preset voltage, the output voltage of the comparator flips, and the frequency detection result of the first clock signal is obtained by detecting the pulse width of the clock detection signal based on the Taylor expansion of the first preset function expression.

[0065] Optionally, the first preset function expression is:

[0066] The Taylor expansion of the first preset function expression is:

[0067] Where Vin is the input voltage at the positive input terminal of the comparator, C1 is the capacitance of the first capacitor, C2 is the capacitance of the second capacitor, V1 is the voltage value of the first preset voltage, and n is the number of cycles.

[0068] Figure 4 This is a timing diagram of a key node for clock detection in an embodiment of this application.

[0069] Please continue to refer to this. Figure 2 , Figure 3 and Figure 4 For example, during the preparation phase, the enable signal is invalid (dec_en = 0, a low-level signal), the second switch S2 is turned on, and the first capacitor C1 is grounded. The upper plate of the second capacitor C2 is charged to the first preset voltage V1, and the second preset voltage Vref is lower than V1 (e.g., Vref = 0.8 * V1). The comparator's output voltage Vo1 = 1, a high-level signal. The flip-flop DFF is in the reset state, and the flip-flop outputs the clock detection result signal Vo = 0, a low-level signal. Before the preparation phase ends, the second switch S2 is turned off, and the charge in the second capacitor C2 is fully stored. For example, during the detection phase, the enable signal dec_en changes from 0 to 1, the DFF flip-flop reset state ends, and the comparator output voltage Vo1=1 is a high-level signal, which is transmitted to the DFF output. The flip-flop outputs the clock detection result signal Vo, which changes from low level 0 to high level 1. Since the enable signal dec_en=1 is a high-level signal, the AND gate is effective, and the input system clock signal clk_in is transmitted to the AND gate output to generate the control signals Vs1 and Vs1b of the first switch S1. The first switch S1 is alternately turned on, and the positive terminal of the first capacitor C1 switches between ground and the positive terminal of the second capacitor C2. The capacitance value of the first capacitor C1 is set to be much smaller than the capacitance value of the second capacitor C2 (for example, the ratio of the capacitance values ​​of the first capacitor and the second capacitor is c1=0.01*c2). The voltage at the Vin node of the comparator positive input terminal will decrease slightly in each cycle, and its voltage expression is as follows:

[0070] Where n represents the number of cycles, its Taylor expansion is as follows:

[0071] Optionally, the second preset voltage is greater than a predetermined voltage value, and the predetermined voltage value is positively correlated with the accuracy of the frequency detection result of the first clock signal. It should be explained that the accuracy of the frequency detection result of the first clock signal indicates whether only the range of the clock detection signal needs to be obtained or a specific value is required. If only the range of the clock detection signal needs to be obtained, the accuracy is low; if a specific value of the clock detection signal is required, the accuracy is high. Therefore, the higher the accuracy requirement, the larger the corresponding predetermined voltage value, and thus the larger the second preset voltage Vref.

[0072] Given a first preset voltage V1, a second preset voltage Vref, and the values ​​of the first capacitor C1 and the second capacitor C2, determine the number of cycles required for the comparator output to flip, ensuring a linear correlation between the input system clock frequency and the detection pulse width. By calibrating the upper and lower limits of the pulse width, it is possible to detect whether the system clock frequency meets the requirements.

[0073] Optionally, the process of using the pulse width of the clock detection signal as the frequency detection result of the first clock signal based on the Taylor expansion of the first preset function expression includes: fixing the number of cycles of the comparator output toggling, so that the frequency of the first clock signal is linearly related to the pulse width of the clock detection signal.

[0074] Optionally, the process of using the pulse width of the clock detection signal as the frequency detection result of the first clock signal, based on the Taylor expansion of the first preset function expression, includes: The detection result of the first clock signal is determined by the pulse width of the clock detection signal, since the clock frequency of the first clock signal is proportional to the pulse width of the clock detection signal.

[0075] For example, the number of cycles required for the comparator output to flip is fixed, therefore the input system clock frequency and the detection pulse width are linearly related. By calibrating the upper and lower limits of the pulse width, it is possible to detect whether the system clock frequency meets the requirements.

[0076] For example, please continue to refer to Figure 2 , Figure 3 and Figure 4 Since the capacitance of the first capacitor C1 is much smaller than that of the second capacitor C2, the Taylor expansion above can be approximately retained by the first two terms, that is:

[0077] Therefore, it can be seen that the voltage drop at the positive input terminal Vin of the comparator is linearly related to n. At this time, the value of the second preset voltage Vref is still lower than V1, Vo1=1, Vo=1.

[0078] Third Embodiment This application also provides an image sensor, including the clock detection circuit described above.

[0079] This application also provides an image sensor, which includes a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, it implements the steps of the clock detection method described above.

[0080] The clock detection method, clock detection circuit, and image sensor provided in this application utilize an input system clock detection circuit. An enable signal is input to the first input terminal of a first AND gate, a first clock signal is input to the second input terminal of the first AND gate, and the output terminal of the first AND gate is connected to the control terminal of a first switch. A first capacitor has its first terminal connected to the first terminal of the first switch, its second terminal grounded, a second capacitor connected between the second terminal of the first switch and ground, and a third terminal of the first switch grounded. A second switch has its first terminal connected to a first preset voltage, and its second terminal connected to the second terminal of the first switch. A comparator has its positive input terminal connected to the second terminal of the second switch, its negative input terminal connected to a second preset voltage, and its output terminal connected to the input terminal of a flip-flop. The trigger terminal of the flip-flop is connected to the second input terminal of the first AND gate, the reset terminal of the flip-flop is connected to the first input terminal of the first AND gate, and the output terminal of the flip-flop outputs a clock detection result signal. This application employs an input system clock detection circuit, which can determine whether the input system clock frequency meets design requirements, thus improving the user experience.

[0081] It should be noted that step designations such as S10 and S20 are used in this application for the purpose of more clearly and concisely describing the corresponding content, and do not constitute a substantial limitation on the order. In specific implementation, those skilled in the art may execute S20 first and then S10, etc., but these should all be within the protection scope of this application.

[0082] The embodiments of the image sensor and clock detection circuit provided in this application may include all the technical features of any of the above-described method embodiments. The extended and explanatory content of the specification is basically the same as that of the embodiments of the above methods, and will not be repeated here.

[0083] This application also provides a computer program product, which includes computer program code. When the computer program code is run on a computer, it causes the computer to perform the methods described in the various possible implementations above.

[0084] This application also provides a chip, including a memory and a processor. The memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that a device with the chip installed performs the methods described in the various possible implementations above.

[0085] It is understood that the above scenarios are merely examples and do not constitute a limitation on the application scenarios of the technical solutions provided in the embodiments of this application. The technical solutions of this application can also be applied to other scenarios. For example, as those skilled in the art will know, with the evolution of system architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0086] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0087] The steps in the method of this application embodiment can be adjusted, combined, or deleted according to actual needs.

[0088] The units in the device of this application embodiment can be merged, divided, and deleted according to actual needs.

[0089] In this application, the same or similar terms, concepts, technical solutions and / or application scenario descriptions are generally described in detail only when they appear for the first time. When they appear again, they are generally not repeated for the sake of brevity. When understanding the technical solutions and other contents of this application, the same or similar terms, concepts, technical solutions and / or application scenario descriptions that are not described in detail later can be referred to their previous relevant detailed descriptions.

[0090] In this application, the descriptions of the various embodiments have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0091] The technical features of the present application can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of the present application.

[0092] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A clock detection circuit, characterized in that, It includes a first AND gate, a first switch, a second switch, a first capacitor, a second capacitor, a comparator, and a flip-flop; An enable signal is connected to the first input terminal of the first AND gate, a first clock signal is connected to the second input terminal of the first AND gate, and the output terminal of the first AND gate is connected to the control terminal of the first switch. The first terminal of the first capacitor is connected to the first terminal of the first switch, the second terminal of the first capacitor is grounded, the second capacitor is connected between the second terminal of the first switch and ground, and the third terminal of the first switch is grounded. The first end of the second switch is connected to a first preset voltage, and the second end of the second switch is connected to the second end of the first switch. The positive input terminal of the comparator is connected to the second terminal of the second switching element, the negative input terminal of the comparator is connected to the second preset voltage, and the output terminal of the comparator is connected to the input terminal of the trigger. The trigger terminal of the flip-flop is connected to the second input terminal of the first AND gate, the reset terminal of the flip-flop is connected to the first input terminal of the first AND gate, and the output terminal of the flip-flop outputs a clock detection result signal.

2. The clock detection circuit according to claim 1, characterized in that, The clock detection circuit further includes a frequency upsampling circuit. The input terminal of the frequency upsampling circuit is connected to the second input terminal of the first AND gate, and the output terminal of the frequency upsampling circuit is connected to the trigger terminal of the flip-flop. The frequency upsampling circuit is used to increase the trigger frequency of the trigger terminal to avoid delay in the flip-flop clock detection result signal output by the trigger terminal.

3. A clock detection circuit according to claim 2, characterized in that, The first switching element includes a first transmission gate and a second transmission gate; The first control terminal of the first transmission gate is connected to the first control signal output from the output terminal of the first AND gate, the second control terminal of the first transmission gate is connected to the second control signal, the input terminal of the first transmission gate serves as the first terminal of the first switching device, and the output terminal of the first transmission gate is grounded. The first control terminal of the second transmission gate is connected to the second control signal, the second control terminal of the second transmission gate is connected to the first control signal output by the output terminal of the first AND gate, the output terminal of the second transmission gate is connected to the output terminal of the second switch, and the input terminal of the second transmission gate is connected to the input terminal of the first transmission gate. The first control signal and the second control signal are complementary control signals.

4. A clock detection circuit according to claim 3, characterized in that, The second switching device is a field-effect transistor.

5. A clock detection circuit according to claim 1, characterized in that, The clock detection circuit also includes a signal stabilization unit, which is connected to the output of the flip-flop.

6. A clock detection circuit according to claim 5, characterized in that, The signal stabilization unit includes a first NOT gate and a second NOT gate. The input of the first NOT gate is connected to the output of the flip-flop, the output of the first NOT gate is connected to the input of the second NOT gate, and the output of the second NOT gate outputs the clock detection result signal.

7. A clock detection circuit according to any one of claims 1-6, characterized in that, The first preset voltage is greater than the second preset voltage.

8. A clock detection circuit according to claim 7, characterized in that, The capacitance of the first capacitor is less than the capacitance of the second capacitor.

9. A clock detection method, characterized in that, The clock detection method, applied to the clock detection circuit as described in any one of claims 1-8, comprises: By disabling the enable signal, the first switch is controlled to ground the two ends of the first capacitor, and the second switch is controlled to turn on to charge the second capacitor to the first preset voltage, wherein the first preset voltage is greater than the second preset voltage. The second switch is turned off, causing the enable signal to flip to active. Based on the first clock signal, the first switch is alternately turned on. The first terminal of the first capacitor is alternately switched between grounding and connecting to the second capacitor, so that the input voltage at the positive input terminal of the comparator conforms to the first preset function expression, wherein the capacitance value of the first capacitor is less than the capacitance value of the second capacitor. When the voltage of the second capacitor drops below the second preset voltage, the output voltage of the comparator flips, and based on the Taylor expansion of the first preset function expression, the pulse width of the clock detection signal is detected as the frequency detection result of the first clock signal.

10. A clock detection method according to claim 9, characterized in that, The first preset function expression is: The Taylor expansion of the first preset function expression is: Where Vin is the input voltage at the positive input terminal of the comparator, C1 is the capacitance of the first capacitor, C2 is the capacitance of the second capacitor, V1 is the voltage value of the first preset voltage, and n is the number of cycles.

11. A clock detection method according to claim 9 or 10, characterized in that, The second preset voltage is greater than a predetermined voltage value, and the predetermined voltage value is positively correlated with the accuracy of the frequency detection result of the first clock signal.

12. A clock detection method according to claim 11, characterized in that, The process of using the pulse width of the clock detection signal as the frequency detection result of the first clock signal based on the Taylor expansion of the first preset function expression includes: fixing the number of cycles of the comparator output toggling, so that the frequency of the first clock signal is linearly related to the pulse width of the clock detection signal.

13. A clock detection method according to claim 12, characterized in that, The process of using the pulse width of the clock detection signal as the frequency detection result of the first clock signal based on the Taylor expansion of the first preset function expression includes: determining the detection result of the first clock signal by means of the pulse width of the clock detection signal, since the clock frequency of the first clock signal is proportional to the pulse width of the clock detection signal.

14. An image sensor, characterized in that, Includes the clock detection circuit as described in any one of claims 1-8; And / or, The image sensor includes a memory and a processor, wherein the memory stores a computer program that, when executed by the processor, implements the steps of the clock detection method as described in any one of claims 9 to 13.

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