Design method of LOD effect test unit

Abstract

The invention provides a design method of an LOD effect test unit, and the method comprises the steps: 1, designing the LOD effect test unit into a first test unit and a second test unit which have asymmetric structures according to a standard unit structure of a ring oscillator; and 2, verifying whether the average threshold voltage of the first test unit and the second test unit is equivalent to the threshold voltage of the standard unit structure or not. By adopting the design of the LOD effect asymmetric test structure, the LOD effect of the INV4 structure of the standard unit can be evaluated more accurately, and the method is simple and feasible.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a design method for a LOD effect test cell. Background Technology

[0002] With the development of the semiconductor industry and the improvement of CMOS manufacturing technology, chip areas are becoming smaller and smaller, leading to increasingly higher requirements for low power consumption, high stability, and high precision of the various modules within the chip. Oscillator modules, as key components for generating system clocks, are widely used in electronic and communication systems. Therefore, oscillator modules, as crucial components for generating system clocks, are essential for... Figure 1 The CMOS-based ring oscillator (RO) shown has become a key component for monitoring the AC performance of the process.

[0003] The most commonly used standard unit (STD cell) in RO is as follows: Figure 2 The diagram shows a 4x INV4 structure (with four active gates having leads) consisting of cascaded four inverters, while Logic PCM devices used in RO configurations are generally as follows: Figure 3 The 1x INV1 structure shown (with one effective gate having a lead) exhibits a threshold voltage Vt between the STD cell and PCM due to LDE effects (a strongly layout-dependent effect, including LOD, OSEY, MBE, GLE, etc.). Furthermore, various effects on the actual silicon substrate can cause mismatches with preset parameters, preventing the Vt of the STD cell and PCM from simultaneously matching the preset parameters, thus affecting the actual chip yield and the device Vt window. Among LDE effects, the stress effect (LOD effect) caused by the difference between shallow trench isolation (STI) and the polysilicon gate distance has a more significant impact on the threshold voltage Vt. Therefore, accurately identifying the LOD effects of the STD cell and PCM and matching the corresponding LOD effects to preset parameters through process optimization is crucial.

[0004] like Figure 2 As shown, due to the difference in distance between the four effective gates in the STD cell and the STI, the LOD effect is not the same. For existing test cells used to analyze the LOD effect of STD cells and PCMs, the LOD test cell used for logic PCMs is as follows... Figure 3 The symmetrical structure shown is also used in the LOD test unit for STD cells. That is, when analyzing the difference in LOD effect between STD cells and PCM, the LOD test unit of the INV4 structure used for STD cells is bilaterally symmetrical, which does not match the actual situation and leads to errors in the analysis of the difference in LOD effect between STD cells and PCM. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a design method for a LOD effect test unit to solve the problem of errors in the analysis of the differences in LOD effects between STD cells and PCMs in the prior art.

[0006] To achieve the above and other related objectives, this application provides a design method for a LOD effect test unit, comprising: Step 1: Based on the standard unit structure of a ring oscillator, design the LOD effect test unit as a first test unit and a second test unit with an asymmetric structure. Step 2: Verify whether the averaged threshold voltages of the first and second test units are equivalent to the threshold voltages of the standard unit structure.

[0007] Preferably, in step one, a first test unit is designed based on the leftmost effective gate according to the standard cell structure. In the first test unit, there is one gate on the left side of the effective gate and four gates on the right side, i.e., LOD 1+4.

[0008] Preferably, in step one, a second test unit is designed based on the effective gate located in the middle left, according to the standard cell structure. In the second test unit, there are two gates on the left side of the effective gate and three gates on the right side, i.e., LOD 2+3.

[0009] Preferably, in step two, if the difference between the averaged threshold voltages of the first and second test units and the threshold voltage of the standard unit structure is less than 5mV, the verification result is considered to be passed.

[0010] Preferably, if the verification result of step two is passed, the first test unit and the second test unit are used simultaneously as LOD effect test units of the standard unit structure.

[0011] As described above, the design method of the LOD effect test unit provided in this application has the following advantages: by adopting the design of an asymmetric LOD effect test structure, the LOD effect of the STDcell INV4 structure can be evaluated more accurately, and it is simple and feasible. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0013] Figure 1 The circuit diagram shown is of a ring oscillator. Figure 2 The diagram shows a typical STD cell structure commonly used in ring oscillators. Figure 3 The diagram shows the structure of a logic PCM. Figure 4 The diagram shows the structure of an existing LOD effect testing unit. Figure 5 The flowchart shown is a design method for the LOD effect test unit provided in an embodiment of this application. Figure 6 The diagram shown is a schematic representation of the structure of the LOD effect test unit obtained by the design method of the LOD effect test unit provided in the embodiments of this application. Detailed Implementation

[0014] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this invention.

[0015] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0016] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," indicating orientation or positional relationships, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0017] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0018] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0019] like Figure 4 As shown, existing LOD effect test units are all symmetrical structures (i.e., LOD N+N), for Figure 3 The structure of the logic PCM shown can be adopted Figure 4 The LOD 2+2 shown is used as a LOD effect test unit, which means there are two gates on each side of the effective gate.

[0020] for Figure 2 The STD cell structure shown in the figure is symmetrically represented by existing methods based on the actual situation, i.e., by adopting... Figure 4 The suitable symmetrical structure shown in the figure is used as the LOD effect test unit. To some extent, it ignores the distance difference between the four effective gates in the STD cell structure and the STI, which leads to errors in the analysis of the difference in LOD effect between the STD cell and the PCM.

[0021] To address this issue, this application provides a design method for a LOD effect test unit.

[0022] Please see Figure 5 The flowchart illustrates the design method of the LOD effect test unit provided in the embodiments of this application.

[0023] like Figure 5 As shown, the design method of this LOD effect test unit includes the following steps: Step 1: Based on the standard unit structure of a ring oscillator, design the LOD effect test unit as a first test unit and a second test unit with an asymmetric structure. Step 2: Verify whether the averaged threshold voltages of the first and second test units are equivalent to the threshold voltages of the standard unit structure.

[0024] In step one, according to Figure 2 The standard cell structure shown is designed based on the leftmost effective gate. Figure 6 The first test unit shown in the upper middle figure has one gate on the left and four gates on the right, i.e., LOD 1+4; the design is based on the effective gate located in the middle left. Figure 6 The second test unit shown in the lower figure has two gates on the left side and three gates on the right side, i.e., LOD 2+3.

[0025] In step two, the difference between the averaged threshold voltages of the first test unit and the second test unit and the threshold voltage of the standard unit structure is less than 5mV. Therefore, it can be determined that the averaged threshold voltages of the first test unit and the second test unit are equivalent to the threshold voltage of the standard unit structure.

[0026] The verification results of step two are satisfactory, and the first and second test units are used as LOD effect test units of the standard unit structure.

[0027] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this invention and are not drawn according to the actual number, shape and size of the components. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0028] In summary, the design method for the LOD effect test cell provided in this application, employing an asymmetric LOD effect test structure, more accurately evaluates the LOD effect of the standard cell INV4 structure, and is simple and feasible. Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0029] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this invention should still be covered by the claims of this application.

Claims

1. A design method for a LOD effect test unit, characterized in that, The method includes: Step 1: Based on the standard unit structure of a ring oscillator, design the LOD effect test unit as a first test unit and a second test unit with an asymmetric structure. Step 2: Verify whether the averaged threshold voltages of the first and second test units are equivalent to the threshold voltage of the standard unit structure.

2. The method according to claim 1, characterized in that, In step one, the first test unit is designed based on the leftmost effective gate according to the standard cell structure. In the first test unit, there is one gate on the left side of the effective gate and four gates on the right side.

3. The method according to claim 1, characterized in that, In step one, the second test unit is designed based on the standard unit structure and the effective gate located in the middle left. In the second test unit, there are two gates on the left side of the effective gate and three gates on the right side.

4. The method according to claim 1, characterized in that, In step two, if the difference between the averaged threshold voltages of the first and second test units and the threshold voltage of the standard unit structure is less than 5mV, the verification result is considered to be passed.

5. The method according to claim 1, characterized in that, If the verification result of step two is passed, the first test unit and the second test unit will be used as LOD effect test units of the standard unit structure.

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