Bias current generating circuit and electronic equipment

Abstract

The invention discloses a bias current generation circuit and electronic equipment, and relates to the technical field of bias current, the bias current generation circuit comprises a current mirror circuit used for generating bias current based on power supply voltage, and the current mirror circuit comprises a first transistor, a second transistor, a third transistor and a fourth transistor; the channel modulation effect suppression circuit is used for suppressing the influence of the channel modulation effect generated by the current mirror circuit on the bias current and transconductance of the bias current generation circuit, and the channel modulation effect suppression circuit comprises a first switched capacitor resistor and a second switched capacitor resistor; and the adjusting circuit is used for adjusting the bias current and the transconductance. Therefore, the bias current generating circuit has the advantages that the channel modulation effect is effectively suppressed, the stability of the bias current and transconductance is improved, and meanwhile, the additional circuit complexity is prevented from being increased.

Description

Technical Field

[0001] This application relates to the field of bias current technology, and in particular to a bias current generating circuit and electronic device. Background Technology

[0002] Bias current generation circuits play a crucial role in analog circuit modules, providing the necessary current bias for operational amplifiers, comparators, reference circuits, analog-to-digital converters, and digital-to-analog converters. Under conditions of process, voltage, and temperature fluctuations, high-performance analog circuits need to maintain good linearity, which requires stable bias current and circuit transconductance.

[0003] In existing self-biased bias current generation circuits, the channel length modulation effect, caused by the difference between the source and drain voltages of the transistors, leads to a correlation between the output current and the supply voltage, severely degrading circuit performance. For example, the voltage difference between the current source of a P-type transistor and the current sink of an N-type transistor causes instability in the transistor's operating state, affecting the accuracy of the bias current. Although some techniques use operational amplifiers to clamp the transistor drain voltage to suppress the channel length modulation effect, this method increases circuit area and power consumption, hindering the miniaturization and low-power design of integrated circuits. Summary of the Invention

[0004] In view of this, embodiments of this application provide a bias current generating circuit and an electronic device.

[0005] According to a first aspect of this application, embodiments of this application provide a bias current generating circuit, including:

[0006] A current mirror circuit is used to generate a bias current based on the power supply voltage. The current mirror circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The channel modulation effect suppression circuit is used to suppress the influence of the channel modulation effect generated by the current mirror circuit on the bias current and transconductance of the bias current generating circuit. The channel modulation effect suppression circuit includes a first switched capacitor resistor and a second switched capacitor resistor. Adjustment circuit, used to adjust the bias current and transconductance; The gate and drain of the first transistor are connected, and the first transistor is connected to the drain of the third transistor through a first switched capacitor and resistor; the gate of the first transistor is connected to the gate of the second transistor; the source of the first transistor is grounded; the source of the third transistor is connected to the power supply voltage; the gate of the third transistor is connected to the gate of the fourth transistor; the source of the fourth transistor is connected to the power supply voltage; the gate of the fourth transistor is connected to the drain of the fourth transistor, and the second transistor is connected to the drain of the second transistor through a second switched capacitor and resistor; the source of the second transistor is grounded through an adjustment circuit.

[0007] Optionally, the first transistor and the second transistor are N-type MOS transistors.

[0008] Optionally, the third and fourth transistors are P-type MOS transistors.

[0009] Optionally, the regulating circuit includes a first resistor.

[0010] Optionally, the first switched capacitor resistor includes a first capacitor, a first controllable switch, and a second controllable switch. One end of the first capacitor is connected to the drain of the third transistor and one end of the first controllable switch, respectively, and the other end is connected to the other end of the first controllable switch and one end of the second controllable switch, respectively. The other end of the second controllable switch is connected to the drain of the first transistor.

[0011] Optionally, the second switched capacitor resistor includes a second capacitor, a third controllable switch, and a fourth controllable switch. One end of the second capacitor is connected to one end of the third controllable switch and the drain of the fourth transistor, respectively, and the other end is connected to the other end of the third controllable switch and one end of the fourth controllable switch, respectively. The other end of the fourth controllable switch is connected to the drain of the second transistor.

[0012] Optionally, the bias current generating circuit further includes: The first filter capacitor has one end connected to the drain of the first transistor and the other end grounded.

[0013] Optionally, the bias current generating circuit further includes: The second filter capacitor has one end connected to the drain of the fourth transistor and the other end grounded.

[0014] Optionally, the bias current generating circuit further includes: The first control circuit is used to monitor the power supply voltage and control the switching frequency of the first and second switched capacitor resistors based on the power supply voltage, so as to suppress the influence of the channel modulation effect generated by the current mirror circuit on the bias current and transconductance of the bias current generation circuit.

[0015] Optionally, the regulating circuit includes a third switched capacitor resistor and a corresponding second control circuit; The second control circuit is used to control the switching frequency of the third switched capacitor resistor based on the reference voltage signal and the control voltage signal, so as to control the transconductance of the bias current generating circuit.

[0016] Optionally, the third switched capacitor resistor includes a third capacitor, a fifth controllable switch, and a sixth controllable switch; One end of the third capacitor is connected to one end of the fifth controllable switch and the source terminal of the second transistor, and the other end is connected to the other end of the fifth controllable switch and one end of the sixth controllable switch; the other end of the sixth controllable switch is grounded.

[0017] Optionally, the second control circuit includes: Operational amplifier, fifth transistor, sixth transistor, seventh transistor, eighth transistor, ninth transistor, tenth transistor, eleventh transistor, twelfth transistor, thirteenth transistor, first voltage-controlled current source, second voltage-controlled current source and third voltage-controlled current source; The negative terminal of the operational amplifier is connected to a reference voltage, and its positive terminal is connected to the drain of the fifth transistor and simultaneously connected to the positive terminal of the first voltage-controlled current source. The negative terminal of the first voltage-controlled current source is grounded. The control terminals of the first, second, and third voltage-controlled current sources are connected to a control voltage. The input terminal of the operational amplifier is connected to the gate of the fifth transistor and simultaneously connected to the gates of the sixth, seventh, eighth, and ninth transistors. The sources of the fifth, sixth, seventh, eighth, and ninth transistors are connected to the power supply voltage. The drain of the sixth transistor is connected to the drain of the tenth transistor and then connected to the thirteenth transistor. The gate of the tenth transistor, the source of the tenth transistor, and the positive terminal of the second voltage-controlled current source are connected to the source of the eleventh transistor. The drain of the eleventh transistor and the drain of the seventh transistor are connected to the gate of the twelfth transistor. The gate of the eleventh transistor and the drain of the twelfth transistor are connected to the control terminal of the fifth controllable switch and connected to the drain of the eighth transistor. The source of the twelfth transistor and the source of the thirteenth transistor are connected to the positive terminal of the third voltage-controlled current source. The negative terminal of the third voltage-controlled current source is connected to ground. The drain of the thirteenth transistor and the drain of the ninth transistor are connected to the control terminal of the sixth controllable switch.

[0018] Optionally, the fifth, sixth, seventh, eighth, and ninth transistors are P-type MOS transistors.

[0019] Optionally, the tenth, eleventh, twelfth, and thirteenth transistors are N-type MOS transistors.

[0020] According to a second aspect of this application, embodiments of this application provide an electronic device, including: Such as the bias current generating circuit in the first aspect or any embodiment of the first aspect.

[0021] The bias current generation circuit provided in this application uses a current mirror circuit to generate a bias current based on the power supply voltage. The channel modulation effect suppression circuit effectively compensates for the channel modulation effect caused by power supply voltage fluctuations by dynamically adjusting the equivalent resistance of the switched capacitor and resistor, ensuring the transistor operates in a stable state. The adjustment circuit provides flexible bias current and transconductance adjustment capabilities. The entire circuit structure is compact, avoiding the increase in area and power consumption caused by introducing an operational amplifier, while achieving good suppression of PVT fluctuations and ensuring the stability of bias current and transconductance.

[0022] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the structure of a bias current generating circuit in an embodiment of this application. Figure 1 ; Figure 2 This is a schematic diagram of the structure of a bias current generating circuit in an embodiment of this application. Figure 2 ; Figure 3 This is a schematic diagram of the structure of a bias current generating circuit in an embodiment of this application. Figure 3 ; Figure 4 This is a schematic diagram of the structure of a bias current generating circuit in an embodiment of this application. Figure 4 ; Figure 5 This is a schematic diagram of the structure of the second control circuit in the embodiments of this application; Figure 6 This is a schematic diagram of the hardware structure of an electronic device according to an embodiment of this application.

[0024] Explanation of the labels in the diagram: 11-Current mirror circuit; 121-First switched capacitor resistor; 122-Second switched capacitor resistor; 13-Adjustment circuit; 131-Third switched capacitor resistor; 132-Second control circuit. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] For ease of understanding, the following explains some key terms in this embodiment: Bias current generation circuits are widely used circuit modules in analog integrated circuits. Their main function is to provide stable and accurate DC bias current to other circuit units (such as operational amplifiers, comparators, etc.). These bias currents are crucial for ensuring the normal operating point, linearity, and performance stability of the circuit.

[0027] A current mirror circuit is a circuit structure that can replicate or proportionally replicate current. It typically consists of two or more matched transistors that share a gate voltage to ensure a specific proportional relationship between the currents flowing through them. This circuit is commonly used in analog design for applications such as current sources, current biasing, and current amplification.

[0028] Channel modulation effect suppression circuits aim to mitigate or eliminate the negative impact of transistor channel length modulation. Channel modulation refers to the phenomenon where changes in the drain-source voltage of a transistor alter the effective channel length, thereby affecting the transistor's output current and output resistance. This effect causes the output current of the current source to fluctuate with the power supply voltage, reducing the circuit's power supply rejection ratio and accuracy.

[0029] An adjustment circuit is a module used to adjust circuit parameters. In this embodiment, the adjustment circuit is configured to change the magnitude of the bias current and transconductance to adapt to different application requirements or to compensate for the effects of process, voltage, and temperature (PVT) variations.

[0030] A switched-capacitor resistor is a circuit element that simulates the behavior of resistance by using the periodic switching of a capacitor and a switch. Its equivalent resistance value can be adjusted by changing the switching frequency or the capacitance value. Compared to traditional resistors, switched-capacitor resistors offer advantages such as better integration, smaller area, lower temperature coefficient, and greater adjustability.

[0031] A transistor is a semiconductor device, and in this embodiment, it mainly refers to a metal-oxide-semiconductor field-effect transistor (MOSFET). A MOSFET controls the current in the channel through the gate voltage and is a basic unit that constitutes an integrated circuit.

[0032] Bias current is the DC current required to set the operating point of a transistor or circuit module. A stable bias current is crucial for ensuring the performance of analog circuits.

[0033] Transconductance (Gm) is a parameter that measures the ability of a transistor or amplifier to convert a change in input voltage into a change in output current. A constant transconductance is crucial for maintaining the gain stability and linearity of an amplifier.

[0034] This application provides a bias current generating circuit, such as... Figure 1 As shown, it includes: The current mirror circuit 11 is used to generate a bias current based on the power supply voltage. The current mirror circuit 11 includes a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4.

[0035] The channel modulation effect suppression circuit is used to suppress the influence of the channel modulation effect generated by the current mirror circuit 11 on the bias current and transconductance of the bias current generating circuit. The channel modulation effect suppression circuit includes a first switched capacitor resistor 121 and a second switched capacitor resistor 122.

[0036] Adjustment circuit 13 is used to adjust the bias current and transconductance.

[0037] The gate and drain of the first transistor M1 are connected, and are connected to the drain of the third transistor M3 through the first switched capacitor resistor 121; the gate of the first transistor M1 is connected to the gate of the second transistor M2; the source of the first transistor M1 is grounded; the source of the third transistor M3 is connected to the power supply voltage (VDD); the gate of the third transistor M3 is connected to the gate of the fourth transistor M4; the source of the fourth transistor M4 is connected to the power supply voltage; the gate of the fourth transistor M4 is connected to the drain of the fourth transistor M4, and is connected to the drain of the second transistor M2 through the second switched capacitor resistor 122; the source of the second transistor M2 is grounded through the adjustment circuit 13.

[0038] The specific working principle of this application embodiment is as follows: M1 and M4 form a current generating circuit, and M3 and M2 form a current source output circuit, wherein M1 and M2 share a common gate, and =K Where W is the transistor width, L is the transistor length, and K is the scaling factor. The aspect ratio of transistor M1, Given the aspect ratio of transistor M2, the overdrive voltage of M2 is much smaller than that of M1. A current balance circuit needs to be connected in series with the source of M2. M4 is used as a diode to replicate the current, which is then copied to M3 to self-bias M1. Due to VDS... M4 =VGS M4 =Vth + Vod, approximately equal to Vth, while VDS M3 =VDD-VGS M1 , approximately equal to VDD - Vth, where Vod is the overdrive voltage, Vth is the threshold voltage, VDS is the drain-source voltage, and VGS is the gate-source voltage; therefore For VDD=5V, The channel modulation effect is significant, leading to I3 is the current of M3, and I4 is the current of M4. This significantly reduces the power supply rejection performance of the bias circuit. Similarly, VDS M2 =VGS M1 =Vth+Vod,VDS M4 =VDD-VGS M1To address this, this embodiment of the application uses a switched capacitor resistor connected in series between M3 and M1, and another switched capacitor resistor connected in series between M2 and M4. The resistance value of the switched capacitor resistor is R = 1 / (Cf), where C is the capacitance of the capacitor in the switched capacitor resistor, and f is the switching frequency of the switch in the switched capacitor resistor. This allows for dynamic monitoring of the VDD voltage and dynamic adjustment of the switching frequency of the switched capacitor resistor, controlling the voltage across the switched capacitor resistor to its maximum value that allows M1~M4 to enter the saturation region. This maximizes the suppression of the bias current caused by power supply voltage fluctuations and improves the power supply rejection characteristics of the output current.

[0039] In this embodiment, Gm of M1 is determined by K and the adjustment circuit. Based on the circuit's requirement for Gm, the resistance value of the adjustment circuit is controlled to change the circuit's Gm. By directly connecting the first switched capacitor resistor in series between M1 and M4, and directly connecting the second switched capacitor resistor in series between M2 and M3, the VDS voltage difference between M1 and M2, and between M3 and M4, is compensated through the switched capacitor resistors. The switching frequency of the first and second switched capacitor resistors can be controlled based on the power supply voltage. A higher power supply voltage results in a lower switching frequency and a larger equivalent resistance; a lower power supply frequency results in a lower equivalent resistance and a lower voltage drop. This adapts to changes in VDD, ensuring that M1, M2, M3, and M4 operate in the saturation region and that their VDS are kept approximately equal, suppressing the short-channel effect on the bias current, and further reducing the bias current and the power factor of Gm.

[0040] In this embodiment, the first transistor and the second transistor can form a current mirror pair, while the third transistor and the fourth transistor form another current mirror pair. They work together to generate a stable bias current.

[0041] In this embodiment, a channel modulation effect suppression circuit is introduced. This suppression circuit aims to reduce or eliminate the adverse effects of channel modulation on bias current and transconductance stability. The channel modulation effect suppression circuit may include a first switched-capacitor resistor and a second switched-capacitor resistor. These switched-capacitor resistors can be configured in the critical path of the current mirror circuit to provide dynamically adjustable equivalent resistance, thereby compensating for variations in transistor drain-source voltage. For example, the first switched-capacitor resistor may be configured between the first and third transistors, while the second switched-capacitor resistor may be configured between the second and fourth transistors.

[0042] This embodiment also includes an adjustment circuit for regulating the bias current and transconductance. This adjustment circuit can be implemented in various forms; for example, it can be a variable resistor, whose resistance value is changed to adjust the current flowing through the circuit, thereby affecting the bias current and transconductance. In another implementation, the adjustment circuit can be a controllable current source, whose output current is adjusted to achieve the regulation purpose.

[0043] The bias current generation circuit provided in this application uses a current mirror circuit to generate a bias current based on the power supply voltage. The channel modulation effect suppression circuit effectively compensates for the channel modulation effect caused by power supply voltage fluctuations by dynamically adjusting the equivalent resistance of the switched capacitor and resistor, ensuring the transistor operates in a stable state. The adjustment circuit provides flexible bias current and transconductance adjustment capabilities. The entire circuit structure is compact, avoiding the increase in area and power consumption caused by introducing an operational amplifier, while achieving good suppression of PVT fluctuations and ensuring the stability of bias current and transconductance.

[0044] In some embodiments of this application, the current mirror circuit of the bias current generation circuit includes a first transistor and a second transistor; however, their specific conduction types are not explicitly defined. This uncertainty may make it difficult to optimize the matching accuracy, response speed, and overall power consumption and noise performance of the current mirror during actual design and implementation, thereby affecting the stability of the bias current and the precise control of transconductance.

[0045] In this regard, this application further proposes that the first transistor and the second transistor are N-type MOS transistors.

[0046] An N-type MOSFET is a field-effect transistor whose conductive channel is primarily composed of electrons. When a positive voltage is applied to the gate exceeding its threshold voltage, an N-type inversion layer forms on the substrate surface beneath the gate oxide layer, serving as a conductive channel and allowing current to flow from the drain to the source. As one possible implementation, the first and second transistors can be enhancement-mode N-type MOSFETs. This type of transistor is off when the gate-source voltage is zero and requires a positive gate-source voltage to form a conductive channel and turn on. Enhancement-mode N-type MOSFETs are the most commonly used transistor type in digital and analog integrated circuits due to their ease of control and low quiescent power consumption. As another possible implementation, the first and second transistors can also be depletion-mode N-type MOSFETs. This type of transistor is on when the gate-source voltage is zero and requires a negative gate-source voltage to turn off. Depletion-mode N-type MOSFETs offer unique advantages in certain applications, such as those requiring normally-on characteristics or as load transistors. In addition, the first transistor and the second transistor can also be N-type MOS transistors optimized based on specific semiconductor manufacturing processes, which can provide N-type MOS transistors with specific performance characteristics (such as low noise, high frequency response, and low power consumption).

[0047] By explicitly defining the first and second transistors as N-type MOSFETs, the current mirror circuit can utilize the inherent high electron mobility and good matching characteristics of N-type MOSFETs. This helps improve the current mirror's current replication accuracy and response speed, thereby ensuring the stability of the bias current and precise control of transconductance. Compared to cases where the transistor type is not specified, this solution simplifies the circuit design and optimization process and effectively improves the performance and reliability of the bias current generation circuit under different operating conditions.

[0048] In some other embodiments, this application further proposes that the third transistor and the fourth transistor are P-type MOS transistors.

[0049] A P-type MOSFET is a metal-oxide-semiconductor field-effect transistor whose primary charge carriers are holes. A P-type MOSFET typically consists of a gate, source, and drain. When the gate voltage is sufficiently low relative to the source voltage, a P-type inversion layer is formed in the substrate beneath the gate, serving as a conductive channel and allowing current to flow from the source to the drain. P-type MOSFETs are commonly used in circuits as pull-up transistors, current sources, or input transistors for differential pairs due to their good conduction characteristics near the power supply voltage. As a specific implementation, P-type MOSFETs can be enhancement-mode P-type MOSFETs manufactured using standard complementary metal-oxide-semiconductor (CMOS) processes, which have a defined threshold voltage and good switching characteristics. Alternatively, low-threshold-voltage P-type MOSFETs can be used to accommodate applications requiring lower power supply voltages or faster switching speeds; or high-threshold-voltage P-type MOSFETs can be used to reduce leakage current or improve noise immunity.

[0050] By employing the aforementioned technical solution, setting the third and fourth transistors as P-type MOSFETs effectively utilizes the power supply voltage, improving the voltage margin of the current mirror circuit, especially in low power supply voltage environments. This configuration facilitates more precise current matching, thereby enhancing the stability and accuracy of the bias current. Furthermore, as the upper arm of the current mirror, the P-type MOSFET typically exhibits a better power supply rejection ratio, effectively suppressing the impact of power supply voltage fluctuations on the bias current, thus improving the performance and reliability of the entire bias current generation circuit.

[0051] In some embodiments described above in this application, a bias current generating circuit is proposed, which includes an adjustment circuit for regulating the bias current and transconductance. However, in practical applications, how to effectively regulate the bias current and transconductance in a simple and easy-to-implement manner to meet the performance requirements under different operating conditions is a problem that needs to be considered.

[0052] In this regard, such as Figure 2 As shown, this application further proposes that the above-mentioned adjustment circuit 13 includes a first resistor Rs.

[0053] The resistance value of the first resistor can be preset according to the required bias current and transconductance. For example, if a smaller bias current and transconductance are required, a first resistor with a larger resistance value can be selected; conversely, if a larger bias current and transconductance are required, a first resistor with a smaller resistance value can be selected.

[0054] The solution in this application integrates a first resistor into the adjustment circuit and connects it between the source terminal of the second transistor and ground, thereby achieving effective regulation of the bias current and transconductance, and fixing the bias current and transconductance of the bias current generation circuit. Specifically, the current mirror circuit establishes the bias current through the first transistor, the second transistor, the third transistor, and the fourth transistor. When the first resistor is connected in series between the source terminal of the second transistor and ground, the first resistor introduces a source degradation effect. This source degradation resistor increases the effective source voltage of the second transistor, thereby affecting its drain current. By changing the resistance value of the first resistor, the source voltage of the second transistor can be changed, thereby regulating the current flowing through the second transistor. Since the second transistor is part of the current mirror circuit, changes in its current directly affect the bias current of the entire current mirror circuit. At the same time, the source degradation resistor also affects the transconductance of the transistor; generally, increasing the source resistor reduces the effective transconductance of the transistor. The channel modulation effect suppression circuit, including a first switched capacitor resistor and a second switched capacitor resistor, functions to suppress the channel modulation effect, ensuring the accuracy and stability of the current mirror circuit. This suppression mechanism is relatively independent of the adjustment mechanism of the first resistor. Therefore, the first resistor, as a key component of the regulating circuit, effectively regulates the bias current and transconductance by changing the source impedance of the second transistor.

[0055] By introducing a first resistor into the adjustment circuit of the bias current generation circuit using the above technical solution, the bias current and transconductance of the bias current generation circuit can be effectively adjusted in a simple and easy-to-implement manner. This first resistor directly affects the operating point and transconductance characteristics of the second transistor by changing its source impedance, thereby making the output characteristics of the entire bias current generation circuit controllable. This adjustment method eliminates the need for complex control circuits, reducing circuit complexity and power consumption, while ensuring the stability of the bias current and transconductance, thus improving the adaptability and performance of the bias current generation circuit.

[0056] In other implementations, such as Figure 2 As shown, this application further proposes that the aforementioned first switched capacitor resistor 121 includes a first capacitor C1, a first controllable switch S3, and a second controllable switch S4. One end of the first capacitor C1 is connected to the drain of the third transistor M3 and one end of the first controllable switch S3, respectively, and the other end is connected to the other end of the first controllable switch S3 and one end of the second controllable switch S4, respectively; the other end of the second controllable switch S4 is connected to the drain of the first transistor M1.

[0057] In this circuit, the first capacitor C1 refers to the capacitor element used to store charge in the first switched capacitor resistor. Its capacitance directly affects the value of the equivalent resistance and the frequency response characteristics of the circuit. The first capacitor C1 can take various forms, such as a metal-oxide-semiconductor (MOS) capacitor, a metal-insulator-metal (MIM) capacitor, or a PN junction capacitor, depending on the process, area, and performance requirements. The first controllable switch S3 and the second controllable switch S4 refer to the switching elements used to control the charge path in the first switched capacitor resistor. They are periodically turned on and off by an external control signal, thereby realizing the charging, discharging, and charge transfer of the first capacitor C1. The first controllable switch can be implemented using a MOSFET transistor (such as an N-type MOS transistor or a P-type MOS transistor), a bipolar transistor, or other semiconductor switching devices. For example, a pair of complementary MOSFET transistors can be used as switches, controlled by a non-overlapping two-phase clock signal.

[0058] The above technical solution specifically implements the first switched-capacitor resistor as a structure consisting of a first capacitor, a first controllable switch, and a second controllable switch, connected to the current mirror circuit in a specific manner. This design allows the channel modulation effect suppression circuit to provide the required equivalent resistance in a highly efficient and integrated manner. Compared to using traditional resistors, the switched-capacitor resistor is better suited to integrated circuit processes, and its equivalent resistance value can be precisely controlled by adjusting the switching frequency and capacitance value, thus more flexibly suppressing the channel modulation effect. This helps improve the stability of the bias current and the accuracy of the transconductance of the bias current generation circuit, especially maintaining good matching characteristics of the current mirror circuit under changes in power supply voltage or temperature, thereby improving the performance and reliability of the entire circuit.

[0059] In some embodiments described above, this application further proposes that, in the aforementioned bias current generating circuit, such as... Figure 2 As shown, the second switched capacitor resistor 122 includes a second capacitor C2, a third controllable switch S5, and a fourth controllable switch S6. One end of the second capacitor C2 is connected to one end of the third controllable switch S5 and the drain of the fourth transistor M4, respectively, and the other end is connected to the other end of the third controllable switch S5 and one end of the fourth controllable switch S6, respectively. The other end of the fourth controllable switch S6 is connected to the drain of the second transistor M2.

[0060] The second capacitor is the core component of the second switched capacitor resistor, used to store charge and simulate resistance characteristics. It can be implemented in various forms; for example, it can be a metal-insulator-metal (MIM) capacitor, which has good linearity and matching characteristics; or it can be a metal-oxide-semiconductor (MOS) capacitor, which has high area efficiency in integrated circuits. Alternatively, it can be a PN junction capacitor, formed by reverse biasing the PN junction. The third controllable switch controls the charging and discharging path of the second capacitor and is an important component in realizing the switched capacitor resistor function. This controllable switch can be a MOS transistor, such as an N-type or P-type MOS transistor, which is turned on or off by controlling its gate voltage; or it can be a bipolar junction transistor (BJT), whose switching state is controlled by controlling its base current. The fourth controllable switch works in conjunction with the third controllable switch to jointly control the charging and discharging process of the second capacitor, thereby simulating resistance. Similar to the third controllable switch, the fourth controllable switch can also be a MOS transistor, such as an N-type or P-type MOS transistor, which is turned on or off by controlling its gate voltage; or it can be a bipolar junction transistor (BJT), which controls its switching state by controlling its base current.

[0061] The above technical solution clarifies the specific structure and connection method of the second switched capacitor resistor in the channel modulation effect suppression circuit, enabling the resistor to be implemented as a switched capacitor. This implementation not only makes the equivalent resistance value adjustable, allowing for precise adjustment according to actual needs, but also, due to the characteristics of the switched capacitor resistor, its sensitivity to process changes and temperature drift is low, thereby improving the stability and reliability of the bias current generation circuit under different operating conditions. Furthermore, by connecting one end of the second capacitor to one end of the third controllable switch and the drain of the fourth transistor, the other end to the other end of the third controllable switch and one end of the fourth controllable switch, and the other end of the fourth controllable switch to the drain of the second transistor, an effective feedback path is constructed. This path can more accurately compensate for the channel modulation effect in the current mirror circuit, thereby significantly improving the stability of the bias current and transconductance, ensuring that the bias current and transconductance output by the bias current generation circuit have higher accuracy and lower distortion.

[0062] In some other embodiments, this application proposes a bias current generating circuit that generates a bias current through a current mirror circuit. However, in practical applications, noise in the circuit, especially high-frequency noise, may couple to critical nodes of the current mirror circuit, such as the drain of the first transistor, thereby affecting the stability and accuracy of the bias current and thus reducing the performance of the entire bias current generating circuit.

[0063] In this regard, such as Figure 2As shown, this application further proposes that the above-mentioned bias current generating circuit also includes a first filter capacitor C. B1 The first filter capacitor C B1 One end is connected to the drain of the first transistor M1, and the other end is grounded.

[0064] The first filter capacitor is a passive electronic component used to filter out high-frequency noise or ripple in a circuit. Various types of capacitors can be used for the first filter capacitor, such as ceramic capacitors, tantalum capacitors, electrolytic capacitors, or film capacitors. The specific type of capacitor chosen depends on parameters such as the required filtering frequency range, capacitance value, ESR (equivalent series resistance), ESL (equivalent series inductance), and the circuit's operating voltage and temperature. For example, in scenarios requiring filtering out higher-frequency noise, ceramic capacitors with lower ESR and ESL are typically chosen; while in scenarios requiring larger capacitance values ​​to filter out lower-frequency ripple, electrolytic or tantalum capacitors may be used. Grounding refers to connecting a point in a circuit to a common reference potential, typically zero potential or system ground. In a circuit, grounding not only provides a stable reference potential but also serves as a return path for current and helps suppress noise and provide safety protection. Grounding can be achieved in various ways, such as directly connecting to the common ground plane of the circuit board or connecting to the negative terminal of the power supply. In analog circuits, strategies such as star grounding, single-point grounding, or multi-point grounding are typically used to reduce noise interference, ensuring stable ground potential and mutual isolation between different modules.

[0065] By connecting a first filter capacitor to ground at the drain of the first transistor, high-frequency noise and ripple coupled to this critical node can be effectively filtered out. This significantly improves the voltage stability at the input of the current mirror circuit, thereby ensuring the accuracy and stability of the bias current. Therefore, this solution can effectively suppress the impact of noise on the performance of the bias current generation circuit, improving the overall circuit's anti-interference capability and the quality of the output bias current.

[0066] In some other embodiments, this application proposes a bias current generation circuit that generates a bias current based on the power supply voltage through a current mirror circuit. However, in practical applications, the drain voltage of the transistors in the current mirror circuit, especially the fourth transistor, is easily affected by power supply noise, coupling noise, etc., causing voltage fluctuations at this node, which in turn affects the matching accuracy of the current mirror and the stability of the bias current, resulting in an impure and unstable bias current.

[0067] In this regard, such as Figure 2 As shown, this application further proposes that the above-mentioned bias current generating circuit also includes a second filter capacitor C. B2 The second filter capacitor C B2One end is connected to the drain of the fourth transistor M4, and the other end is grounded.

[0068] The second filter capacitor is a passive device used to filter high-frequency noise and stabilize DC voltage or current in a circuit. Its main function is to absorb transient voltage fluctuations, smooth ripple on power supply or signal lines, and provide a low-impedance path for high-frequency noise to flow to ground, thereby improving circuit stability. The second filter capacitor can be implemented in various forms. For example, it can be a multilayer ceramic capacitor with good high-frequency characteristics and a small equivalent series resistance, effectively filtering high-frequency noise; or it can be an electrolytic capacitor with a large capacitance, suitable for filtering lower-frequency ripple. One end of the second filter capacitor is connected to the drain of the fourth transistor, and the other end is grounded. This connection method puts the second filter capacitor in parallel with the drain of the fourth transistor, forming a low-pass filter. This filter can effectively bypass any high-frequency noise components that may be present on the drain of the fourth transistor to ground, thereby stabilizing the voltage at that node.

[0069] By adding a second filter capacitor to the bias current generation circuit and connecting it between the drain of the fourth transistor and ground, the high-frequency noise and transient interference at the drain of the fourth transistor can be significantly suppressed. This helps stabilize the operating point of the fourth transistor, thereby improving the matching accuracy of the current mirror circuit and the stability of the output bias current. Ultimately, this solution enables the bias current generation circuit to output a cleaner and more stable bias current, improving the performance and reliability of the entire circuit system.

[0070] In some other embodiments, this application further proposes that the bias current generating circuit also includes a first control circuit for monitoring the power supply voltage and controlling the switching frequency of the first switched capacitor resistor and the second switched capacitor resistor based on the power supply voltage, so as to suppress the influence of the channel modulation effect generated by the current mirror circuit on the bias current and transconductance of the bias current generating circuit.

[0071] The first control circuit is an electronic module used to monitor and control other circuits or components. It can be implemented using digital logic circuits such as microcontrollers (MCUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), or field-programmable gate arrays (FPGAs), or it can be implemented using analog circuits such as operational amplifiers and comparators in conjunction with logic gates. Its core function is to receive input signals, process them, and output control signals.

[0072] Through the above technical solution, the first control circuit introduced in this application can dynamically monitor the power supply voltage and adjust the switching frequency of the first and second switched capacitor resistors in real time accordingly. This adaptive control method enables the channel modulation effect suppression circuit to flexibly adjust its suppression strategy according to changes in actual operating conditions, thereby significantly improving the suppression effect of the channel modulation effect. Especially when there are fluctuations in the power supply voltage, this solution can effectively compensate for the impact of voltage changes on the bias current and transconductance stability, ensuring that the bias current generation circuit can output stable and accurate bias current and transconductance under various operating environments, avoiding performance degradation caused by power supply voltage fluctuations, and thus improving the reliability and robustness of the entire circuit.

[0073] In some embodiments described above in this application, the bias current generating circuit adjusts the magnitude of the bias current and transconductance through an adjustment circuit. However, in practical applications, it may be necessary to perform more precise and flexible dynamic control of the transconductance of the bias current generating circuit to adapt to different operating conditions or performance requirements, and a simple adjustment circuit may be insufficient to meet such refined control needs.

[0074] In this regard, such as Figure 3 As shown, this application proposes a bias current generating circuit, whose regulating circuit 13 includes a third switched capacitor resistor 131 and a corresponding second control circuit 132. The second control circuit 132 is used to control the switching frequency of the third switched capacitor resistor 131 based on a reference voltage signal and a control voltage signal, so as to control the transconductance of the bias current generating circuit.

[0075] The third switched capacitor resistor 131 is a circuit element that simulates resistive behavior through periodic switching operations. Its effective resistance value can be adjusted by changing the switching frequency or duty cycle. For example, the third switched capacitor resistor can consist of a capacitor and two or more controllable switches. By controlling the on / off sequence and frequency of these switches, precise control of the equivalent resistance can be achieved. Another implementation is to use multiple parallel switched capacitor units, changing the total equivalent resistance by selectively turning these units on or off. Because capacitors have a good temperature coefficient, and temperature coefficient compensation can be achieved through simple frequency compensation, precise and stable adjustment of the bias current generating circuit Gm can be achieved. The second control circuit 132 is an electronic module for generating control signals to adjust the switching frequency of the third switched capacitor resistor. This second control circuit can receive a reference voltage signal and a control voltage signal as inputs, and output a frequency-adjustable pulse signal to drive the controllable switches in the third switched capacitor resistor based on the difference between these input signals or a specific algorithm. The reference voltage signal provides a stable reference level for the second control circuit, used for comparison with the control voltage signal or as a reference point for the control algorithm. The reference voltage signal can be provided by a high-precision voltage reference source, ensuring the accuracy and stability of the control. The control voltage signal is an externally input voltage signal used to indicate the desired transconductance value.

[0076] Through the above technical solution, the adjustment circuit of the bias current generation circuit is specifically defined as a third switched capacitor resistor and a second control circuit, which significantly improves the transconductance adjustment capability of the circuit. The second control circuit can precisely control the switching frequency of the third switched capacitor resistor based on the reference voltage signal and the control voltage signal, thereby achieving fine and dynamic adjustment of the transconductance of the bias current generation circuit. This not only overcomes the limitations of traditional fixed resistor or simple variable resistor adjustment methods, but also enables the bias current generation circuit to better adapt to changes in the external environment or system performance requirements, such as adjusting the amplifier gain or bandwidth in different operating modes, thereby improving the flexibility, stability, and performance of the entire electronic device.

[0077] In some of the embodiments described above in this application, such as Figure 4 As shown, this application further proposes a third switched capacitor resistor 131 including a third capacitor Cs, a fifth controllable switch S1, and a sixth controllable switch S2. One end of the third capacitor Cs is connected to one end of the fifth controllable switch S1 and the source terminal of the second transistor M2, respectively, and the other end is connected to the other end of the fifth controllable switch S1 and one end of the sixth controllable switch S2, respectively; the other end of the sixth controllable switch S2 is grounded.

[0078] The third capacitor, as the core energy storage element, stores and releases charge during switching operations, thus generating an equivalent resistance effect. Its capacitance, parasitic parameters, and withstand voltage characteristics directly affect the equivalent resistance, linearity, and operating frequency range of the third switched capacitor resistor. The third capacitor can be implemented using various structures; for example, a metal-insulator-metal (MIM) capacitor can be used, which has good linearity and stability; or a metal-oxide-semiconductor (MOS) capacitor can be used, which can provide a larger capacitance value per unit area. The fifth and sixth controllable switches are key control elements in the third switched capacitor resistor. Their function is to turn on or off according to external control signals, thereby controlling the charging and discharging path of the third capacitor. The on-resistance, turn-off leakage current, switching speed, and control voltage range of these switches are important parameters to consider during design. The fifth and sixth controllable switches can be composed of a single MOSFET transistor, such as an N-type MOSFET or a P-type MOSFET, with its gate connected to the control signal; or they can be composed of transmission gates (CMOS switches) to provide better signal transmission characteristics and lower on-resistance.

[0079] During operation, the second control circuit generates complementary control signals CK and They respectively drive the fifth and sixth controllable switches to alternately turn on and off.

[0080] The above technical solution clarifies the specific structure and connection method of the third switched capacitor resistor in the adjustment circuit, enabling it to effectively function as a variable resistor. This structure allows for precise control of the switching frequencies of the fifth and sixth controllable switches via the second control circuit, thereby finely adjusting the equivalent resistance of the third switched capacitor resistor. Since the third switched capacitor resistor is connected between the source terminal of the second transistor and ground, changes in its equivalent resistance directly affect the source potential and current flowing through the second transistor, thus achieving precise and flexible adjustment of the transconductance of the bias current generation circuit. This not only overcomes the limitations of traditional fixed resistors or analog variable resistors in terms of integration and adjustment accuracy, but also provides a wider range of transconductance adjustment capabilities while maintaining the stability of the current mirror circuit, thereby optimizing the performance and adaptability of the bias current generation circuit.

[0081] In some of the embodiments described above in this application, such as Figure 5 As shown, this application further proposes a second control circuit including: operational amplifier A1, fifth transistor M5, sixth transistor M6, seventh transistor M7, eighth transistor M8, ninth transistor M9, tenth transistor M10, eleventh transistor M11, twelfth transistor M12, thirteenth transistor M13, first voltage-controlled current source I1, and second voltage-controlled current source I2. SS1 and the third voltage-controlled current source ISS2 The negative terminal of operational amplifier A1 is connected to the reference voltage V. REF The positive terminal is connected to the drain of the fifth transistor M5 and simultaneously connected to the positive terminal of the first voltage-controlled current source I1, while the negative terminal of the first voltage-controlled current source I1 is grounded; the first voltage-controlled current source I1 and the second voltage-controlled current source I... SS1 and the third voltage-controlled current source I SS2 The control terminal is connected to the control voltage Vcont. The input terminal of operational amplifier A1 is connected to the gate of the fifth transistor M5, and also to the gates of the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9. The sources of the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 are connected to the power supply voltage VDD. The drain of the sixth transistor M6 is connected to the drain of the tenth transistor M10 and then to the gate of the thirteenth transistor M13. The source of the tenth transistor M10 is connected to the second voltage-controlled current source I. SS1 The positive terminal of transistor M11 is connected to the source of transistor M11. The drain of transistor M11 is connected to the drain of transistor M7 and simultaneously connected to the gate of transistor M12. The gate of transistor M11 and the drain of transistor M12 are connected to the control terminal of the fifth controllable switch S1 and to the drain of transistor M8. The source of transistor M12 is connected to the source of transistor M13 and connected to the third voltage-controlled current source I. SS2 The positive terminal, the third voltage-controlled current source I SS2 The negative terminal is connected to ground; the drain of the thirteenth transistor M13 is connected to the drain of the ninth transistor M9 and simultaneously connected to the control terminal of the sixth controllable switch S2.

[0082] In this embodiment, M2 and M4 form a current source, simultaneously mirroring to M3 to generate a mirror current. M1 replicates the mirror current and provides bias for M2. Cs and switches S1 and S2 form the equivalent resistance of a switched capacitor, controlled by a non-overlapping CK signal. Operational amplifier A1 clamps the drain of M5 and controls the swing of the CK signal. M6, M7, M10, M11, and I... SS1 The delay unit that forms a voltage-controlled oscillator is controlled by I. SS1 Tail current controls frequency adjustment, and frequency adjustment is used to control and adjust the bias circuit Gm.

[0083] Through the above technical solution, the internal structure of the second control circuit is clearly defined. Its combination of operational amplifiers, multi-stage transistors, and voltage-controlled current sources enables precise processing of the reference voltage signal and the control voltage signal, and a stable output control signal to adjust the switching frequency of the third switched capacitor resistor. This allows the transconductance of the bias current generation circuit to be stably and precisely adjusted, significantly improving the accuracy and stability of transconductance control. This optimizes the overall performance of the bias current generation circuit, enabling it to provide accurate bias current and transconductance under different operating conditions, effectively solving the problems of insufficient control accuracy and poor stability that may exist in traditional control circuits.

[0084] This application also proposes an electronic device, such as Figure 6 As shown, the electronic device includes the bias current generating circuit in any of the above embodiments.

[0085] Electronic devices refer to devices that utilize electrical energy to operate and perform specific functions. Their scope is broad, ranging from simple consumer electronics to complex industrial control systems. For example, they can be computing devices for data processing, communication devices for information transmission, sensor devices for environmental sensing, or power management devices for energy conversion. Electronic devices integrate various circuit modules that work together to complete preset tasks. The aforementioned bias current generation circuit is based on the bias current generation circuit described above. Its core function is to generate a stable and adjustable bias current and effectively suppress channel modulation effects. This circuit typically includes key components such as a current mirror circuit, a channel modulation effect suppression circuit, and an adjustment circuit. Through sophisticated connection and control mechanisms, it ensures the accuracy and stability of the output bias current and allows for flexible adjustment of the bias current and transconductance.

[0086] The solution of this application integrates the aforementioned bias current generation circuit into an electronic device, enabling the device to obtain a stable, controllable bias current suppressed by channel modulation effects. Specifically, the bias current generation circuit, as a key power management or signal processing module within the electronic device, provides precise bias current to other active circuits (e.g., amplifiers, filters, data converters, or sensor interface circuits) within the device. This bias current generation circuit utilizes its current mirror circuit to generate a basic bias based on the power supply voltage and actively compensates for and suppresses bias current and transconductance drift caused by transistor channel length modulation effects through a channel modulation effect suppression circuit (including a first switched capacitor resistor and a second switched capacitor resistor). Simultaneously, an adjustment circuit (e.g., including a first resistor or a third switched capacitor resistor) allows the electronic device to dynamically adjust the magnitude of the bias current and transconductance according to its operating mode, environmental conditions, or performance requirements. This integration ensures that each functional module within the electronic device obtains ideal bias conditions under different operating conditions, thereby guaranteeing high performance, high stability, and low power consumption operation of the entire electronic device. A specific example is provided below; the aforementioned electronic device can be a wireless communication module. In this wireless communication module, the aforementioned bias current generation circuit can be integrated into the RF front-end or baseband processing unit. For example, in the RF front-end, this bias current generation circuit can provide a stable bias current to the bias stages of a low-noise amplifier (LNA), mixer, or power amplifier (PA), ensuring optimal linearity and gain stability for these critical RF components when receiving and transmitting signals. In the baseband processing unit, this circuit can provide precise bias to an analog-to-digital converter (ADC) or digital-to-analog converter (DAC), thereby guaranteeing the accuracy and speed of data conversion. This bias current generation circuit typically exists as an integrated circuit (IC) on the motherboard of the wireless communication module, forming a complete communication system together with other components such as the processor, memory, and RF transceiver.

[0087] By integrating the aforementioned bias current generation circuit into the electronic device, the device can fully utilize the stable, controllable bias current provided by this circuit, which is suppressed by channel modulation effects. This significantly improves the operational stability, accuracy, and reliability of the active circuitry within the electronic device, especially in analog and mixed-signal circuits sensitive to bias current. Because channel modulation effects are effectively suppressed, the electronic device exhibits more consistent and predictable performance in the face of power supply voltage fluctuations, temperature variations, or process variations. Furthermore, the adjustability of the bias current and transconductance gives the electronic device greater adaptability, allowing it to be optimized for specific application scenarios or power consumption requirements, thereby achieving more efficient and flexible functional configurations. Ultimately, this integrated solution enables the electronic device to deliver superior overall performance and user experience.

[0088] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0089] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0090] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0091] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application can be achieved, and this is not limited herein.

[0092] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0093] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A bias current generating circuit, characterized in that, include: A current mirror circuit for generating a bias current based on a power supply voltage, the current mirror circuit including a first transistor, a second transistor, a third transistor, and a fourth transistor; A channel modulation effect suppression circuit is used to suppress the influence of the channel modulation effect generated by the current mirror circuit on the bias current and transconductance of the bias current generating circuit. The channel modulation effect suppression circuit includes a first switched capacitor resistor and a second switched capacitor resistor. Adjustment circuit, used to adjust the bias current and transconductance; The gate and drain of the first transistor are connected, and the first transistor is connected to the drain of the third transistor via a first switched capacitor resistor; the gate of the first transistor is connected to the gate of the second transistor; the source of the first transistor is grounded; the source of the third transistor is connected to the power supply voltage; the gate of the third transistor is connected to the gate of the fourth transistor; the source of the fourth transistor is connected to the power supply voltage; the gate of the fourth transistor is connected to the drain of the fourth transistor, and the third transistor is connected to the drain of the second transistor via a second switched capacitor resistor; the source of the second transistor is grounded via the adjustment circuit.

2. The bias current generating circuit according to claim 1, characterized in that, The first transistor and the second transistor are N-type MOS transistors.

3. The bias current generating circuit according to claim 1, characterized in that, The third transistor and the fourth transistor are P-type MOS transistors.

4. The bias current generating circuit according to claim 1, characterized in that, The regulating circuit includes a first resistor.

5. The bias current generating circuit according to claim 1, characterized in that, The first switched capacitor resistor includes a first capacitor, a first controllable switch, and a second controllable switch. One end of the first capacitor is connected to the drain of the third transistor and one end of the first controllable switch, respectively, and the other end is connected to the other end of the first controllable switch and one end of the second controllable switch, respectively. The other end of the second controllable switch is connected to the drain of the first transistor.

6. The bias current generating circuit according to claim 1, characterized in that, The second switched capacitor resistor includes a second capacitor, a third controllable switch, and a fourth controllable switch. One end of the second capacitor is connected to one end of the third controllable switch and the drain of the fourth transistor, respectively, and the other end is connected to the other end of the third controllable switch and one end of the fourth controllable switch, respectively. The other end of the fourth controllable switch is connected to the drain of the second transistor.

7. The bias current generating circuit according to claim 1, characterized in that, Also includes: The first filter capacitor has one end connected to the drain of the first transistor and the other end grounded.

8. The bias current generating circuit according to claim 1, characterized in that, Also includes: The second filter capacitor has one end connected to the drain of the fourth transistor and the other end grounded.

9. The bias current generating circuit according to claim 1, characterized in that, Also includes: The first control circuit is used to monitor the power supply voltage and control the switching frequency of the first and second switched capacitor resistors based on the power supply voltage, so as to suppress the influence of the channel modulation effect generated by the current mirror circuit on the bias current and transconductance of the bias current generation circuit.

10. The bias current generating circuit according to claim 1, characterized in that, The adjustment circuit includes a third switched capacitor resistor and a corresponding second control circuit. The second control circuit is used to control the switching frequency of the third switched capacitor resistor based on the reference voltage signal and the control voltage signal, so as to control the transconductance of the bias current generating circuit.

11. The bias current generating circuit according to claim 10, characterized in that, The third switched capacitor resistor includes a third capacitor, a fifth controllable switch, and a sixth controllable switch; One end of the third capacitor is connected to one end of the fifth controllable switch and the source terminal of the second transistor, and the other end is connected to the other end of the fifth controllable switch and one end of the sixth controllable switch; the other end of the sixth controllable switch is grounded.

12. The bias current generating circuit according to claim 11, characterized in that, The second control circuit includes: Operational amplifier, fifth transistor, sixth transistor, seventh transistor, eighth transistor, ninth transistor, tenth transistor, eleventh transistor, twelfth transistor, thirteenth transistor, first voltage-controlled current source, second voltage-controlled current source and third voltage-controlled current source; The negative terminal of the operational amplifier is connected to a reference voltage, and its positive terminal is connected to the drain of the fifth transistor and simultaneously connected to the positive terminal of the first voltage-controlled current source. The negative terminal of the first voltage-controlled current source is grounded. The control terminals of the first, second, and third voltage-controlled current sources are connected to a control voltage. The input terminal of the operational amplifier is connected to the gate of the fifth transistor and simultaneously connected to the gates of the sixth, seventh, eighth, and ninth transistors. The sources of the fifth, sixth, seventh, eighth, and ninth transistors are connected to the power supply voltage. The drain of the sixth transistor is connected to the drain of the tenth transistor and then connected to the thirteenth transistor. The gate of the tenth transistor, the source of the tenth transistor, and the positive terminal of the second voltage-controlled current source are connected to the source of the eleventh transistor. The drain of the eleventh transistor and the drain of the seventh transistor are connected to the gate of the twelfth transistor. The gate of the eleventh transistor and the drain of the twelfth transistor are connected to the control terminal of the fifth controllable switch and connected to the drain of the eighth transistor. The source of the twelfth transistor and the source of the thirteenth transistor are connected to the positive terminal of the third voltage-controlled current source. The negative terminal of the third voltage-controlled current source is connected to ground. The drain of the thirteenth transistor and the drain of the ninth transistor are connected to the control terminal of the sixth controllable switch.

13. The bias current generating circuit according to claim 12, characterized in that, The fifth, sixth, seventh, eighth, and ninth transistors are P-type MOS transistors.

14. The bias current generating circuit according to claim 12, characterized in that, The tenth, eleventh, twelfth, and thirteenth transistors are N-type MOS transistors.

15. An electronic device, characterized in that, include: The bias current generating circuit as described in any one of claims 1-14.

Images