Embedded system and power saving control method thereof

Abstract

The invention provides an embedded system and a power saving control method thereof. The embedded system comprises a clock controller circuit, a clock gating circuit and a bus control circuit. The clock controller circuit is configured to set a memory control signal according to a sleep signal from the processor to control the first memory to enter a sleep mode and set a clock control signal and a request signal according to the sleep signal. The clock gating circuit is configured to cause the processor and the first memory to interrupt reception of a plurality of clock signals according to the clock control signal. The bus control circuit is configured to stop sending an access request to the processor and the first memory according to the request signal.

Description

Technical Field

[0001] This disclosure relates to embedded systems, and more particularly to embedded systems capable of gating clock signals and power supply voltages, and power-saving control methods thereof. Background Technology

[0002] In existing embedded systems, when the system enters power-saving mode, some clock circuits and internal memories continue to operate, resulting in additional power consumption. For example, if the signal path in this part of the clock circuit is long, it will still cause some power consumption even in power-saving mode. Summary of the Invention

[0003] In some embodiments, one of the objectives of this disclosure is (but not limited to) to provide an embedded system and a power-saving control method thereof that can gate clock signals and power supply voltages to improve the shortcomings of the prior art.

[0004] In some embodiments, an embedded system includes a clock controller circuit, a clock gating circuit, and a bus control circuit. The clock controller circuit sets a memory control signal based on a sleep signal from the processor to control a first memory to enter sleep mode, and sets a clock control signal and a request signal based on the sleep signal. The clock gating circuit interrupts the processor and the first memory from receiving multiple clock signals based on the clock control signal. The bus control circuit stops sending access requests to the processor and the first memory based on the request signal.

[0005] In some embodiments, a power-saving control method includes the following operations: setting a memory control signal to control a first memory to enter a sleep mode based on a sleep signal from a processor, and setting a clock control signal and a request signal based on the sleep signal; interrupting the processor and the first memory from receiving multiple clock signals based on the clock control signal; and stopping the sending of access requests to the processor and the first memory based on the request signal.

[0006] The features, implementation, and effects of this disclosure are described in detail below with reference to the accompanying drawings, using preferred embodiments. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of an embedded system according to some embodiments of the present disclosure;

[0008] Figure 2A Drawings based on some embodiments of this disclosure Figure 1 A flowchart of the relevant operations performed when an embedded system enters the first power-saving mode;

[0009] Figure 2B Drawings based on some embodiments of this disclosure Figure 1 A flowchart of the relevant operations performed by the embedded system when it leaves the first power-saving mode;

[0010] Figure 3A Drawings based on some embodiments of this disclosure Figure 1 A flowchart of the relevant operations performed when an embedded system enters the second power-saving mode;

[0011] Figure 3B Drawings based on some embodiments of this disclosure Figure 1 A flowchart of the relevant operations performed by the embedded system when it leaves the second power-saving mode;

[0012] Figure 4A Drawings based on some embodiments of this disclosure Figure 1 A flowchart of the relevant operations performed when an embedded system enters the third power-saving mode;

[0013] Figure 4B Drawings based on some embodiments of this disclosure Figure 1 A flowchart of the relevant operations performed by the embedded system when it leaves the third power-saving mode;

[0014] Figure 5 Drawings based on some embodiments of this disclosure Figure 1 A flowchart of the relevant operations for selecting the processor's power-saving mode; and

[0015] Figure 6 A flowchart of a power-saving control method is provided based on some embodiments of this disclosure. Detailed Implementation

[0016] All terms used herein have their ordinary meanings. The definitions of the terms above in commonly used dictionaries, and examples of the use of any term discussed herein, are merely illustrative and should not be construed as limiting the scope and meaning of this disclosure. Similarly, this disclosure is not limited to the various embodiments shown in this specification.

[0017] As used herein, “coupled” or “connected” can refer to two or more components making direct physical or electrical contact with each other, or indirectly making direct physical or electrical contact with each other, or to two or more components operating or acting on each other. As used herein, the term “circuit” can refer to a system implemented by one or more circuits, and the term “circuit” can refer to a device consisting of at least one transistor and / or at least one main passive component connected in a certain manner to process signals.

[0018] As used herein, the term "and / or" includes any combination of one or more of the listed related items. The terms first, second, third, etc., are used herein to describe and identify individual elements. Therefore, a first element herein may also be referred to as a second element without departing from the intent of this disclosure. For ease of understanding, similar elements in the figures will be designated with the same reference numerals.

[0019] Figure 1 This is a schematic diagram of an embedded system 100 according to some embodiments of the present disclosure. In different embodiments, the embedded system 100 can be applied to various electronic devices, such as, but not limited to, smartphones, laptops, etc. The embedded system 100 includes a processor 110, a clock controller circuit 120, a clock gating circuit 130, a bus control circuit 140, a power gating circuit 150, a memory 160, a memory 165, a clock generator circuit 170, and a clock tree circuit 175. The processor 110 is coupled to the clock controller circuit 120 and, when entering a wait-for-interrupt (WFI) mode (or sleep mode), sends a sleep signal PS to the clock controller circuit 120, allowing the clock controller circuit 120 to control other circuits (e.g., including the processor 110, clock gating circuit 130, bus control circuit 140, power gating circuit 150, and memory 160) to enter a power-saving mode, thereby saving overall power consumption.

[0020] The clock controller circuit 120 can set the memory control signal MC according to the sleep signal PS from the processor 110 to control the memory 160 to enter sleep mode, and set the clock control signal CC and the request signal SQ according to the sleep signal PS. In some embodiments, the clock controller circuit 120 may include one or more registers (not shown) for storing the values ​​of the sleep signal PS, the clock control signal CC, and the request signal SQ. The memory 160, the clock gating circuit 130, and the bus control circuit 140 may be coupled to the one or more registers to perform corresponding operations according to the values ​​of these signals when they are set. Alternatively, the clock controller circuit 120 may clear the values ​​of these signals in the one or more registers to allow the memory 160, the clock gating circuit 130, and the bus control circuit 140 to resume their original operations. In some embodiments, the clock controller circuit 120 is further configured to receive an interrupt signal SI1 from another device or circuit (not shown), generate an interrupt signal SI2 based on the interrupt signal SI1, and transmit the interrupt signal SI2 to the processor 110, thereby waking up the processor 110 operating in sleep mode. In some embodiments, the bus control circuit 140 is configured to stop sending access requests RQ to the processor 110 and / or the memory 160 based on a request signal SQ. In some embodiments, if the access request RQ is for accessing a specific memory module in the memory 160, the processor 110 may forward this access request RQ to a controller (not shown) in the memory 160, so that the controller may access the specific memory module based on the access request RQ.

[0021] In some embodiments, when the bus control circuit 140 receives an access request from another device or circuit (not shown), the bus control circuit 140 may send a request activation signal QV to the clock controller circuit 120, thereby interacting with the clock controller circuit 120 based on a protocol request of a predetermined transmission interface to notify the clock controller circuit 120 to wake up the processor 110. In other words, in different examples, when the clock controller circuit 120 detects an interrupt signal SI1 or a request activation signal QV, the clock controller circuit 120 may send an interrupt signal SI2 to wake up the processor 110 and clear the request signal SQ. Accordingly, the bus control circuit 140 may send an acknowledgment signal ACK in response to the clock controller circuit 120 and begin sending an access request RQ.

[0022] Clock generator circuit 170 operates as a clock source to provide the raw clock signal CK1. Clock gating circuit 130 is coupled to clock generator circuit 170 to receive the raw clock signal CK1 and output the raw clock signal CK1 as the system clock signal CKS. Clock tree circuit 175 generates clock signals CK2 and CK3 based on the system clock signal CKS, and transmits clock signals CK2 and CK3 to processor 110 and memory 160 respectively. Clock gating circuit 130 also interrupts processor 110 and memory 160 from receiving clock signals CK2 and CK3 based on clock control signal CC. For example, after clock controller circuit 120 sets clock control signal CC, clock gating circuit 130 can shield the system clock signal CKS based on clock control signal CC, that is, stop sending the system clock signal CKS to clock tree circuit 175, thereby causing clock tree circuit 175 to stop generating clock signals CK2 and CK3. In this way, processor 110 and memory 160 will interrupt the reception of clock signals CK2 and CK3, thereby reducing the dynamic power consumption of processor 110 and memory 160. In some embodiments, clock gating circuit 130 may be implemented by, but is not limited to, an integrated clock gating cell. In some embodiments, clock generator circuit 170 may be implemented by, but is not limited to, a phase-locked loop circuit. In some embodiments, clock tree circuit 175 may be implemented by, but is not limited to, one or more buffers or delay circuits.

[0023] In some embodiments, the clock controller circuit 120 further sets the power control signal PG1 according to the sleep signal PS, and the power gating circuit 150 is used to stop supplying power to the processor 110 according to the power control signal PG1. For example, the power gating circuit 150 includes a switching circuit (not shown) that is selectively turned on according to the power control signal PG1 to transmit the power supply voltage VCORE to the processor 110. In other words, the power control signal PG1 can be used to determine whether to supply power to the processor 110. In some embodiments, the clock controller circuit 120 further sets the power control signal PG2 according to the sleep signal PS, and the power gating circuit 150 is used to stop supplying power to the memory 160 according to the power control signal PG2. For example, the power gating circuit 150 includes a switching circuit (not shown) that is selectively turned on according to the power control signal PG2 to transmit the power supply voltage VRAM to a portion of the memory modules in the memory 160 (e.g., multiple memory modules 160[2] to 160[5]). In other words, the power control signal PG2 can be used to determine whether to supply power to that portion of the memory modules. In some embodiments, memory 160 may be volatile memory (e.g., but not limited to, static random access memory), which may include memory module 160[1] and a plurality of memory modules 160[2] to 160[5], wherein memory module 160[1] is powered without power gating, and the plurality of memory modules 160[2] to 160[5] are powered with power gating (e.g., receiving power supply voltage VRAM via power gating circuit 150).

[0024] In some embodiments, the processor 110 may set a power-saving level signal PL via system software and / or firmware, and the clock controller circuit 120 may determine whether to set power control signals PG1 and / or PG2 based on this power-saving level signal PL and a sleep signal PS. For example, if the embedded system 100 is applied to a laptop computer, when the laptop computer is connected to a charger (i.e., the laptop computer can rely on an external power source), the processor 110 may set the power-saving level signal PL to a first value. Under this condition, the clock controller circuit 120 may generate a clock control signal CC and a request signal SQ based on the sleep signal PS and the power-saving level signal PL to control the clock gating circuit 130 and the bus control circuit 140 to enter a first power-saving mode. Alternatively, when the laptop computer is not connected to a charger and its battery level is not lower than a threshold, the processor 110 may set the power-saving level signal PL to a second value. Under these conditions, the clock controller circuit 120 can generate a clock control signal CC, a request signal SQ, and a power control signal PG1 based on the sleep signal PS and the power saving level signal PL, to control the clock gating circuit 130, the bus control circuit 140, and the power gating circuit 150 to enter the second power saving mode. Further, when the laptop is not connected to a charger and its battery level is below a critical value, the processor 110 can set the power saving level signal PL to a third value. Under these conditions, the clock controller circuit 120 can generate a clock control signal CC, a request signal SQ, and multiple power control signals PG1 and PG2 based on the sleep signal PS and the power saving level signal PL, to control the clock gating circuit 130, the bus control circuit 140, and the power gating circuit 150 to enter the third power saving mode.

[0025] In the first power-saving mode, the clock gating circuit 130 can stop providing the system clock signal CKS to the clock tree circuit 175, thereby interrupting the processor 110 and memory 160 from receiving clock signals CK2 and CK3, thus saving dynamic power consumption. In the second power-saving mode, the power gating circuit 150 also stops supplying power to the processor 110. In the third power-saving mode, the power gating circuit 150 also stops supplying power to multiple memory modules 160[2] to 160[5]. In other words, the power saving of the third power-saving mode is greater than that of the second power-saving mode or the first power-saving mode, and the power saving of the second power-saving mode is greater than that of the first power-saving mode.

[0026] For ease of explanation, the following description, in conjunction with different accompanying drawings, will illustrate the operations related to the embedded system 100 entering and exiting the first, second, and third power-saving modes. In different embodiments, any of the aforementioned circuits in the embedded system 100 may be implemented by at least one digital logic circuit, wherein the at least one digital logic circuit may be configured as a state machine to perform the operations related to the following figures, but this disclosure is not limited thereto.

[0027] Figure 2A Drawings based on some embodiments of this disclosure Figure 1 This is a flowchart illustrating the operations performed when the embedded system 100 enters a first power-saving mode. In operation S201, the processor 110 enters a sleep mode and issues a sleep signal PS. In operation S202, the clock controller circuit 120 sets the memory control signal MC, the clock control signal CC, and the request signal SQ according to the sleep signal PS. In some embodiments, the clock controller circuit 120 may confirm that the processor 110 is operating in sleep mode based on the sleep signal PS. In operation S203, the memory 160 operates in sleep mode according to the memory control signal MC. In operation S204, the clock gating circuit 130 stops providing the system clock signal CKS to the clock tree circuit 175 according to the clock control signal CC, thereby interrupting the processor 110 and memory 160 from receiving clock signals CK2 and CK3. In operation S205, the bus control circuit 140 stops sending access requests RQ to the processor 110 and memory 160 according to the request signal SQ. Through the above operations, the clock controller circuit 120 can stop the processor 110 and memory 160 from receiving access request RQ, clock signal CK2 and clock signal CK3 in the first power saving mode, so as to save overall dynamic power consumption.

[0028] Figure 2B Drawings based on some embodiments of this disclosure Figure 1 This is a flowchart of the operations performed by the embedded system 100 when it leaves the first power-saving mode. In operation S211, when the clock controller circuit 120 detects an interrupt signal SI1 from another device or a request signal QV from the bus control circuit 140, the clock controller circuit 120 clears the clock control signal CC and the memory control signal MC, and begins timing a preset period. In response to the cleared clock control signal CC, the clock gating circuit 130 can begin providing the system clock signal CKS, thereby causing the clock tree circuit 175 to begin emitting clock signals CK2 and CK3 (i.e., operation S213). Similarly, in response to the cleared memory control signal MC, the memory 160 can leave the power-saving mode and operate in normal mode. In operation S212, when the preset period expires, the clock controller circuit 120 clears the request signal SQ and issues an interrupt signal SI2, causing the memory 160 to leave the sleep mode. In operation S213, clock gating circuit 130 provides system clock signal CKS, causing clock tree circuit 175 to begin providing clock signals CK2 and CK3 to processor 110 and memory 160. In operation S214, processor 110 begins operation based on interrupt signal SI2. In operation S215, bus control circuit 140 begins sending access request RQ.

[0029] In some embodiments, upon receiving an interrupt signal SI1 and / or a request signal QV, the clock controller circuit 120 may clear the clock control signal CC, causing the clock gating circuit 130 to begin providing the system clock signal CKS, thereby causing the clock tree circuit 175 to begin providing clock signals CK2 and CK3. In some embodiments, to ensure that the processor 110 and memory 160 receive stable clock signals CK2 and CK3, the clock controller circuit 120 may start timing a preset period when the clock control signal CC is cleared, and after the preset period expires, issue an interrupt signal SI2 to wake up the processor 110, and clear the request signal SQ to cause the clock gating circuit 130 to begin providing the system clock signal CKS, thereby causing the clock tree circuit 175 to begin providing clock signals CK2 and CK3. This improves the overall operational reliability and compatibility of the system. In some embodiments, the preset period is sufficient for the clock signal CK2 (and / or clock signal CK3) to reach a stable preset waveform after the switching begins. In some embodiments, the clock controller circuit 120 may include several delay circuits for timing the preset time period, but this disclosure is not limited thereto.

[0030] Figure 3A Drawings based on some embodiments of this disclosure Figure 1 The flowchart shows the relevant operations performed when the embedded system 100 enters the second power-saving mode. In operation S301, before entering the sleep mode, the processor 110 stores the data D1 in its general-purpose temporary register to the memory module 160 of the memory 160 [1]. For example, as Figure 1As shown, processor 110 includes a general-purpose temporary register 110A, which can be used to store data D1. In some embodiments, data D1 may include intermediate results of various operations performed by processor 110, memory addresses, function and / or control information, but this disclosure is not limited thereto. In operation S302, processor 110 enters sleep mode and issues a sleep signal PS. In operation S303, clock controller circuit 120 sets memory control signal MC, clock control signal CC, request signal SQ, and power control signal PG1 according to sleep signal PS. In operation S304, memory 160 operates in sleep mode according to memory control signal MC. In operation S305, clock gating circuit 130 stops providing system clock signal CKS according to clock control signal CC, so that clock tree circuit 175 does not provide clock signals CK2 and CK3, thereby interrupting processor 110 and memory 160 from receiving clock signals CK2 and CK3. In operation S306, power gating circuit 150 stops supplying power to processor 110 according to power control signal PG1. In operation S307, bus control circuit 140 stops sending access request RQ to processor 110 and memory 160 according to request signal SQ. Compared to the first power saving mode, clock controller circuit 120 can further interrupt processor 110 from receiving power supply voltage VCORE (e.g., in operation S306) in the second power saving mode, thereby further improving power saving.

[0031] Figure 3B Drawings based on some embodiments of this disclosure Figure 1The embedded system 100 performs the following operations and flowcharts when it exits the second power-saving mode. In operation S311, when the clock controller circuit 120 detects an interrupt signal SI1 from another device or a request signal QV from the bus control circuit 140, the clock controller circuit 120 clears the clock control signal CC and the memory control signal MC, and begins timing a preset period. In operation S312, when the preset period expires, the clock controller circuit 120 clears the request signal SQ and the power control signal PG1 and issues an interrupt signal SI2 to cause the memory 160 to exit sleep mode. The power control signal PG1 determines whether to supply power to the processor 110. In operation S313, the clock gating circuit 130 provides the system clock signal CKS, causing the clock tree circuit 175 to begin providing clock signals CK2 and CK3 to the processor 110 and the memory 160. In operation S314, the power gating circuit 150 begins supplying power to the processor 110. In operation S315, processor 110 writes the data D1 stored in memory module 160[1] in memory 160 back to general-purpose temporary register 110A, and starts running according to interrupt signal SI2. In operation S316, bus control circuit 140 starts sending access request RQ.

[0032] Figure 4A Drawings based on some embodiments of this disclosure Figure 1The flowchart shows the relevant operations performed when the embedded system 100 enters the third power-saving mode. In operation S401, before entering the sleep mode, the processor 110 stores the data D1 in the general-purpose temporary register 110A into the memory module 160[1] in the memory 160, and stores the data D2 of at least one of the memory modules 160[2] to 160[5] in the memory 160 into the memory 165. In this example, the memory 165 may be a non-volatile memory, such as, but not limited to, flash memory. Thus, the memory 165 can continuously hold the data D2. In operation S402, the processor 110 enters the sleep mode and issues a sleep signal PS. In operation S403, the clock controller circuit 120 sets the memory control signal MC, the clock control signal CC, the request signal SQ, the power control signal PG1, and the power control signal PG2 according to the sleep signal PS. In operation S404, the memory module 160[1] of the memory 160 operates in the sleep mode according to the memory control signal MC. In operation S405, the clock gating circuit 130 does not provide the system clock signal CKS according to the clock control signal CC, so that the clock tree circuit 175 does not generate clock signals CK2 and CK3, thereby interrupting the processor 110 and memory 160 from receiving clock signals CK2 and CK3. In operation S406, the power gating circuit 150 stops supplying power to the processor 110 according to the power control signal PG1, and stops supplying power to the memory modules 160[2] to 160[5] in the memory 160 according to the power control signal PG2. In operation S407, the bus control circuit 140 stops sending access request RQ to the processor 110 and memory 160 according to the request signal SQ. Compared with the second power saving mode, the clock controller circuit 120 can further interrupt some memory modules (e.g., memory modules 160[2] to 160[5]) in the second power saving mode from receiving the power supply voltage VRAM, thereby further improving power saving.

[0033] Figure 4B Drawings based on some embodiments of this disclosure Figure 1The flowchart shows the relevant operations performed by the embedded system 100 when it leaves the third power-saving mode. In operation S411, when the clock controller circuit 120 detects the interrupt signal SI1 from another device or the request signal QV from the bus control circuit 140, the clock controller circuit 120 clears the clock control signal CC and the memory control signal MC, and starts timing a preset period. In operation S412, when the preset period expires, the clock controller circuit 120 clears the request signal SQ, the power control signal PG1 and the power control signal PG2, and issues the interrupt signal SI2 to make the memory 160 leave the hibernation mode. The power control signals PG1 and PG2 are used to determine whether to supply power to the processor 110 and the multiple memory modules 160[2] to 160[5]. In operation S413, the clock gating circuit 130 starts to provide the system clock signal CKS, so that the clock tree circuit 175 starts to provide the clock signals CK2 and CK3 to the processor 110 and the memory 160. In operation S414, the power gating circuit 150 begins to supply power to the processor 110 and the plurality of memory modules 160[2] to 160[5]. In operation S415, the processor 110 writes back the data D1 stored in memory module 160[1] in memory 160 to the general-purpose temporary register 110A, and writes back the data D2 stored in memory 165 to at least one of the corresponding memory modules 160[2] to 160[5], and starts running according to the interrupt signal SI2. In operation S416, the bus control circuit 140 begins to send access request RQ. Through the above operations, when leaving the third power saving mode, the processor 110 can write back the data D1 stored in memory module 160[1] to the general-purpose temporary register 110A, and write back the data D2 stored in memory 165 to the memory modules 160[2] to 160[5]. In this way, the processor 110 can return to the operating state when entering the third power saving mode.

[0034] Figure 5 Drawings based on some embodiments of this disclosure Figure 1 The flowchart illustrates the relevant operations of the processor 110 in selecting a power-saving mode. In operation S510, a power-saving level signal PL is set according to system operating conditions. In operation S520, a corresponding power-saving mode is selected from multiple power-saving modes based on the power-saving level signal PL, and the processor enters that corresponding power-saving mode and issues a sleep signal PS. For example, as previously described, if the embedded system 100 can be powered by an external power source (e.g., a charger), the processor 110 can set the power-saving level signal PL to a first value to enter a first power-saving mode and perform related operations (e.g., for...). Figure 2A(Operation S201). Alternatively, when the embedded system 100 is not connected to a charger and its battery charge is not lower than a threshold, the processor 110 can set the power-saving level signal PL to a second value to enter a second power-saving mode and perform related operations (e.g., for...). Figure 3A Operations S301 and S302). When the embedded system 100 is not connected to a charger and its battery power is below a threshold, the processor 110 can set the power-saving level signal PL to a third value to enter a third power-saving mode and perform related operations (e.g., for...). Figure 4A (Operations S401 and S402). Accordingly, the clock controller circuit 120 can control other circuits to enter the corresponding power-saving mode according to the power-saving level signal PL and the sleep signal PS. It should be understood that the above examples are based on the first to third power-saving modes, but this disclosure is not limited thereto. In different embodiments, the multiple power-saving modes in operation S520 may be at least two of the first to third power-saving modes described above.

[0035] Figure 6 A flowchart of a power-saving control method 600 is provided according to some embodiments of the present disclosure. In some embodiments, the power-saving control method 600 may be applied to an embedded system (e.g., but not limited to, [system name]). Figure 1 (Embedded system 100). In operation S610, a memory control signal is set according to a sleep signal from the processor to control the first memory to enter sleep mode, and a clock control signal and a request signal are set according to the sleep signal. In operation S620, the processor and the first memory are interrupted from receiving multiple clock signals according to the clock control signal. In operation S630, the sending of access requests to the processor and the first memory is stopped according to the request signal.

[0036] The descriptions of the above operations can be found in the aforementioned embodiments, and therefore will not be repeated here. Figures 2A to 6 The operations shown in the figures are merely examples and are not intended to be performed in the specified order. Without departing from the mode and scope of operation of the embodiments of this disclosure, the related operations in the above figures may be appropriately added, replaced, omitted, or performed in a different order. Alternatively, the related operations in the above figures may be performed simultaneously or partially simultaneously.

[0037] In summary, the embedded system and power-saving control method provided in some embodiments of this disclosure can further gate the clock signal and power supply voltage when the processor is operating in sleep mode, so as to save more power consumption, and can be compatible with the original power-saving mechanism.

[0038] Although the embodiments of this disclosure are described above, these embodiments are not intended to limit this disclosure. Those skilled in the art can make changes to the technical features of this disclosure based on the express or implied content of this disclosure. All such changes may fall within the scope of patent protection sought by this disclosure. In other words, the scope of patent protection of this disclosure shall be determined by the scope of the patent application in this specification.

[0039] [Symbol Explanation]

[0040] 100: Embedded Systems

[0041] 110: Processor

[0042] 110A: General Purpose Temporary Register

[0043] 120: Clock controller circuit

[0044] 130: Clock Gating Circuit

[0045] 140: Bus control circuit

[0046] 150: Power supply gating circuit

[0047] 160, 165: Memory

[0048] 160[1]~160[5]: Memory module

[0049] 170: Clock Generator Circuit

[0050] 175: Clock Tree Circuit

[0051] 600: Power-saving control method

[0052] ACK: Acknowledgment signal

[0053] CC: Clock control signal

[0054] CK1: Original clock signal

[0055] CK2, CK3: Clock signals

[0056] CKS: System clock signal

[0057] D1, D2: Data

[0058] MC: Memory Control Signal

[0059] PG1, PG2: Power control signals

[0060] PL: Power saving level signal

[0061] PS: Sleep signal

[0062] QV: Request for activation signal

[0063] RQ: Access Request

[0064] S201~S205, S211~215, S301~307, S311~S316: Operation

[0065] S401~S407, S411~S416, S510, S520, S610, S620, S630: Operation

[0066] SI1, SI2: Interrupt signals

[0067] SQ: Request signal

[0068] VCORE, VRAM: Power supply voltage

Claims

1. An embedded system, comprising: A clock controller circuit is used to set a memory control signal according to a sleep signal from the processor to control the first memory to enter sleep mode, and to set a clock control signal and a request signal according to the sleep signal. A clock gating circuit is used to interrupt the processor and the first memory from receiving multiple clock signals according to the clock control signal. as well as A bus control circuit is used to stop sending access requests to the processor and the first memory based on the request signal.

2. The embedded system of claim 1, wherein when the clock controller circuit detects the first interrupt signal or receives a request activation signal from the bus control circuit, the clock controller circuit is further configured to clear the clock control signal and the memory control signal and start timing a preset period, and when the preset period expires, clear the request signal and issue a second interrupt signal to cause the first memory to leave the sleep mode, the clock gating circuit starts to provide the plurality of clock signals to the processor and the first memory, the processor starts running according to the second interrupt signal, and the bus control circuit starts to send the access request.

3. The embedded system of claim 1, wherein the processor is further configured to store data stored in the processor's general-purpose temporary register to the first memory before issuing the sleep signal.

4. The embedded system of claim 1, further comprising: A power gating circuit is used to stop supplying power to the processor based on a power control signal. The clock controller circuit is also used to set the power control signal according to the sleep signal.

5. The embedded system of claim 4, wherein when the clock controller circuit detects the first interrupt signal or receives a request activation signal from the bus control circuit, the clock controller circuit is further configured to clear the clock control signal and the memory control signal and start timing a preset period, and when the preset period expires, clear the power control signal and the request signal and issue a second interrupt signal to cause the first memory to leave the sleep mode, the clock gating circuit starts to provide the plurality of clock signals to the processor and the first memory, the power gating circuit starts to supply power to the processor, the processor stores the data in the first memory back to the processor's general-purpose temporary register and starts running according to the second interrupt signal, the bus control circuit starts to send the access request, and the power control signal is used to determine whether to supply power to the processor.

6. The embedded system of claim 1, wherein the first memory includes a first memory module and a second memory module, the processor is configured to store first data in the processor's general-purpose temporary register in the first memory module before issuing the sleep signal, and to store second data in the second memory module into the second memory.

7. The embedded system of claim 6, further comprising: A power gating circuit is used to stop supplying power to the processor and the second memory module based on multiple power control signals. The clock controller circuit is also used to generate the multiple power control signals based on the sleep signal.

8. The embedded system of claim 7, wherein when the clock controller circuit detects a first interrupt signal or receives a request activation signal from the bus control circuit, the clock controller circuit is further configured to clear the clock control signal and the memory control signal and start timing a preset period, and when the preset period expires, clear the plurality of power control signals and the request signal and issue a second interrupt signal to cause the first memory to leave the sleep mode, the clock gating circuit starts to provide the plurality of clock signals to the processor and the first memory, the power gating circuit starts to supply power to the processor and the second memory module, the processor stores the first data in the first memory module back to the general-purpose temporary register, stores the second data in the second memory back to the second memory module, and starts running according to the second interrupt signal, the bus control circuit starts to send the access request, and the plurality of power control signals are used to determine whether to supply power to the processor and the second memory module.

9. The embedded system of claim 6, wherein the first memory module is powered without power gating, and the second memory module is powered with power gating.

10. A power-saving control method, comprising: The memory control signal is set according to the sleep signal from the processor to control the first memory to enter sleep mode, and the clock control signal and request signal are set according to the sleep signal. The clock control signal causes the processor and the first memory to receive multiple clock signals. as well as Based on the request signal, the sending of access requests to the processor and the first memory is stopped.

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